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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FStar.All.ML | val print_proc (name: string) (code: code) (label: int) (p: printer) : FStar.All.ML int | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_proc (name:string) (code:code) (label:int) (p:printer) : FStar.All.ML int =
let proc = p.proc_name name in
let code_str, final_label = print_code code label p in
let ret = p.ret name in
print_string (proc ^ code_str ^ ret);
final_label | val print_proc (name: string) (code: code) (label: int) (p: printer) : FStar.All.ML int
let print_proc (name: string) (code: code) (label: int) (p: printer) : FStar.All.ML int = | true | null | false | let proc = p.proc_name name in
let code_str, final_label = print_code code label p in
let ret = p.ret name in
print_string (proc ^ code_str ^ ret);
final_label | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"ml"
] | [
"Prims.string",
"Vale.X64.Machine_Semantics_s.code",
"Prims.int",
"Vale.X64.Print_s.printer",
"Prims.unit",
"FStar.IO.print_string",
"Prims.op_Hat",
"Vale.X64.Print_s.__proj__Mkprinter__item__ret",
"FStar.Pervasives.Native.tuple2",
"Vale.X64.Print_s.print_code",
"Vale.X64.Print_s.__proj__Mkprinter__item__proc_name"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second
let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs)
let print_ins (ins:ins) (p:printer) : string =
let print_pair (dst src:string) = print_pair dst src p in
let print_op_pair (dst:operand64) (src:operand64) (print_dst:operand64 -> printer -> string) (print_src:operand64 -> printer -> string) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst:operand64) (src:operand64) =
print_op_pair dst src print_operand print_operand
in
let print_shift (dst:operand64) (amount:operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst:operand64) (src:reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst:reg_xmm) (src:reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2:reg_xmm) =
print_pair (print_xmm dst p) (print_xmms src1 src2)
in
let print_vpxor (dst src1:reg_xmm) (src2:operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip:instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
let print_cmp (c:ocmp) (counter:int) (p:printer) : string =
let print_ops (o1:operand64) (o2:operand64) : string =
let first, second = p.op_order (print_operand o1 p) (print_operand o2 p) in
" cmp " ^ first ^ ", " ^ second ^ "\n"
in
match c with
| OEq o1 o2 -> print_ops o1 o2 ^ " je " ^ "L" ^ string_of_int counter ^ "\n"
| ONe o1 o2 -> print_ops o1 o2 ^ " jne "^ "L" ^ string_of_int counter ^ "\n"
| OLe o1 o2 -> print_ops o1 o2 ^ " jbe "^ "L" ^ string_of_int counter ^ "\n"
| OGe o1 o2 -> print_ops o1 o2 ^ " jae "^ "L" ^ string_of_int counter ^ "\n"
| OLt o1 o2 -> print_ops o1 o2 ^ " jb " ^ "L" ^ string_of_int counter ^ "\n"
| OGt o1 o2 -> print_ops o1 o2 ^ " ja " ^ "L" ^ string_of_int counter ^ "\n"
let rec print_block (b:codes) (n:int) (p:printer) : string & int =
match b with
| Nil -> ("", n)
| Ins (Instr _ _ (AnnotateSpace _)) :: tail -> print_block tail n p
| Ins (Instr _ _ (AnnotateGhost _)) :: tail -> print_block tail n p
| head :: tail ->
let (head_str, n') = print_code head n p in
let (rest, n'') = print_block tail n' p in
(head_str ^ rest, n'')
and print_code (c:code) (n:int) (p:printer) : string & int =
match c with
| Ins ins -> (print_ins ins p ^ "\n", n)
| Block b -> print_block b n p
| IfElse cond true_code false_code ->
let n1 = n in
let n2 = n + 1 in
let cmp = print_cmp (cmp_not cond) n1 p in
let (true_str, n') = print_code true_code (n + 2) p in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = "L" ^ string_of_int n1 ^ ":\n" in
let (false_str, n') = print_code false_code n' p in
let label2 = "L" ^ string_of_int n2 ^ ":\n" in
(cmp ^ true_str ^ jmp ^ label1 ^ false_str ^ label2, n')
| While cond body ->
let n1 = n in
let n2 = n + 1 in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = p.align() ^ " 16\nL" ^ string_of_int n1 ^ ":\n" in
let (body_str, n') = print_code body (n + 2) p in
let label2 = p.align() ^ " 16\nL" ^ string_of_int n2 ^ ":\n" in
let cmp = print_cmp cond n1 p in
(jmp ^ label1 ^ body_str ^ label2 ^ cmp, n')
let print_header (p:printer) =
print_string (p.header()) | false | false | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_proc (name: string) (code: code) (label: int) (p: printer) : FStar.All.ML int | [] | Vale.X64.Print_s.print_proc | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
name: Prims.string ->
code: Vale.X64.Machine_Semantics_s.code ->
label: Prims.int ->
p: Vale.X64.Print_s.printer
-> FStar.All.ML Prims.int | {
"end_col": 13,
"end_line": 296,
"start_col": 85,
"start_line": 291
} |
Prims.Tot | val print_small_reg_name (r: reg_64) : string | [
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl." | val print_small_reg_name (r: reg_64) : string
let print_small_reg_name (r: reg_64) : string = | false | null | false | match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl." | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.reg_64",
"Prims.int",
"Prims.string"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d" | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_small_reg_name (r: reg_64) : string | [] | Vale.X64.Print_s.print_small_reg_name | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.X64.Machine_s.reg_64 -> Prims.string | {
"end_col": 70,
"end_line": 68,
"start_col": 2,
"start_line": 63
} |
Prims.Tot | val print_reg32_name (r: reg_64) : string | [
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d" | val print_reg32_name (r: reg_64) : string
let print_reg32_name (r: reg_64) : string = | false | null | false | match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d" | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.reg_64",
"Prims.int",
"Prims.op_Hat",
"Vale.X64.Print_s.print_reg_name",
"Prims.string"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15" | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_reg32_name (r: reg_64) : string | [] | Vale.X64.Print_s.print_reg32_name | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.X64.Machine_s.reg_64 -> Prims.string | {
"end_col": 31,
"end_line": 60,
"start_col": 2,
"start_line": 51
} |
Prims.Tot | val print_small_reg (r: reg_64) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r | val print_small_reg (r: reg_64) (p: printer) : string
let print_small_reg (r: reg_64) (p: printer) : string = | false | null | false | p.reg_prefix () ^ p.print_small_reg_name r | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.reg_64",
"Vale.X64.Print_s.printer",
"Prims.op_Hat",
"Vale.X64.Print_s.__proj__Mkprinter__item__reg_prefix",
"Vale.X64.Print_s.__proj__Mkprinter__item__print_small_reg_name",
"Prims.string"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_small_reg (r: reg_64) (p: printer) : string | [] | Vale.X64.Print_s.print_small_reg | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.X64.Machine_s.reg_64 -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 43,
"end_line": 77,
"start_col": 2,
"start_line": 77
} |
Prims.Tot | val print_pair (dst src: string) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second | val print_pair (dst src: string) (p: printer) : string
let print_pair (dst src: string) (p: printer) : string = | false | null | false | let first, second = p.op_order dst src in
first ^ ", " ^ second | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Prims.string",
"Vale.X64.Print_s.printer",
"Prims.op_Hat",
"FStar.Pervasives.Native.tuple2",
"Vale.X64.Print_s.__proj__Mkprinter__item__op_order"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o)) | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_pair (dst src: string) (p: printer) : string | [] | Vale.X64.Print_s.print_pair | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | dst: Prims.string -> src: Prims.string -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 25,
"end_line": 156,
"start_col": 54,
"start_line": 154
} |
Prims.Tot | val print_xmm (x: reg_xmm) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x | val print_xmm (x: reg_xmm) (p: printer) : string
let print_xmm (x: reg_xmm) (p: printer) : string = | false | null | false | p.reg_prefix () ^ "xmm" ^ string_of_int x | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.reg_xmm",
"Vale.X64.Print_s.printer",
"Prims.op_Hat",
"Vale.X64.Print_s.__proj__Mkprinter__item__reg_prefix",
"Prims.string_of_int",
"Prims.string"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_xmm (x: reg_xmm) (p: printer) : string | [] | Vale.X64.Print_s.print_xmm | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | x: Vale.X64.Machine_s.reg_xmm -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 43,
"end_line": 124,
"start_col": 2,
"start_line": 124
} |
FStar.All.ML | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_footer (p:printer) =
print_string (p.footer()) | let print_footer (p: printer) = | true | null | false | print_string (p.footer ()) | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"ml"
] | [
"Vale.X64.Print_s.printer",
"FStar.IO.print_string",
"Vale.X64.Print_s.__proj__Mkprinter__item__footer",
"Prims.unit"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second
let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs)
let print_ins (ins:ins) (p:printer) : string =
let print_pair (dst src:string) = print_pair dst src p in
let print_op_pair (dst:operand64) (src:operand64) (print_dst:operand64 -> printer -> string) (print_src:operand64 -> printer -> string) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst:operand64) (src:operand64) =
print_op_pair dst src print_operand print_operand
in
let print_shift (dst:operand64) (amount:operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst:operand64) (src:reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst:reg_xmm) (src:reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2:reg_xmm) =
print_pair (print_xmm dst p) (print_xmms src1 src2)
in
let print_vpxor (dst src1:reg_xmm) (src2:operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip:instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
let print_cmp (c:ocmp) (counter:int) (p:printer) : string =
let print_ops (o1:operand64) (o2:operand64) : string =
let first, second = p.op_order (print_operand o1 p) (print_operand o2 p) in
" cmp " ^ first ^ ", " ^ second ^ "\n"
in
match c with
| OEq o1 o2 -> print_ops o1 o2 ^ " je " ^ "L" ^ string_of_int counter ^ "\n"
| ONe o1 o2 -> print_ops o1 o2 ^ " jne "^ "L" ^ string_of_int counter ^ "\n"
| OLe o1 o2 -> print_ops o1 o2 ^ " jbe "^ "L" ^ string_of_int counter ^ "\n"
| OGe o1 o2 -> print_ops o1 o2 ^ " jae "^ "L" ^ string_of_int counter ^ "\n"
| OLt o1 o2 -> print_ops o1 o2 ^ " jb " ^ "L" ^ string_of_int counter ^ "\n"
| OGt o1 o2 -> print_ops o1 o2 ^ " ja " ^ "L" ^ string_of_int counter ^ "\n"
let rec print_block (b:codes) (n:int) (p:printer) : string & int =
match b with
| Nil -> ("", n)
| Ins (Instr _ _ (AnnotateSpace _)) :: tail -> print_block tail n p
| Ins (Instr _ _ (AnnotateGhost _)) :: tail -> print_block tail n p
| head :: tail ->
let (head_str, n') = print_code head n p in
let (rest, n'') = print_block tail n' p in
(head_str ^ rest, n'')
and print_code (c:code) (n:int) (p:printer) : string & int =
match c with
| Ins ins -> (print_ins ins p ^ "\n", n)
| Block b -> print_block b n p
| IfElse cond true_code false_code ->
let n1 = n in
let n2 = n + 1 in
let cmp = print_cmp (cmp_not cond) n1 p in
let (true_str, n') = print_code true_code (n + 2) p in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = "L" ^ string_of_int n1 ^ ":\n" in
let (false_str, n') = print_code false_code n' p in
let label2 = "L" ^ string_of_int n2 ^ ":\n" in
(cmp ^ true_str ^ jmp ^ label1 ^ false_str ^ label2, n')
| While cond body ->
let n1 = n in
let n2 = n + 1 in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = p.align() ^ " 16\nL" ^ string_of_int n1 ^ ":\n" in
let (body_str, n') = print_code body (n + 2) p in
let label2 = p.align() ^ " 16\nL" ^ string_of_int n2 ^ ":\n" in
let cmp = print_cmp cond n1 p in
(jmp ^ label1 ^ body_str ^ label2 ^ cmp, n')
let print_header (p:printer) =
print_string (p.header())
let print_proc (name:string) (code:code) (label:int) (p:printer) : FStar.All.ML int =
let proc = p.proc_name name in
let code_str, final_label = print_code code label p in
let ret = p.ret name in
print_string (proc ^ code_str ^ ret);
final_label | false | false | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_footer : p: Vale.X64.Print_s.printer -> FStar.All.ML Prims.unit | [] | Vale.X64.Print_s.print_footer | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | p: Vale.X64.Print_s.printer -> FStar.All.ML Prims.unit | {
"end_col": 27,
"end_line": 299,
"start_col": 2,
"start_line": 299
} |
|
Prims.Tot | val gcc_linux:printer | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let gcc_linux : printer =
let footer () : string = ".section .note.GNU-stack,\"\",%progbits\n" in
{gcc with footer} | val gcc_linux:printer
let gcc_linux:printer = | false | null | false | let footer () : string = ".section .note.GNU-stack,\"\",%progbits\n" in
{ gcc with footer = footer } | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Print_s.Mkprinter",
"Vale.X64.Print_s.__proj__Mkprinter__item__print_reg_name",
"Vale.X64.Print_s.gcc",
"Vale.X64.Print_s.__proj__Mkprinter__item__print_reg32_name",
"Vale.X64.Print_s.__proj__Mkprinter__item__print_small_reg_name",
"Vale.X64.Print_s.__proj__Mkprinter__item__reg_prefix",
"Vale.X64.Print_s.__proj__Mkprinter__item__mem_prefix",
"Vale.X64.Print_s.__proj__Mkprinter__item__maddr",
"Vale.X64.Print_s.__proj__Mkprinter__item__const",
"Vale.X64.Print_s.__proj__Mkprinter__item__ins_name",
"Vale.X64.Print_s.__proj__Mkprinter__item__op_order",
"Vale.X64.Print_s.__proj__Mkprinter__item__align",
"Vale.X64.Print_s.__proj__Mkprinter__item__header",
"Vale.X64.Print_s.__proj__Mkprinter__item__proc_name",
"Vale.X64.Print_s.__proj__Mkprinter__item__ret",
"Vale.X64.Print_s.__proj__Mkprinter__item__sha256rnds2_explicit_xmm0",
"Prims.unit",
"Prims.string"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second
let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs)
let print_ins (ins:ins) (p:printer) : string =
let print_pair (dst src:string) = print_pair dst src p in
let print_op_pair (dst:operand64) (src:operand64) (print_dst:operand64 -> printer -> string) (print_src:operand64 -> printer -> string) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst:operand64) (src:operand64) =
print_op_pair dst src print_operand print_operand
in
let print_shift (dst:operand64) (amount:operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst:operand64) (src:reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst:reg_xmm) (src:reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2:reg_xmm) =
print_pair (print_xmm dst p) (print_xmms src1 src2)
in
let print_vpxor (dst src1:reg_xmm) (src2:operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip:instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
let print_cmp (c:ocmp) (counter:int) (p:printer) : string =
let print_ops (o1:operand64) (o2:operand64) : string =
let first, second = p.op_order (print_operand o1 p) (print_operand o2 p) in
" cmp " ^ first ^ ", " ^ second ^ "\n"
in
match c with
| OEq o1 o2 -> print_ops o1 o2 ^ " je " ^ "L" ^ string_of_int counter ^ "\n"
| ONe o1 o2 -> print_ops o1 o2 ^ " jne "^ "L" ^ string_of_int counter ^ "\n"
| OLe o1 o2 -> print_ops o1 o2 ^ " jbe "^ "L" ^ string_of_int counter ^ "\n"
| OGe o1 o2 -> print_ops o1 o2 ^ " jae "^ "L" ^ string_of_int counter ^ "\n"
| OLt o1 o2 -> print_ops o1 o2 ^ " jb " ^ "L" ^ string_of_int counter ^ "\n"
| OGt o1 o2 -> print_ops o1 o2 ^ " ja " ^ "L" ^ string_of_int counter ^ "\n"
let rec print_block (b:codes) (n:int) (p:printer) : string & int =
match b with
| Nil -> ("", n)
| Ins (Instr _ _ (AnnotateSpace _)) :: tail -> print_block tail n p
| Ins (Instr _ _ (AnnotateGhost _)) :: tail -> print_block tail n p
| head :: tail ->
let (head_str, n') = print_code head n p in
let (rest, n'') = print_block tail n' p in
(head_str ^ rest, n'')
and print_code (c:code) (n:int) (p:printer) : string & int =
match c with
| Ins ins -> (print_ins ins p ^ "\n", n)
| Block b -> print_block b n p
| IfElse cond true_code false_code ->
let n1 = n in
let n2 = n + 1 in
let cmp = print_cmp (cmp_not cond) n1 p in
let (true_str, n') = print_code true_code (n + 2) p in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = "L" ^ string_of_int n1 ^ ":\n" in
let (false_str, n') = print_code false_code n' p in
let label2 = "L" ^ string_of_int n2 ^ ":\n" in
(cmp ^ true_str ^ jmp ^ label1 ^ false_str ^ label2, n')
| While cond body ->
let n1 = n in
let n2 = n + 1 in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = p.align() ^ " 16\nL" ^ string_of_int n1 ^ ":\n" in
let (body_str, n') = print_code body (n + 2) p in
let label2 = p.align() ^ " 16\nL" ^ string_of_int n2 ^ ":\n" in
let cmp = print_cmp cond n1 p in
(jmp ^ label1 ^ body_str ^ label2 ^ cmp, n')
let print_header (p:printer) =
print_string (p.header())
let print_proc (name:string) (code:code) (label:int) (p:printer) : FStar.All.ML int =
let proc = p.proc_name name in
let code_str, final_label = print_code code label p in
let ret = p.ret name in
print_string (proc ^ code_str ^ ret);
final_label
let print_footer (p:printer) =
print_string (p.footer())
(* Concrete printers for MASM and GCC syntax *)
let masm : printer =
let reg_prefix unit = "" in
let mem_prefix (ptr_type:string) = ptr_type ^ " ptr " in
let maddr (base:string) (adj:option(string & string)) (offset:string) =
match adj with
| None -> "[" ^ base ^ " + " ^ offset ^ "]"
| Some (scale, index) -> "[" ^ base ^ " + " ^ scale ^ " * " ^ index ^ " + " ^ offset ^ "]"
in
let const (n:int) = string_of_int n in
let ins_name (name:string) (ops:list operand64) : string = name ^ " " in
let op_order dst src = dst, src in
let align() = "ALIGN" in
let header() = ".code\n" in
let footer() = "end\n" in
let proc_name (name:string) = "ALIGN 16\n" ^ name ^ " proc\n" in
let ret (name:string) = " ret\n" ^ name ^ " endp\n" in
{
print_reg_name = print_reg_name;
print_reg32_name = print_reg32_name;
print_small_reg_name = print_small_reg_name;
reg_prefix = reg_prefix;
mem_prefix = mem_prefix;
maddr = maddr;
const = const;
ins_name = ins_name;
op_order = op_order;
align = align;
header = header;
footer = footer;
proc_name = proc_name;
ret = ret;
sha256rnds2_explicit_xmm0 = (fun unit -> true);
}
let gcc : printer =
let reg_prefix unit = "%" in
let mem_prefix (ptr_type:string) = "" in
let maddr (base:string) (adj:option(string & string)) (offset:string) =
match adj with
| None -> offset ^ "(" ^ base ^ ")"
| Some (scale, index) -> offset ^ " (" ^ base ^ ", " ^ scale ^ ", " ^ index ^ ")"
in
let const (n:int) = "$" ^ string_of_int n in
let rec ins_name (name:string) (ops:list operand64) : string =
match ops with
| Nil -> name ^ " "
| OMem _ :: _ -> name ^ "q "
| _ :: tail -> ins_name name tail
in
let op_order dst src = src, dst in
let align() = ".balign" in
let header() = ".text\n" in
let footer() = "\n" in
let proc_name (name:string) = ".global " ^ name ^ "\n" ^ name ^ ":\n" in
let ret (name:string) = " ret\n\n" in
{
print_reg_name = print_reg_name;
print_reg32_name = print_reg32_name;
print_small_reg_name = print_small_reg_name;
reg_prefix = reg_prefix;
mem_prefix = mem_prefix;
maddr = maddr;
const = const;
ins_name = ins_name;
op_order = op_order;
align = align;
header = header;
footer = footer;
proc_name = proc_name;
ret = ret;
sha256rnds2_explicit_xmm0 = (fun unit -> false);
} | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val gcc_linux:printer | [] | Vale.X64.Print_s.gcc_linux | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | Vale.X64.Print_s.printer | {
"end_col": 19,
"end_line": 379,
"start_col": 25,
"start_line": 377
} |
FStar.All.ML | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_header (p:printer) =
print_string (p.header()) | let print_header (p: printer) = | true | null | false | print_string (p.header ()) | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"ml"
] | [
"Vale.X64.Print_s.printer",
"FStar.IO.print_string",
"Vale.X64.Print_s.__proj__Mkprinter__item__header",
"Prims.unit"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second
let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs)
let print_ins (ins:ins) (p:printer) : string =
let print_pair (dst src:string) = print_pair dst src p in
let print_op_pair (dst:operand64) (src:operand64) (print_dst:operand64 -> printer -> string) (print_src:operand64 -> printer -> string) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst:operand64) (src:operand64) =
print_op_pair dst src print_operand print_operand
in
let print_shift (dst:operand64) (amount:operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst:operand64) (src:reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst:reg_xmm) (src:reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2:reg_xmm) =
print_pair (print_xmm dst p) (print_xmms src1 src2)
in
let print_vpxor (dst src1:reg_xmm) (src2:operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip:instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
let print_cmp (c:ocmp) (counter:int) (p:printer) : string =
let print_ops (o1:operand64) (o2:operand64) : string =
let first, second = p.op_order (print_operand o1 p) (print_operand o2 p) in
" cmp " ^ first ^ ", " ^ second ^ "\n"
in
match c with
| OEq o1 o2 -> print_ops o1 o2 ^ " je " ^ "L" ^ string_of_int counter ^ "\n"
| ONe o1 o2 -> print_ops o1 o2 ^ " jne "^ "L" ^ string_of_int counter ^ "\n"
| OLe o1 o2 -> print_ops o1 o2 ^ " jbe "^ "L" ^ string_of_int counter ^ "\n"
| OGe o1 o2 -> print_ops o1 o2 ^ " jae "^ "L" ^ string_of_int counter ^ "\n"
| OLt o1 o2 -> print_ops o1 o2 ^ " jb " ^ "L" ^ string_of_int counter ^ "\n"
| OGt o1 o2 -> print_ops o1 o2 ^ " ja " ^ "L" ^ string_of_int counter ^ "\n"
let rec print_block (b:codes) (n:int) (p:printer) : string & int =
match b with
| Nil -> ("", n)
| Ins (Instr _ _ (AnnotateSpace _)) :: tail -> print_block tail n p
| Ins (Instr _ _ (AnnotateGhost _)) :: tail -> print_block tail n p
| head :: tail ->
let (head_str, n') = print_code head n p in
let (rest, n'') = print_block tail n' p in
(head_str ^ rest, n'')
and print_code (c:code) (n:int) (p:printer) : string & int =
match c with
| Ins ins -> (print_ins ins p ^ "\n", n)
| Block b -> print_block b n p
| IfElse cond true_code false_code ->
let n1 = n in
let n2 = n + 1 in
let cmp = print_cmp (cmp_not cond) n1 p in
let (true_str, n') = print_code true_code (n + 2) p in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = "L" ^ string_of_int n1 ^ ":\n" in
let (false_str, n') = print_code false_code n' p in
let label2 = "L" ^ string_of_int n2 ^ ":\n" in
(cmp ^ true_str ^ jmp ^ label1 ^ false_str ^ label2, n')
| While cond body ->
let n1 = n in
let n2 = n + 1 in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = p.align() ^ " 16\nL" ^ string_of_int n1 ^ ":\n" in
let (body_str, n') = print_code body (n + 2) p in
let label2 = p.align() ^ " 16\nL" ^ string_of_int n2 ^ ":\n" in
let cmp = print_cmp cond n1 p in
(jmp ^ label1 ^ body_str ^ label2 ^ cmp, n') | false | false | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_header : p: Vale.X64.Print_s.printer -> FStar.All.ML Prims.unit | [] | Vale.X64.Print_s.print_header | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | p: Vale.X64.Print_s.printer -> FStar.All.ML Prims.unit | {
"end_col": 27,
"end_line": 289,
"start_col": 2,
"start_line": 289
} |
|
Prims.Tot | val print_reg_int (r: reg) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!" | val print_reg_int (r: reg) (p: printer) : string
let print_reg_int (r: reg) (p: printer) : string = | false | null | false | match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!" | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.reg",
"Vale.X64.Print_s.printer",
"Vale.X64.Machine_s.reg_id",
"Vale.X64.Print_s.print_reg64",
"Prims.string"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64 | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_reg_int (r: reg) (p: printer) : string | [] | Vale.X64.Print_s.print_reg_int | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.X64.Machine_s.reg -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 43,
"end_line": 94,
"start_col": 2,
"start_line": 92
} |
Prims.Tot | val print_reg_name (r: reg_64) : string | [
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15" | val print_reg_name (r: reg_64) : string
let print_reg_name (r: reg_64) : string = | false | null | false | match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15" | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.reg_64",
"Prims.string"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
} | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_reg_name (r: reg_64) : string | [] | Vale.X64.Print_s.print_reg_name | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.X64.Machine_s.reg_64 -> Prims.string | {
"end_col": 15,
"end_line": 48,
"start_col": 2,
"start_line": 32
} |
Prims.Tot | val masm:printer | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let masm : printer =
let reg_prefix unit = "" in
let mem_prefix (ptr_type:string) = ptr_type ^ " ptr " in
let maddr (base:string) (adj:option(string & string)) (offset:string) =
match adj with
| None -> "[" ^ base ^ " + " ^ offset ^ "]"
| Some (scale, index) -> "[" ^ base ^ " + " ^ scale ^ " * " ^ index ^ " + " ^ offset ^ "]"
in
let const (n:int) = string_of_int n in
let ins_name (name:string) (ops:list operand64) : string = name ^ " " in
let op_order dst src = dst, src in
let align() = "ALIGN" in
let header() = ".code\n" in
let footer() = "end\n" in
let proc_name (name:string) = "ALIGN 16\n" ^ name ^ " proc\n" in
let ret (name:string) = " ret\n" ^ name ^ " endp\n" in
{
print_reg_name = print_reg_name;
print_reg32_name = print_reg32_name;
print_small_reg_name = print_small_reg_name;
reg_prefix = reg_prefix;
mem_prefix = mem_prefix;
maddr = maddr;
const = const;
ins_name = ins_name;
op_order = op_order;
align = align;
header = header;
footer = footer;
proc_name = proc_name;
ret = ret;
sha256rnds2_explicit_xmm0 = (fun unit -> true);
} | val masm:printer
let masm:printer = | false | null | false | let reg_prefix unit = "" in
let mem_prefix (ptr_type: string) = ptr_type ^ " ptr " in
let maddr (base: string) (adj: option (string & string)) (offset: string) =
match adj with
| None -> "[" ^ base ^ " + " ^ offset ^ "]"
| Some (scale, index) -> "[" ^ base ^ " + " ^ scale ^ " * " ^ index ^ " + " ^ offset ^ "]"
in
let const (n: int) = string_of_int n in
let ins_name (name: string) (ops: list operand64) : string = name ^ " " in
let op_order dst src = dst, src in
let align () = "ALIGN" in
let header () = ".code\n" in
let footer () = "end\n" in
let proc_name (name: string) = "ALIGN 16\n" ^ name ^ " proc\n" in
let ret (name: string) = " ret\n" ^ name ^ " endp\n" in
{
print_reg_name = print_reg_name;
print_reg32_name = print_reg32_name;
print_small_reg_name = print_small_reg_name;
reg_prefix = reg_prefix;
mem_prefix = mem_prefix;
maddr = maddr;
const = const;
ins_name = ins_name;
op_order = op_order;
align = align;
header = header;
footer = footer;
proc_name = proc_name;
ret = ret;
sha256rnds2_explicit_xmm0 = (fun unit -> true)
} | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Print_s.Mkprinter",
"Vale.X64.Print_s.print_reg_name",
"Vale.X64.Print_s.print_reg32_name",
"Vale.X64.Print_s.print_small_reg_name",
"Prims.unit",
"Prims.bool",
"Prims.string",
"Prims.op_Hat",
"FStar.Pervasives.Native.tuple2",
"FStar.Pervasives.Native.Mktuple2",
"Prims.list",
"Vale.X64.Machine_s.operand64",
"Prims.int",
"Prims.string_of_int",
"FStar.Pervasives.Native.option"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second
let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs)
let print_ins (ins:ins) (p:printer) : string =
let print_pair (dst src:string) = print_pair dst src p in
let print_op_pair (dst:operand64) (src:operand64) (print_dst:operand64 -> printer -> string) (print_src:operand64 -> printer -> string) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst:operand64) (src:operand64) =
print_op_pair dst src print_operand print_operand
in
let print_shift (dst:operand64) (amount:operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst:operand64) (src:reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst:reg_xmm) (src:reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2:reg_xmm) =
print_pair (print_xmm dst p) (print_xmms src1 src2)
in
let print_vpxor (dst src1:reg_xmm) (src2:operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip:instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
let print_cmp (c:ocmp) (counter:int) (p:printer) : string =
let print_ops (o1:operand64) (o2:operand64) : string =
let first, second = p.op_order (print_operand o1 p) (print_operand o2 p) in
" cmp " ^ first ^ ", " ^ second ^ "\n"
in
match c with
| OEq o1 o2 -> print_ops o1 o2 ^ " je " ^ "L" ^ string_of_int counter ^ "\n"
| ONe o1 o2 -> print_ops o1 o2 ^ " jne "^ "L" ^ string_of_int counter ^ "\n"
| OLe o1 o2 -> print_ops o1 o2 ^ " jbe "^ "L" ^ string_of_int counter ^ "\n"
| OGe o1 o2 -> print_ops o1 o2 ^ " jae "^ "L" ^ string_of_int counter ^ "\n"
| OLt o1 o2 -> print_ops o1 o2 ^ " jb " ^ "L" ^ string_of_int counter ^ "\n"
| OGt o1 o2 -> print_ops o1 o2 ^ " ja " ^ "L" ^ string_of_int counter ^ "\n"
let rec print_block (b:codes) (n:int) (p:printer) : string & int =
match b with
| Nil -> ("", n)
| Ins (Instr _ _ (AnnotateSpace _)) :: tail -> print_block tail n p
| Ins (Instr _ _ (AnnotateGhost _)) :: tail -> print_block tail n p
| head :: tail ->
let (head_str, n') = print_code head n p in
let (rest, n'') = print_block tail n' p in
(head_str ^ rest, n'')
and print_code (c:code) (n:int) (p:printer) : string & int =
match c with
| Ins ins -> (print_ins ins p ^ "\n", n)
| Block b -> print_block b n p
| IfElse cond true_code false_code ->
let n1 = n in
let n2 = n + 1 in
let cmp = print_cmp (cmp_not cond) n1 p in
let (true_str, n') = print_code true_code (n + 2) p in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = "L" ^ string_of_int n1 ^ ":\n" in
let (false_str, n') = print_code false_code n' p in
let label2 = "L" ^ string_of_int n2 ^ ":\n" in
(cmp ^ true_str ^ jmp ^ label1 ^ false_str ^ label2, n')
| While cond body ->
let n1 = n in
let n2 = n + 1 in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = p.align() ^ " 16\nL" ^ string_of_int n1 ^ ":\n" in
let (body_str, n') = print_code body (n + 2) p in
let label2 = p.align() ^ " 16\nL" ^ string_of_int n2 ^ ":\n" in
let cmp = print_cmp cond n1 p in
(jmp ^ label1 ^ body_str ^ label2 ^ cmp, n')
let print_header (p:printer) =
print_string (p.header())
let print_proc (name:string) (code:code) (label:int) (p:printer) : FStar.All.ML int =
let proc = p.proc_name name in
let code_str, final_label = print_code code label p in
let ret = p.ret name in
print_string (proc ^ code_str ^ ret);
final_label
let print_footer (p:printer) =
print_string (p.footer()) | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val masm:printer | [] | Vale.X64.Print_s.masm | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | Vale.X64.Print_s.printer | {
"end_col": 3,
"end_line": 335,
"start_col": 20,
"start_line": 303
} |
Prims.Tot | val print_small_operand (o: operand64) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl." | val print_small_operand (o: operand64) (p: printer) : string
let print_small_operand (o: operand64) (p: printer) : string = | false | null | false | match o with
| OConst n -> if n < 64 then p.const n else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl." | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.operand64",
"Vale.X64.Print_s.printer",
"Vale.X64.Machine_s.nat64",
"Prims.op_LessThan",
"Vale.X64.Print_s.__proj__Mkprinter__item__const",
"Prims.bool",
"Prims.op_Hat",
"Prims.string_of_int",
"Prims.string",
"Vale.X64.Machine_s.reg_64",
"Vale.X64.Print_s.print_small_reg",
"Vale.X64.Machine_s.operand"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_small_operand (o: operand64) (p: printer) : string | [] | Vale.X64.Print_s.print_small_operand | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | o: Vale.X64.Machine_s.operand64 -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 68,
"end_line": 118,
"start_col": 2,
"start_line": 113
} |
Prims.Tot | val print_shift_operand (o: operand64) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl." | val print_shift_operand (o: operand64) (p: printer) : string
let print_shift_operand (o: operand64) (p: printer) : string = | false | null | false | match o with
| OConst n ->
if n < 64
then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl." | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.operand64",
"Vale.X64.Print_s.printer",
"Vale.X64.Machine_s.nat64",
"Prims.op_LessThan",
"Vale.X64.Print_s.__proj__Mkprinter__item__const",
"Prims.bool",
"Prims.op_Hat",
"Prims.string_of_int",
"Prims.string",
"Vale.X64.Machine_s.reg_64",
"Vale.X64.Print_s.print_small_reg",
"Vale.X64.Machine_s.__proj__OReg__item__r",
"Vale.X64.Machine_s.operand"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_shift_operand (o: operand64) (p: printer) : string | [] | Vale.X64.Print_s.print_shift_operand | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | o: Vale.X64.Machine_s.operand64 -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 65,
"end_line": 140,
"start_col": 2,
"start_line": 135
} |
Prims.Tot | val print_operand (o: operand64) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p | val print_operand (o: operand64) (p: printer) : string
let print_operand (o: operand64) (p: printer) : string = | false | null | false | match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.operand64",
"Vale.X64.Print_s.printer",
"Vale.X64.Machine_s.nat64",
"Prims.op_AmpAmp",
"Prims.op_LessThanOrEqual",
"Prims.op_LessThan",
"Vale.X64.Machine_s.pow2_64",
"Vale.X64.Print_s.__proj__Mkprinter__item__const",
"Prims.bool",
"Prims.op_Hat",
"Prims.string_of_int",
"Prims.string",
"Vale.X64.Machine_s.reg_64",
"Vale.X64.Print_s.print_reg64",
"Vale.X64.Machine_s.maddr",
"Vale.Arch.HeapTypes_s.taint",
"Vale.X64.Print_s.print_maddr",
"Vale.X64.Print_s.print_reg_int"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!" | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_operand (o: operand64) (p: printer) : string | [] | Vale.X64.Print_s.print_operand | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | o: Vale.X64.Machine_s.operand64 -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 72,
"end_line": 102,
"start_col": 2,
"start_line": 97
} |
Prims.Tot | val print_maddr (m: maddr) (ptr_type: string) (reg_printer: (reg -> printer -> string)) (p: printer)
: string | [
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
) | val print_maddr (m: maddr) (ptr_type: string) (reg_printer: (reg -> printer -> string)) (p: printer)
: string
let print_maddr (m: maddr) (ptr_type: string) (reg_printer: (reg -> printer -> string)) (p: printer)
: string = | false | null | false | p.mem_prefix ptr_type ^
(match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)) | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.maddr",
"Prims.string",
"Vale.X64.Machine_s.reg",
"Vale.X64.Print_s.printer",
"Prims.op_Hat",
"Vale.X64.Print_s.__proj__Mkprinter__item__mem_prefix",
"Prims.int",
"Vale.X64.Print_s.__proj__Mkprinter__item__const",
"Vale.X64.Print_s.__proj__Mkprinter__item__maddr",
"FStar.Pervasives.Native.None",
"FStar.Pervasives.Native.tuple2",
"Prims.string_of_int",
"FStar.Pervasives.Native.Some",
"FStar.Pervasives.Native.Mktuple2"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_maddr (m: maddr) (ptr_type: string) (reg_printer: (reg -> printer -> string)) (p: printer)
: string | [] | Vale.X64.Print_s.print_maddr | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
m: Vale.X64.Machine_s.maddr ->
ptr_type: Prims.string ->
reg_printer: (_: Vale.X64.Machine_s.reg -> _: Vale.X64.Print_s.printer -> Prims.string) ->
p: Vale.X64.Print_s.printer
-> Prims.string | {
"end_col": 3,
"end_line": 88,
"start_col": 2,
"start_line": 80
} |
Prims.Tot | val print_cmp (c: ocmp) (counter: int) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_cmp (c:ocmp) (counter:int) (p:printer) : string =
let print_ops (o1:operand64) (o2:operand64) : string =
let first, second = p.op_order (print_operand o1 p) (print_operand o2 p) in
" cmp " ^ first ^ ", " ^ second ^ "\n"
in
match c with
| OEq o1 o2 -> print_ops o1 o2 ^ " je " ^ "L" ^ string_of_int counter ^ "\n"
| ONe o1 o2 -> print_ops o1 o2 ^ " jne "^ "L" ^ string_of_int counter ^ "\n"
| OLe o1 o2 -> print_ops o1 o2 ^ " jbe "^ "L" ^ string_of_int counter ^ "\n"
| OGe o1 o2 -> print_ops o1 o2 ^ " jae "^ "L" ^ string_of_int counter ^ "\n"
| OLt o1 o2 -> print_ops o1 o2 ^ " jb " ^ "L" ^ string_of_int counter ^ "\n"
| OGt o1 o2 -> print_ops o1 o2 ^ " ja " ^ "L" ^ string_of_int counter ^ "\n" | val print_cmp (c: ocmp) (counter: int) (p: printer) : string
let print_cmp (c: ocmp) (counter: int) (p: printer) : string = | false | null | false | let print_ops (o1 o2: operand64) : string =
let first, second = p.op_order (print_operand o1 p) (print_operand o2 p) in
" cmp " ^ first ^ ", " ^ second ^ "\n"
in
match c with
| OEq o1 o2 -> print_ops o1 o2 ^ " je " ^ "L" ^ string_of_int counter ^ "\n"
| ONe o1 o2 -> print_ops o1 o2 ^ " jne " ^ "L" ^ string_of_int counter ^ "\n"
| OLe o1 o2 -> print_ops o1 o2 ^ " jbe " ^ "L" ^ string_of_int counter ^ "\n"
| OGe o1 o2 -> print_ops o1 o2 ^ " jae " ^ "L" ^ string_of_int counter ^ "\n"
| OLt o1 o2 -> print_ops o1 o2 ^ " jb " ^ "L" ^ string_of_int counter ^ "\n"
| OGt o1 o2 -> print_ops o1 o2 ^ " ja " ^ "L" ^ string_of_int counter ^ "\n" | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_Semantics_s.ocmp",
"Prims.int",
"Vale.X64.Print_s.printer",
"Vale.X64.Machine_s.operand64",
"Prims.b2t",
"Prims.op_Negation",
"Prims.op_BarBar",
"Vale.X64.Machine_s.uu___is_OMem",
"Vale.X64.Machine_s.nat64",
"Vale.X64.Machine_s.reg_64",
"Vale.X64.Machine_s.uu___is_OStack",
"Prims.op_Hat",
"Prims.string_of_int",
"Prims.string",
"FStar.Pervasives.Native.tuple2",
"Vale.X64.Print_s.__proj__Mkprinter__item__op_order",
"Vale.X64.Print_s.print_operand"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second
let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs)
let print_ins (ins:ins) (p:printer) : string =
let print_pair (dst src:string) = print_pair dst src p in
let print_op_pair (dst:operand64) (src:operand64) (print_dst:operand64 -> printer -> string) (print_src:operand64 -> printer -> string) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst:operand64) (src:operand64) =
print_op_pair dst src print_operand print_operand
in
let print_shift (dst:operand64) (amount:operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst:operand64) (src:reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst:reg_xmm) (src:reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2:reg_xmm) =
print_pair (print_xmm dst p) (print_xmms src1 src2)
in
let print_vpxor (dst src1:reg_xmm) (src2:operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip:instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n) | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_cmp (c: ocmp) (counter: int) (p: printer) : string | [] | Vale.X64.Print_s.print_cmp | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | c: Vale.X64.Machine_Semantics_s.ocmp -> counter: Prims.int -> p: Vale.X64.Print_s.printer
-> Prims.string | {
"end_col": 79,
"end_line": 253,
"start_col": 59,
"start_line": 242
} |
Prims.Tot | val print_operand32 (o: operand64) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p | val print_operand32 (o: operand64) (p: printer) : string
let print_operand32 (o: operand64) (p: printer) : string = | false | null | false | match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.operand64",
"Vale.X64.Print_s.printer",
"Vale.X64.Machine_s.nat64",
"Prims.op_AmpAmp",
"Prims.op_LessThanOrEqual",
"Prims.op_LessThan",
"Vale.X64.Machine_s.pow2_32",
"Vale.X64.Print_s.__proj__Mkprinter__item__const",
"Prims.bool",
"Prims.op_Hat",
"Prims.string_of_int",
"Prims.string",
"Vale.X64.Machine_s.reg_64",
"Vale.X64.Print_s.print_reg32",
"Vale.X64.Machine_s.maddr",
"Vale.Arch.HeapTypes_s.taint",
"Vale.X64.Print_s.print_maddr",
"Vale.X64.Print_s.print_reg_int"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_operand32 (o: operand64) (p: printer) : string | [] | Vale.X64.Print_s.print_operand32 | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | o: Vale.X64.Machine_s.operand64 -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 72,
"end_line": 110,
"start_col": 2,
"start_line": 105
} |
Prims.Tot | val cmp_not (o: ocmp) : ocmp | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2 | val cmp_not (o: ocmp) : ocmp
let cmp_not (o: ocmp) : ocmp = | false | null | false | match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2 | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_Semantics_s.ocmp",
"Vale.X64.Machine_s.operand64",
"Prims.b2t",
"Prims.op_Negation",
"Prims.op_BarBar",
"Vale.X64.Machine_s.uu___is_OMem",
"Vale.X64.Machine_s.nat64",
"Vale.X64.Machine_s.reg_64",
"Vale.X64.Machine_s.uu___is_OStack",
"Vale.X64.Bytes_Code_s.ONe",
"Vale.X64.Bytes_Code_s.OEq",
"Vale.X64.Bytes_Code_s.OGt",
"Vale.X64.Bytes_Code_s.OLt",
"Vale.X64.Bytes_Code_s.OGe",
"Vale.X64.Bytes_Code_s.OLe"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl." | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val cmp_not (o: ocmp) : ocmp | [] | Vale.X64.Print_s.cmp_not | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | o: Vale.X64.Machine_Semantics_s.ocmp -> Vale.X64.Machine_Semantics_s.ocmp | {
"end_col": 26,
"end_line": 149,
"start_col": 2,
"start_line": 143
} |
Prims.Tot | val gcc:printer | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let gcc : printer =
let reg_prefix unit = "%" in
let mem_prefix (ptr_type:string) = "" in
let maddr (base:string) (adj:option(string & string)) (offset:string) =
match adj with
| None -> offset ^ "(" ^ base ^ ")"
| Some (scale, index) -> offset ^ " (" ^ base ^ ", " ^ scale ^ ", " ^ index ^ ")"
in
let const (n:int) = "$" ^ string_of_int n in
let rec ins_name (name:string) (ops:list operand64) : string =
match ops with
| Nil -> name ^ " "
| OMem _ :: _ -> name ^ "q "
| _ :: tail -> ins_name name tail
in
let op_order dst src = src, dst in
let align() = ".balign" in
let header() = ".text\n" in
let footer() = "\n" in
let proc_name (name:string) = ".global " ^ name ^ "\n" ^ name ^ ":\n" in
let ret (name:string) = " ret\n\n" in
{
print_reg_name = print_reg_name;
print_reg32_name = print_reg32_name;
print_small_reg_name = print_small_reg_name;
reg_prefix = reg_prefix;
mem_prefix = mem_prefix;
maddr = maddr;
const = const;
ins_name = ins_name;
op_order = op_order;
align = align;
header = header;
footer = footer;
proc_name = proc_name;
ret = ret;
sha256rnds2_explicit_xmm0 = (fun unit -> false);
} | val gcc:printer
let gcc:printer = | false | null | false | let reg_prefix unit = "%" in
let mem_prefix (ptr_type: string) = "" in
let maddr (base: string) (adj: option (string & string)) (offset: string) =
match adj with
| None -> offset ^ "(" ^ base ^ ")"
| Some (scale, index) -> offset ^ " (" ^ base ^ ", " ^ scale ^ ", " ^ index ^ ")"
in
let const (n: int) = "$" ^ string_of_int n in
let rec ins_name (name: string) (ops: list operand64) : string =
match ops with
| Nil -> name ^ " "
| OMem _ :: _ -> name ^ "q "
| _ :: tail -> ins_name name tail
in
let op_order dst src = src, dst in
let align () = ".balign" in
let header () = ".text\n" in
let footer () = "\n" in
let proc_name (name: string) = ".global " ^ name ^ "\n" ^ name ^ ":\n" in
let ret (name: string) = " ret\n\n" in
{
print_reg_name = print_reg_name;
print_reg32_name = print_reg32_name;
print_small_reg_name = print_small_reg_name;
reg_prefix = reg_prefix;
mem_prefix = mem_prefix;
maddr = maddr;
const = const;
ins_name = ins_name;
op_order = op_order;
align = align;
header = header;
footer = footer;
proc_name = proc_name;
ret = ret;
sha256rnds2_explicit_xmm0 = (fun unit -> false)
} | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Print_s.Mkprinter",
"Vale.X64.Print_s.print_reg_name",
"Vale.X64.Print_s.print_reg32_name",
"Vale.X64.Print_s.print_small_reg_name",
"Prims.unit",
"Prims.bool",
"Prims.string",
"Prims.op_Hat",
"FStar.Pervasives.Native.tuple2",
"FStar.Pervasives.Native.Mktuple2",
"Prims.list",
"Vale.X64.Machine_s.operand64",
"Vale.X64.Machine_s.tmaddr",
"Prims.int",
"Prims.string_of_int",
"FStar.Pervasives.Native.option"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second
let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs)
let print_ins (ins:ins) (p:printer) : string =
let print_pair (dst src:string) = print_pair dst src p in
let print_op_pair (dst:operand64) (src:operand64) (print_dst:operand64 -> printer -> string) (print_src:operand64 -> printer -> string) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst:operand64) (src:operand64) =
print_op_pair dst src print_operand print_operand
in
let print_shift (dst:operand64) (amount:operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst:operand64) (src:reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst:reg_xmm) (src:reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2:reg_xmm) =
print_pair (print_xmm dst p) (print_xmms src1 src2)
in
let print_vpxor (dst src1:reg_xmm) (src2:operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip:instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
let print_cmp (c:ocmp) (counter:int) (p:printer) : string =
let print_ops (o1:operand64) (o2:operand64) : string =
let first, second = p.op_order (print_operand o1 p) (print_operand o2 p) in
" cmp " ^ first ^ ", " ^ second ^ "\n"
in
match c with
| OEq o1 o2 -> print_ops o1 o2 ^ " je " ^ "L" ^ string_of_int counter ^ "\n"
| ONe o1 o2 -> print_ops o1 o2 ^ " jne "^ "L" ^ string_of_int counter ^ "\n"
| OLe o1 o2 -> print_ops o1 o2 ^ " jbe "^ "L" ^ string_of_int counter ^ "\n"
| OGe o1 o2 -> print_ops o1 o2 ^ " jae "^ "L" ^ string_of_int counter ^ "\n"
| OLt o1 o2 -> print_ops o1 o2 ^ " jb " ^ "L" ^ string_of_int counter ^ "\n"
| OGt o1 o2 -> print_ops o1 o2 ^ " ja " ^ "L" ^ string_of_int counter ^ "\n"
let rec print_block (b:codes) (n:int) (p:printer) : string & int =
match b with
| Nil -> ("", n)
| Ins (Instr _ _ (AnnotateSpace _)) :: tail -> print_block tail n p
| Ins (Instr _ _ (AnnotateGhost _)) :: tail -> print_block tail n p
| head :: tail ->
let (head_str, n') = print_code head n p in
let (rest, n'') = print_block tail n' p in
(head_str ^ rest, n'')
and print_code (c:code) (n:int) (p:printer) : string & int =
match c with
| Ins ins -> (print_ins ins p ^ "\n", n)
| Block b -> print_block b n p
| IfElse cond true_code false_code ->
let n1 = n in
let n2 = n + 1 in
let cmp = print_cmp (cmp_not cond) n1 p in
let (true_str, n') = print_code true_code (n + 2) p in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = "L" ^ string_of_int n1 ^ ":\n" in
let (false_str, n') = print_code false_code n' p in
let label2 = "L" ^ string_of_int n2 ^ ":\n" in
(cmp ^ true_str ^ jmp ^ label1 ^ false_str ^ label2, n')
| While cond body ->
let n1 = n in
let n2 = n + 1 in
let jmp = " jmp L" ^ string_of_int n2 ^ "\n" in
let label1 = p.align() ^ " 16\nL" ^ string_of_int n1 ^ ":\n" in
let (body_str, n') = print_code body (n + 2) p in
let label2 = p.align() ^ " 16\nL" ^ string_of_int n2 ^ ":\n" in
let cmp = print_cmp cond n1 p in
(jmp ^ label1 ^ body_str ^ label2 ^ cmp, n')
let print_header (p:printer) =
print_string (p.header())
let print_proc (name:string) (code:code) (label:int) (p:printer) : FStar.All.ML int =
let proc = p.proc_name name in
let code_str, final_label = print_code code label p in
let ret = p.ret name in
print_string (proc ^ code_str ^ ret);
final_label
let print_footer (p:printer) =
print_string (p.footer())
(* Concrete printers for MASM and GCC syntax *)
let masm : printer =
let reg_prefix unit = "" in
let mem_prefix (ptr_type:string) = ptr_type ^ " ptr " in
let maddr (base:string) (adj:option(string & string)) (offset:string) =
match adj with
| None -> "[" ^ base ^ " + " ^ offset ^ "]"
| Some (scale, index) -> "[" ^ base ^ " + " ^ scale ^ " * " ^ index ^ " + " ^ offset ^ "]"
in
let const (n:int) = string_of_int n in
let ins_name (name:string) (ops:list operand64) : string = name ^ " " in
let op_order dst src = dst, src in
let align() = "ALIGN" in
let header() = ".code\n" in
let footer() = "end\n" in
let proc_name (name:string) = "ALIGN 16\n" ^ name ^ " proc\n" in
let ret (name:string) = " ret\n" ^ name ^ " endp\n" in
{
print_reg_name = print_reg_name;
print_reg32_name = print_reg32_name;
print_small_reg_name = print_small_reg_name;
reg_prefix = reg_prefix;
mem_prefix = mem_prefix;
maddr = maddr;
const = const;
ins_name = ins_name;
op_order = op_order;
align = align;
header = header;
footer = footer;
proc_name = proc_name;
ret = ret;
sha256rnds2_explicit_xmm0 = (fun unit -> true);
} | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val gcc:printer | [] | Vale.X64.Print_s.gcc | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | Vale.X64.Print_s.printer | {
"end_col": 3,
"end_line": 374,
"start_col": 19,
"start_line": 337
} |
Prims.Tot | val print_mov128_op (o: operand128) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p | val print_mov128_op (o: operand128) (p: printer) : string
let print_mov128_op (o: operand128) (p: printer) : string = | false | null | false | match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_s.operand128",
"Vale.X64.Print_s.printer",
"Vale.X64.Machine_s.quad32",
"Vale.X64.Machine_s.reg_xmm",
"Vale.X64.Print_s.print_xmm",
"Vale.X64.Machine_s.maddr",
"Vale.Arch.HeapTypes_s.taint",
"Vale.X64.Print_s.print_maddr",
"Vale.X64.Print_s.print_reg_int",
"Prims.string"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_mov128_op (o: operand128) (p: printer) : string | [] | Vale.X64.Print_s.print_mov128_op | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | o: Vale.X64.Machine_s.operand128 -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 74,
"end_line": 130,
"start_col": 2,
"start_line": 127
} |
Prims.Tot | val print_ins (ins: ins) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_ins (ins:ins) (p:printer) : string =
let print_pair (dst src:string) = print_pair dst src p in
let print_op_pair (dst:operand64) (src:operand64) (print_dst:operand64 -> printer -> string) (print_src:operand64 -> printer -> string) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst:operand64) (src:operand64) =
print_op_pair dst src print_operand print_operand
in
let print_shift (dst:operand64) (amount:operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst:reg_xmm) (src:operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst:operand64) (src:reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst:reg_xmm) (src:reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2:reg_xmm) =
print_pair (print_xmm dst p) (print_xmms src1 src2)
in
let print_vpxor (dst src1:reg_xmm) (src2:operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip:instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n) | val print_ins (ins: ins) (p: printer) : string
let print_ins (ins: ins) (p: printer) : string = | false | null | false | let print_pair (dst src: string) = print_pair dst src p in
let print_op_pair (dst src: operand64) (print_dst print_src: (operand64 -> printer -> string)) =
print_pair (print_dst dst p) (print_src src p)
in
let print_ops (dst src: operand64) = print_op_pair dst src print_operand print_operand in
let print_shift (dst amount: operand64) =
print_op_pair dst amount print_operand print_shift_operand
in
let print_xmm_op (dst: reg_xmm) (src: operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand src p) in
first ^ ", " ^ second
in
let print_xmm_op32 (dst: reg_xmm) (src: operand64) =
let first, second = p.op_order (print_xmm dst p) (print_operand32 src p) in
first ^ ", " ^ second
in
let print_op_xmm (dst: operand64) (src: reg_xmm) =
let first, second = p.op_order (print_operand dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms (dst src: reg_xmm) =
let first, second = p.op_order (print_xmm dst p) (print_xmm src p) in
first ^ ", " ^ second
in
let print_xmms_3 (dst src1 src2: reg_xmm) = print_pair (print_xmm dst p) (print_xmms src1 src2) in
let print_vpxor (dst src1: reg_xmm) (src2: operand128) =
print_pair (print_xmm dst p) (print_pair (print_xmm src1 p) (print_mov128_op src2 p))
in
let print_instr (ip: instr_print) : string = print_instr ip p in
match ins with
| Instr (InstrTypeRecord i) oprs _ -> print_instr (instr_printer i oprs)
| Push src _ -> p.ins_name " push" [src] ^ print_operand src p
| Pop dst _ -> p.ins_name " pop" [dst] ^ print_operand dst p
| Alloc n -> p.ins_name " sub" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n)
| Dealloc n -> p.ins_name " add" [OReg rRsp; OConst n] ^ print_ops (OReg rRsp) (OConst n) | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Machine_Semantics_s.ins",
"Vale.X64.Print_s.printer",
"Prims.list",
"Vale.X64.Instruction_s.instr_out",
"Vale.X64.Instruction_s.instr_operand",
"Vale.X64.Instruction_s.flag_havoc",
"Vale.X64.Instruction_s.instr_t",
"Vale.X64.Instruction_s.instr_operands_t",
"Vale.X64.Instruction_s.__proj__InstrTypeRecord__item__outs",
"Vale.X64.Instruction_s.InstrTypeRecord",
"Vale.X64.Instruction_s.__proj__InstrTypeRecord__item__args",
"Vale.X64.Machine_Semantics_s.instr_annotation",
"Vale.X64.Instruction_s.instr_printer",
"Vale.X64.Machine_s.operand64",
"Vale.Arch.HeapTypes_s.taint",
"Prims.op_Hat",
"Vale.X64.Print_s.__proj__Mkprinter__item__ins_name",
"Prims.Cons",
"Prims.Nil",
"Vale.X64.Print_s.print_operand",
"Vale.X64.Machine_s.nat64",
"Vale.X64.Machine_s.OReg",
"Vale.X64.Machine_s.reg_64",
"Vale.X64.Machine_s.rRsp",
"Vale.X64.Machine_s.OConst",
"Prims.string",
"Vale.X64.Instruction_s.instr_print",
"Vale.X64.Print_s.print_instr",
"Vale.X64.Machine_s.reg_xmm",
"Vale.X64.Machine_s.operand128",
"Vale.X64.Print_s.print_xmm",
"Vale.X64.Print_s.print_mov128_op",
"FStar.Pervasives.Native.tuple2",
"Vale.X64.Print_s.__proj__Mkprinter__item__op_order",
"Vale.X64.Print_s.print_operand32",
"Vale.X64.Print_s.print_shift_operand",
"Vale.X64.Print_s.print_pair"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second
let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs) | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_ins (ins: ins) (p: printer) : string | [] | Vale.X64.Print_s.print_ins | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ins: Vale.X64.Machine_Semantics_s.ins -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 98,
"end_line": 240,
"start_col": 46,
"start_line": 201
} |
Prims.Tot | val print_instr (ip: instr_print) (p: printer) : string | [
{
"abbrev": false,
"full_module": "FStar.UInt64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.IO",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_Semantics_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Bytes_Code_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Instruction_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.List.Tot",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.X64",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let print_instr (ip:instr_print) (p:printer) : string =
let Print name kind oprs = ip in
let (suffix, oprs) =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs:list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| (P8 o)::oprs -> o::(get_operands oprs)
| (P16 o)::oprs -> o::(get_operands oprs)
| (P32 o)::oprs -> o::(get_operands oprs)
| (P64 o)::oprs -> o::(get_operands oprs)
| _::oprs -> get_operands oprs
in
let (opcode, space) =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po:instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs:list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o::oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs) | val print_instr (ip: instr_print) (p: printer) : string
let print_instr (ip: instr_print) (p: printer) : string = | false | null | false | let Print name kind oprs = ip in
let suffix, oprs =
match kind with
| POpcode -> (false, oprs)
| PSuffix -> (true, oprs)
| PrintPSha256rnds2 ->
(false, (if p.sha256rnds2_explicit_xmm0 () then oprs @ [PXmm (OReg 0)] else oprs))
in
let rec get_operands (oprs: list instr_print_operand) : list operand64 =
match oprs with
| [] -> []
| P8 o :: oprs -> o :: (get_operands oprs)
| P16 o :: oprs -> o :: (get_operands oprs)
| P32 o :: oprs -> o :: (get_operands oprs)
| P64 o :: oprs -> o :: (get_operands oprs)
| _ :: oprs -> get_operands oprs
in
let opcode, space =
match suffix with
| false -> (name, " ")
| true -> (p.ins_name name (get_operands oprs), "")
in
let print_operand (po: instr_print_operand) : string =
match po with
| P8 o -> print_small_operand o p
| P16 o -> "!!! UNSUPPORTED OPERAND !!!"
| P32 o -> print_operand32 o p
| P64 o -> print_operand o p
| PXmm o -> print_mov128_op o p
| PImm i -> p.const i
| PShift o -> print_shift_operand o p
in
let rec print_operands (oprs: list instr_print_operand) : string =
match oprs with
| [] -> ""
| [o] -> print_operand o
| o :: oprs -> print_pair (print_operand o) (print_operands oprs) p
in
match oprs with
| [] -> " " ^ opcode
| _ -> " " ^ opcode ^ space ^ (print_operands oprs) | {
"checked_file": "Vale.X64.Print_s.fst.checked",
"dependencies": [
"Vale.X64.Machine_Semantics_s.fst.checked",
"Vale.X64.Machine_s.fst.checked",
"Vale.X64.Instruction_s.fsti.checked",
"Vale.X64.Bytes_Code_s.fst.checked",
"prims.fst.checked",
"FStar.UInt64.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.List.Tot.fst.checked",
"FStar.IO.fst.checked",
"FStar.All.fst.checked"
],
"interface_file": false,
"source_file": "Vale.X64.Print_s.fst"
} | [
"total"
] | [
"Vale.X64.Instruction_s.instr_print",
"Vale.X64.Print_s.printer",
"Prims.string",
"Vale.X64.Instruction_s.instr_print_kind",
"Prims.list",
"Vale.X64.Instruction_s.instr_print_operand",
"Prims.bool",
"Prims.op_Hat",
"Vale.X64.Print_s.print_pair",
"Vale.X64.Machine_s.operand64",
"Vale.X64.Print_s.print_small_operand",
"Vale.X64.Print_s.print_operand32",
"Vale.X64.Print_s.print_operand",
"Vale.X64.Machine_s.operand128",
"Vale.X64.Print_s.print_mov128_op",
"Prims.int",
"Vale.X64.Print_s.__proj__Mkprinter__item__const",
"Vale.X64.Print_s.print_shift_operand",
"FStar.Pervasives.Native.tuple2",
"FStar.Pervasives.Native.Mktuple2",
"Vale.X64.Print_s.__proj__Mkprinter__item__ins_name",
"Prims.Nil",
"Prims.Cons",
"Vale.X64.Print_s.__proj__Mkprinter__item__sha256rnds2_explicit_xmm0",
"FStar.List.Tot.Base.op_At",
"Vale.X64.Instruction_s.PXmm",
"Vale.X64.Machine_s.OReg",
"Vale.X64.Machine_s.quad32",
"Vale.X64.Machine_s.reg_xmm"
] | [] | module Vale.X64.Print_s
open FStar.Mul
open FStar.List.Tot
// Trusted code for producing assembly code
open Vale.X64.Machine_s
open Vale.X64.Instruction_s
open Vale.X64.Bytes_Code_s
open Vale.X64.Machine_Semantics_s
open FStar.IO
noeq type printer = {
print_reg_name: reg_64 -> string;
print_reg32_name: reg_64 -> string;
print_small_reg_name: reg_64 -> string;
reg_prefix : unit -> string;
mem_prefix : string -> string;
maddr : string -> option (string & string) -> string -> string;
const : int -> string;
ins_name : string -> list operand64 -> string;
op_order : string -> string -> string & string;
align : unit -> string;
header : unit -> string;
footer : unit -> string;
proc_name : string -> string;
ret : string -> string;
sha256rnds2_explicit_xmm0: unit -> bool;
}
let print_reg_name (r:reg_64) : string =
match r with
| 0 -> "rax"
| 1 -> "rbx"
| 2 -> "rcx"
| 3 -> "rdx"
| 4 -> "rsi"
| 5 -> "rdi"
| 6 -> "rbp"
| 7 -> "rsp"
| 8 -> "r8"
| 9 -> "r9"
| 10 -> "r10"
| 11 -> "r11"
| 12 -> "r12"
| 13 -> "r13"
| 14 -> "r14"
| 15 -> "r15"
let print_reg32_name (r:reg_64) : string =
match r with
| 0 -> "eax"
| 1 -> "ebx"
| 2 -> "ecx"
| 3 -> "edx"
| 4 -> "esi"
| 5 -> "edi"
| 6 -> "ebp"
| 7 -> "esp"
| _ -> print_reg_name r ^ "d"
let print_small_reg_name (r:reg_64) : string =
match r with
| 0 -> "al"
| 1 -> "bl"
| 2 -> "cl"
| 3 -> "dl"
| _ -> " !!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_reg64 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg_name r
let print_reg32 (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_reg32_name r
let print_small_reg (r:reg_64) (p:printer) : string =
p.reg_prefix() ^ p.print_small_reg_name r
let print_maddr (m:maddr) (ptr_type:string) (reg_printer:reg -> printer -> string) (p:printer) : string =
p.mem_prefix ptr_type ^
( match m with
| MConst n -> p.const n
| MReg r offset -> p.maddr (reg_printer r p) None (string_of_int offset)
| MIndex base scale index offset ->
p.maddr (reg_printer base p)
(Some (string_of_int scale, reg_printer index p))
(string_of_int offset)
)
open FStar.UInt64
let print_reg_int (r:reg) (p:printer) : string =
match r with
| Reg 0 r -> print_reg64 r p
| _ -> "!!! INVALID integer register !!!"
let print_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg64 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "qword" print_reg_int p
let print_operand32 (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if 0 <= n && n < pow2_32 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!"
| OReg r -> print_reg32 r p
| OMem (m, _) | OStack (m, _) -> print_maddr m "dword" print_reg_int p
let print_small_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID constant: " ^ string_of_int n ^ " !!!!"
| OReg r -> print_small_reg r p
| _ -> "!!! INVALID small operand !!! Expected al, bl, cl, or dl."
let print_imm8 (i:int) (p:printer) : string =
p.const i
let print_xmm (x:reg_xmm) (p:printer) : string =
p.reg_prefix () ^ "xmm" ^ string_of_int x
let print_mov128_op (o:operand128) (p:printer) : string =
match o with
| OConst _ -> "!!! INVALID xmm constants not allowed !!!"
| OReg x -> print_xmm x p
| OMem (m, _) | OStack (m, _) -> print_maddr m "xmmword" print_reg_int p
assume val print_any: 'a -> string
let print_shift_operand (o:operand64) (p:printer) : string =
match o with
| OConst n ->
if n < 64 then p.const n
else "!!! INVALID shift operand: " ^ string_of_int n ^ " is too large !!!"
| OReg rRcx -> print_small_reg (OReg?.r o) p
| _ -> "!!! INVALID shift operand !!! Expected constant or cl."
let cmp_not(o:ocmp) : ocmp =
match o with
| OEq o1 o2 -> ONe o1 o2
| ONe o1 o2 -> OEq o1 o2
| OLe o1 o2 -> OGt o1 o2
| OGe o1 o2 -> OLt o1 o2
| OLt o1 o2 -> OGe o1 o2
| OGt o1 o2 -> OLe o1 o2
// Sanity check
let _ = assert (forall o . o == cmp_not (cmp_not o))
let print_pair (dst src:string) (p:printer) : string =
let first, second = p.op_order dst src in
first ^ ", " ^ second | false | true | Vale.X64.Print_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val print_instr (ip: instr_print) (p: printer) : string | [] | Vale.X64.Print_s.print_instr | {
"file_name": "vale/specs/hardware/Vale.X64.Print_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ip: Vale.X64.Instruction_s.instr_print -> p: Vale.X64.Print_s.printer -> Prims.string | {
"end_col": 54,
"end_line": 199,
"start_col": 55,
"start_line": 158
} |
Prims.Tot | val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res | val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a = | false | null | false | let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"total"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Hacl.Spec.Bignum.Base.carry",
"FStar.Pervasives.Native.tuple2",
"Hacl.Spec.Bignum.Addition.bn_add",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag",
"Lib.LoopCombinators.repeati",
"Hacl.Spec.Bignum.Squaring.bn_sqr_f",
"Lib.Sequence.lseq",
"Hacl.Spec.Bignum.Definitions.limb",
"Prims.l_and",
"Prims.eq2",
"FStar.Seq.Base.seq",
"Lib.Sequence.to_seq",
"FStar.Seq.Base.create",
"Lib.IntTypes.mk_int",
"Lib.IntTypes.SEC",
"Prims.l_Forall",
"Prims.nat",
"Prims.l_imp",
"Prims.op_LessThan",
"Lib.Sequence.index",
"Lib.Sequence.create",
"Lib.IntTypes.uint"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen
-> Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen) | {
"end_col": 5,
"end_line": 64,
"start_col": 23,
"start_line": 58
} |
FStar.Pervasives.Lemma | val bn_sqr_lemma: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_sqr a == SM.bn_mul a a /\ bn_v (bn_sqr a) == bn_v a * bn_v a) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_lemma #t #aLen a =
let res = bn_sqr a in
bn_sqr_lemma_eval a;
assert (bn_v res == bn_v a * bn_v a);
let res' = SM.bn_mul a a in
SM.bn_mul_lemma a a;
assert (bn_v res' == bn_v a * bn_v a);
bn_eval_inj (aLen + aLen) res res';
assert (bn_sqr a == SM.bn_mul a a) | val bn_sqr_lemma: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_sqr a == SM.bn_mul a a /\ bn_v (bn_sqr a) == bn_v a * bn_v a)
let bn_sqr_lemma #t #aLen a = | false | null | true | let res = bn_sqr a in
bn_sqr_lemma_eval a;
assert (bn_v res == bn_v a * bn_v a);
let res' = SM.bn_mul a a in
SM.bn_mul_lemma a a;
assert (bn_v res' == bn_v a * bn_v a);
bn_eval_inj (aLen + aLen) res res';
assert (bn_sqr a == SM.bn_mul a a) | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims._assert",
"Prims.eq2",
"Hacl.Spec.Bignum.Squaring.bn_sqr",
"Hacl.Spec.Bignum.Multiplication.bn_mul",
"Prims.unit",
"Hacl.Spec.Bignum.Definitions.bn_eval_inj",
"Prims.int",
"Hacl.Spec.Bignum.Definitions.bn_v",
"FStar.Mul.op_Star",
"Hacl.Spec.Bignum.Multiplication.bn_mul_lemma",
"Hacl.Spec.Bignum.Squaring.bn_sqr_lemma_eval"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k))
val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_sqr_diag_loop_step #t #aLen a i =
let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
//assert (eval_ (aLen + aLen) acc1 (i + i) ==
//eval_ (aLen + aLen) acc1 (i + i - 2) + v acc1.[i + i - 2] * (pow2 (p * (i + i - 2))) + v acc1.[i + i - 1] * pow2 (p * (i + i - 1)));
calc (==) {
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * pow2 (pbits * (i + i - 1));
(==) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
(==) { Math.Lemmas.paren_mul_right (v acc1.[i + i - 1]) (pow2 pbits) (pow2 (pbits * (i + i - 2))) }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + (v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { Math.Lemmas.distributivity_add_left (v acc1.[i + i - 2]) (v acc1.[i + i - 1] * pow2 pbits) (pow2 (pbits * (i + i - 2))) }
(v acc1.[i + i - 2] + v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { bn_sqr_diag_lemma a i }
v a.[i - 1] * v a.[i - 1] * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * (pow2 (pbits * (i + i - 2))))
val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i)
let bn_sqr_f_lemma #t #aLen a j acc i =
let resLen = aLen + aLen in
let c, acc' = SM.bn_mul1_add_in_place #t #j (sub a 0 j) a.[j] (sub acc j j) in
let acc1 = update_sub acc j j acc' in
assert (index acc1 i == index acc i);
let res = acc1.[j + j] <- c in
assert (index res i == index acc i);
SM.bn_mul1_lshift_add_lemma #t #j #resLen (sub a 0 j) a.[j] j acc;
bn_eval_extensionality_j acc1 res (j + j);
bn_eval_unfold_i res (j + j + 1);
bn_eval_extensionality_j a (sub a 0 j) j
val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i)))
let bn_sqr_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_f a) acc0;
repeati_inductive #(lbignum t (aLen + aLen)) k
(fun i acci ->
acci == repeati i (bn_sqr_f a) acc0 /\
(forall (i0:nat{i + i < i0 /\ i0 < aLen + aLen}). Seq.index acci i0 == Seq.index acc0 i0))
(fun i acci ->
unfold_repeati k (bn_sqr_f a) acc0 i;
let acc1 = bn_sqr_f a i acci in
assert (acc1 == repeati (i + 1) (bn_sqr_f a) acc0);
Classical.forall_intro (bn_sqr_f_lemma a i acci);
assert (forall (i0:nat{i + i + 2 < i0 /\ i0 < aLen + aLen}). Seq.index acc1 i0 == Seq.index acc0 i0);
acc1)
acc0
val bn_sqr_tail:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_f a) acc0 in
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index acc i == uint #t 0))
let bn_sqr_tail #t #aLen a k =
let _ = bn_sqr_inductive a k in ()
val square_of_sum: a:nat -> b:nat -> Lemma ((a + b) * (a + b) == a * a + 2 * a * b + b * b)
let square_of_sum a b = ()
val bn_eval_square:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (eval_ aLen a i * eval_ aLen a i == eval_ aLen a (i - 1) * eval_ aLen a (i - 1) +
2 * eval_ aLen a (i - 1) * v a.[i - 1] * pow2 (bits t * (i - 1)) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_eval_square #t #aLen a i =
let e1 = eval_ aLen a (i - 1) in
let p1 = pow2 (bits t * (i - 1)) in
let p2 = pow2 (bits t * (i + i - 2)) in
calc (==) {
eval_ aLen a i * eval_ aLen a i;
(==) { bn_eval_unfold_i a i }
(e1 + v a.[i - 1] * p1) * (e1 + v a.[i - 1] * p1);
(==) { square_of_sum e1 (v a.[i - 1] * p1) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + (v a.[i - 1] * p1) * (v a.[i - 1] * p1);
(==) { Math.Lemmas.paren_mul_right (v a.[i - 1]) p1 (v a.[i - 1] * p1); Math.Lemmas.paren_mul_right p1 p1 (v a.[i - 1]) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * (p1 * p1 * v a.[i - 1]);
(==) { Math.Lemmas.pow2_plus (bits t * (i - 1)) (bits t * (i - 1)) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * (p2 * v a.[i - 1]);
(==) { Math.Lemmas.paren_mul_right (v a.[i - 1]) (v a.[i - 1]) p2 }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Math.Lemmas.paren_mul_right (2 * e1) (v a.[i - 1]) p1 }
e1 * e1 + 2 * e1 * v a.[i - 1] * p1 + v a.[i - 1] * v a.[i - 1] * p2;
}
val bn_sqr_loop_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i <= aLen} ->
Lemma (let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i) == eval_ aLen a i * eval_ aLen a i)
let rec bn_sqr_loop_lemma #t #aLen a i =
let pbits = bits t in
let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
if i = 0 then begin
bn_eval0 acc;
bn_eval0 tmp;
bn_eval0 a end
else begin
let p1 = pow2 (pbits * (i + i - 1)) in
let p2 = pow2 (pbits * (i + i - 2)) in
let p3 = pow2 (pbits * (i - 1)) in
let acc1 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_f a) bn_zero in
let tmp1 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) bn_zero in
unfold_repeati i (bn_sqr_f a) bn_zero (i - 1);
assert (acc == bn_sqr_f a (i - 1) acc1);
bn_sqr_f_lemma a (i - 1) acc1 (i + i - 1);
assert (acc.[i + i - 1] == acc1.[i + i - 1]);
bn_sqr_tail a (i - 1);
assert (acc.[i + i - 1] == uint #t 0);
calc (==) {
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i);
(==) { bn_sqr_diag_loop_step a i }
2 * eval_ resLen acc (i + i) + eval_ resLen tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_eval_unfold_i acc (i + i) }
2 * (eval_ resLen acc (i + i - 1) + v acc.[i + i - 1] * p1) +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Classical.forall_intro (bn_sqr_f_lemma a (i - 1) acc1) }
2 * (eval_ resLen acc1 (i + i - 2) + eval_ aLen a (i - 1) * v a.[i - 1] * p3) +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Math.Lemmas.distributivity_add_right 2 (eval_ resLen acc1 (i + i - 2)) (eval_ aLen a (i - 1) * v a.[i - 1] * p3) }
2 * eval_ resLen acc1 (i + i - 2) + 2 * eval_ aLen a (i - 1) * v a.[i - 1] * p3 +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_sqr_loop_lemma a (i - 1) }
eval_ aLen a (i - 1) * eval_ aLen a (i - 1) + 2 * eval_ aLen a (i - 1) * v a.[i - 1] * p3 + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_eval_square a i }
eval_ aLen a i * eval_ aLen a i;
}; () end
val bn_sqr_lemma_eval: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_v (bn_sqr a) == bn_v a * bn_v a)
let bn_sqr_lemma_eval #t #aLen a =
let pbits = bits t in
let resLen = aLen + aLen in
let res0 = create (aLen + aLen) (uint #t 0) in
let res1 = repeati aLen (bn_sqr_f a) res0 in
let c0, res2 = Hacl.Spec.Bignum.Addition.bn_add res1 res1 in
Hacl.Spec.Bignum.Addition.bn_add_lemma res1 res1;
let tmp = bn_sqr_diag a in
let c1, res3 = Hacl.Spec.Bignum.Addition.bn_add res2 tmp in
Hacl.Spec.Bignum.Addition.bn_add_lemma res2 tmp;
assert ((v c0 + v c1) * pow2 (pbits * resLen) + bn_v res3 == 2 * bn_v res1 + bn_v tmp);
bn_sqr_loop_lemma a aLen;
assert (2 * bn_v res1 + bn_v tmp == bn_v a * bn_v a);
bn_eval_bound a aLen;
Math.Lemmas.lemma_mult_lt_sqr (bn_v a) (bn_v a) (pow2 (pbits * aLen));
Math.Lemmas.pow2_plus (pbits * aLen) (pbits * aLen);
assert (bn_v a * bn_v a < pow2 (pbits * resLen));
bn_eval_bound res3 resLen;
assert ((v c0 + v c1) = 0)
val bn_sqr_lemma: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_sqr a == SM.bn_mul a a /\ bn_v (bn_sqr a) == bn_v a * bn_v a) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_lemma: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_sqr a == SM.bn_mul a a /\ bn_v (bn_sqr a) == bn_v a * bn_v a) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_lemma | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen
-> FStar.Pervasives.Lemma
(ensures
Hacl.Spec.Bignum.Squaring.bn_sqr a == Hacl.Spec.Bignum.Multiplication.bn_mul a a /\
Hacl.Spec.Bignum.Definitions.bn_v (Hacl.Spec.Bignum.Squaring.bn_sqr a) ==
Hacl.Spec.Bignum.Definitions.bn_v a * Hacl.Spec.Bignum.Definitions.bn_v a) | {
"end_col": 36,
"end_line": 423,
"start_col": 29,
"start_line": 415
} |
Prims.Tot | val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c | val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc = | false | null | false | let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[ j ] j acc in
acc.[ j + j ] <- c | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"total"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Prims.op_LessThan",
"Hacl.Spec.Bignum.Definitions.limb",
"Lib.Sequence.op_String_Assignment",
"FStar.Pervasives.Native.tuple2",
"Hacl.Spec.Bignum.Multiplication.bn_mul1_lshift_add",
"Lib.Sequence.sub",
"Lib.Sequence.op_String_Access"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_f | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
a: Hacl.Spec.Bignum.Definitions.lbignum t aLen ->
j: Prims.nat{j < aLen} ->
acc: Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen)
-> Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen) | {
"end_col": 18,
"end_line": 54,
"start_col": 31,
"start_line": 52
} |
Prims.Tot | val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0 | val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a = | false | null | false | let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0 | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"total"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Lib.LoopCombinators.repeati",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f",
"Lib.Sequence.lseq",
"Hacl.Spec.Bignum.Definitions.limb",
"Prims.l_and",
"Prims.eq2",
"FStar.Seq.Base.seq",
"Lib.Sequence.to_seq",
"FStar.Seq.Base.create",
"Lib.IntTypes.mk_int",
"Lib.IntTypes.SEC",
"Prims.l_Forall",
"Prims.nat",
"Prims.l_imp",
"Prims.op_LessThan",
"Lib.Sequence.index",
"Lib.Sequence.create",
"Lib.IntTypes.uint"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_diag | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen
-> Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen) | {
"end_col": 37,
"end_line": 41,
"start_col": 28,
"start_line": 39
} |
FStar.Pervasives.Lemma | val bn_sqr_tail:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_f a) acc0 in
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index acc i == uint #t 0)) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_tail #t #aLen a k =
let _ = bn_sqr_inductive a k in () | val bn_sqr_tail:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_f a) acc0 in
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index acc i == uint #t 0))
let bn_sqr_tail #t #aLen a k = | false | null | true | let _ = bn_sqr_inductive a k in
() | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Hacl.Spec.Bignum.Squaring.bn_sqr_inductive",
"Prims.unit"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k))
val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_sqr_diag_loop_step #t #aLen a i =
let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
//assert (eval_ (aLen + aLen) acc1 (i + i) ==
//eval_ (aLen + aLen) acc1 (i + i - 2) + v acc1.[i + i - 2] * (pow2 (p * (i + i - 2))) + v acc1.[i + i - 1] * pow2 (p * (i + i - 1)));
calc (==) {
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * pow2 (pbits * (i + i - 1));
(==) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
(==) { Math.Lemmas.paren_mul_right (v acc1.[i + i - 1]) (pow2 pbits) (pow2 (pbits * (i + i - 2))) }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + (v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { Math.Lemmas.distributivity_add_left (v acc1.[i + i - 2]) (v acc1.[i + i - 1] * pow2 pbits) (pow2 (pbits * (i + i - 2))) }
(v acc1.[i + i - 2] + v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { bn_sqr_diag_lemma a i }
v a.[i - 1] * v a.[i - 1] * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * (pow2 (pbits * (i + i - 2))))
val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i)
let bn_sqr_f_lemma #t #aLen a j acc i =
let resLen = aLen + aLen in
let c, acc' = SM.bn_mul1_add_in_place #t #j (sub a 0 j) a.[j] (sub acc j j) in
let acc1 = update_sub acc j j acc' in
assert (index acc1 i == index acc i);
let res = acc1.[j + j] <- c in
assert (index res i == index acc i);
SM.bn_mul1_lshift_add_lemma #t #j #resLen (sub a 0 j) a.[j] j acc;
bn_eval_extensionality_j acc1 res (j + j);
bn_eval_unfold_i res (j + j + 1);
bn_eval_extensionality_j a (sub a 0 j) j
val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i)))
let bn_sqr_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_f a) acc0;
repeati_inductive #(lbignum t (aLen + aLen)) k
(fun i acci ->
acci == repeati i (bn_sqr_f a) acc0 /\
(forall (i0:nat{i + i < i0 /\ i0 < aLen + aLen}). Seq.index acci i0 == Seq.index acc0 i0))
(fun i acci ->
unfold_repeati k (bn_sqr_f a) acc0 i;
let acc1 = bn_sqr_f a i acci in
assert (acc1 == repeati (i + 1) (bn_sqr_f a) acc0);
Classical.forall_intro (bn_sqr_f_lemma a i acci);
assert (forall (i0:nat{i + i + 2 < i0 /\ i0 < aLen + aLen}). Seq.index acc1 i0 == Seq.index acc0 i0);
acc1)
acc0
val bn_sqr_tail:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_f a) acc0 in
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index acc i == uint #t 0)) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_tail:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_f a) acc0 in
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index acc i == uint #t 0)) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_tail | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen -> k: Prims.nat{k <= aLen}
-> FStar.Pervasives.Lemma
(ensures
(let acc0 = Lib.Sequence.create (aLen + aLen) (Lib.IntTypes.uint 0) in
let acc = Lib.LoopCombinators.repeati k (Hacl.Spec.Bignum.Squaring.bn_sqr_f a) acc0 in
forall (i: Prims.nat{k + k < i /\ i < aLen + aLen}).
FStar.Seq.Base.index acc i == Lib.IntTypes.uint 0)) | {
"end_col": 36,
"end_line": 294,
"start_col": 30,
"start_line": 293
} |
FStar.Pervasives.Lemma | val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1))) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in () | val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k = | false | null | true | let _ = bn_sqr_diag_inductive a k in
() | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_inductive",
"Prims.unit"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1))) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1))) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_diag_lemma | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen -> k: Prims.nat{k <= aLen}
-> FStar.Pervasives.Lemma
(ensures
(let acc0 = Lib.Sequence.create (aLen + aLen) (Lib.IntTypes.uint 0) in
let acc = Lib.LoopCombinators.repeati k (Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f a) acc0 in
(forall (i: Prims.nat{i < k}).
let _ = Hacl.Spec.Bignum.Base.mul_wide a.[ i ] a.[ i ] in
(let FStar.Pervasives.Native.Mktuple2 #_ #_ hi lo = _ in
FStar.Seq.Base.index acc (2 * i) == lo /\ FStar.Seq.Base.index acc (2 * i + 1) == hi)
<:
Type0) /\
(forall (i: Prims.nat{k <= i /\ i < aLen}).
FStar.Seq.Base.index acc (2 * i) == FStar.Seq.Base.index acc0 (2 * i) /\
FStar.Seq.Base.index acc (2 * i + 1) == FStar.Seq.Base.index acc0 (2 * i + 1)))) | {
"end_col": 41,
"end_line": 155,
"start_col": 36,
"start_line": 154
} |
Prims.Tot | val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc | val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc = | false | null | false | let hi, lo = mul_wide a.[ i ] a.[ i ] in
let acc = acc.[ 2 * i ] <- lo in
let acc = acc.[ 2 * i + 1 ] <- hi in
acc | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"total"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Prims.op_LessThan",
"Hacl.Spec.Bignum.Definitions.limb",
"Lib.Sequence.lseq",
"Prims.l_and",
"Prims.eq2",
"FStar.Seq.Base.seq",
"Lib.Sequence.to_seq",
"FStar.Seq.Base.upd",
"Prims.op_Multiply",
"Lib.Sequence.index",
"Prims.l_Forall",
"Prims.op_Subtraction",
"Prims.pow2",
"Prims.l_imp",
"Prims.op_disEquality",
"Prims.l_or",
"FStar.Seq.Base.index",
"Lib.Sequence.op_String_Assignment",
"FStar.Mul.op_Star",
"FStar.Pervasives.Native.tuple2",
"Hacl.Spec.Bignum.Base.mul_wide",
"Lib.Sequence.op_String_Access"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
a: Hacl.Spec.Bignum.Definitions.lbignum t aLen ->
i: Prims.nat{i < aLen} ->
acc: Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen)
-> Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen) | {
"end_col": 5,
"end_line": 30,
"start_col": 36,
"start_line": 26
} |
FStar.Pervasives.Lemma | val bn_sqr_lemma_eval: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_v (bn_sqr a) == bn_v a * bn_v a) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_lemma_eval #t #aLen a =
let pbits = bits t in
let resLen = aLen + aLen in
let res0 = create (aLen + aLen) (uint #t 0) in
let res1 = repeati aLen (bn_sqr_f a) res0 in
let c0, res2 = Hacl.Spec.Bignum.Addition.bn_add res1 res1 in
Hacl.Spec.Bignum.Addition.bn_add_lemma res1 res1;
let tmp = bn_sqr_diag a in
let c1, res3 = Hacl.Spec.Bignum.Addition.bn_add res2 tmp in
Hacl.Spec.Bignum.Addition.bn_add_lemma res2 tmp;
assert ((v c0 + v c1) * pow2 (pbits * resLen) + bn_v res3 == 2 * bn_v res1 + bn_v tmp);
bn_sqr_loop_lemma a aLen;
assert (2 * bn_v res1 + bn_v tmp == bn_v a * bn_v a);
bn_eval_bound a aLen;
Math.Lemmas.lemma_mult_lt_sqr (bn_v a) (bn_v a) (pow2 (pbits * aLen));
Math.Lemmas.pow2_plus (pbits * aLen) (pbits * aLen);
assert (bn_v a * bn_v a < pow2 (pbits * resLen));
bn_eval_bound res3 resLen;
assert ((v c0 + v c1) = 0) | val bn_sqr_lemma_eval: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_v (bn_sqr a) == bn_v a * bn_v a)
let bn_sqr_lemma_eval #t #aLen a = | false | null | true | let pbits = bits t in
let resLen = aLen + aLen in
let res0 = create (aLen + aLen) (uint #t 0) in
let res1 = repeati aLen (bn_sqr_f a) res0 in
let c0, res2 = Hacl.Spec.Bignum.Addition.bn_add res1 res1 in
Hacl.Spec.Bignum.Addition.bn_add_lemma res1 res1;
let tmp = bn_sqr_diag a in
let c1, res3 = Hacl.Spec.Bignum.Addition.bn_add res2 tmp in
Hacl.Spec.Bignum.Addition.bn_add_lemma res2 tmp;
assert ((v c0 + v c1) * pow2 (pbits * resLen) + bn_v res3 == 2 * bn_v res1 + bn_v tmp);
bn_sqr_loop_lemma a aLen;
assert (2 * bn_v res1 + bn_v tmp == bn_v a * bn_v a);
bn_eval_bound a aLen;
Math.Lemmas.lemma_mult_lt_sqr (bn_v a) (bn_v a) (pow2 (pbits * aLen));
Math.Lemmas.pow2_plus (pbits * aLen) (pbits * aLen);
assert (bn_v a * bn_v a < pow2 (pbits * resLen));
bn_eval_bound res3 resLen;
assert ((v c0 + v c1) = 0) | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Hacl.Spec.Bignum.Base.carry",
"Prims._assert",
"Prims.op_Equality",
"Prims.int",
"Lib.IntTypes.v",
"Lib.IntTypes.SEC",
"Prims.unit",
"Hacl.Spec.Bignum.Definitions.bn_eval_bound",
"Prims.op_LessThan",
"FStar.Mul.op_Star",
"Hacl.Spec.Bignum.Definitions.bn_v",
"Prims.pow2",
"FStar.Math.Lemmas.pow2_plus",
"FStar.Math.Lemmas.lemma_mult_lt_sqr",
"Prims.eq2",
"Hacl.Spec.Bignum.Squaring.bn_sqr_loop_lemma",
"Hacl.Spec.Bignum.Addition.bn_add_lemma",
"FStar.Pervasives.Native.tuple2",
"Hacl.Spec.Bignum.Addition.bn_add",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag",
"Lib.LoopCombinators.repeati",
"Hacl.Spec.Bignum.Squaring.bn_sqr_f",
"Lib.Sequence.lseq",
"Hacl.Spec.Bignum.Definitions.limb",
"Prims.l_and",
"FStar.Seq.Base.seq",
"Lib.Sequence.to_seq",
"FStar.Seq.Base.create",
"Lib.IntTypes.mk_int",
"Prims.l_Forall",
"Prims.nat",
"Prims.l_imp",
"Lib.Sequence.index",
"Lib.Sequence.create",
"Lib.IntTypes.uint",
"Lib.IntTypes.bits"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k))
val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_sqr_diag_loop_step #t #aLen a i =
let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
//assert (eval_ (aLen + aLen) acc1 (i + i) ==
//eval_ (aLen + aLen) acc1 (i + i - 2) + v acc1.[i + i - 2] * (pow2 (p * (i + i - 2))) + v acc1.[i + i - 1] * pow2 (p * (i + i - 1)));
calc (==) {
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * pow2 (pbits * (i + i - 1));
(==) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
(==) { Math.Lemmas.paren_mul_right (v acc1.[i + i - 1]) (pow2 pbits) (pow2 (pbits * (i + i - 2))) }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + (v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { Math.Lemmas.distributivity_add_left (v acc1.[i + i - 2]) (v acc1.[i + i - 1] * pow2 pbits) (pow2 (pbits * (i + i - 2))) }
(v acc1.[i + i - 2] + v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { bn_sqr_diag_lemma a i }
v a.[i - 1] * v a.[i - 1] * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * (pow2 (pbits * (i + i - 2))))
val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i)
let bn_sqr_f_lemma #t #aLen a j acc i =
let resLen = aLen + aLen in
let c, acc' = SM.bn_mul1_add_in_place #t #j (sub a 0 j) a.[j] (sub acc j j) in
let acc1 = update_sub acc j j acc' in
assert (index acc1 i == index acc i);
let res = acc1.[j + j] <- c in
assert (index res i == index acc i);
SM.bn_mul1_lshift_add_lemma #t #j #resLen (sub a 0 j) a.[j] j acc;
bn_eval_extensionality_j acc1 res (j + j);
bn_eval_unfold_i res (j + j + 1);
bn_eval_extensionality_j a (sub a 0 j) j
val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i)))
let bn_sqr_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_f a) acc0;
repeati_inductive #(lbignum t (aLen + aLen)) k
(fun i acci ->
acci == repeati i (bn_sqr_f a) acc0 /\
(forall (i0:nat{i + i < i0 /\ i0 < aLen + aLen}). Seq.index acci i0 == Seq.index acc0 i0))
(fun i acci ->
unfold_repeati k (bn_sqr_f a) acc0 i;
let acc1 = bn_sqr_f a i acci in
assert (acc1 == repeati (i + 1) (bn_sqr_f a) acc0);
Classical.forall_intro (bn_sqr_f_lemma a i acci);
assert (forall (i0:nat{i + i + 2 < i0 /\ i0 < aLen + aLen}). Seq.index acc1 i0 == Seq.index acc0 i0);
acc1)
acc0
val bn_sqr_tail:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_f a) acc0 in
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index acc i == uint #t 0))
let bn_sqr_tail #t #aLen a k =
let _ = bn_sqr_inductive a k in ()
val square_of_sum: a:nat -> b:nat -> Lemma ((a + b) * (a + b) == a * a + 2 * a * b + b * b)
let square_of_sum a b = ()
val bn_eval_square:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (eval_ aLen a i * eval_ aLen a i == eval_ aLen a (i - 1) * eval_ aLen a (i - 1) +
2 * eval_ aLen a (i - 1) * v a.[i - 1] * pow2 (bits t * (i - 1)) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_eval_square #t #aLen a i =
let e1 = eval_ aLen a (i - 1) in
let p1 = pow2 (bits t * (i - 1)) in
let p2 = pow2 (bits t * (i + i - 2)) in
calc (==) {
eval_ aLen a i * eval_ aLen a i;
(==) { bn_eval_unfold_i a i }
(e1 + v a.[i - 1] * p1) * (e1 + v a.[i - 1] * p1);
(==) { square_of_sum e1 (v a.[i - 1] * p1) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + (v a.[i - 1] * p1) * (v a.[i - 1] * p1);
(==) { Math.Lemmas.paren_mul_right (v a.[i - 1]) p1 (v a.[i - 1] * p1); Math.Lemmas.paren_mul_right p1 p1 (v a.[i - 1]) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * (p1 * p1 * v a.[i - 1]);
(==) { Math.Lemmas.pow2_plus (bits t * (i - 1)) (bits t * (i - 1)) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * (p2 * v a.[i - 1]);
(==) { Math.Lemmas.paren_mul_right (v a.[i - 1]) (v a.[i - 1]) p2 }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Math.Lemmas.paren_mul_right (2 * e1) (v a.[i - 1]) p1 }
e1 * e1 + 2 * e1 * v a.[i - 1] * p1 + v a.[i - 1] * v a.[i - 1] * p2;
}
val bn_sqr_loop_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i <= aLen} ->
Lemma (let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i) == eval_ aLen a i * eval_ aLen a i)
let rec bn_sqr_loop_lemma #t #aLen a i =
let pbits = bits t in
let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
if i = 0 then begin
bn_eval0 acc;
bn_eval0 tmp;
bn_eval0 a end
else begin
let p1 = pow2 (pbits * (i + i - 1)) in
let p2 = pow2 (pbits * (i + i - 2)) in
let p3 = pow2 (pbits * (i - 1)) in
let acc1 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_f a) bn_zero in
let tmp1 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) bn_zero in
unfold_repeati i (bn_sqr_f a) bn_zero (i - 1);
assert (acc == bn_sqr_f a (i - 1) acc1);
bn_sqr_f_lemma a (i - 1) acc1 (i + i - 1);
assert (acc.[i + i - 1] == acc1.[i + i - 1]);
bn_sqr_tail a (i - 1);
assert (acc.[i + i - 1] == uint #t 0);
calc (==) {
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i);
(==) { bn_sqr_diag_loop_step a i }
2 * eval_ resLen acc (i + i) + eval_ resLen tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_eval_unfold_i acc (i + i) }
2 * (eval_ resLen acc (i + i - 1) + v acc.[i + i - 1] * p1) +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Classical.forall_intro (bn_sqr_f_lemma a (i - 1) acc1) }
2 * (eval_ resLen acc1 (i + i - 2) + eval_ aLen a (i - 1) * v a.[i - 1] * p3) +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Math.Lemmas.distributivity_add_right 2 (eval_ resLen acc1 (i + i - 2)) (eval_ aLen a (i - 1) * v a.[i - 1] * p3) }
2 * eval_ resLen acc1 (i + i - 2) + 2 * eval_ aLen a (i - 1) * v a.[i - 1] * p3 +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_sqr_loop_lemma a (i - 1) }
eval_ aLen a (i - 1) * eval_ aLen a (i - 1) + 2 * eval_ aLen a (i - 1) * v a.[i - 1] * p3 + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_eval_square a i }
eval_ aLen a i * eval_ aLen a i;
}; () end
val bn_sqr_lemma_eval: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_v (bn_sqr a) == bn_v a * bn_v a) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_lemma_eval: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen ->
Lemma (bn_v (bn_sqr a) == bn_v a * bn_v a) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_lemma_eval | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen
-> FStar.Pervasives.Lemma
(ensures
Hacl.Spec.Bignum.Definitions.bn_v (Hacl.Spec.Bignum.Squaring.bn_sqr a) ==
Hacl.Spec.Bignum.Definitions.bn_v a * Hacl.Spec.Bignum.Definitions.bn_v a) | {
"end_col": 28,
"end_line": 409,
"start_col": 34,
"start_line": 391
} |
Prims.Pure | val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i))) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_f a) acc0;
repeati_inductive #(lbignum t (aLen + aLen)) k
(fun i acci ->
acci == repeati i (bn_sqr_f a) acc0 /\
(forall (i0:nat{i + i < i0 /\ i0 < aLen + aLen}). Seq.index acci i0 == Seq.index acc0 i0))
(fun i acci ->
unfold_repeati k (bn_sqr_f a) acc0 i;
let acc1 = bn_sqr_f a i acci in
assert (acc1 == repeati (i + 1) (bn_sqr_f a) acc0);
Classical.forall_intro (bn_sqr_f_lemma a i acci);
assert (forall (i0:nat{i + i + 2 < i0 /\ i0 < aLen + aLen}). Seq.index acc1 i0 == Seq.index acc0 i0);
acc1)
acc0 | val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i)))
let bn_sqr_inductive #t #aLen a k = | false | null | false | let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_f a) acc0;
repeati_inductive #(lbignum t (aLen + aLen))
k
(fun i acci ->
acci == repeati i (bn_sqr_f a) acc0 /\
(forall (i0: nat{i + i < i0 /\ i0 < aLen + aLen}). Seq.index acci i0 == Seq.index acc0 i0))
(fun i acci ->
unfold_repeati k (bn_sqr_f a) acc0 i;
let acc1 = bn_sqr_f a i acci in
assert (acc1 == repeati (i + 1) (bn_sqr_f a) acc0);
Classical.forall_intro (bn_sqr_f_lemma a i acci);
assert (forall (i0: nat{i + i + 2 < i0 /\ i0 < aLen + aLen}).
Seq.index acc1 i0 == Seq.index acc0 i0);
acc1)
acc0 | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Lib.LoopCombinators.repeati_inductive",
"Prims.l_and",
"Prims.eq2",
"Lib.LoopCombinators.repeati",
"Hacl.Spec.Bignum.Squaring.bn_sqr_f",
"Prims.l_Forall",
"Prims.op_LessThan",
"Hacl.Spec.Bignum.Definitions.limb",
"FStar.Seq.Base.index",
"Prims.unit",
"Prims._assert",
"FStar.Classical.forall_intro",
"Prims.int",
"Hacl.Spec.Bignum.Definitions.eval_",
"FStar.Mul.op_Star",
"Lib.IntTypes.v",
"Lib.IntTypes.SEC",
"Lib.Sequence.op_String_Access",
"Prims.pow2",
"Lib.IntTypes.bits",
"Hacl.Spec.Bignum.Squaring.bn_sqr_f_lemma",
"Lib.LoopCombinators.unfold_repeati",
"Lib.LoopCombinators.eq_repeati0",
"Lib.Sequence.lseq",
"FStar.Seq.Base.seq",
"Lib.Sequence.to_seq",
"FStar.Seq.Base.create",
"Lib.IntTypes.mk_int",
"Prims.l_imp",
"Lib.Sequence.index",
"Lib.Sequence.create",
"Lib.IntTypes.uint"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k))
val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_sqr_diag_loop_step #t #aLen a i =
let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
//assert (eval_ (aLen + aLen) acc1 (i + i) ==
//eval_ (aLen + aLen) acc1 (i + i - 2) + v acc1.[i + i - 2] * (pow2 (p * (i + i - 2))) + v acc1.[i + i - 1] * pow2 (p * (i + i - 1)));
calc (==) {
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * pow2 (pbits * (i + i - 1));
(==) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
(==) { Math.Lemmas.paren_mul_right (v acc1.[i + i - 1]) (pow2 pbits) (pow2 (pbits * (i + i - 2))) }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + (v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { Math.Lemmas.distributivity_add_left (v acc1.[i + i - 2]) (v acc1.[i + i - 1] * pow2 pbits) (pow2 (pbits * (i + i - 2))) }
(v acc1.[i + i - 2] + v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { bn_sqr_diag_lemma a i }
v a.[i - 1] * v a.[i - 1] * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * (pow2 (pbits * (i + i - 2))))
val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i)
let bn_sqr_f_lemma #t #aLen a j acc i =
let resLen = aLen + aLen in
let c, acc' = SM.bn_mul1_add_in_place #t #j (sub a 0 j) a.[j] (sub acc j j) in
let acc1 = update_sub acc j j acc' in
assert (index acc1 i == index acc i);
let res = acc1.[j + j] <- c in
assert (index res i == index acc i);
SM.bn_mul1_lshift_add_lemma #t #j #resLen (sub a 0 j) a.[j] j acc;
bn_eval_extensionality_j acc1 res (j + j);
bn_eval_unfold_i res (j + j + 1);
bn_eval_extensionality_j a (sub a 0 j) j
val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i))) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i))) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_inductive | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen -> k: Prims.nat{k <= aLen}
-> Prims.Pure (Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen)) | {
"end_col": 6,
"end_line": 281,
"start_col": 35,
"start_line": 267
} |
FStar.Pervasives.Lemma | val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_f_lemma #t #aLen a j acc i =
let resLen = aLen + aLen in
let c, acc' = SM.bn_mul1_add_in_place #t #j (sub a 0 j) a.[j] (sub acc j j) in
let acc1 = update_sub acc j j acc' in
assert (index acc1 i == index acc i);
let res = acc1.[j + j] <- c in
assert (index res i == index acc i);
SM.bn_mul1_lshift_add_lemma #t #j #resLen (sub a 0 j) a.[j] j acc;
bn_eval_extensionality_j acc1 res (j + j);
bn_eval_unfold_i res (j + j + 1);
bn_eval_extensionality_j a (sub a 0 j) j | val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i)
let bn_sqr_f_lemma #t #aLen a j acc i = | false | null | true | let resLen = aLen + aLen in
let c, acc' = SM.bn_mul1_add_in_place #t #j (sub a 0 j) a.[ j ] (sub acc j j) in
let acc1 = update_sub acc j j acc' in
assert (index acc1 i == index acc i);
let res = acc1.[ j + j ] <- c in
assert (index res i == index acc i);
SM.bn_mul1_lshift_add_lemma #t #j #resLen (sub a 0 j) a.[ j ] j acc;
bn_eval_extensionality_j acc1 res (j + j);
bn_eval_unfold_i res (j + j + 1);
bn_eval_extensionality_j a (sub a 0 j) j | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.op_LessThan",
"Prims.nat",
"Prims.l_and",
"Hacl.Spec.Bignum.Definitions.limb",
"Hacl.Spec.Bignum.Definitions.bn_eval_extensionality_j",
"Lib.Sequence.sub",
"Prims.unit",
"Hacl.Spec.Bignum.Definitions.bn_eval_unfold_i",
"Hacl.Spec.Bignum.Multiplication.bn_mul1_lshift_add_lemma",
"Lib.Sequence.op_String_Access",
"Prims._assert",
"Prims.eq2",
"Prims.l_or",
"FStar.Seq.Base.index",
"Lib.Sequence.to_seq",
"Lib.Sequence.index",
"Lib.Sequence.lseq",
"FStar.Seq.Base.seq",
"FStar.Seq.Base.upd",
"Prims.l_Forall",
"Prims.op_Subtraction",
"Prims.pow2",
"Prims.l_imp",
"Prims.op_disEquality",
"Lib.Sequence.op_String_Assignment",
"Lib.Sequence.update_sub",
"FStar.Pervasives.Native.tuple2",
"Hacl.Spec.Bignum.Multiplication.bn_mul1_add_in_place",
"Prims.int"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k))
val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_sqr_diag_loop_step #t #aLen a i =
let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
//assert (eval_ (aLen + aLen) acc1 (i + i) ==
//eval_ (aLen + aLen) acc1 (i + i - 2) + v acc1.[i + i - 2] * (pow2 (p * (i + i - 2))) + v acc1.[i + i - 1] * pow2 (p * (i + i - 1)));
calc (==) {
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * pow2 (pbits * (i + i - 1));
(==) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
(==) { Math.Lemmas.paren_mul_right (v acc1.[i + i - 1]) (pow2 pbits) (pow2 (pbits * (i + i - 2))) }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + (v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { Math.Lemmas.distributivity_add_left (v acc1.[i + i - 2]) (v acc1.[i + i - 1] * pow2 pbits) (pow2 (pbits * (i + i - 2))) }
(v acc1.[i + i - 2] + v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { bn_sqr_diag_lemma a i }
v a.[i - 1] * v a.[i - 1] * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * (pow2 (pbits * (i + i - 2))))
val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_f_lemma | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
a: Hacl.Spec.Bignum.Definitions.lbignum t aLen ->
j: Lib.IntTypes.size_nat{j < aLen} ->
acc: Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen) ->
i: Prims.nat{j + j < i /\ i < aLen + aLen}
-> FStar.Pervasives.Lemma
(ensures
(let res = Hacl.Spec.Bignum.Squaring.bn_sqr_f a j acc in
Hacl.Spec.Bignum.Definitions.eval_ (aLen + aLen) res (j + j + 1) ==
Hacl.Spec.Bignum.Definitions.eval_ (aLen + aLen) acc (j + j) +
(Hacl.Spec.Bignum.Definitions.eval_ aLen a j * Lib.IntTypes.v a.[ j ]) *
Prims.pow2 (Lib.IntTypes.bits t * j) /\
FStar.Seq.Base.index res i == FStar.Seq.Base.index acc i)) | {
"end_col": 42,
"end_line": 252,
"start_col": 39,
"start_line": 240
} |
Prims.Pure | val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1)))) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0 | val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k = | false | null | false | let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0: nat{i0 < i}).
let hi, lo = mul_wide a.[ i0 ] a.[ i0 ] in
Seq.index acci (2 * i0) == lo /\ Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0: nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0 | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Lib.LoopCombinators.repeati_inductive",
"FStar.Seq.Base.seq",
"Hacl.Spec.Bignum.Definitions.limb",
"Prims.l_and",
"Prims.eq2",
"Lib.LoopCombinators.repeati",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f",
"Prims.l_Forall",
"Prims.op_LessThan",
"FStar.Seq.Base.index",
"FStar.Mul.op_Star",
"FStar.Pervasives.Native.tuple2",
"Hacl.Spec.Bignum.Base.mul_wide",
"Lib.Sequence.op_String_Access",
"Prims.unit",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f_lemma",
"Lib.LoopCombinators.unfold_repeati",
"Lib.LoopCombinators.eq_repeati0",
"Lib.Sequence.lseq",
"Lib.Sequence.to_seq",
"FStar.Seq.Base.create",
"Lib.IntTypes.mk_int",
"Lib.IntTypes.SEC",
"Prims.l_imp",
"Lib.Sequence.index",
"Lib.Sequence.create",
"Lib.IntTypes.uint"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1)))) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1)))) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_diag_inductive | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen -> k: Prims.nat{k <= aLen}
-> Prims.Pure (Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen)) | {
"end_col": 6,
"end_line": 136,
"start_col": 40,
"start_line": 117
} |
FStar.Pervasives.Lemma | val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k)) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k)) | val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k = | false | null | true | let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1:lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2:lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i: nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert (Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i)
in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k)) | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Prims.op_LessThan",
"Lib.Sequence.eq_intro",
"Hacl.Spec.Bignum.Definitions.limb",
"Prims.op_Subtraction",
"FStar.Mul.op_Star",
"Lib.Sequence.slice",
"Prims.unit",
"FStar.Classical.forall_intro",
"Prims.eq2",
"FStar.Seq.Base.index",
"Prims.op_Multiply",
"Prims.l_True",
"Prims.squash",
"Prims.Nil",
"FStar.Pervasives.pattern",
"Prims._assert",
"FStar.Math.Lemmas.euclidean_division_definition",
"Prims.l_and",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_lemma",
"Prims.int",
"Prims.op_Division",
"Lib.LoopCombinators.repeati",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f",
"Lib.Sequence.lseq",
"FStar.Seq.Base.seq",
"Lib.Sequence.to_seq",
"FStar.Seq.Base.create",
"Lib.IntTypes.mk_int",
"Lib.IntTypes.SEC",
"Prims.l_Forall",
"Prims.l_imp",
"Lib.Sequence.index",
"Lib.Sequence.create",
"Lib.IntTypes.uint"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k)) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k)) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_diag_eq | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen -> k: Prims.nat{k < aLen}
-> FStar.Pervasives.Lemma
(ensures
(let acc0 = Lib.Sequence.create (aLen + aLen) (Lib.IntTypes.uint 0) in
let acc1 = Lib.LoopCombinators.repeati k (Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f a) acc0 in
let acc2 =
Lib.LoopCombinators.repeati (k + 1) (Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f a) acc0
in
Lib.Sequence.slice acc1 0 (2 * k) == Lib.Sequence.slice acc2 0 (2 * k))) | {
"end_col": 56,
"end_line": 184,
"start_col": 33,
"start_line": 168
} |
FStar.Pervasives.Lemma | val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1])) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2 | val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc = | false | null | true | let hi, lo = mul_wide a.[ i ] a.[ i ] in
let res1 = acc.[ 2 * i ] <- lo in
let res = res1.[ 2 * i + 1 ] <- hi in
let aux (i0: nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1})
: Lemma (acc.[ i0 ] == res.[ i0 ]) =
()
in
let aux2 (i0: nat{i0 < aLen /\ i0 <> i})
: Lemma (acc.[ 2 * i0 ] == res.[ 2 * i0 ] /\ acc.[ 2 * i0 + 1 ] == res.[ 2 * i0 + 1 ]) =
aux (2 * i0);
aux (2 * i0 + 1);
()
in
Classical.forall_intro aux2 | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Prims.op_LessThan",
"Hacl.Spec.Bignum.Definitions.limb",
"FStar.Classical.forall_intro",
"Prims.l_and",
"Prims.op_disEquality",
"Prims.eq2",
"Prims.l_or",
"FStar.Seq.Base.index",
"Lib.Sequence.to_seq",
"FStar.Mul.op_Star",
"Lib.Sequence.op_String_Access",
"Prims.unit",
"Prims.l_True",
"Prims.squash",
"Prims.op_Multiply",
"Lib.Sequence.index",
"Prims.Nil",
"FStar.Pervasives.pattern",
"Prims.int",
"Lib.Sequence.lseq",
"FStar.Seq.Base.seq",
"FStar.Seq.Base.upd",
"Prims.l_Forall",
"Prims.op_Subtraction",
"Prims.pow2",
"Prims.l_imp",
"Lib.Sequence.op_String_Assignment",
"FStar.Pervasives.Native.tuple2",
"Hacl.Spec.Bignum.Base.mul_wide"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1])) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1])) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f_lemma | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
a: Hacl.Spec.Bignum.Definitions.lbignum t aLen ->
i: Prims.nat{i < aLen} ->
acc: Hacl.Spec.Bignum.Definitions.lbignum t (aLen + aLen)
-> FStar.Pervasives.Lemma
(ensures
(let _ = Hacl.Spec.Bignum.Base.mul_wide a.[ i ] a.[ i ] in
(let FStar.Pervasives.Native.Mktuple2 #_ #_ hi lo = _ in
let res = Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f a i acc in
res.[ 2 * i ] == lo /\ res.[ 2 * i + 1 ] == hi /\
(forall (i0: Prims.nat{i0 < aLen /\ i0 <> i}).
acc.[ 2 * i0 ] == res.[ 2 * i0 ] /\ acc.[ 2 * i0 + 1 ] == res.[ 2 * i0 + 1 ]))
<:
Type0)) | {
"end_col": 29,
"end_line": 96,
"start_col": 42,
"start_line": 80
} |
FStar.Pervasives.Lemma | val bn_eval_square:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (eval_ aLen a i * eval_ aLen a i == eval_ aLen a (i - 1) * eval_ aLen a (i - 1) +
2 * eval_ aLen a (i - 1) * v a.[i - 1] * pow2 (bits t * (i - 1)) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2))) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_eval_square #t #aLen a i =
let e1 = eval_ aLen a (i - 1) in
let p1 = pow2 (bits t * (i - 1)) in
let p2 = pow2 (bits t * (i + i - 2)) in
calc (==) {
eval_ aLen a i * eval_ aLen a i;
(==) { bn_eval_unfold_i a i }
(e1 + v a.[i - 1] * p1) * (e1 + v a.[i - 1] * p1);
(==) { square_of_sum e1 (v a.[i - 1] * p1) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + (v a.[i - 1] * p1) * (v a.[i - 1] * p1);
(==) { Math.Lemmas.paren_mul_right (v a.[i - 1]) p1 (v a.[i - 1] * p1); Math.Lemmas.paren_mul_right p1 p1 (v a.[i - 1]) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * (p1 * p1 * v a.[i - 1]);
(==) { Math.Lemmas.pow2_plus (bits t * (i - 1)) (bits t * (i - 1)) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * (p2 * v a.[i - 1]);
(==) { Math.Lemmas.paren_mul_right (v a.[i - 1]) (v a.[i - 1]) p2 }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Math.Lemmas.paren_mul_right (2 * e1) (v a.[i - 1]) p1 }
e1 * e1 + 2 * e1 * v a.[i - 1] * p1 + v a.[i - 1] * v a.[i - 1] * p2;
} | val bn_eval_square:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (eval_ aLen a i * eval_ aLen a i == eval_ aLen a (i - 1) * eval_ aLen a (i - 1) +
2 * eval_ aLen a (i - 1) * v a.[i - 1] * pow2 (bits t * (i - 1)) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_eval_square #t #aLen a i = | false | null | true | let e1 = eval_ aLen a (i - 1) in
let p1 = pow2 (bits t * (i - 1)) in
let p2 = pow2 (bits t * (i + i - 2)) in
calc ( == ) {
eval_ aLen a i * eval_ aLen a i;
( == ) { bn_eval_unfold_i a i }
(e1 + v a.[ i - 1 ] * p1) * (e1 + v a.[ i - 1 ] * p1);
( == ) { square_of_sum e1 (v a.[ i - 1 ] * p1) }
e1 * e1 + (2 * e1) * (v a.[ i - 1 ] * p1) + (v a.[ i - 1 ] * p1) * (v a.[ i - 1 ] * p1);
( == ) { (Math.Lemmas.paren_mul_right (v a.[ i - 1 ]) p1 (v a.[ i - 1 ] * p1);
Math.Lemmas.paren_mul_right p1 p1 (v a.[ i - 1 ])) }
e1 * e1 + (2 * e1) * (v a.[ i - 1 ] * p1) + v a.[ i - 1 ] * ((p1 * p1) * v a.[ i - 1 ]);
( == ) { Math.Lemmas.pow2_plus (bits t * (i - 1)) (bits t * (i - 1)) }
e1 * e1 + (2 * e1) * (v a.[ i - 1 ] * p1) + v a.[ i - 1 ] * (p2 * v a.[ i - 1 ]);
( == ) { Math.Lemmas.paren_mul_right (v a.[ i - 1 ]) (v a.[ i - 1 ]) p2 }
e1 * e1 + (2 * e1) * (v a.[ i - 1 ] * p1) + (v a.[ i - 1 ] * v a.[ i - 1 ]) * p2;
( == ) { Math.Lemmas.paren_mul_right (2 * e1) (v a.[ i - 1 ]) p1 }
e1 * e1 + ((2 * e1) * v a.[ i - 1 ]) * p1 + (v a.[ i - 1 ] * v a.[ i - 1 ]) * p2;
} | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.pos",
"FStar.Calc.calc_finish",
"Prims.int",
"Prims.eq2",
"FStar.Mul.op_Star",
"Hacl.Spec.Bignum.Definitions.eval_",
"Lib.IntTypes.v",
"Lib.IntTypes.SEC",
"Lib.Sequence.op_String_Access",
"Hacl.Spec.Bignum.Definitions.limb",
"Prims.op_Subtraction",
"Prims.Cons",
"FStar.Preorder.relation",
"Prims.Nil",
"Prims.unit",
"FStar.Calc.calc_step",
"FStar.Calc.calc_init",
"FStar.Calc.calc_pack",
"Hacl.Spec.Bignum.Definitions.bn_eval_unfold_i",
"Prims.squash",
"Hacl.Spec.Bignum.Squaring.square_of_sum",
"FStar.Math.Lemmas.paren_mul_right",
"FStar.Math.Lemmas.pow2_plus",
"Lib.IntTypes.bits",
"Prims.pow2",
"Prims.nat"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k))
val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_sqr_diag_loop_step #t #aLen a i =
let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
//assert (eval_ (aLen + aLen) acc1 (i + i) ==
//eval_ (aLen + aLen) acc1 (i + i - 2) + v acc1.[i + i - 2] * (pow2 (p * (i + i - 2))) + v acc1.[i + i - 1] * pow2 (p * (i + i - 1)));
calc (==) {
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * pow2 (pbits * (i + i - 1));
(==) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
(==) { Math.Lemmas.paren_mul_right (v acc1.[i + i - 1]) (pow2 pbits) (pow2 (pbits * (i + i - 2))) }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + (v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { Math.Lemmas.distributivity_add_left (v acc1.[i + i - 2]) (v acc1.[i + i - 1] * pow2 pbits) (pow2 (pbits * (i + i - 2))) }
(v acc1.[i + i - 2] + v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { bn_sqr_diag_lemma a i }
v a.[i - 1] * v a.[i - 1] * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * (pow2 (pbits * (i + i - 2))))
val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i)
let bn_sqr_f_lemma #t #aLen a j acc i =
let resLen = aLen + aLen in
let c, acc' = SM.bn_mul1_add_in_place #t #j (sub a 0 j) a.[j] (sub acc j j) in
let acc1 = update_sub acc j j acc' in
assert (index acc1 i == index acc i);
let res = acc1.[j + j] <- c in
assert (index res i == index acc i);
SM.bn_mul1_lshift_add_lemma #t #j #resLen (sub a 0 j) a.[j] j acc;
bn_eval_extensionality_j acc1 res (j + j);
bn_eval_unfold_i res (j + j + 1);
bn_eval_extensionality_j a (sub a 0 j) j
val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i)))
let bn_sqr_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_f a) acc0;
repeati_inductive #(lbignum t (aLen + aLen)) k
(fun i acci ->
acci == repeati i (bn_sqr_f a) acc0 /\
(forall (i0:nat{i + i < i0 /\ i0 < aLen + aLen}). Seq.index acci i0 == Seq.index acc0 i0))
(fun i acci ->
unfold_repeati k (bn_sqr_f a) acc0 i;
let acc1 = bn_sqr_f a i acci in
assert (acc1 == repeati (i + 1) (bn_sqr_f a) acc0);
Classical.forall_intro (bn_sqr_f_lemma a i acci);
assert (forall (i0:nat{i + i + 2 < i0 /\ i0 < aLen + aLen}). Seq.index acc1 i0 == Seq.index acc0 i0);
acc1)
acc0
val bn_sqr_tail:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_f a) acc0 in
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index acc i == uint #t 0))
let bn_sqr_tail #t #aLen a k =
let _ = bn_sqr_inductive a k in ()
val square_of_sum: a:nat -> b:nat -> Lemma ((a + b) * (a + b) == a * a + 2 * a * b + b * b)
let square_of_sum a b = ()
val bn_eval_square:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (eval_ aLen a i * eval_ aLen a i == eval_ aLen a (i - 1) * eval_ aLen a (i - 1) +
2 * eval_ aLen a (i - 1) * v a.[i - 1] * pow2 (bits t * (i - 1)) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2))) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_eval_square:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (eval_ aLen a i * eval_ aLen a i == eval_ aLen a (i - 1) * eval_ aLen a (i - 1) +
2 * eval_ aLen a (i - 1) * v a.[i - 1] * pow2 (bits t * (i - 1)) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2))) | [] | Hacl.Spec.Bignum.Squaring.bn_eval_square | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen -> i: Prims.pos{i <= aLen}
-> FStar.Pervasives.Lemma
(ensures
Hacl.Spec.Bignum.Definitions.eval_ aLen a i * Hacl.Spec.Bignum.Definitions.eval_ aLen a i ==
Hacl.Spec.Bignum.Definitions.eval_ aLen a (i - 1) *
Hacl.Spec.Bignum.Definitions.eval_ aLen a (i - 1) +
((2 * Hacl.Spec.Bignum.Definitions.eval_ aLen a (i - 1)) * Lib.IntTypes.v a.[ i - 1 ]) *
Prims.pow2 (Lib.IntTypes.bits t * (i - 1)) +
(Lib.IntTypes.v a.[ i - 1 ] * Lib.IntTypes.v a.[ i - 1 ]) *
Prims.pow2 (Lib.IntTypes.bits t * (i + i - 2))) | {
"end_col": 5,
"end_line": 328,
"start_col": 33,
"start_line": 309
} |
FStar.Pervasives.Lemma | val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2))) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let bn_sqr_diag_loop_step #t #aLen a i =
let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
//assert (eval_ (aLen + aLen) acc1 (i + i) ==
//eval_ (aLen + aLen) acc1 (i + i - 2) + v acc1.[i + i - 2] * (pow2 (p * (i + i - 2))) + v acc1.[i + i - 1] * pow2 (p * (i + i - 1)));
calc (==) {
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * pow2 (pbits * (i + i - 1));
(==) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
(==) { Math.Lemmas.paren_mul_right (v acc1.[i + i - 1]) (pow2 pbits) (pow2 (pbits * (i + i - 2))) }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + (v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { Math.Lemmas.distributivity_add_left (v acc1.[i + i - 2]) (v acc1.[i + i - 1] * pow2 pbits) (pow2 (pbits * (i + i - 2))) }
(v acc1.[i + i - 2] + v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { bn_sqr_diag_lemma a i }
v a.[i - 1] * v a.[i - 1] * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * (pow2 (pbits * (i + i - 2)))) | val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_sqr_diag_loop_step #t #aLen a i = | false | null | true | let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1:lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2:lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
calc ( == ) {
v acc1.[ i + i - 2 ] * pow2 (pbits * (i + i - 2)) +
v acc1.[ i + i - 1 ] * pow2 (pbits * (i + i - 1));
( == ) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[ i + i - 2 ] * pow2 (pbits * (i + i - 2)) +
v acc1.[ i + i - 1 ] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
( == ) { Math.Lemmas.paren_mul_right (v acc1.[ i + i - 1 ])
(pow2 pbits)
(pow2 (pbits * (i + i - 2))) }
v acc1.[ i + i - 2 ] * pow2 (pbits * (i + i - 2)) +
(v acc1.[ i + i - 1 ] * pow2 pbits) * pow2 (pbits * (i + i - 2));
( == ) { Math.Lemmas.distributivity_add_left (v acc1.[ i + i - 2 ])
(v acc1.[ i + i - 1 ] * pow2 pbits)
(pow2 (pbits * (i + i - 2))) }
(v acc1.[ i + i - 2 ] + v acc1.[ i + i - 1 ] * pow2 pbits) * pow2 (pbits * (i + i - 2));
( == ) { bn_sqr_diag_lemma a i }
(v a.[ i - 1 ] * v a.[ i - 1 ]) * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) +
(v a.[ i - 1 ] * v a.[ i - 1 ]) * (pow2 (pbits * (i + i - 2)))) | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_pos",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.pos",
"Prims._assert",
"Prims.eq2",
"Prims.int",
"Hacl.Spec.Bignum.Definitions.eval_",
"Prims.op_Subtraction",
"FStar.Mul.op_Star",
"Lib.IntTypes.v",
"Lib.IntTypes.SEC",
"Lib.Sequence.op_String_Access",
"Hacl.Spec.Bignum.Definitions.limb",
"Prims.pow2",
"Prims.unit",
"Hacl.Spec.Bignum.Definitions.bn_eval_extensionality_j",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_eq",
"FStar.Calc.calc_finish",
"Prims.Cons",
"FStar.Preorder.relation",
"Prims.Nil",
"FStar.Calc.calc_step",
"FStar.Calc.calc_init",
"FStar.Calc.calc_pack",
"FStar.Math.Lemmas.pow2_plus",
"Prims.squash",
"FStar.Math.Lemmas.paren_mul_right",
"FStar.Math.Lemmas.distributivity_add_left",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_lemma",
"Hacl.Spec.Bignum.Definitions.bn_eval_unfold_i",
"Lib.LoopCombinators.repeati",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f",
"Lib.Sequence.lseq",
"Prims.l_and",
"FStar.Seq.Base.seq",
"Lib.Sequence.to_seq",
"FStar.Seq.Base.create",
"Lib.IntTypes.mk_int",
"Prims.l_Forall",
"Prims.nat",
"Prims.l_imp",
"Prims.op_LessThan",
"Lib.Sequence.index",
"Lib.Sequence.create",
"Lib.IntTypes.uint",
"Lib.IntTypes.bits"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k))
val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2))) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2))) | [] | Hacl.Spec.Bignum.Squaring.bn_sqr_diag_loop_step | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen -> i: Prims.pos{i <= aLen}
-> FStar.Pervasives.Lemma
(ensures
(let acc0 = Lib.Sequence.create (aLen + aLen) (Lib.IntTypes.uint 0) in
let acc1 = Lib.LoopCombinators.repeati i (Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f a) acc0 in
let acc2 =
Lib.LoopCombinators.repeati (i - 1) (Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f a) acc0
in
Hacl.Spec.Bignum.Definitions.eval_ (aLen + aLen) acc1 (i + i) ==
Hacl.Spec.Bignum.Definitions.eval_ (aLen + aLen) acc2 (i + i - 2) +
(Lib.IntTypes.v a.[ i - 1 ] * Lib.IntTypes.v a.[ i - 1 ]) *
Prims.pow2 (Lib.IntTypes.bits t * (i + i - 2)))) | {
"end_col": 100,
"end_line": 225,
"start_col": 40,
"start_line": 198
} |
FStar.Pervasives.Lemma | val bn_sqr_loop_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i <= aLen} ->
Lemma (let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i) == eval_ aLen a i * eval_ aLen a i) | [
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Addition",
"short_module": "SA"
},
{
"abbrev": true,
"full_module": "Hacl.Spec.Bignum.Multiplication",
"short_module": "SM"
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Lib",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum.Definitions",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.LoopCombinators",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.Sequence",
"short_module": null
},
{
"abbrev": false,
"full_module": "Lib.IntTypes",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "Hacl.Spec.Bignum",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let rec bn_sqr_loop_lemma #t #aLen a i =
let pbits = bits t in
let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
if i = 0 then begin
bn_eval0 acc;
bn_eval0 tmp;
bn_eval0 a end
else begin
let p1 = pow2 (pbits * (i + i - 1)) in
let p2 = pow2 (pbits * (i + i - 2)) in
let p3 = pow2 (pbits * (i - 1)) in
let acc1 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_f a) bn_zero in
let tmp1 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) bn_zero in
unfold_repeati i (bn_sqr_f a) bn_zero (i - 1);
assert (acc == bn_sqr_f a (i - 1) acc1);
bn_sqr_f_lemma a (i - 1) acc1 (i + i - 1);
assert (acc.[i + i - 1] == acc1.[i + i - 1]);
bn_sqr_tail a (i - 1);
assert (acc.[i + i - 1] == uint #t 0);
calc (==) {
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i);
(==) { bn_sqr_diag_loop_step a i }
2 * eval_ resLen acc (i + i) + eval_ resLen tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_eval_unfold_i acc (i + i) }
2 * (eval_ resLen acc (i + i - 1) + v acc.[i + i - 1] * p1) +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Classical.forall_intro (bn_sqr_f_lemma a (i - 1) acc1) }
2 * (eval_ resLen acc1 (i + i - 2) + eval_ aLen a (i - 1) * v a.[i - 1] * p3) +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Math.Lemmas.distributivity_add_right 2 (eval_ resLen acc1 (i + i - 2)) (eval_ aLen a (i - 1) * v a.[i - 1] * p3) }
2 * eval_ resLen acc1 (i + i - 2) + 2 * eval_ aLen a (i - 1) * v a.[i - 1] * p3 +
eval_ (aLen + aLen) tmp1 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_sqr_loop_lemma a (i - 1) }
eval_ aLen a (i - 1) * eval_ aLen a (i - 1) + 2 * eval_ aLen a (i - 1) * v a.[i - 1] * p3 + v a.[i - 1] * v a.[i - 1] * p2;
(==) { bn_eval_square a i }
eval_ aLen a i * eval_ aLen a i;
}; () end | val bn_sqr_loop_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i <= aLen} ->
Lemma (let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i) == eval_ aLen a i * eval_ aLen a i)
let rec bn_sqr_loop_lemma #t #aLen a i = | false | null | true | let pbits = bits t in
let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc:lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp:lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
if i = 0
then
(bn_eval0 acc;
bn_eval0 tmp;
bn_eval0 a)
else
let p1 = pow2 (pbits * (i + i - 1)) in
let p2 = pow2 (pbits * (i + i - 2)) in
let p3 = pow2 (pbits * (i - 1)) in
let acc1:lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_f a) bn_zero in
let tmp1:lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) bn_zero in
unfold_repeati i (bn_sqr_f a) bn_zero (i - 1);
assert (acc == bn_sqr_f a (i - 1) acc1);
bn_sqr_f_lemma a (i - 1) acc1 (i + i - 1);
assert (acc.[ i + i - 1 ] == acc1.[ i + i - 1 ]);
bn_sqr_tail a (i - 1);
assert (acc.[ i + i - 1 ] == uint #t 0);
calc ( == ) {
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i);
( == ) { bn_sqr_diag_loop_step a i }
2 * eval_ resLen acc (i + i) + eval_ resLen tmp1 (i + i - 2) +
(v a.[ i - 1 ] * v a.[ i - 1 ]) * p2;
( == ) { bn_eval_unfold_i acc (i + i) }
2 * (eval_ resLen acc (i + i - 1) + v acc.[ i + i - 1 ] * p1) +
eval_ (aLen + aLen) tmp1 (i + i - 2) +
(v a.[ i - 1 ] * v a.[ i - 1 ]) * p2;
( == ) { Classical.forall_intro (bn_sqr_f_lemma a (i - 1) acc1) }
2 * (eval_ resLen acc1 (i + i - 2) + (eval_ aLen a (i - 1) * v a.[ i - 1 ]) * p3) +
eval_ (aLen + aLen) tmp1 (i + i - 2) +
(v a.[ i - 1 ] * v a.[ i - 1 ]) * p2;
( == ) { Math.Lemmas.distributivity_add_right 2
(eval_ resLen acc1 (i + i - 2))
((eval_ aLen a (i - 1) * v a.[ i - 1 ]) * p3) }
2 * eval_ resLen acc1 (i + i - 2) + ((2 * eval_ aLen a (i - 1)) * v a.[ i - 1 ]) * p3 +
eval_ (aLen + aLen) tmp1 (i + i - 2) +
(v a.[ i - 1 ] * v a.[ i - 1 ]) * p2;
( == ) { bn_sqr_loop_lemma a (i - 1) }
eval_ aLen a (i - 1) * eval_ aLen a (i - 1) + ((2 * eval_ aLen a (i - 1)) * v a.[ i - 1 ]) * p3 +
(v a.[ i - 1 ] * v a.[ i - 1 ]) * p2;
( == ) { bn_eval_square a i }
eval_ aLen a i * eval_ aLen a i;
};
() | {
"checked_file": "Hacl.Spec.Bignum.Squaring.fst.checked",
"dependencies": [
"prims.fst.checked",
"Lib.Sequence.fsti.checked",
"Lib.LoopCombinators.fsti.checked",
"Lib.IntTypes.fsti.checked",
"Hacl.Spec.Lib.fst.checked",
"Hacl.Spec.Bignum.Multiplication.fst.checked",
"Hacl.Spec.Bignum.Definitions.fst.checked",
"Hacl.Spec.Bignum.Base.fst.checked",
"Hacl.Spec.Bignum.Addition.fst.checked",
"FStar.Seq.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Math.Lemmas.fst.checked",
"FStar.Classical.fsti.checked",
"FStar.Calc.fsti.checked"
],
"interface_file": false,
"source_file": "Hacl.Spec.Bignum.Squaring.fst"
} | [
"lemma"
] | [
"Hacl.Spec.Bignum.Definitions.limb_t",
"Lib.IntTypes.size_nat",
"Prims.b2t",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Lib.IntTypes.max_size_t",
"Hacl.Spec.Bignum.Definitions.lbignum",
"Prims.nat",
"Prims.op_Equality",
"Prims.int",
"Hacl.Spec.Bignum.Definitions.bn_eval0",
"Prims.unit",
"Prims.bool",
"FStar.Calc.calc_finish",
"Prims.eq2",
"FStar.Mul.op_Star",
"Hacl.Spec.Bignum.Definitions.eval_",
"Prims.Cons",
"FStar.Preorder.relation",
"Prims.Nil",
"FStar.Calc.calc_step",
"Prims.op_Subtraction",
"Lib.IntTypes.v",
"Lib.IntTypes.SEC",
"Lib.Sequence.op_String_Access",
"Hacl.Spec.Bignum.Definitions.limb",
"FStar.Calc.calc_init",
"FStar.Calc.calc_pack",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_loop_step",
"Prims.squash",
"Hacl.Spec.Bignum.Definitions.bn_eval_unfold_i",
"FStar.Classical.forall_intro",
"Prims.l_and",
"Prims.op_LessThan",
"Hacl.Spec.Bignum.Squaring.bn_sqr_f",
"Prims.pow2",
"Lib.IntTypes.bits",
"FStar.Seq.Base.index",
"Hacl.Spec.Bignum.Squaring.bn_sqr_f_lemma",
"FStar.Math.Lemmas.distributivity_add_right",
"Hacl.Spec.Bignum.Squaring.bn_sqr_loop_lemma",
"Hacl.Spec.Bignum.Squaring.bn_eval_square",
"Prims._assert",
"Lib.IntTypes.int_t",
"Prims.l_or",
"Lib.IntTypes.range",
"Lib.Sequence.to_seq",
"Lib.IntTypes.uint",
"Hacl.Spec.Bignum.Squaring.bn_sqr_tail",
"Lib.LoopCombinators.unfold_repeati",
"Lib.LoopCombinators.repeati",
"Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f",
"Prims.pos",
"Lib.Sequence.lseq",
"FStar.Seq.Base.seq",
"FStar.Seq.Base.create",
"Lib.IntTypes.mk_int",
"Prims.l_Forall",
"Prims.l_imp",
"Lib.Sequence.index",
"Lib.Sequence.create"
] | [] | module Hacl.Spec.Bignum.Squaring
open FStar.Mul
open Lib.IntTypes
open Lib.Sequence
open Lib.LoopCombinators
open Hacl.Spec.Bignum.Definitions
open Hacl.Spec.Bignum.Base
open Hacl.Spec.Lib
module SM = Hacl.Spec.Bignum.Multiplication
module SA = Hacl.Spec.Bignum.Addition
#reset-options "--z3rlimit 50 --fuel 0 --ifuel 0"
val bn_sqr_diag_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_diag_f #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let acc = acc.[2 * i] <- lo in
let acc = acc.[2 * i + 1] <- hi in
acc
val bn_sqr_diag:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen ->
lbignum t (aLen + aLen)
let bn_sqr_diag #t #aLen a =
let acc0 = create (aLen + aLen) (uint #t 0) in
repeati aLen (bn_sqr_diag_f a) acc0
val bn_sqr_f:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:nat{j < aLen}
-> acc:lbignum t (aLen + aLen) ->
lbignum t (aLen + aLen)
let bn_sqr_f #t #aLen a j acc =
let c, acc = SM.bn_mul1_lshift_add (sub a 0 j) a.[j] j acc in
acc.[j + j] <- c
val bn_sqr: #t:limb_t -> #aLen:size_nat{aLen + aLen <= max_size_t} -> a:lbignum t aLen -> lbignum t (aLen + aLen)
let bn_sqr #t #aLen a =
let res = create (aLen + aLen) (uint #t 0) in
let res = repeati aLen (bn_sqr_f a) res in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res res in
let tmp = bn_sqr_diag a in
let c, res = Hacl.Spec.Bignum.Addition.bn_add res tmp in
res
val bn_sqr_diag_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i < aLen}
-> acc:lbignum t (aLen + aLen) ->
Lemma (let (hi, lo) = mul_wide a.[i] a.[i] in
let res = bn_sqr_diag_f a i acc in
res.[2 * i] == lo /\ res.[2 * i + 1] == hi /\
(forall (i0:nat{i0 < aLen /\ i0 <> i}).
acc.[2 * i0] == res.[2 * i0] /\
acc.[2 * i0 + 1] == res.[2 * i0 + 1]))
let bn_sqr_diag_f_lemma #t #aLen a i acc =
let (hi, lo) = mul_wide a.[i] a.[i] in
let res1 = acc.[2 * i] <- lo in
let res = res1.[2 * i + 1] <- hi in
let aux (i0:nat{i0 < aLen + aLen /\ i0 <> 2 * i /\ i0 <> 2 * i + 1}) :
Lemma (acc.[i0] == res.[i0]) = () in
let aux2 (i0:nat{i0 < aLen /\ i0 <> i}) :
Lemma (acc.[2 * i0] == res.[2 * i0] /\ acc.[2 * i0 + 1] == res.[2 * i0 + 1]) =
aux (2 * i0);
//assert (acc.[2 * i0] == res.[2 * i0]);
aux (2 * i0 + 1);
//assert (acc.[2 * i0 + 1] == res.[2 * i0 + 1]);
() in
Classical.forall_intro aux2
val bn_sqr_diag_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_diag_f a) acc0 /\
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index res (2 * i) == lo /\
Seq.index res (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index res (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index res (2 * i + 1) == Seq.index acc0 (2 * i + 1))))
let bn_sqr_diag_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_diag_f a) acc0;
repeati_inductive k
(fun i acci ->
acci == repeati i (bn_sqr_diag_f a) acc0 /\
(forall (i0:nat{i0 < i}).
let (hi, lo) = mul_wide a.[i0] a.[i0] in
Seq.index acci (2 * i0) == lo /\
Seq.index acci (2 * i0 + 1) == hi) /\
(forall (i0:nat{i <= i0 /\ i0 < aLen}).
Seq.index acci (2 * i0) == Seq.index acc0 (2 * i0) /\
Seq.index acci (2 * i0 + 1) == Seq.index acc0 (2 * i0 + 1)))
(fun i acci ->
unfold_repeati k (bn_sqr_diag_f a) acc0 i;
let acc = bn_sqr_diag_f a i acci in
bn_sqr_diag_f_lemma #t #aLen a i acci;
acc)
acc0
val bn_sqr_diag_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
(forall (i:nat{i < k}).
let (hi, lo) = mul_wide a.[i] a.[i] in
Seq.index acc (2 * i) == lo /\
Seq.index acc (2 * i + 1) == hi) /\
(forall (i:nat{k <= i /\ i < aLen}).
Seq.index acc (2 * i) == Seq.index acc0 (2 * i) /\
Seq.index acc (2 * i + 1) == Seq.index acc0 (2 * i + 1)))
let bn_sqr_diag_lemma #t #aLen a k =
let _ = bn_sqr_diag_inductive a k in ()
val bn_sqr_diag_eq:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k < aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
slice acc1 0 (2 * k) == slice acc2 0 (2 * k))
let bn_sqr_diag_eq #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati k (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (k + 1) (bn_sqr_diag_f a) acc0 in
let aux (i:nat{i < 2 * k}) : Lemma (Seq.index acc1 i == Seq.index acc2 i) =
let i2 = i / 2 in
bn_sqr_diag_lemma a k;
bn_sqr_diag_lemma a (k + 1);
assert
(Seq.index acc1 (2 * i2) == Seq.index acc2 (2 * i2) /\
Seq.index acc1 (2 * i2 + 1) == Seq.index acc2 (2 * i2 + 1));
Math.Lemmas.euclidean_division_definition i 2;
assert (Seq.index acc1 i == Seq.index acc2 i) in
Classical.forall_intro aux;
eq_intro (slice acc1 0 (2 * k)) (slice acc2 0 (2 * k))
val bn_sqr_diag_loop_step:
#t:limb_t
-> #aLen:size_pos{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_sqr_diag_loop_step #t #aLen a i =
let pbits = bits t in
let acc0 = create (aLen + aLen) (uint #t 0) in
let acc1 : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) acc0 in
let acc2 : lbignum t (aLen + aLen) = repeati (i - 1) (bn_sqr_diag_f a) acc0 in
bn_eval_unfold_i acc1 (i + i);
bn_eval_unfold_i acc1 (i + i - 1);
//assert (eval_ (aLen + aLen) acc1 (i + i) ==
//eval_ (aLen + aLen) acc1 (i + i - 2) + v acc1.[i + i - 2] * (pow2 (p * (i + i - 2))) + v acc1.[i + i - 1] * pow2 (p * (i + i - 1)));
calc (==) {
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * pow2 (pbits * (i + i - 1));
(==) { Math.Lemmas.pow2_plus (pbits * (i + i - 2)) pbits }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + v acc1.[i + i - 1] * (pow2 (pbits * (i + i - 2)) * pow2 pbits);
(==) { Math.Lemmas.paren_mul_right (v acc1.[i + i - 1]) (pow2 pbits) (pow2 (pbits * (i + i - 2))) }
v acc1.[i + i - 2] * pow2 (pbits * (i + i - 2)) + (v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { Math.Lemmas.distributivity_add_left (v acc1.[i + i - 2]) (v acc1.[i + i - 1] * pow2 pbits) (pow2 (pbits * (i + i - 2))) }
(v acc1.[i + i - 2] + v acc1.[i + i - 1] * pow2 pbits) * pow2 (pbits * (i + i - 2));
(==) { bn_sqr_diag_lemma a i }
v a.[i - 1] * v a.[i - 1] * pow2 (pbits * (i + i - 2));
};
bn_sqr_diag_eq a (i - 1);
bn_eval_extensionality_j acc1 acc2 (i + i - 2);
assert (eval_ (aLen + aLen) acc1 (i + i) ==
eval_ (aLen + aLen) acc2 (i + i - 2) + v a.[i - 1] * v a.[i - 1] * (pow2 (pbits * (i + i - 2))))
val bn_sqr_f_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> j:size_nat{j < aLen}
-> acc:lbignum t (aLen + aLen)
-> i:nat{j + j < i /\ i < aLen + aLen} ->
Lemma (let res = bn_sqr_f a j acc in
eval_ (aLen + aLen) res (j + j + 1) ==
eval_ (aLen + aLen) acc (j + j) + eval_ aLen a j * v a.[j] * pow2 (bits t * j) /\
Seq.index res i == Seq.index acc i)
let bn_sqr_f_lemma #t #aLen a j acc i =
let resLen = aLen + aLen in
let c, acc' = SM.bn_mul1_add_in_place #t #j (sub a 0 j) a.[j] (sub acc j j) in
let acc1 = update_sub acc j j acc' in
assert (index acc1 i == index acc i);
let res = acc1.[j + j] <- c in
assert (index res i == index acc i);
SM.bn_mul1_lshift_add_lemma #t #j #resLen (sub a 0 j) a.[j] j acc;
bn_eval_extensionality_j acc1 res (j + j);
bn_eval_unfold_i res (j + j + 1);
bn_eval_extensionality_j a (sub a 0 j) j
val bn_sqr_inductive:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Pure (lbignum t (aLen + aLen))
(requires True)
(ensures fun res ->
(let acc0 = create (aLen + aLen) (uint #t 0) in
res == repeati k (bn_sqr_f a) acc0 /\
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index res i == Seq.index acc0 i)))
let bn_sqr_inductive #t #aLen a k =
let acc0 = create (aLen + aLen) (uint #t 0) in
eq_repeati0 k (bn_sqr_f a) acc0;
repeati_inductive #(lbignum t (aLen + aLen)) k
(fun i acci ->
acci == repeati i (bn_sqr_f a) acc0 /\
(forall (i0:nat{i + i < i0 /\ i0 < aLen + aLen}). Seq.index acci i0 == Seq.index acc0 i0))
(fun i acci ->
unfold_repeati k (bn_sqr_f a) acc0 i;
let acc1 = bn_sqr_f a i acci in
assert (acc1 == repeati (i + 1) (bn_sqr_f a) acc0);
Classical.forall_intro (bn_sqr_f_lemma a i acci);
assert (forall (i0:nat{i + i + 2 < i0 /\ i0 < aLen + aLen}). Seq.index acc1 i0 == Seq.index acc0 i0);
acc1)
acc0
val bn_sqr_tail:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> k:nat{k <= aLen} ->
Lemma (let acc0 = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati k (bn_sqr_f a) acc0 in
(forall (i:nat{k + k < i /\ i < aLen + aLen}). Seq.index acc i == uint #t 0))
let bn_sqr_tail #t #aLen a k =
let _ = bn_sqr_inductive a k in ()
val square_of_sum: a:nat -> b:nat -> Lemma ((a + b) * (a + b) == a * a + 2 * a * b + b * b)
let square_of_sum a b = ()
val bn_eval_square:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:pos{i <= aLen} ->
Lemma (eval_ aLen a i * eval_ aLen a i == eval_ aLen a (i - 1) * eval_ aLen a (i - 1) +
2 * eval_ aLen a (i - 1) * v a.[i - 1] * pow2 (bits t * (i - 1)) + v a.[i - 1] * v a.[i - 1] * pow2 (bits t * (i + i - 2)))
let bn_eval_square #t #aLen a i =
let e1 = eval_ aLen a (i - 1) in
let p1 = pow2 (bits t * (i - 1)) in
let p2 = pow2 (bits t * (i + i - 2)) in
calc (==) {
eval_ aLen a i * eval_ aLen a i;
(==) { bn_eval_unfold_i a i }
(e1 + v a.[i - 1] * p1) * (e1 + v a.[i - 1] * p1);
(==) { square_of_sum e1 (v a.[i - 1] * p1) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + (v a.[i - 1] * p1) * (v a.[i - 1] * p1);
(==) { Math.Lemmas.paren_mul_right (v a.[i - 1]) p1 (v a.[i - 1] * p1); Math.Lemmas.paren_mul_right p1 p1 (v a.[i - 1]) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * (p1 * p1 * v a.[i - 1]);
(==) { Math.Lemmas.pow2_plus (bits t * (i - 1)) (bits t * (i - 1)) }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * (p2 * v a.[i - 1]);
(==) { Math.Lemmas.paren_mul_right (v a.[i - 1]) (v a.[i - 1]) p2 }
e1 * e1 + 2 * e1 * (v a.[i - 1] * p1) + v a.[i - 1] * v a.[i - 1] * p2;
(==) { Math.Lemmas.paren_mul_right (2 * e1) (v a.[i - 1]) p1 }
e1 * e1 + 2 * e1 * v a.[i - 1] * p1 + v a.[i - 1] * v a.[i - 1] * p2;
}
val bn_sqr_loop_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i <= aLen} ->
Lemma (let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i) == eval_ aLen a i * eval_ aLen a i) | false | false | Hacl.Spec.Bignum.Squaring.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 0,
"initial_ifuel": 0,
"max_fuel": 0,
"max_ifuel": 0,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": false,
"smtencoding_l_arith_repr": "boxwrap",
"smtencoding_nl_arith_repr": "boxwrap",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [],
"z3refresh": false,
"z3rlimit": 50,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val bn_sqr_loop_lemma:
#t:limb_t
-> #aLen:size_nat{aLen + aLen <= max_size_t}
-> a:lbignum t aLen
-> i:nat{i <= aLen} ->
Lemma (let resLen = aLen + aLen in
let bn_zero = create (aLen + aLen) (uint #t 0) in
let acc : lbignum t (aLen + aLen) = repeati i (bn_sqr_f a) bn_zero in
let tmp : lbignum t (aLen + aLen) = repeati i (bn_sqr_diag_f a) bn_zero in
2 * eval_ resLen acc (i + i) + eval_ resLen tmp (i + i) == eval_ aLen a i * eval_ aLen a i) | [
"recursion"
] | Hacl.Spec.Bignum.Squaring.bn_sqr_loop_lemma | {
"file_name": "code/bignum/Hacl.Spec.Bignum.Squaring.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Hacl.Spec.Bignum.Definitions.lbignum t aLen -> i: Prims.nat{i <= aLen}
-> FStar.Pervasives.Lemma
(ensures
(let resLen = aLen + aLen in
let bn_zero = Lib.Sequence.create (aLen + aLen) (Lib.IntTypes.uint 0) in
let acc = Lib.LoopCombinators.repeati i (Hacl.Spec.Bignum.Squaring.bn_sqr_f a) bn_zero in
let tmp =
Lib.LoopCombinators.repeati i (Hacl.Spec.Bignum.Squaring.bn_sqr_diag_f a) bn_zero
in
2 * Hacl.Spec.Bignum.Definitions.eval_ resLen acc (i + i) +
Hacl.Spec.Bignum.Definitions.eval_ resLen tmp (i + i) ==
Hacl.Spec.Bignum.Definitions.eval_ aLen a i * Hacl.Spec.Bignum.Definitions.eval_ aLen a i)) | {
"end_col": 13,
"end_line": 385,
"start_col": 40,
"start_line": 342
} |
Prims.Tot | val valid_mem128_reg (r: reg) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap) | val valid_mem128_reg (r: reg) (s: state) : bool
let valid_mem128_reg (r: reg) (s: state) : bool = | false | null | false | valid_addr128 (eval_reg r s) (heap_get s.ms_heap) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.reg",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.MachineHeap_s.valid_addr128",
"Vale.PPC64LE.Semantics_s.eval_reg",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_mem128_reg (r: reg) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_mem128_reg | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.PPC64LE.Machine_s.reg -> s: Vale.PPC64LE.Machine_s.state -> Prims.bool | {
"end_col": 51,
"end_line": 339,
"start_col": 2,
"start_line": 339
} |
Prims.Tot | val eval_maddr (m: maddr) (s: state) : int | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset | val eval_maddr (m: maddr) (s: state) : int
let eval_maddr (m: maddr) (s: state) : int = | false | null | false | eval_reg m.address s + m.offset | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.maddr",
"Vale.PPC64LE.Machine_s.state",
"Prims.op_Addition",
"Vale.PPC64LE.Semantics_s.eval_reg",
"Vale.PPC64LE.Machine_s.__proj__Mkmaddr__item__address",
"Vale.PPC64LE.Machine_s.__proj__Mkmaddr__item__offset",
"Prims.int"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr] | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_maddr (m: maddr) (s: state) : int | [] | Vale.PPC64LE.Semantics_s.eval_maddr | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | m: Vale.PPC64LE.Machine_s.maddr -> s: Vale.PPC64LE.Machine_s.state -> Prims.int | {
"end_col": 33,
"end_line": 263,
"start_col": 2,
"start_line": 263
} |
Prims.Tot | val eval_reg (r: reg) (s: state) : nat64 | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_reg (r:reg) (s:state) : nat64 = s.regs r | val eval_reg (r: reg) (s: state) : nat64
let eval_reg (r: reg) (s: state) : nat64 = | false | null | false | s.regs r | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.reg",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.Def.Types_s.nat64"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_reg (r: reg) (s: state) : nat64 | [] | Vale.PPC64LE.Semantics_s.eval_reg | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.PPC64LE.Machine_s.reg -> s: Vale.PPC64LE.Machine_s.state -> Vale.Def.Types_s.nat64 | {
"end_col": 56,
"end_line": 102,
"start_col": 48,
"start_line": 102
} |
Prims.Tot | val valid_mem (m: maddr) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap) | val valid_mem (m: maddr) (s: state) : bool
let valid_mem (m: maddr) (s: state) : bool = | false | null | false | valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.maddr",
"Vale.PPC64LE.Machine_s.state",
"Prims.op_AmpAmp",
"Vale.PPC64LE.Machine_s.valid_maddr_offset64",
"Vale.PPC64LE.Machine_s.__proj__Mkmaddr__item__offset",
"Vale.Arch.MachineHeap_s.valid_addr64",
"Vale.PPC64LE.Semantics_s.eval_maddr",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_mem (m: maddr) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_mem | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | m: Vale.PPC64LE.Machine_s.maddr -> s: Vale.PPC64LE.Machine_s.state -> Prims.bool | {
"end_col": 85,
"end_line": 330,
"start_col": 2,
"start_line": 330
} |
Prims.Tot | val valid_mem128 (r i: reg) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap) | val valid_mem128 (r i: reg) (s: state) : bool
let valid_mem128 (r i: reg) (s: state) : bool = | false | null | false | valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.reg",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.MachineHeap_s.valid_addr128",
"Prims.op_Addition",
"Vale.PPC64LE.Semantics_s.eval_reg",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_mem128 (r i: reg) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_mem128 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.PPC64LE.Machine_s.reg -> i: Vale.PPC64LE.Machine_s.reg -> s: Vale.PPC64LE.Machine_s.state
-> Prims.bool | {
"end_col": 66,
"end_line": 336,
"start_col": 2,
"start_line": 336
} |
Prims.Tot | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let st (a:Type) = state -> a & state | let st (a: Type) = | false | null | false | state -> a & state | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"FStar.Pervasives.Native.tuple2"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca } | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val st : a: Type -> Type | [] | Vale.PPC64LE.Semantics_s.st | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | a: Type -> Type | {
"end_col": 36,
"end_line": 374,
"start_col": 18,
"start_line": 374
} |
|
Prims.Tot | val return (#a: Type) (x: a) : st a | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let return (#a:Type) (x:a) :st a =
fun s -> x, s | val return (#a: Type) (x: a) : st a
let return (#a: Type) (x: a) : st a = | false | null | false | fun s -> x, s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"FStar.Pervasives.Native.Mktuple2",
"FStar.Pervasives.Native.tuple2",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold | false | false | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val return (#a: Type) (x: a) : st a | [] | Vale.PPC64LE.Semantics_s.return | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | x: a -> Vale.PPC64LE.Semantics_s.st a | {
"end_col": 15,
"end_line": 378,
"start_col": 2,
"start_line": 378
} |
Prims.Tot | val xer_ov (xer: xer_t) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let xer_ov (xer:xer_t) : bool =
xer.ov | val xer_ov (xer: xer_t) : bool
let xer_ov (xer: xer_t) : bool = | false | null | false | xer.ov | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.xer_t",
"Vale.PPC64LE.Machine_s.__proj__Mkxer_t__item__ov",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1 | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val xer_ov (xer: xer_t) : bool | [] | Vale.PPC64LE.Semantics_s.xer_ov | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | xer: Vale.PPC64LE.Machine_s.xer_t -> Prims.bool | {
"end_col": 8,
"end_line": 362,
"start_col": 2,
"start_line": 362
} |
Prims.Tot | val eval_mem (ptr: int) (s: state) : nat64 | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap) | val eval_mem (ptr: int) (s: state) : nat64
let eval_mem (ptr: int) (s: state) : nat64 = | false | null | false | get_heap_val64 ptr (heap_get s.ms_heap) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.MachineHeap_s.get_heap_val64",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.Def.Types_s.nat64"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_mem (ptr: int) (s: state) : nat64 | [] | Vale.PPC64LE.Semantics_s.eval_mem | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> s: Vale.PPC64LE.Machine_s.state -> Vale.Def.Types_s.nat64 | {
"end_col": 89,
"end_line": 104,
"start_col": 50,
"start_line": 104
} |
Prims.Tot | val run (f: st unit) (s: state) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let run (f:st unit) (s:state) : state = snd (f s) | val run (f: st unit) (s: state) : state
let run (f: st unit) (s: state) : state = | false | null | false | snd (f s) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Semantics_s.st",
"Prims.unit",
"Vale.PPC64LE.Machine_s.state",
"FStar.Pervasives.Native.snd"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold
let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val run (f: st unit) (s: state) : state | [] | Vale.PPC64LE.Semantics_s.run | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | f: Vale.PPC64LE.Semantics_s.st Prims.unit -> s: Vale.PPC64LE.Machine_s.state
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 49,
"end_line": 408,
"start_col": 40,
"start_line": 408
} |
Prims.Tot | val fail:st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let fail :st unit =
fun s -> (), {s with ok=false} | val fail:st unit
let fail:st unit = | false | null | false | fun s -> (), { s with ok = false } | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"FStar.Pervasives.Native.Mktuple2",
"Prims.unit",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"FStar.Pervasives.Native.tuple2"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val fail:st unit | [] | Vale.PPC64LE.Semantics_s.fail | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 32,
"end_line": 397,
"start_col": 2,
"start_line": 397
} |
Prims.Tot | val op_let_Star (#a #b: Type) (m: st a) (f: (a -> st b)) : st b | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok} | val op_let_Star (#a #b: Type) (m: st a) (f: (a -> st b)) : st b
let op_let_Star (#a #b: Type) (m: st a) (f: (a -> st b)) : st b = | false | null | false | fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, { s2 with ok = s0.ok && s1.ok && s2.ok } | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Semantics_s.st",
"Vale.PPC64LE.Machine_s.state",
"FStar.Pervasives.Native.Mktuple2",
"Vale.PPC64LE.Machine_s.Mkstate",
"Prims.op_AmpAmp",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"FStar.Pervasives.Native.tuple2"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold | false | false | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val op_let_Star (#a #b: Type) (m: st a) (f: (a -> st b)) : st b | [] | Vale.PPC64LE.Semantics_s.op_let_Star | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | m: Vale.PPC64LE.Semantics_s.st a -> f: (_: a -> Vale.PPC64LE.Semantics_s.st b)
-> Vale.PPC64LE.Semantics_s.st b | {
"end_col": 41,
"end_line": 385,
"start_col": 0,
"start_line": 382
} |
Prims.Tot | val valid_dst_stack64 (r1: nat64) (ptr: int) (st: machine_stack) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1 | val valid_dst_stack64 (r1: nat64) (ptr: int) (st: machine_stack) : bool
let valid_dst_stack64 (r1: nat64) (ptr: int) (st: machine_stack) : bool = | false | null | false | let Machine_stack init_r1 mem = st in
ptr >= r1 && ptr + 8 <= init_r1 | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.Def.Types_s.nat64",
"Prims.int",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Prims.op_AmpAmp",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_dst_stack64 (r1: nat64) (ptr: int) (st: machine_stack) : bool | [] | Vale.PPC64LE.Semantics_s.valid_dst_stack64 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r1: Vale.Def.Types_s.nat64 -> ptr: Prims.int -> st: Vale.PPC64LE.Machine_s.machine_stack
-> Prims.bool | {
"end_col": 33,
"end_line": 292,
"start_col": 70,
"start_line": 289
} |
Prims.Tot | val update_stack128_and_taint (ptr: int) (v: quad32) (s: state) (t: taint) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
} | val update_stack128_and_taint (ptr: int) (v: quad32) (s: state) (t: taint) : state
let update_stack128_and_taint (ptr: int) (v: quad32) (s: state) (t: taint) : state = | false | null | false | let Machine_stack init_r1 mem = s.ms_stack in
{
s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
} | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.Def.Types_s.quad32",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.HeapTypes_s.taint",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Semantics_s.update_stack128'",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Semantics_s.update_n",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Vale.PPC64LE.Machine_s.machine_stack"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
} | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_stack128_and_taint (ptr: int) (v: quad32) (s: state) (t: taint) : state | [] | Vale.PPC64LE.Semantics_s.update_stack128_and_taint | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
ptr: Prims.int ->
v: Vale.Def.Types_s.quad32 ->
s: Vale.PPC64LE.Machine_s.state ->
t: Vale.Arch.HeapTypes_s.taint
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 3,
"end_line": 238,
"start_col": 80,
"start_line": 233
} |
Prims.Tot | val free_stack' (start finish: int) (st: machine_stack) : machine_stack | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem | val free_stack' (start finish: int) (st: machine_stack) : machine_stack
let free_stack' (start finish: int) (st: machine_stack) : machine_stack = | false | null | false | let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.PPC64LE.Machine_s.Machine_stack",
"Vale.Def.Words_s.nat8",
"FStar.Map.restrict",
"FStar.Set.set",
"Vale.Lib.Set.remove_between",
"FStar.Map.domain"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val free_stack' (start finish: int) (st: machine_stack) : machine_stack | [] | Vale.PPC64LE.Semantics_s.free_stack' | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | start: Prims.int -> finish: Prims.int -> st: Vale.PPC64LE.Machine_s.machine_stack
-> Vale.PPC64LE.Machine_s.machine_stack | {
"end_col": 31,
"end_line": 327,
"start_col": 71,
"start_line": 320
} |
Prims.Tot | val update_reg (r: reg) (v: nat64) : st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_reg (r:reg) (v:nat64) :st unit =
let* s = get in
set (update_reg' r v s) | val update_reg (r: reg) (v: nat64) : st unit
let update_reg (r: reg) (v: nat64) : st unit = | false | null | false | let* s = get in
set (update_reg' r v s) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.reg",
"Vale.Def.Types_s.nat64",
"Vale.PPC64LE.Semantics_s.op_let_Star",
"Vale.PPC64LE.Machine_s.state",
"Prims.unit",
"Vale.PPC64LE.Semantics_s.get",
"Vale.PPC64LE.Semantics_s.set",
"Vale.PPC64LE.Semantics_s.update_reg'",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold
let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail
unfold
let run (f:st unit) (s:state) : state = snd (f s) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_reg (r: reg) (v: nat64) : st unit | [] | Vale.PPC64LE.Semantics_s.update_reg | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.PPC64LE.Machine_s.reg -> v: Vale.Def.Types_s.nat64 -> Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 25,
"end_line": 412,
"start_col": 2,
"start_line": 411
} |
Prims.Tot | val update_vec (vr: vec) (v: quad32) : st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_vec (vr:vec) (v:quad32) :st unit =
let* s = get in
set (update_vec' vr v s) | val update_vec (vr: vec) (v: quad32) : st unit
let update_vec (vr: vec) (v: quad32) : st unit = | false | null | false | let* s = get in
set (update_vec' vr v s) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.vec",
"Vale.Def.Types_s.quad32",
"Vale.PPC64LE.Semantics_s.op_let_Star",
"Vale.PPC64LE.Machine_s.state",
"Prims.unit",
"Vale.PPC64LE.Semantics_s.get",
"Vale.PPC64LE.Semantics_s.set",
"Vale.PPC64LE.Semantics_s.update_vec'",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold
let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail
unfold
let run (f:st unit) (s:state) : state = snd (f s)
let update_reg (r:reg) (v:nat64) :st unit =
let* s = get in
set (update_reg' r v s) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_vec (vr: vec) (v: quad32) : st unit | [] | Vale.PPC64LE.Semantics_s.update_vec | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | vr: Vale.PPC64LE.Machine_s.vec -> v: Vale.Def.Types_s.quad32
-> Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 26,
"end_line": 416,
"start_col": 2,
"start_line": 415
} |
Prims.Tot | val valid_mem64 (r: reg) (i: int) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap) | val valid_mem64 (r: reg) (i: int) (s: state) : bool
let valid_mem64 (r: reg) (i: int) (s: state) : bool = | false | null | false | valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.reg",
"Prims.int",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.MachineHeap_s.valid_addr64",
"Prims.op_Addition",
"Vale.PPC64LE.Semantics_s.eval_reg",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_mem64 (r: reg) (i: int) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_mem64 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.PPC64LE.Machine_s.reg -> i: Prims.int -> s: Vale.PPC64LE.Machine_s.state -> Prims.bool | {
"end_col": 54,
"end_line": 333,
"start_col": 2,
"start_line": 333
} |
Prims.Tot | val valid_dst_stack64_addr (m: maddr) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack | val valid_dst_stack64_addr (m: maddr) (s: state) : bool
let valid_dst_stack64_addr (m: maddr) (s: state) : bool = | false | null | false | valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.maddr",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Semantics_s.valid_dst_stack64",
"Vale.PPC64LE.Semantics_s.eval_reg",
"Vale.PPC64LE.Semantics_s.eval_maddr",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1 | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_dst_stack64_addr (m: maddr) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_dst_stack64_addr | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | m: Vale.PPC64LE.Machine_s.maddr -> s: Vale.PPC64LE.Machine_s.state -> Prims.bool | {
"end_col": 62,
"end_line": 301,
"start_col": 2,
"start_line": 301
} |
Prims.Tot | val valid_src_stack64 (ptr: int) (st: machine_stack) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem | val valid_src_stack64 (ptr: int) (st: machine_stack) : bool
let valid_src_stack64 (ptr: int) (st: machine_stack) : bool = | false | null | false | let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.Arch.MachineHeap_s.valid_addr64",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
} | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_src_stack64 (ptr: int) (st: machine_stack) : bool | [] | Vale.PPC64LE.Semantics_s.valid_src_stack64 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> st: Vale.PPC64LE.Machine_s.machine_stack -> Prims.bool | {
"end_col": 22,
"end_line": 243,
"start_col": 59,
"start_line": 241
} |
Prims.Tot | val eval_vec (v: vec) (s: state) : quad32 | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_vec (v:vec) (s:state) : quad32 = s.vecs v | val eval_vec (v: vec) (s: state) : quad32
let eval_vec (v: vec) (s: state) : quad32 = | false | null | false | s.vecs v | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.vec",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.Def.Types_s.quad32"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_vec (v: vec) (s: state) : quad32 | [] | Vale.PPC64LE.Semantics_s.eval_vec | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | v: Vale.PPC64LE.Machine_s.vec -> s: Vale.PPC64LE.Machine_s.state -> Vale.Def.Types_s.quad32 | {
"end_col": 57,
"end_line": 103,
"start_col": 49,
"start_line": 103
} |
Prims.Tot | val update_xer (new_xer: xer_t) : st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_xer (new_xer:xer_t) :st unit =
let* s = get in
set ( { s with xer = new_xer } ) | val update_xer (new_xer: xer_t) : st unit
let update_xer (new_xer: xer_t) : st unit = | false | null | false | let* s = get in
set ({ s with xer = new_xer }) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.xer_t",
"Vale.PPC64LE.Semantics_s.op_let_Star",
"Vale.PPC64LE.Machine_s.state",
"Prims.unit",
"Vale.PPC64LE.Semantics_s.get",
"Vale.PPC64LE.Semantics_s.set",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold
let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail
unfold
let run (f:st unit) (s:state) : state = snd (f s)
let update_reg (r:reg) (v:nat64) :st unit =
let* s = get in
set (update_reg' r v s)
let update_vec (vr:vec) (v:quad32) :st unit =
let* s = get in
set (update_vec' vr v s) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_xer (new_xer: xer_t) : st unit | [] | Vale.PPC64LE.Semantics_s.update_xer | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | new_xer: Vale.PPC64LE.Machine_s.xer_t -> Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 34,
"end_line": 420,
"start_col": 2,
"start_line": 419
} |
Prims.Tot | val update_r1 (i: int) : st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_r1 (i:int) : st unit =
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
check (fun s -> i >= s.ms_stack.initial_r1 - 65536);*
check (fun s -> i <= s.ms_stack.initial_r1);*
let* s = get in
set (update_r1' i s) | val update_r1 (i: int) : st unit
let update_r1 (i: int) : st unit = | false | null | false | let* _ = check (fun s -> i >= s.ms_stack.initial_r1 - 65536) in
let* _ = check (fun s -> i <= s.ms_stack.initial_r1) in
let* s = get in
set (update_r1' i s) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Semantics_s.op_let_Star",
"Prims.unit",
"Vale.PPC64LE.Semantics_s.check",
"Vale.PPC64LE.Machine_s.state",
"Prims.op_GreaterThanOrEqual",
"Prims.op_Subtraction",
"Vale.PPC64LE.Machine_s.__proj__Machine_stack__item__initial_r1",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Prims.bool",
"Prims.op_LessThanOrEqual",
"Vale.PPC64LE.Semantics_s.get",
"Vale.PPC64LE.Semantics_s.set",
"Vale.PPC64LE.Semantics_s.update_r1'",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold
let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail
unfold
let run (f:st unit) (s:state) : state = snd (f s)
let update_reg (r:reg) (v:nat64) :st unit =
let* s = get in
set (update_reg' r v s)
let update_vec (vr:vec) (v:quad32) :st unit =
let* s = get in
set (update_vec' vr v s)
let update_xer (new_xer:xer_t) :st unit =
let* s = get in
set ( { s with xer = new_xer } )
let update_cr0 (new_cr0:cr0_t) :st unit =
let* s = get in
set ( { s with cr0 = new_cr0 } )
unfold
let update_r1 (i:int) : st unit = | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_r1 (i: int) : st unit | [] | Vale.PPC64LE.Semantics_s.update_r1 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | i: Prims.int -> Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 21,
"end_line": 432,
"start_col": 1,
"start_line": 429
} |
Prims.Tot | val check (valid: (state -> bool)) : st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail | val check (valid: (state -> bool)) : st unit
let check (valid: (state -> bool)) : st unit = | false | null | false | let* s = get in
if valid s then return () else fail | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"Prims.bool",
"Vale.PPC64LE.Semantics_s.op_let_Star",
"Prims.unit",
"Vale.PPC64LE.Semantics_s.get",
"Vale.PPC64LE.Semantics_s.return",
"Vale.PPC64LE.Semantics_s.fail",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val check (valid: (state -> bool)) : st unit | [] | Vale.PPC64LE.Semantics_s.check | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | valid: (_: Vale.PPC64LE.Machine_s.state -> Prims.bool) -> Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 8,
"end_line": 405,
"start_col": 2,
"start_line": 401
} |
Prims.Tot | val eval_stack (ptr: int) (s: machine_stack) : nat64 | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem | val eval_stack (ptr: int) (s: machine_stack) : nat64
let eval_stack (ptr: int) (s: machine_stack) : nat64 = | false | null | false | let Machine_stack _ mem = s in
get_heap_val64 ptr mem | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.Arch.MachineHeap_s.get_heap_val64",
"Vale.Def.Types_s.nat64"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_stack (ptr: int) (s: machine_stack) : nat64 | [] | Vale.PPC64LE.Semantics_s.eval_stack | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> s: Vale.PPC64LE.Machine_s.machine_stack -> Vale.Def.Types_s.nat64 | {
"end_col": 24,
"end_line": 109,
"start_col": 59,
"start_line": 107
} |
Prims.Tot | val set (s: state) : st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let set (s:state) :st unit =
fun _ -> (), s | val set (s: state) : st unit
let set (s: state) : st unit = | false | null | false | fun _ -> (), s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"FStar.Pervasives.Native.Mktuple2",
"Prims.unit",
"FStar.Pervasives.Native.tuple2",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val set (s: state) : st unit | [] | Vale.PPC64LE.Semantics_s.set | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | s: Vale.PPC64LE.Machine_s.state -> Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 16,
"end_line": 393,
"start_col": 2,
"start_line": 393
} |
Prims.Tot | val valid_dst_stack128 (r1: nat64) (ptr: int) (st: machine_stack) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1 | val valid_dst_stack128 (r1: nat64) (ptr: int) (st: machine_stack) : bool
let valid_dst_stack128 (r1: nat64) (ptr: int) (st: machine_stack) : bool = | false | null | false | let Machine_stack init_r1 mem = st in
ptr >= r1 && ptr + 16 <= init_r1 | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.Def.Types_s.nat64",
"Prims.int",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Prims.op_AmpAmp",
"Prims.op_LessThanOrEqual",
"Prims.op_Addition",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1 | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_dst_stack128 (r1: nat64) (ptr: int) (st: machine_stack) : bool | [] | Vale.PPC64LE.Semantics_s.valid_dst_stack128 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r1: Vale.Def.Types_s.nat64 -> ptr: Prims.int -> st: Vale.PPC64LE.Machine_s.machine_stack
-> Prims.bool | {
"end_col": 36,
"end_line": 298,
"start_col": 71,
"start_line": 295
} |
Prims.Tot | val update_stack_and_taint (ptr: int) (v: nat64) (s: state) (t: taint) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
} | val update_stack_and_taint (ptr: int) (v: nat64) (s: state) (t: taint) : state
let update_stack_and_taint (ptr: int) (v: nat64) (s: state) (t: taint) : state = | false | null | false | let Machine_stack init_r1 mem = s.ms_stack in
{
s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t
} | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.Def.Types_s.nat64",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.HeapTypes_s.taint",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Semantics_s.update_stack64'",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Semantics_s.update_n",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Vale.PPC64LE.Machine_s.machine_stack"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_stack_and_taint (ptr: int) (v: nat64) (s: state) (t: taint) : state | [] | Vale.PPC64LE.Semantics_s.update_stack_and_taint | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
ptr: Prims.int ->
v: Vale.Def.Types_s.nat64 ->
s: Vale.PPC64LE.Machine_s.state ->
t: Vale.Arch.HeapTypes_s.taint
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 3,
"end_line": 231,
"start_col": 76,
"start_line": 226
} |
Prims.Tot | val valid_mem128' (m: maddr) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap) | val valid_mem128' (m: maddr) (s: state) : bool
let valid_mem128' (m: maddr) (s: state) : bool = | false | null | false | valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.maddr",
"Vale.PPC64LE.Machine_s.state",
"Prims.op_AmpAmp",
"Vale.PPC64LE.Machine_s.valid_maddr_offset128",
"Vale.PPC64LE.Machine_s.__proj__Mkmaddr__item__offset",
"Vale.Arch.MachineHeap_s.valid_addr128",
"Vale.PPC64LE.Semantics_s.eval_maddr",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_mem128' (m: maddr) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_mem128' | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | m: Vale.PPC64LE.Machine_s.maddr -> s: Vale.PPC64LE.Machine_s.state -> Prims.bool | {
"end_col": 87,
"end_line": 342,
"start_col": 2,
"start_line": 342
} |
Prims.Tot | val valid_dst_stack128_addr (m: maddr) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack | val valid_dst_stack128_addr (m: maddr) (s: state) : bool
let valid_dst_stack128_addr (m: maddr) (s: state) : bool = | false | null | false | valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.maddr",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Semantics_s.valid_dst_stack128",
"Vale.PPC64LE.Semantics_s.eval_reg",
"Vale.PPC64LE.Semantics_s.eval_maddr",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_dst_stack128_addr (m: maddr) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_dst_stack128_addr | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | m: Vale.PPC64LE.Machine_s.maddr -> s: Vale.PPC64LE.Machine_s.state -> Prims.bool | {
"end_col": 63,
"end_line": 304,
"start_col": 2,
"start_line": 304
} |
Prims.Tot | val update_stack128' (ptr: int) (v: quad32) (s: machine_stack) : machine_stack | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem | val update_stack128' (ptr: int) (v: quad32) (s: machine_stack) : machine_stack
let update_stack128' (ptr: int) (v: quad32) (s: machine_stack) : machine_stack = | false | null | false | let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.Def.Types_s.quad32",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.PPC64LE.Machine_s.Machine_stack",
"Vale.Arch.MachineHeap_s.machine_heap",
"Vale.Arch.MachineHeap_s.update_heap128"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_stack128' (ptr: int) (v: quad32) (s: machine_stack) : machine_stack | [] | Vale.PPC64LE.Semantics_s.update_stack128' | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> v: Vale.Def.Types_s.quad32 -> s: Vale.PPC64LE.Machine_s.machine_stack
-> Vale.PPC64LE.Machine_s.machine_stack | {
"end_col": 27,
"end_line": 224,
"start_col": 77,
"start_line": 221
} |
Prims.Tot | val free_stack (start finish: int) : st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let free_stack (start finish:int) : st unit =
let* s = get in
set ( { s with ms_stack = free_stack' start finish s.ms_stack} ) | val free_stack (start finish: int) : st unit
let free_stack (start finish: int) : st unit = | false | null | false | let* s = get in
set ({ s with ms_stack = free_stack' start finish s.ms_stack }) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Semantics_s.op_let_Star",
"Vale.PPC64LE.Machine_s.state",
"Prims.unit",
"Vale.PPC64LE.Semantics_s.get",
"Vale.PPC64LE.Semantics_s.set",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Semantics_s.free_stack'",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold
let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail
unfold
let run (f:st unit) (s:state) : state = snd (f s)
let update_reg (r:reg) (v:nat64) :st unit =
let* s = get in
set (update_reg' r v s)
let update_vec (vr:vec) (v:quad32) :st unit =
let* s = get in
set (update_vec' vr v s)
let update_xer (new_xer:xer_t) :st unit =
let* s = get in
set ( { s with xer = new_xer } )
let update_cr0 (new_cr0:cr0_t) :st unit =
let* s = get in
set ( { s with cr0 = new_cr0 } )
unfold
let update_r1 (i:int) : st unit =
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
check (fun s -> i >= s.ms_stack.initial_r1 - 65536);*
check (fun s -> i <= s.ms_stack.initial_r1);*
let* s = get in
set (update_r1' i s) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val free_stack (start finish: int) : st unit | [] | Vale.PPC64LE.Semantics_s.free_stack | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | start: Prims.int -> finish: Prims.int -> Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 66,
"end_line": 436,
"start_col": 2,
"start_line": 435
} |
Prims.Tot | val get:st state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let get :st state =
fun s -> s, s | val get:st state
let get:st state = | false | null | false | fun s -> s, s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"FStar.Pervasives.Native.Mktuple2",
"FStar.Pervasives.Native.tuple2"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val get:st state | [] | Vale.PPC64LE.Semantics_s.get | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | Vale.PPC64LE.Semantics_s.st Vale.PPC64LE.Machine_s.state | {
"end_col": 15,
"end_line": 389,
"start_col": 2,
"start_line": 389
} |
Prims.Tot | val valid_mem_and_taint (m: maddr) (t: taint) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t | val valid_mem_and_taint (m: maddr) (t: taint) (s: state) : bool
let valid_mem_and_taint (m: maddr) (t: taint) (s: state) : bool = | false | null | false | let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) &&
match_n ptr 8 (heap_taint s.ms_heap) t | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.maddr",
"Vale.Arch.HeapTypes_s.taint",
"Vale.PPC64LE.Machine_s.state",
"Prims.op_AmpAmp",
"Vale.PPC64LE.Machine_s.valid_maddr_offset64",
"Vale.PPC64LE.Machine_s.__proj__Mkmaddr__item__offset",
"Vale.Arch.MachineHeap_s.valid_addr64",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Semantics_s.match_n",
"Vale.Arch.Heap.heap_taint",
"Prims.int",
"Vale.PPC64LE.Semantics_s.eval_maddr",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_mem_and_taint (m: maddr) (t: taint) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_mem_and_taint | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | m: Vale.PPC64LE.Machine_s.maddr -> t: Vale.Arch.HeapTypes_s.taint -> s: Vale.PPC64LE.Machine_s.state
-> Prims.bool | {
"end_col": 114,
"end_line": 346,
"start_col": 62,
"start_line": 344
} |
Prims.Tot | val eval_mem128 (ptr: int) (s: state) : quad32 | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap) | val eval_mem128 (ptr: int) (s: state) : quad32
let eval_mem128 (ptr: int) (s: state) : quad32 = | false | null | false | get_heap_val128 ptr (heap_get s.ms_heap) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.MachineHeap_s.get_heap_val128",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.Def.Types_s.quad32"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_mem128 (ptr: int) (s: state) : quad32 | [] | Vale.PPC64LE.Semantics_s.eval_mem128 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> s: Vale.PPC64LE.Machine_s.state -> Vale.Def.Types_s.quad32 | {
"end_col": 94,
"end_line": 105,
"start_col": 54,
"start_line": 105
} |
Prims.Tot | val eval_stack128 (ptr: int) (s: machine_stack) : quad32 | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem | val eval_stack128 (ptr: int) (s: machine_stack) : quad32
let eval_stack128 (ptr: int) (s: machine_stack) : quad32 = | false | null | false | let Machine_stack _ mem = s in
get_heap_val128 ptr mem | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.Arch.MachineHeap_s.get_heap_val128",
"Vale.Def.Types_s.quad32"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_stack128 (ptr: int) (s: machine_stack) : quad32 | [] | Vale.PPC64LE.Semantics_s.eval_stack128 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> s: Vale.PPC64LE.Machine_s.machine_stack -> Vale.Def.Types_s.quad32 | {
"end_col": 25,
"end_line": 112,
"start_col": 63,
"start_line": 110
} |
Prims.Tot | val valid_src_stack64_and_taint (ptr: int) (s: state) (t: taint) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t | val valid_src_stack64_and_taint (ptr: int) (s: state) (t: taint) : bool
let valid_src_stack64_and_taint (ptr: int) (s: state) (t: taint) : bool = | false | null | false | valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.HeapTypes_s.taint",
"Prims.op_AmpAmp",
"Vale.PPC64LE.Semantics_s.valid_src_stack64",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Semantics_s.match_n",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_src_stack64_and_taint (ptr: int) (s: state) (t: taint) : bool | [] | Vale.PPC64LE.Semantics_s.valid_src_stack64_and_taint | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> s: Vale.PPC64LE.Machine_s.state -> t: Vale.Arch.HeapTypes_s.taint -> Prims.bool | {
"end_col": 69,
"end_line": 252,
"start_col": 2,
"start_line": 252
} |
Prims.Tot | val xer_ca (xer: xer_t) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let xer_ca (xer:xer_t) : bool =
xer.ca | val xer_ca (xer: xer_t) : bool
let xer_ca (xer: xer_t) : bool = | false | null | false | xer.ca | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.xer_t",
"Vale.PPC64LE.Machine_s.__proj__Mkxer_t__item__ca",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val xer_ca (xer: xer_t) : bool | [] | Vale.PPC64LE.Semantics_s.xer_ca | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | xer: Vale.PPC64LE.Machine_s.xer_t -> Prims.bool | {
"end_col": 8,
"end_line": 365,
"start_col": 2,
"start_line": 365
} |
Prims.Tot | val valid_src_stack (r: reg) (s: state) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack | val valid_src_stack (r: reg) (s: state) : bool
let valid_src_stack (r: reg) (s: state) : bool = | false | null | false | valid_src_stack64 (eval_reg r s) s.ms_stack | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.reg",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Semantics_s.valid_src_stack64",
"Vale.PPC64LE.Semantics_s.eval_reg",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_src_stack (r: reg) (s: state) : bool | [] | Vale.PPC64LE.Semantics_s.valid_src_stack | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.PPC64LE.Machine_s.reg -> s: Vale.PPC64LE.Machine_s.state -> Prims.bool | {
"end_col": 45,
"end_line": 259,
"start_col": 2,
"start_line": 259
} |
Prims.Tot | val valid_src_stack128_and_taint (ptr: int) (s: state) (t: taint) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t | val valid_src_stack128_and_taint (ptr: int) (s: state) (t: taint) : bool
let valid_src_stack128_and_taint (ptr: int) (s: state) (t: taint) : bool = | false | null | false | valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.HeapTypes_s.taint",
"Prims.op_AmpAmp",
"Vale.PPC64LE.Semantics_s.valid_src_stack128",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Semantics_s.match_n",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_src_stack128_and_taint (ptr: int) (s: state) (t: taint) : bool | [] | Vale.PPC64LE.Semantics_s.valid_src_stack128_and_taint | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> s: Vale.PPC64LE.Machine_s.state -> t: Vale.Arch.HeapTypes_s.taint -> Prims.bool | {
"end_col": 71,
"end_line": 256,
"start_col": 2,
"start_line": 256
} |
Prims.Tot | val valid_src_stack128 (ptr: int) (st: machine_stack) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem | val valid_src_stack128 (ptr: int) (st: machine_stack) : bool
let valid_src_stack128 (ptr: int) (st: machine_stack) : bool = | false | null | false | let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.Arch.MachineHeap_s.valid_addr128",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_src_stack128 (ptr: int) (st: machine_stack) : bool | [] | Vale.PPC64LE.Semantics_s.valid_src_stack128 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> st: Vale.PPC64LE.Machine_s.machine_stack -> Prims.bool | {
"end_col": 23,
"end_line": 248,
"start_col": 60,
"start_line": 246
} |
Prims.Tot | val update_stack64' (ptr: int) (v: nat64) (s: machine_stack) : machine_stack | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem | val update_stack64' (ptr: int) (v: nat64) (s: machine_stack) : machine_stack
let update_stack64' (ptr: int) (v: nat64) (s: machine_stack) : machine_stack = | false | null | false | let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.Def.Types_s.nat64",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Vale.PPC64LE.Machine_s.Machine_stack",
"Vale.Arch.MachineHeap_s.machine_heap",
"Vale.Arch.MachineHeap_s.update_heap64"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_stack64' (ptr: int) (v: nat64) (s: machine_stack) : machine_stack | [] | Vale.PPC64LE.Semantics_s.update_stack64' | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> v: Vale.Def.Types_s.nat64 -> s: Vale.PPC64LE.Machine_s.machine_stack
-> Vale.PPC64LE.Machine_s.machine_stack | {
"end_col": 27,
"end_line": 218,
"start_col": 75,
"start_line": 215
} |
Prims.Tot | val valid_mem128_and_taint (m: maddr) (s: state) (t: taint) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t | val valid_mem128_and_taint (m: maddr) (s: state) (t: taint) : bool
let valid_mem128_and_taint (m: maddr) (s: state) (t: taint) : bool = | false | null | false | let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.maddr",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.HeapTypes_s.taint",
"Prims.op_AmpAmp",
"Vale.Arch.MachineHeap_s.valid_addr128",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Semantics_s.match_n",
"Vale.Arch.Heap.heap_taint",
"Prims.int",
"Vale.PPC64LE.Semantics_s.eval_maddr",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val valid_mem128_and_taint (m: maddr) (s: state) (t: taint) : bool | [] | Vale.PPC64LE.Semantics_s.valid_mem128_and_taint | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | m: Vale.PPC64LE.Machine_s.maddr -> s: Vale.PPC64LE.Machine_s.state -> t: Vale.Arch.HeapTypes_s.taint
-> Prims.bool | {
"end_col": 83,
"end_line": 350,
"start_col": 65,
"start_line": 348
} |
Prims.Tot | val update_cr0 (new_cr0: cr0_t) : st unit | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_cr0 (new_cr0:cr0_t) :st unit =
let* s = get in
set ( { s with cr0 = new_cr0 } ) | val update_cr0 (new_cr0: cr0_t) : st unit
let update_cr0 (new_cr0: cr0_t) : st unit = | false | null | false | let* s = get in
set ({ s with cr0 = new_cr0 }) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.cr0_t",
"Vale.PPC64LE.Semantics_s.op_let_Star",
"Vale.PPC64LE.Machine_s.state",
"Prims.unit",
"Vale.PPC64LE.Semantics_s.get",
"Vale.PPC64LE.Semantics_s.set",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Vale.PPC64LE.Semantics_s.st"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold
let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail
unfold
let run (f:st unit) (s:state) : state = snd (f s)
let update_reg (r:reg) (v:nat64) :st unit =
let* s = get in
set (update_reg' r v s)
let update_vec (vr:vec) (v:quad32) :st unit =
let* s = get in
set (update_vec' vr v s)
let update_xer (new_xer:xer_t) :st unit =
let* s = get in
set ( { s with xer = new_xer } ) | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_cr0 (new_cr0: cr0_t) : st unit | [] | Vale.PPC64LE.Semantics_s.update_cr0 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | new_cr0: Vale.PPC64LE.Machine_s.cr0_t -> Vale.PPC64LE.Semantics_s.st Prims.unit | {
"end_col": 34,
"end_line": 424,
"start_col": 2,
"start_line": 423
} |
Prims.Tot | val update_mem (ptr: int) (v: nat64) (s: state) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s | val update_mem (ptr: int) (v: nat64) (s: state) : state
let update_mem (ptr: int) (v: nat64) (s: state) : state = | false | null | false | if valid_addr64 ptr (heap_get s.ms_heap)
then
{
s with
ms_heap = heap_upd s.ms_heap (update_heap64 ptr v (heap_get s.ms_heap)) (heap_taint s.ms_heap)
}
else s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.Def.Types_s.nat64",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.MachineHeap_s.valid_addr64",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.Arch.Heap.heap_upd",
"Vale.Arch.MachineHeap_s.update_heap64",
"Vale.Arch.Heap.heap_taint",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_mem (ptr: int) (v: nat64) (s: state) : state | [] | Vale.PPC64LE.Semantics_s.update_mem | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> v: Vale.Def.Types_s.nat64 -> s: Vale.PPC64LE.Machine_s.state
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 8,
"end_line": 169,
"start_col": 2,
"start_line": 163
} |
Prims.Tot | val run_ocmp (s: state) (c: ocmp) : state & bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let run_ocmp (s:state) (c:ocmp) : state & bool =
let s = run (check (valid_ocmp c)) s in
({s with cr0 = eval_cmp_cr0 s c}, eval_ocmp s c) | val run_ocmp (s: state) (c: ocmp) : state & bool
let run_ocmp (s: state) (c: ocmp) : state & bool = | false | null | false | let s = run (check (valid_ocmp c)) s in
({ s with cr0 = eval_cmp_cr0 s c }, eval_ocmp s c) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Semantics_s.ocmp",
"FStar.Pervasives.Native.Mktuple2",
"Prims.bool",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Semantics_s.eval_cmp_cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Vale.PPC64LE.Semantics_s.eval_ocmp",
"Vale.PPC64LE.Semantics_s.run",
"Vale.PPC64LE.Semantics_s.check",
"Vale.PPC64LE.Semantics_s.valid_ocmp",
"FStar.Pervasives.Native.tuple2"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov }
let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca }
// Define a stateful monad to simplify defining the instruction semantics
let st (a:Type) = state -> a & state
unfold
let return (#a:Type) (x:a) :st a =
fun s -> x, s
unfold
let (let*) (#a:Type) (#b:Type) (m:st a) (f:a -> st b) :st b =
fun s0 ->
let x, s1 = m s0 in
let y, s2 = f x s1 in
y, {s2 with ok=s0.ok && s1.ok && s2.ok}
unfold
let get :st state =
fun s -> s, s
unfold
let set (s:state) :st unit =
fun _ -> (), s
unfold
let fail :st unit =
fun s -> (), {s with ok=false}
unfold
let check (valid: state -> bool) : st unit =
let* s = get in
if valid s then
return ()
else
fail
unfold
let run (f:st unit) (s:state) : state = snd (f s)
let update_reg (r:reg) (v:nat64) :st unit =
let* s = get in
set (update_reg' r v s)
let update_vec (vr:vec) (v:quad32) :st unit =
let* s = get in
set (update_vec' vr v s)
let update_xer (new_xer:xer_t) :st unit =
let* s = get in
set ( { s with xer = new_xer } )
let update_cr0 (new_cr0:cr0_t) :st unit =
let* s = get in
set ( { s with cr0 = new_cr0 } )
unfold
let update_r1 (i:int) : st unit =
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
check (fun s -> i >= s.ms_stack.initial_r1 - 65536);*
check (fun s -> i <= s.ms_stack.initial_r1);*
let* s = get in
set (update_r1' i s)
let free_stack (start finish:int) : st unit =
let* s = get in
set ( { s with ms_stack = free_stack' start finish s.ms_stack} )
// Core definition of instruction semantics
let eval_ins (ins:ins) : st unit =
let* s = get in
match ins with
| Move dst src ->
update_reg dst (eval_reg src s)
| Load64 dst base offset ->
check (fun s -> valid_maddr_offset64 offset);*
check (valid_mem64 base offset);*
update_reg dst (eval_mem (eval_reg base s + offset) s)
| Store64 src base offset ->
check (fun s -> valid_maddr_offset64 offset);*
check (valid_mem64 base offset);*
set (update_mem (eval_reg base s + offset) (eval_reg src s) s)
| LoadImm64 dst src ->
update_reg dst (src % pow2_64)
| LoadImmShl64 dst src ->
update_reg dst (ishl64 (src % pow2_64) 16)
| AddLa dst src1 src2 ->
update_reg dst ((eval_reg src1 s + src2) % pow2_64)
| Add dst src1 src2 ->
update_reg dst ((eval_reg src1 s + eval_reg src2 s) % pow2_64)
| AddImm dst src1 src2 ->
update_reg dst ((eval_reg src1 s + int_to_nat64 src2) % pow2_64)
| AddCarry dst src1 src2 ->
let sum = (eval_reg src1 s) + (eval_reg src2 s) in
let new_carry = sum >= pow2_64 in
update_reg dst (sum % pow2_64);*
update_xer (update_xer_ca s.xer new_carry)
| AddExtended dst src1 src2 ->
let old_carry = if xer_ca(s.xer) then 1 else 0 in
let sum = (eval_reg src1 s) + (eval_reg src2 s) + old_carry in
let new_carry = sum >= pow2_64 in
update_reg dst (sum % pow2_64);*
update_xer (update_xer_ca s.xer new_carry)
| AddExtendedOV dst src1 src2 ->
let old_carry = if xer_ov(s.xer) then 1 else 0 in
let sum = (eval_reg src1 s) + (eval_reg src2 s) + old_carry in
let new_carry = sum >= pow2_64 in
update_reg dst (sum % pow2_64);*
update_xer (update_xer_ov s.xer new_carry)
| Sub dst src1 src2 ->
update_reg dst ((eval_reg src1 s - eval_reg src2 s) % pow2_64)
| SubImm dst src1 src2 ->
update_reg dst ((eval_reg src1 s - int_to_nat64 src2) % pow2_64)
| MulLow64 dst src1 src2 ->
update_reg dst ((eval_reg src1 s * eval_reg src2 s) % pow2_64)
| MulHigh64U dst src1 src2 ->
update_reg dst (FStar.UInt.mul_div #64 (eval_reg src1 s) (eval_reg src2 s))
| Xor dst src1 src2 ->
update_reg dst (ixor (eval_reg src1 s) (eval_reg src2 s))
| And dst src1 src2 ->
update_reg dst (iand (eval_reg src1 s) (eval_reg src2 s))
| Sr64Imm dst src1 src2 ->
update_reg dst (ishr (eval_reg src1 s) src2)
| Sl64Imm dst src1 src2 ->
update_reg dst (ishl (eval_reg src1 s) src2)
| Sr64 dst src1 src2 ->
update_reg dst (ishr (eval_reg src1 s) ((eval_reg src2 s) % 64))
| Sl64 dst src1 src2 ->
update_reg dst (ishl (eval_reg src1 s) ((eval_reg src2 s) % 64))
| Vmr dst src ->
update_vec dst (eval_vec src s)
| Mfvsrd dst src ->
let src_q = eval_vec src s in
let src_two = four_to_two_two src_q in
let extracted_nat64 = two_to_nat 32 (two_select src_two 1) in
update_reg dst extracted_nat64
| Mfvsrld dst src ->
let src_q = eval_vec src s in
let src_two = four_to_two_two src_q in
let extracted_nat64 = two_to_nat 32 (two_select src_two 0) in
update_reg dst extracted_nat64
| Mtvsrdd dst src1 src2 ->
let val_src1 = eval_reg src1 s in
let val_src2 = eval_reg src2 s in
update_vec dst (Mkfour
(val_src2 % pow2_32)
(val_src2 / pow2_32)
(val_src1 % pow2_32)
(val_src1 / pow2_32))
| Mtvsrws dst src ->
let val_src = eval_reg src s in
update_vec dst (Mkfour
(val_src % pow2_32)
(val_src % pow2_32)
(val_src % pow2_32)
(val_src % pow2_32))
| Vadduwm dst src1 src2 ->
update_vec dst (add_wrap_quad32 (eval_vec src1 s) (eval_vec src2 s))
| Vxor dst src1 src2 ->
update_vec dst (quad32_xor (eval_vec src1 s) (eval_vec src2 s))
| Vand dst src1 src2 ->
update_vec dst (four_map2 (fun di si -> iand di si) (eval_vec src1 s) (eval_vec src2 s))
| Vslw dst src1 src2 ->
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
update_vec dst (Mkfour
(ishl src1_q.lo0 (src2_q.lo0 % 32))
(ishl src1_q.lo1 (src2_q.lo1 % 32))
(ishl src1_q.hi2 (src2_q.hi2 % 32))
(ishl src1_q.hi3 (src2_q.hi3 % 32)))
| Vsrw dst src1 src2 ->
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
update_vec dst (Mkfour
(ishr src1_q.lo0 (src2_q.lo0 % 32))
(ishr src1_q.lo1 (src2_q.lo1 % 32))
(ishr src1_q.hi2 (src2_q.hi2 % 32))
(ishr src1_q.hi3 (src2_q.hi3 % 32)))
| Vsl dst src1 src2 ->
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
let sh = (index (nat32_to_be_bytes src2_q.lo0) 3) % 8 in
let chk (v:nat32) (sh:nat8):bool = (let bytes = nat32_to_be_bytes v in
sh = (index bytes 3) % 8 && sh = (index bytes 2) % 8 && sh = (index bytes 1) % 8 && sh = (index bytes 0) % 8) in
check (fun s -> chk src2_q.lo0 sh);*
check (fun s -> chk src2_q.lo1 sh);*
check (fun s -> chk src2_q.hi2 sh);*
check (fun s -> chk src2_q.hi3 sh);*
let l = four_map (fun (i:nat32) -> ishl i sh) src1_q in
let r = four_map (fun (i:nat32) -> ishr i (32 - sh)) src1_q in
let Mkfour r0 r1 r2 r3 = r in
update_vec dst (quad32_xor l (Mkfour 0 r0 r1 r2))
| Vcmpequw dst src1 src2 ->
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in
let eq_val = Mkfour
(eq_result (src1_q.lo0 = src2_q.lo0))
(eq_result (src1_q.lo1 = src2_q.lo1))
(eq_result (src1_q.hi2 = src2_q.hi2))
(eq_result (src1_q.hi3 = src2_q.hi3))
in
update_vec dst eq_val
| Vsldoi dst src1 src2 count ->
check (fun s -> (count = 4 || count = 8 || count = 12));* // We only spec the one very special case we need
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
if count = 4 then update_vec dst (Mkfour src2_q.hi3 src1_q.lo0 src1_q.lo1 src1_q.hi2)
else if count = 8 then update_vec dst (Mkfour src2_q.hi2 src2_q.hi3 src1_q.lo0 src1_q.lo1)
else if count = 12 then update_vec dst (Mkfour src2_q.lo1 src2_q.hi2 src2_q.hi3 src1_q.lo0)
else fail
| Vmrghw dst src1 src2 ->
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
update_vec dst (Mkfour src2_q.lo1 src1_q.lo1 src2_q.hi3 src1_q.hi3)
| Xxmrghd dst src1 src2 ->
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
update_vec dst (Mkfour src2_q.hi2 src2_q.hi3 src1_q.hi2 src1_q.hi3)
| Vsel dst src1 src2 sel ->
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
let sel_q = eval_vec sel s in
update_vec dst (Mkfour
(isel32 src2_q.lo0 src1_q.lo0 sel_q.lo0)
(isel32 src2_q.lo1 src1_q.lo1 sel_q.lo1)
(isel32 src2_q.hi2 src1_q.hi2 sel_q.hi2)
(isel32 src2_q.hi3 src1_q.hi3 sel_q.hi3))
| Vspltw dst src uim ->
let src_q = eval_vec src s in
if uim = 0 then update_vec dst (Mkfour src_q.hi3 src_q.hi3 src_q.hi3 src_q.hi3)
else if uim = 1 then update_vec dst (Mkfour src_q.hi2 src_q.hi2 src_q.hi2 src_q.hi2)
else if uim = 2 then update_vec dst (Mkfour src_q.lo1 src_q.lo1 src_q.lo1 src_q.lo1)
else update_vec dst (Mkfour src_q.lo0 src_q.lo0 src_q.lo0 src_q.lo0)
| Vspltisw dst src ->
let src_nat32 = int_to_nat32 src in
update_vec dst (Mkfour src_nat32 src_nat32 src_nat32 src_nat32)
| Vspltisb dst src ->
let src_nat8 = int_to_nat8 src in
let src_nat32 = be_bytes_to_nat32 (four_to_seq_BE (Mkfour src_nat8 src_nat8 src_nat8 src_nat8)) in
update_vec dst (Mkfour src_nat32 src_nat32 src_nat32 src_nat32)
| Load128 dst base offset ->
check (valid_mem128 base offset);*
update_vec dst (eval_mem128 (eval_reg base s + eval_reg offset s) s)
| Store128 src base offset ->
check (valid_mem128 base offset);*
set (update_mem128 (eval_reg base s + eval_reg offset s) (eval_vec src s) s)
| Load128Word4 dst base ->
check (valid_mem128_reg base);*
let src_q = eval_mem128 (eval_reg base s) s in
update_vec dst (Mkfour src_q.hi3 src_q.hi2 src_q.lo1 src_q.lo0)
| Load128Word4Index dst base offset ->
check (fun s -> offset <> 0);*
check (valid_mem128 base offset);*
let src_q = eval_mem128 (eval_reg base s + eval_reg offset s) s in
update_vec dst (Mkfour src_q.hi3 src_q.hi2 src_q.lo1 src_q.lo0)
| Store128Word4 src base ->
check (valid_mem128_reg base);*
let src_q = eval_vec src s in
set (update_mem128 (eval_reg base s) (Mkfour src_q.hi3 src_q.hi2 src_q.lo1 src_q.lo0) s)
| Store128Word4Index src base offset ->
check (fun s -> offset <> 0);*
check (valid_mem128 base offset);*
let src_q = eval_vec src s in
set (update_mem128 (eval_reg base s + eval_reg offset s) (Mkfour src_q.hi3 src_q.hi2 src_q.lo1 src_q.lo0) s)
| Load128Byte16 dst base ->
check (valid_mem128_reg base);*
update_vec dst (reverse_bytes_quad32 (eval_mem128 (eval_reg base s) s))
| Load128Byte16Index dst base offset ->
check (fun s -> offset <> 0);*
check (valid_mem128 base offset);*
update_vec dst (reverse_bytes_quad32 (eval_mem128 (eval_reg base s + eval_reg offset s) s))
| Store128Byte16 src base ->
check (valid_mem128_reg base);*
set (update_mem128 (eval_reg base s) (reverse_bytes_quad32 (eval_vec src s)) s)
| Store128Byte16Index src base offset ->
check (fun s -> offset <> 0);*
check (valid_mem128 base offset);*
set (update_mem128 (eval_reg base s + eval_reg offset s) (reverse_bytes_quad32 (eval_vec src s)) s)
| Vshasigmaw0 dst src ->
let src_q = eval_vec src s in
update_vec dst (Mkfour
(sigma256_0_0 src_q.lo0)
(sigma256_0_0 src_q.lo1)
(sigma256_0_0 src_q.hi2)
(sigma256_0_0 src_q.hi3))
| Vshasigmaw1 dst src ->
let src_q = eval_vec src s in
update_vec dst (Mkfour
(sigma256_0_1 src_q.lo0)
(sigma256_0_1 src_q.lo1)
(sigma256_0_1 src_q.hi2)
(sigma256_0_1 src_q.hi3))
| Vshasigmaw2 dst src ->
let src_q = eval_vec src s in
update_vec dst (Mkfour
(sigma256_1_0 src_q.lo0)
(sigma256_1_0 src_q.lo1)
(sigma256_1_0 src_q.hi2)
(sigma256_1_0 src_q.hi3))
| Vshasigmaw3 dst src ->
let src_q = eval_vec src s in
update_vec dst (Mkfour
(sigma256_1_1 src_q.lo0)
(sigma256_1_1 src_q.lo1)
(sigma256_1_1 src_q.hi2)
(sigma256_1_1 src_q.hi3))
| Vsbox dst src ->
let src_q = eval_vec src s in
update_vec dst (Mkfour
(Vale.AES.AES_BE_s.sub_word src_q.lo0)
(Vale.AES.AES_BE_s.sub_word src_q.lo1)
(Vale.AES.AES_BE_s.sub_word src_q.hi2)
(Vale.AES.AES_BE_s.sub_word src_q.hi3))
| RotWord dst src1 src2 ->
let src1_q = eval_vec src1 s in
let src2_q = eval_vec src2 s in
check (fun s -> (src2_q.lo0 = 8 && src2_q.lo1 = 8 && src2_q.hi2 = 8 && src2_q.hi3 = 8));*
update_vec dst (Mkfour
(Vale.AES.AES_BE_s.rot_word src1_q.lo0)
(Vale.AES.AES_BE_s.rot_word src1_q.lo1)
(Vale.AES.AES_BE_s.rot_word src1_q.hi2)
(Vale.AES.AES_BE_s.rot_word src1_q.hi3))
| Vcipher dst src1 src2 ->
update_vec dst (quad32_xor (Vale.AES.AES_BE_s.mix_columns (Vale.AES.AES_BE_s.shift_rows (Vale.AES.AES_BE_s.sub_bytes (eval_vec src1 s)))) (eval_vec src2 s))
| Vcipherlast dst src1 src2 ->
update_vec dst (quad32_xor (Vale.AES.AES_BE_s.shift_rows (Vale.AES.AES_BE_s.sub_bytes (eval_vec src1 s))) (eval_vec src2 s))
| Vncipher dst src1 src2 ->
update_vec dst (Vale.AES.AES_BE_s.inv_mix_columns (quad32_xor (Vale.AES.AES_BE_s.inv_sub_bytes (Vale.AES.AES_BE_s.inv_shift_rows (eval_vec src1 s))) (eval_vec src2 s)))
| Vncipherlast dst src1 src2 ->
update_vec dst (quad32_xor (Vale.AES.AES_BE_s.inv_sub_bytes (Vale.AES.AES_BE_s.inv_shift_rows (eval_vec src1 s))) (eval_vec src2 s))
| Vpmsumd dst src1 src2 ->
let Mkfour a0 a1 a2 a3 = eval_vec src1 s in
let Mkfour b0 b1 b2 b3 = eval_vec src2 s in
let x0 = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo a0 a1) in
let x1 = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo a2 a3) in
let y0 = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo b0 b1) in
let y1 = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo b2 b3) in
let sum = Vale.Math.Poly2_s.add (Vale.Math.Poly2_s.mul x0 y0) (Vale.Math.Poly2_s.mul x1 y1) in
update_vec dst (Vale.Math.Poly2.Bits_s.to_quad32 sum)
| Alloc n ->
check (fun s -> n % 16 = 0);*
update_r1 (eval_reg 1 s - n)
| Dealloc n ->
let old_r1 = eval_reg 1 s in
let new_r1 = old_r1 + n in
update_r1 new_r1;*
// The deallocated stack memory should now be considered invalid
free_stack old_r1 new_r1
| StoreStack128 src t offset ->
check (fun s -> valid_maddr_offset128 offset);*
let r1_pos = eval_reg 1 s + offset in
check (fun s -> r1_pos <= s.ms_stack.initial_r1 - 16);*
set (update_stack128_and_taint r1_pos (eval_vec src s) s t)
| LoadStack128 dst t offset ->
check (fun s -> valid_maddr_offset128 offset);*
let r1_pos = eval_reg 1 s + offset in
check (fun s -> r1_pos + 16 <= s.ms_stack.initial_r1);*
check (fun s -> valid_src_stack128_and_taint r1_pos s t);*
update_vec dst (eval_stack128 r1_pos s.ms_stack)
| StoreStack64 src t offset ->
check (fun s -> valid_maddr_offset64 offset);*
let r1_pos = eval_reg 1 s + offset in
check (fun s -> r1_pos <= s.ms_stack.initial_r1 - 8);*
set (update_stack_and_taint r1_pos (eval_reg src s) s t)
| LoadStack64 dst t offset ->
check (fun s -> valid_maddr_offset64 offset);*
let r1_pos = eval_reg 1 s + offset in
check (fun s -> r1_pos + 8 <= s.ms_stack.initial_r1);*
check (fun s -> valid_src_stack64_and_taint r1_pos s t);*
update_reg dst (eval_stack r1_pos s.ms_stack)
| Ghost _ ->
set s | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val run_ocmp (s: state) (c: ocmp) : state & bool | [] | Vale.PPC64LE.Semantics_s.run_ocmp | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | s: Vale.PPC64LE.Machine_s.state -> c: Vale.PPC64LE.Semantics_s.ocmp
-> Vale.PPC64LE.Machine_s.state * Prims.bool | {
"end_col": 50,
"end_line": 813,
"start_col": 48,
"start_line": 811
} |
Prims.Tot | val update_mem128_and_taint (ptr: int) (v: quad32) (s: state) (t: taint) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s | val update_mem128_and_taint (ptr: int) (v: quad32) (s: state) (t: taint) : state
let update_mem128_and_taint (ptr: int) (v: quad32) (s: state) (t: taint) : state = | false | null | false | if valid_addr128 ptr (heap_get s.ms_heap)
then
{
s with
ms_heap
=
heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.Def.Types_s.quad32",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.HeapTypes_s.taint",
"Vale.Arch.MachineHeap_s.valid_addr128",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.Arch.Heap.heap_upd",
"Vale.Arch.MachineHeap_s.update_heap128",
"Vale.PPC64LE.Semantics_s.update_n",
"Vale.Arch.Heap.heap_taint",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_mem128_and_taint (ptr: int) (v: quad32) (s: state) (t: taint) : state | [] | Vale.PPC64LE.Semantics_s.update_mem128_and_taint | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
ptr: Prims.int ->
v: Vale.Def.Types_s.quad32 ->
s: Vale.PPC64LE.Machine_s.state ->
t: Vale.Arch.HeapTypes_s.taint
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 8,
"end_line": 212,
"start_col": 2,
"start_line": 206
} |
Prims.Tot | val eval_cmp_opr (o: cmp_opr) (s: state) : nat64 | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n | val eval_cmp_opr (o: cmp_opr) (s: state) : nat64
let eval_cmp_opr (o: cmp_opr) (s: state) : nat64 = | false | null | false | match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.cmp_opr",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Machine_s.reg",
"Vale.PPC64LE.Semantics_s.eval_reg",
"Vale.PPC64LE.Machine_s.imm16",
"Vale.PPC64LE.Machine_s.int_to_nat64",
"Vale.Def.Types_s.nat64"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_cmp_opr (o: cmp_opr) (s: state) : nat64 | [] | Vale.PPC64LE.Semantics_s.eval_cmp_opr | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | o: Vale.PPC64LE.Machine_s.cmp_opr -> s: Vale.PPC64LE.Machine_s.state -> Vale.Def.Types_s.nat64 | {
"end_col": 28,
"end_line": 268,
"start_col": 2,
"start_line": 266
} |
Prims.Tot | val eval_cmp_cr0 (s: state) (c: ocmp) : cr0_t | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64) | val eval_cmp_cr0 (s: state) (c: ocmp) : cr0_t
let eval_cmp_cr0 (s: state) (c: ocmp) : cr0_t = | false | null | false | match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64) | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Semantics_s.ocmp",
"Vale.PPC64LE.Machine_s.cmp_opr",
"Vale.PPC64LE.Machine_s.get_cr0",
"Prims.op_Modulus",
"Prims.op_Subtraction",
"Vale.PPC64LE.Semantics_s.eval_cmp_opr",
"Vale.Def.Words_s.pow2_64",
"Vale.PPC64LE.Machine_s.cr0_t"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_cmp_cr0 (s: state) (c: ocmp) : cr0_t | [] | Vale.PPC64LE.Semantics_s.eval_cmp_cr0 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | s: Vale.PPC64LE.Machine_s.state -> c: Vale.PPC64LE.Semantics_s.ocmp -> Vale.PPC64LE.Machine_s.cr0_t | {
"end_col": 76,
"end_line": 286,
"start_col": 2,
"start_line": 280
} |
Prims.Tot | val update_r1' (new_r1: int) (s: state) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s | val update_r1' (new_r1: int) (s: state) : state
let update_r1' (new_r1: int) (s: state) : state = | false | null | false | let Machine_stack init_r1 mem = s.ms_stack in
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then update_reg' 1 new_r1 s else s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Machine_s.nat64",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"FStar.Map.t",
"Vale.PPC64LE.Machine_s.nat8",
"Prims.op_AmpAmp",
"Prims.op_Subtraction",
"Prims.op_LessThanOrEqual",
"Vale.PPC64LE.Semantics_s.update_reg'",
"Prims.bool",
"Vale.PPC64LE.Machine_s.machine_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') } | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_r1' (new_r1: int) (s: state) : state | [] | Vale.PPC64LE.Semantics_s.update_r1' | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | new_r1: Prims.int -> s: Vale.PPC64LE.Machine_s.state -> Vale.PPC64LE.Machine_s.state | {
"end_col": 5,
"end_line": 318,
"start_col": 47,
"start_line": 312
} |
Prims.Tot | val update_xer_ov (xer: xer_t) (new_xer_ov: bool) : (new_xer: xer_t{xer_ov new_xer == new_xer_ov}) | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov } | val update_xer_ov (xer: xer_t) (new_xer_ov: bool) : (new_xer: xer_t{xer_ov new_xer == new_xer_ov})
let update_xer_ov (xer: xer_t) (new_xer_ov: bool) : (new_xer: xer_t{xer_ov new_xer == new_xer_ov}) = | false | null | false | { xer with ov = new_xer_ov } | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.xer_t",
"Prims.bool",
"Vale.PPC64LE.Machine_s.Mkxer_t",
"Vale.PPC64LE.Machine_s.__proj__Mkxer_t__item__ca",
"Prims.eq2",
"Vale.PPC64LE.Semantics_s.xer_ov"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca | false | false | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_xer_ov (xer: xer_t) (new_xer_ov: bool) : (new_xer: xer_t{xer_ov new_xer == new_xer_ov}) | [] | Vale.PPC64LE.Semantics_s.update_xer_ov | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | xer: Vale.PPC64LE.Machine_s.xer_t -> new_xer_ov: Prims.bool
-> new_xer: Vale.PPC64LE.Machine_s.xer_t{Vale.PPC64LE.Semantics_s.xer_ov new_xer == new_xer_ov} | {
"end_col": 28,
"end_line": 368,
"start_col": 4,
"start_line": 368
} |
Prims.Tot | val update_n (addr: int) (n: nat) (memTaint: memTaint_t) (t: taint)
: Tot
(m:
memTaint_t
{ (forall i. {:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[ i ] == t) /\
((i < addr \/ i >= addr + n) ==> m.[ i ] == memTaint.[ i ])) }) (decreases n) | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t | val update_n (addr: int) (n: nat) (memTaint: memTaint_t) (t: taint)
: Tot
(m:
memTaint_t
{ (forall i. {:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[ i ] == t) /\
((i < addr \/ i >= addr + n) ==> m.[ i ] == memTaint.[ i ])) }) (decreases n)
let rec update_n (addr: int) (n: nat) (memTaint: memTaint_t) (t: taint)
: Tot
(m:
memTaint_t
{ (forall i. {:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[ i ] == t) /\
((i < addr \/ i >= addr + n) ==> m.[ i ] == memTaint.[ i ])) }) (decreases n) = | false | null | false | if n = 0 then memTaint else update_n (addr + 1) (n - 1) (memTaint.[ addr ] <- t) t | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total",
""
] | [
"Prims.int",
"Prims.nat",
"Vale.Arch.HeapTypes_s.memTaint_t",
"Vale.Arch.HeapTypes_s.taint",
"Prims.op_Equality",
"Prims.bool",
"Vale.PPC64LE.Semantics_s.update_n",
"Prims.op_Addition",
"Prims.op_Subtraction",
"Vale.PPC64LE.Semantics_s.op_String_Assignment",
"Prims.l_Forall",
"Prims.l_and",
"Prims.l_imp",
"Prims.b2t",
"Prims.op_GreaterThanOrEqual",
"Prims.op_LessThan",
"Prims.eq2",
"Vale.PPC64LE.Semantics_s.op_String_Access",
"Prims.l_or",
"FStar.Map.sel"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n) | false | false | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_n (addr: int) (n: nat) (memTaint: memTaint_t) (t: taint)
: Tot
(m:
memTaint_t
{ (forall i. {:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[ i ] == t) /\
((i < addr \/ i >= addr + n) ==> m.[ i ] == memTaint.[ i ])) }) (decreases n) | [
"recursion"
] | Vale.PPC64LE.Semantics_s.update_n | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
addr: Prims.int ->
n: Prims.nat ->
memTaint: Vale.Arch.HeapTypes_s.memTaint_t ->
t: Vale.Arch.HeapTypes_s.taint
-> Prims.Tot
(m:
Vale.Arch.HeapTypes_s.memTaint_t
{ forall (i: Prims.int). {:pattern FStar.Map.sel m i}
(i >= addr /\ i < addr + n ==> m.[ i ] == t) /\
(i < addr \/ i >= addr + n ==> m.[ i ] == memTaint.[ i ]) }) | {
"end_col": 59,
"end_line": 141,
"start_col": 2,
"start_line": 140
} |
Prims.Tot | val update_xer_ca (xer: xer_t) (new_xer_ca: bool) : (new_xer: xer_t{xer_ca new_xer == new_xer_ca}) | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_xer_ca (xer:xer_t) (new_xer_ca:bool) : (new_xer:xer_t{xer_ca new_xer == new_xer_ca}) =
{ xer with ca = new_xer_ca } | val update_xer_ca (xer: xer_t) (new_xer_ca: bool) : (new_xer: xer_t{xer_ca new_xer == new_xer_ca})
let update_xer_ca (xer: xer_t) (new_xer_ca: bool) : (new_xer: xer_t{xer_ca new_xer == new_xer_ca}) = | false | null | false | { xer with ca = new_xer_ca } | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.xer_t",
"Prims.bool",
"Vale.PPC64LE.Machine_s.Mkxer_t",
"Vale.PPC64LE.Machine_s.__proj__Mkxer_t__item__ov",
"Prims.eq2",
"Vale.PPC64LE.Semantics_s.xer_ca"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') }
let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') }
let update_r1' (new_r1:int) (s:state) : state =
let Machine_stack init_r1 mem = s.ms_stack in
// Only modify the stack pointer if the new value is valid, that is in the current stack frame, and in the same page
if new_r1 >= init_r1 - 65536 && new_r1 <= init_r1 then
update_reg' 1 new_r1 s
else
s
let free_stack' (start finish:int) (st:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = st in
let domain = Map.domain mem in
// Returns the domain, without elements between start and finish
let restricted_domain = Vale.Lib.Set.remove_between domain start finish in
// The new domain of the stack does not contain elements between start and finish
let new_mem = Map.restrict restricted_domain mem in
Machine_stack init_r1 new_mem
let valid_mem (m:maddr) (s:state) : bool =
valid_maddr_offset64 m.offset && valid_addr64 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem64 (r:reg) (i:int) (s:state) : bool =
valid_addr64 (eval_reg r s + i) (heap_get s.ms_heap)
let valid_mem128 (r:reg) (i:reg) (s:state) : bool =
valid_addr128 (eval_reg r s + eval_reg i s) (heap_get s.ms_heap)
let valid_mem128_reg (r:reg) (s:state) : bool =
valid_addr128 (eval_reg r s) (heap_get s.ms_heap)
let valid_mem128' (m:maddr) (s:state) : bool =
valid_maddr_offset128 m.offset && valid_addr128 (eval_maddr m s) (heap_get s.ms_heap)
let valid_mem_and_taint (m:maddr) (t:taint) (s:state) : bool =
let ptr = eval_maddr m s in
valid_maddr_offset64 m.offset && valid_addr64 ptr (heap_get s.ms_heap) && match_n ptr 8 (heap_taint s.ms_heap) t
let valid_mem128_and_taint (m:maddr) (s:state) (t:taint) : bool =
let ptr = eval_maddr m s in
valid_addr128 ptr (heap_get s.ms_heap) && match_n ptr 16 (heap_taint s.ms_heap) t
let valid_ocmp (c:ocmp) (s:state) : bool =
match c with
| OEq o1 _ -> valid_first_cmp_opr o1
| ONe o1 _ -> valid_first_cmp_opr o1
| OLe o1 _ -> valid_first_cmp_opr o1
| OGe o1 _ -> valid_first_cmp_opr o1
| OLt o1 _ -> valid_first_cmp_opr o1
| OGt o1 _ -> valid_first_cmp_opr o1
let xer_ov (xer:xer_t) : bool =
xer.ov
let xer_ca (xer:xer_t) : bool =
xer.ca
let update_xer_ov (xer:xer_t) (new_xer_ov:bool) : (new_xer:xer_t{xer_ov new_xer == new_xer_ov}) =
{ xer with ov = new_xer_ov } | false | false | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_xer_ca (xer: xer_t) (new_xer_ca: bool) : (new_xer: xer_t{xer_ca new_xer == new_xer_ca}) | [] | Vale.PPC64LE.Semantics_s.update_xer_ca | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | xer: Vale.PPC64LE.Machine_s.xer_t -> new_xer_ca: Prims.bool
-> new_xer: Vale.PPC64LE.Machine_s.xer_t{Vale.PPC64LE.Semantics_s.xer_ca new_xer == new_xer_ca} | {
"end_col": 28,
"end_line": 371,
"start_col": 4,
"start_line": 371
} |
Prims.Tot | val update_reg' (r: reg) (v: nat64) (s: state) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') } | val update_reg' (r: reg) (v: nat64) (s: state) : state
let update_reg' (r: reg) (v: nat64) (s: state) : state = | false | null | false | { s with regs = regs_make (fun (r': reg) -> if r' = r then v else s.regs r') } | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.reg",
"Vale.Def.Types_s.nat64",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.regs_make",
"Prims.op_Equality",
"Prims.bool",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.nat64",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_reg' (r: reg) (v: nat64) (s: state) : state | [] | Vale.PPC64LE.Semantics_s.update_reg' | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | r: Vale.PPC64LE.Machine_s.reg -> v: Vale.Def.Types_s.nat64 -> s: Vale.PPC64LE.Machine_s.state
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 77,
"end_line": 307,
"start_col": 4,
"start_line": 307
} |
FStar.Pervasives.Lemma | val lemma_is_machine_heap_update128 (ptr: int) (v: quad32) (mh: machine_heap)
: Lemma (requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))] | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3 | val lemma_is_machine_heap_update128 (ptr: int) (v: quad32) (mh: machine_heap)
: Lemma (requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
let lemma_is_machine_heap_update128 (ptr: int) (v: quad32) (mh: machine_heap)
: Lemma (requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))] = | false | null | true | let lemma_is_machine_heap_update32 (ptr: int) (v: nat32) (mh: machine_heap)
: Lemma
(requires
valid_addr ptr mh /\ valid_addr (ptr + 1) mh /\ valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh) (ensures is_machine_heap_update mh (update_heap32 ptr v mh)) =
update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3 | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"lemma"
] | [
"Prims.int",
"Vale.Def.Types_s.quad32",
"Vale.Arch.MachineHeap_s.machine_heap",
"Prims.op_Addition",
"Vale.Def.Words_s.__proj__Mkfour__item__hi3",
"Vale.Def.Types_s.nat32",
"Prims.unit",
"Vale.Def.Words_s.__proj__Mkfour__item__hi2",
"Vale.Def.Words_s.__proj__Mkfour__item__lo1",
"Vale.Def.Words_s.__proj__Mkfour__item__lo0",
"Vale.Arch.MachineHeap_s.update_heap128_reveal",
"FStar.Pervasives.reveal_opaque",
"Prims.bool",
"Vale.Arch.MachineHeap_s.valid_addr128",
"Vale.Arch.MachineHeap_s.update_heap32",
"Vale.Def.Words_s.nat32",
"Prims.l_and",
"Prims.b2t",
"Vale.Arch.MachineHeap_s.valid_addr",
"Prims.squash",
"Vale.Arch.MachineHeap_s.is_machine_heap_update",
"Prims.Nil",
"FStar.Pervasives.pattern",
"Vale.Arch.MachineHeap_s.update_heap32_reveal",
"Vale.Arch.MachineHeap_s.update_heap128",
"Prims.Cons",
"FStar.Pervasives.smt_pat",
"Prims.logical"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh)) | false | false | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val lemma_is_machine_heap_update128 (ptr: int) (v: quad32) (mh: machine_heap)
: Lemma (requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))] | [] | Vale.PPC64LE.Semantics_s.lemma_is_machine_heap_update128 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> v: Vale.Def.Types_s.quad32 -> mh: Vale.Arch.MachineHeap_s.machine_heap
-> FStar.Pervasives.Lemma (requires Vale.Arch.MachineHeap_s.valid_addr128 ptr mh)
(ensures
Vale.Arch.MachineHeap_s.is_machine_heap_update mh
(Vale.Arch.MachineHeap_s.update_heap128 ptr v mh))
[
SMTPat (Vale.Arch.MachineHeap_s.is_machine_heap_update mh
(Vale.Arch.MachineHeap_s.update_heap128 ptr v mh))
] | {
"end_col": 54,
"end_line": 194,
"start_col": 3,
"start_line": 175
} |
Prims.Tot | val update_vec' (vr: vec) (v: quad32) (s: state) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_vec' (vr:vec) (v:quad32) (s:state) : state =
{ s with vecs = vecs_make (fun (vr':vec) -> if vr' = vr then v else s.vecs vr') } | val update_vec' (vr: vec) (v: quad32) (s: state) : state
let update_vec' (vr: vec) (v: quad32) (s: state) : state = | false | null | false | { s with vecs = vecs_make (fun (vr': vec) -> if vr' = vr then v else s.vecs vr') } | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.vec",
"Vale.Def.Types_s.quad32",
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.vecs_make",
"Prims.op_Equality",
"Prims.bool",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.quad32",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n
let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s
let eval_cmp_cr0 (s:state) (c:ocmp) : cr0_t =
match c with
| OEq o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| ONe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGe o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OLt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
| OGt o1 o2 -> get_cr0 ((eval_cmp_opr o1 s - eval_cmp_opr o2 s) % pow2_64)
unfold
let valid_dst_stack64 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 8 <= init_r1
unfold
let valid_dst_stack128 (r1:nat64) (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
// We are allowed to store anywhere between rRsp and the initial stack pointer
ptr >= r1 && ptr + 16 <= init_r1
let valid_dst_stack64_addr (m:maddr) (s:state) : bool =
valid_dst_stack64 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let valid_dst_stack128_addr (m:maddr) (s:state) : bool =
valid_dst_stack128 (eval_reg 1 s) (eval_maddr m s) s.ms_stack
let update_reg' (r:reg) (v:nat64) (s:state) : state =
{ s with regs = regs_make (fun (r':reg) -> if r' = r then v else s.regs r') } | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_vec' (vr: vec) (v: quad32) (s: state) : state | [] | Vale.PPC64LE.Semantics_s.update_vec' | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | vr: Vale.PPC64LE.Machine_s.vec -> v: Vale.Def.Types_s.quad32 -> s: Vale.PPC64LE.Machine_s.state
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 81,
"end_line": 310,
"start_col": 4,
"start_line": 310
} |
Prims.Tot | val match_n (addr: int) (n: nat) (memTaint: memTaint_t) (t: taint)
: Tot
(b:
bool
{ b <==>
(forall i. {:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[ i ] == t) }) (decreases n) | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t | val match_n (addr: int) (n: nat) (memTaint: memTaint_t) (t: taint)
: Tot
(b:
bool
{ b <==>
(forall i. {:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[ i ] == t) }) (decreases n)
let rec match_n (addr: int) (n: nat) (memTaint: memTaint_t) (t: taint)
: Tot
(b:
bool
{ b <==>
(forall i. {:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[ i ] == t) }) (decreases n) = | false | null | false | if n = 0
then true
else if memTaint.[ addr ] <> t then false else match_n (addr + 1) (n - 1) memTaint t | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total",
""
] | [
"Prims.int",
"Prims.nat",
"Vale.Arch.HeapTypes_s.memTaint_t",
"Vale.Arch.HeapTypes_s.taint",
"Prims.op_Equality",
"Prims.bool",
"Prims.op_disEquality",
"Vale.PPC64LE.Semantics_s.op_String_Access",
"Vale.PPC64LE.Semantics_s.match_n",
"Prims.op_Addition",
"Prims.op_Subtraction",
"Prims.l_iff",
"Prims.b2t",
"Prims.l_Forall",
"Prims.l_imp",
"Prims.l_and",
"Prims.op_GreaterThanOrEqual",
"Prims.op_LessThan",
"Prims.eq2",
"FStar.Map.sel"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n) | false | false | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val match_n (addr: int) (n: nat) (memTaint: memTaint_t) (t: taint)
: Tot
(b:
bool
{ b <==>
(forall i. {:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[ i ] == t) }) (decreases n) | [
"recursion"
] | Vale.PPC64LE.Semantics_s.match_n | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
addr: Prims.int ->
n: Prims.nat ->
memTaint: Vale.Arch.HeapTypes_s.memTaint_t ->
t: Vale.Arch.HeapTypes_s.taint
-> Prims.Tot
(b:
Prims.bool
{ b <==>
(forall (i: Prims.int). {:pattern FStar.Map.sel memTaint i}
i >= addr /\ i < addr + n ==> memTaint.[ i ] == t) }) | {
"end_col": 44,
"end_line": 130,
"start_col": 2,
"start_line": 128
} |
Prims.Tot | val eval_ocmp (s: state) (c: ocmp) : bool | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let eval_ocmp (s:state) (c:ocmp) :bool =
match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s | val eval_ocmp (s: state) (c: ocmp) : bool
let eval_ocmp (s: state) (c: ocmp) : bool = | false | null | false | match c with
| OEq o1 o2 -> eval_cmp_opr o1 s = eval_cmp_opr o2 s
| ONe o1 o2 -> eval_cmp_opr o1 s <> eval_cmp_opr o2 s
| OLe o1 o2 -> eval_cmp_opr o1 s <= eval_cmp_opr o2 s
| OGe o1 o2 -> eval_cmp_opr o1 s >= eval_cmp_opr o2 s
| OLt o1 o2 -> eval_cmp_opr o1 s < eval_cmp_opr o2 s
| OGt o1 o2 -> eval_cmp_opr o1 s > eval_cmp_opr o2 s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Vale.PPC64LE.Machine_s.state",
"Vale.PPC64LE.Semantics_s.ocmp",
"Vale.PPC64LE.Machine_s.cmp_opr",
"Prims.op_Equality",
"Vale.Def.Types_s.nat64",
"Vale.PPC64LE.Semantics_s.eval_cmp_opr",
"Prims.op_disEquality",
"Prims.op_LessThanOrEqual",
"Prims.op_GreaterThanOrEqual",
"Prims.op_LessThan",
"Prims.op_GreaterThan",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3
let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let update_mem128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(update_n ptr 16 (heap_taint s.ms_heap) t)
}
else s
unfold
let update_stack64' (ptr:int) (v:nat64) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap64 ptr v mem in
Machine_stack init_r1 mem
unfold
let update_stack128' (ptr:int) (v:quad32) (s:machine_stack) : machine_stack =
let Machine_stack init_r1 mem = s in
let mem = update_heap128 ptr v mem in
Machine_stack init_r1 mem
let update_stack_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack64' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 8 s.ms_stackTaint t;
}
let update_stack128_and_taint (ptr:int) (v:quad32) (s:state) (t:taint) : state =
let Machine_stack init_r1 mem = s.ms_stack in
{ s with
ms_stack = update_stack128' ptr v s.ms_stack;
ms_stackTaint = update_n ptr 16 s.ms_stackTaint t
}
unfold
let valid_src_stack64 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr64 ptr mem
unfold
let valid_src_stack128 (ptr:int) (st:machine_stack) : bool =
let Machine_stack init_r1 mem = st in
valid_addr128 ptr mem
unfold
let valid_src_stack64_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack64 ptr s.ms_stack && match_n ptr 8 s.ms_stackTaint t
unfold
let valid_src_stack128_and_taint (ptr:int) (s:state) (t:taint) : bool =
valid_src_stack128 ptr s.ms_stack && match_n ptr 16 s.ms_stackTaint t
let valid_src_stack (r:reg) (s:state) : bool =
valid_src_stack64 (eval_reg r s) s.ms_stack
[@va_qattr]
let eval_maddr (m:maddr) (s:state) : int =
eval_reg m.address s + m.offset
let eval_cmp_opr (o:cmp_opr) (s:state) : nat64 =
match o with
| CReg r -> eval_reg r s
| CImm n -> int_to_nat64 n | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val eval_ocmp (s: state) (c: ocmp) : bool | [] | Vale.PPC64LE.Semantics_s.eval_ocmp | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | s: Vale.PPC64LE.Machine_s.state -> c: Vale.PPC64LE.Semantics_s.ocmp -> Prims.bool | {
"end_col": 54,
"end_line": 277,
"start_col": 2,
"start_line": 271
} |
Prims.Tot | val update_mem128 (ptr: int) (v: quad32) (s: state) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_mem128 (ptr:int) (v:quad32) (s:state) : state =
if valid_addr128 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap128 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s | val update_mem128 (ptr: int) (v: quad32) (s: state) : state
let update_mem128 (ptr: int) (v: quad32) (s: state) : state = | false | null | false | if valid_addr128 ptr (heap_get s.ms_heap)
then
{
s with
ms_heap = heap_upd s.ms_heap (update_heap128 ptr v (heap_get s.ms_heap)) (heap_taint s.ms_heap)
}
else s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.Def.Types_s.quad32",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.MachineHeap_s.valid_addr128",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.Arch.Heap.heap_upd",
"Vale.Arch.MachineHeap_s.update_heap128",
"Vale.Arch.Heap.heap_taint",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
()
let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s
let update_mem (ptr:int) (v:nat64) (s:state) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(heap_taint s.ms_heap)
}
else s
let lemma_is_machine_heap_update128 (ptr:int) (v:quad32) (mh:machine_heap) : Lemma
(requires valid_addr128 ptr mh)
(ensures is_machine_heap_update mh (update_heap128 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap128 ptr v mh))]
=
let lemma_is_machine_heap_update32 (ptr:int) (v:nat32) (mh:machine_heap) : Lemma
(requires
valid_addr ptr mh /\
valid_addr (ptr + 1) mh /\
valid_addr (ptr + 2) mh /\
valid_addr (ptr + 3) mh
)
(ensures is_machine_heap_update mh (update_heap32 ptr v mh))
= update_heap32_reveal ()
in
let mem1 = update_heap32 ptr v.lo0 mh in
let mem2 = update_heap32 (ptr + 4) v.lo1 mem1 in
let mem3 = update_heap32 (ptr + 8) v.hi2 mem2 in
reveal_opaque (`%valid_addr128) valid_addr128;
update_heap128_reveal ();
lemma_is_machine_heap_update32 ptr v.lo0 mh;
lemma_is_machine_heap_update32 (ptr + 4) v.lo1 mem1;
lemma_is_machine_heap_update32 (ptr + 8) v.hi2 mem2;
lemma_is_machine_heap_update32 (ptr + 12) v.hi3 mem3 | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_mem128 (ptr: int) (v: quad32) (s: state) : state | [] | Vale.PPC64LE.Semantics_s.update_mem128 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> v: Vale.Def.Types_s.quad32 -> s: Vale.PPC64LE.Machine_s.state
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 8,
"end_line": 203,
"start_col": 2,
"start_line": 197
} |
Prims.Tot | val update_mem_and_taint (ptr: int) (v: nat64) (s: state) (t: taint) : state | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let update_mem_and_taint (ptr:int) (v:nat64) (s:state) (t:taint) : state =
if valid_addr64 ptr (heap_get s.ms_heap) then
{ s with
ms_heap = heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s | val update_mem_and_taint (ptr: int) (v: nat64) (s: state) (t: taint) : state
let update_mem_and_taint (ptr: int) (v: nat64) (s: state) (t: taint) : state = | false | null | false | if valid_addr64 ptr (heap_get s.ms_heap)
then
{
s with
ms_heap
=
heap_upd s.ms_heap
(update_heap64 ptr v (heap_get s.ms_heap))
(update_n ptr 8 (heap_taint s.ms_heap) t)
}
else s | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"total"
] | [
"Prims.int",
"Vale.Def.Types_s.nat64",
"Vale.PPC64LE.Machine_s.state",
"Vale.Arch.HeapTypes_s.taint",
"Vale.Arch.MachineHeap_s.valid_addr64",
"Vale.Arch.Heap.heap_get",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_heap",
"Vale.PPC64LE.Machine_s.Mkstate",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ok",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__regs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__vecs",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__cr0",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__xer",
"Vale.Arch.Heap.heap_upd",
"Vale.Arch.MachineHeap_s.update_heap64",
"Vale.PPC64LE.Semantics_s.update_n",
"Vale.Arch.Heap.heap_taint",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stack",
"Vale.PPC64LE.Machine_s.__proj__Mkstate__item__ms_stackTaint",
"Prims.bool"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
() | false | true | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val update_mem_and_taint (ptr: int) (v: nat64) (s: state) (t: taint) : state | [] | Vale.PPC64LE.Semantics_s.update_mem_and_taint | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} |
ptr: Prims.int ->
v: Vale.Def.Types_s.nat64 ->
s: Vale.PPC64LE.Machine_s.state ->
t: Vale.Arch.HeapTypes_s.taint
-> Vale.PPC64LE.Machine_s.state | {
"end_col": 8,
"end_line": 160,
"start_col": 2,
"start_line": 154
} |
FStar.Pervasives.Lemma | val lemma_is_machine_heap_update64 (ptr: int) (v: nat64) (mh: machine_heap)
: Lemma (requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))] | [
{
"abbrev": false,
"full_module": "Vale.SHA2.Wrapper",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Sel",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Types",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.Heap",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.HeapTypes_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Arch.MachineHeap_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Types_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Seq_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Four_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words.Two_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.Def.Words_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE.Machine_s",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Seq.Base",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Mul",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "Vale.PPC64LE",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar.Pervasives",
"short_module": null
},
{
"abbrev": false,
"full_module": "Prims",
"short_module": null
},
{
"abbrev": false,
"full_module": "FStar",
"short_module": null
}
] | false | let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
=
reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
() | val lemma_is_machine_heap_update64 (ptr: int) (v: nat64) (mh: machine_heap)
: Lemma (requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))]
let lemma_is_machine_heap_update64 (ptr: int) (v: nat64) (mh: machine_heap)
: Lemma (requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))] = | false | null | true | reveal_opaque (`%valid_addr64) valid_addr64;
update_heap64_reveal ();
() | {
"checked_file": "Vale.PPC64LE.Semantics_s.fst.checked",
"dependencies": [
"Vale.SHA2.Wrapper.fsti.checked",
"Vale.PPC64LE.Machine_s.fst.checked",
"Vale.Math.Poly2_s.fsti.checked",
"Vale.Math.Poly2.Bits_s.fsti.checked",
"Vale.Lib.Set.fsti.checked",
"Vale.Def.Words_s.fsti.checked",
"Vale.Def.Words.Two_s.fsti.checked",
"Vale.Def.Words.Seq_s.fsti.checked",
"Vale.Def.Words.Four_s.fsti.checked",
"Vale.Def.Types_s.fst.checked",
"Vale.Def.Sel.fst.checked",
"Vale.Arch.Types.fsti.checked",
"Vale.Arch.MachineHeap_s.fst.checked",
"Vale.Arch.HeapTypes_s.fst.checked",
"Vale.Arch.Heap.fsti.checked",
"Vale.AES.AES_BE_s.fst.checked",
"prims.fst.checked",
"FStar.UInt.fsti.checked",
"FStar.Seq.Base.fsti.checked",
"FStar.Pervasives.Native.fst.checked",
"FStar.Pervasives.fsti.checked",
"FStar.Mul.fst.checked",
"FStar.Map.fsti.checked"
],
"interface_file": false,
"source_file": "Vale.PPC64LE.Semantics_s.fst"
} | [
"lemma"
] | [
"Prims.int",
"Vale.Def.Types_s.nat64",
"Vale.Arch.MachineHeap_s.machine_heap",
"Prims.unit",
"Vale.Arch.MachineHeap_s.update_heap64_reveal",
"FStar.Pervasives.reveal_opaque",
"Prims.bool",
"Vale.Arch.MachineHeap_s.valid_addr64",
"Prims.b2t",
"Prims.squash",
"Vale.Arch.MachineHeap_s.is_machine_heap_update",
"Vale.Arch.MachineHeap_s.update_heap64",
"Prims.Cons",
"FStar.Pervasives.pattern",
"FStar.Pervasives.smt_pat",
"Prims.logical",
"Prims.Nil"
] | [] | module Vale.PPC64LE.Semantics_s
open FStar.Mul
open FStar.Seq.Base
open Vale.PPC64LE.Machine_s
open Vale.Def.Words_s
open Vale.Def.Words.Two_s
open Vale.Def.Words.Four_s
open Vale.Def.Words.Seq_s
open Vale.Def.Types_s
include Vale.Arch.MachineHeap_s
open Vale.Arch.HeapTypes_s
open Vale.Arch.Heap
open Vale.Arch.Types
open Vale.Def.Sel
open Vale.SHA2.Wrapper
let (.[]) = Map.sel
let (.[]<-) = Map.upd
type ins =
| Move : dst:reg -> src:reg -> ins
| Load64 : dst:reg -> base:reg -> offset:int -> ins
| Store64 : src:reg -> base:reg -> offset:int -> ins
| LoadImm64 : dst:reg -> src:simm16 -> ins
| LoadImmShl64 : dst:reg -> src:simm16 -> ins
| AddLa : dst:reg -> src1:reg -> src2:simm16 -> ins
| Add : dst:reg -> src1:reg -> src2:reg -> ins
| AddImm : dst:reg -> src1:reg -> src2:simm16 -> ins
| AddCarry : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtended : dst:reg -> src1:reg -> src2:reg -> ins
| AddExtendedOV: dst:reg -> src1:reg -> src2:reg -> ins
| Sub : dst:reg -> src1:reg -> src2:reg -> ins
| SubImm : dst:reg -> src1:reg -> src2:nsimm16 -> ins
| MulLow64 : dst:reg -> src1:reg -> src2:reg -> ins
| MulHigh64U : dst:reg -> src1:reg -> src2:reg -> ins
| Xor : dst:reg -> src1:reg -> src2:reg -> ins
| And : dst:reg -> src1:reg -> src2:reg -> ins
| Sr64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sl64Imm : dst:reg -> src1:reg -> src2:bits64 -> ins
| Sr64 : dst:reg -> src1:reg -> src2:reg -> ins
| Sl64 : dst:reg -> src1:reg -> src2:reg -> ins
| Vmr : dst:vec -> src:vec -> ins
| Mfvsrd : dst:reg -> src:vec -> ins
| Mfvsrld : dst:reg -> src:vec -> ins
| Mtvsrdd : dst:vec -> src1:reg -> src2:reg -> ins
| Mtvsrws : dst:vec -> src:reg -> ins
| Vadduwm : dst:vec -> src1:vec -> src2:vec -> ins
| Vxor : dst:vec -> src1:vec -> src2:vec -> ins
| Vand : dst:vec -> src1:vec -> src2:vec -> ins
| Vslw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsrw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsl : dst:vec -> src1:vec -> src2:vec -> ins
| Vcmpequw : dst:vec -> src1:vec -> src2:vec -> ins
| Vsldoi : dst:vec -> src1:vec -> src2:vec -> count:quad32bytes -> ins
| Vmrghw : dst:vec -> src1:vec -> src2:vec -> ins
| Xxmrghd : dst:vec -> src1:vec -> src2:vec -> ins
| Vsel : dst:vec -> src1:vec -> src2:vec -> sel:vec -> ins
| Vspltw : dst:vec -> src:vec -> uim:nat2 -> ins
| Vspltisw : dst:vec -> src:sim -> ins
| Vspltisb : dst:vec -> src:sim -> ins
| Load128 : dst:vec -> base:reg -> offset:reg -> ins
| Store128 : src:vec -> base:reg -> offset:reg -> ins
| Load128Word4 : dst:vec -> base:reg -> ins
| Load128Word4Index : dst:vec -> base:reg -> offset:reg -> ins
| Store128Word4: src:vec -> base:reg -> ins
| Store128Word4Index: src:vec -> base:reg -> offset:reg -> ins
| Load128Byte16: dst:vec -> base:reg -> ins
| Load128Byte16Index: dst:vec -> base:reg -> offset:reg -> ins
| Store128Byte16: src:vec -> base:reg -> ins
| Store128Byte16Index: src:vec -> base:reg -> offset:reg -> ins
| Vshasigmaw0 : dst:vec -> src:vec -> ins
| Vshasigmaw1 : dst:vec -> src:vec -> ins
| Vshasigmaw2 : dst:vec -> src:vec -> ins
| Vshasigmaw3 : dst:vec -> src:vec -> ins
| Vsbox : dst:vec -> src:vec -> ins
| RotWord : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vcipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipher : dst:vec -> src1:vec -> src2:vec -> ins
| Vncipherlast : dst:vec -> src1:vec -> src2:vec -> ins
| Vpmsumd : dst:vec -> src1:vec -> src2:vec -> ins
| Alloc : n:nat64 -> ins
| Dealloc : n:nat64 -> ins
| StoreStack128: src:vec -> t:taint -> offset:int -> ins
| LoadStack128 : dst:vec -> t:taint -> offset:int -> ins
| StoreStack64 : src:reg -> t:taint -> offset:int -> ins
| LoadStack64 : dst:reg -> t:taint -> offset:int -> ins
| Ghost : (_:unit) -> ins
type ocmp =
| OEq: o1:cmp_opr -> o2:cmp_opr -> ocmp
| ONe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGe: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OLt: o1:cmp_opr -> o2:cmp_opr -> ocmp
| OGt: o1:cmp_opr -> o2:cmp_opr -> ocmp
type code = precode ins ocmp
type codes = list code
unfold let eval_reg (r:reg) (s:state) : nat64 = s.regs r
unfold let eval_vec (v:vec) (s:state) : quad32 = s.vecs v
unfold let eval_mem (ptr:int) (s:state) : nat64 = get_heap_val64 ptr (heap_get s.ms_heap)
unfold let eval_mem128 (ptr:int) (s:state) : quad32 = get_heap_val128 ptr (heap_get s.ms_heap)
unfold let eval_stack (ptr:int) (s:machine_stack) : nat64 =
let Machine_stack _ mem = s in
get_heap_val64 ptr mem
unfold let eval_stack128 (ptr:int) (s:machine_stack) : quad32 =
let Machine_stack _ mem = s in
get_heap_val128 ptr mem
(*
Check if the taint annotation of a memory operand matches the taint in the memory map.
Evaluation will fail in case of a mismatch.
This allows the taint analysis to learn information about the memory map from the annotation,
assuming that the code has been verified not to fail.
(Note that this only relates to memory maps, so non-memory operands need no annotation.)
*)
[@"opaque_to_smt"]
let rec match_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (b:bool{b <==>
(forall i.{:pattern (memTaint `Map.sel` i)}
(i >= addr /\ i < addr + n) ==> memTaint.[i] == t)})
(decreases n)
=
if n = 0 then true
else if memTaint.[addr] <> t then false
else match_n (addr + 1) (n - 1) memTaint t
[@"opaque_to_smt"]
let rec update_n (addr:int) (n:nat) (memTaint:memTaint_t) (t:taint)
: Tot (m:memTaint_t{(
forall i.{:pattern (m `Map.sel` i)}
((i >= addr /\ i < addr + n) ==> m.[i] == t) /\
((i < addr \/ i >= addr + n) ==> m.[i] == memTaint.[i]))})
(decreases n)
=
if n = 0 then memTaint
else update_n (addr + 1) (n - 1) (memTaint.[addr] <- t) t
let lemma_is_machine_heap_update64 (ptr:int) (v:nat64) (mh:machine_heap) : Lemma
(requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))] | false | false | Vale.PPC64LE.Semantics_s.fst | {
"detail_errors": false,
"detail_hint_replay": false,
"initial_fuel": 2,
"initial_ifuel": 0,
"max_fuel": 1,
"max_ifuel": 1,
"no_plugins": false,
"no_smt": false,
"no_tactics": false,
"quake_hi": 1,
"quake_keep": false,
"quake_lo": 1,
"retry": false,
"reuse_hint_for": null,
"smtencoding_elim_box": true,
"smtencoding_l_arith_repr": "native",
"smtencoding_nl_arith_repr": "wrapped",
"smtencoding_valid_elim": false,
"smtencoding_valid_intro": true,
"tcnorm": true,
"trivial_pre_for_unannotated_effectful_fns": false,
"z3cliopt": [
"smt.arith.nl=false",
"smt.QI.EAGER_THRESHOLD=100",
"smt.CASE_SPLIT=3"
],
"z3refresh": false,
"z3rlimit": 5,
"z3rlimit_factor": 1,
"z3seed": 0,
"z3smtopt": [],
"z3version": "4.8.5"
} | null | val lemma_is_machine_heap_update64 (ptr: int) (v: nat64) (mh: machine_heap)
: Lemma (requires valid_addr64 ptr mh)
(ensures is_machine_heap_update mh (update_heap64 ptr v mh))
[SMTPat (is_machine_heap_update mh (update_heap64 ptr v mh))] | [] | Vale.PPC64LE.Semantics_s.lemma_is_machine_heap_update64 | {
"file_name": "vale/specs/hardware/Vale.PPC64LE.Semantics_s.fst",
"git_rev": "12c5e9539c7e3c366c26409d3b86493548c4483e",
"git_url": "https://github.com/hacl-star/hacl-star.git",
"project_name": "hacl-star"
} | ptr: Prims.int -> v: Vale.Def.Types_s.nat64 -> mh: Vale.Arch.MachineHeap_s.machine_heap
-> FStar.Pervasives.Lemma (requires Vale.Arch.MachineHeap_s.valid_addr64 ptr mh)
(ensures
Vale.Arch.MachineHeap_s.is_machine_heap_update mh
(Vale.Arch.MachineHeap_s.update_heap64 ptr v mh))
[
SMTPat (Vale.Arch.MachineHeap_s.is_machine_heap_update mh
(Vale.Arch.MachineHeap_s.update_heap64 ptr v mh))
] | {
"end_col": 4,
"end_line": 151,
"start_col": 2,
"start_line": 149
} |
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