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Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/cmsis_gcc.h | /**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler GCC header file
* @version V5.2.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GCC_H
#define __CMSIS_GCC_H
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
/**
\brief Initializes data and bss sections
\details This default implementations initialized all data and additional bss
sections relying on .copy.table and .zero.table specified properly
in the used linker script.
*/
__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
{
extern void _start(void) __NO_RETURN;
typedef struct {
uint32_t const* src;
uint32_t* dest;
uint32_t wlen;
} __copy_table_t;
typedef struct {
uint32_t* dest;
uint32_t wlen;
} __zero_table_t;
extern const __copy_table_t __copy_table_start__;
extern const __copy_table_t __copy_table_end__;
extern const __zero_table_t __zero_table_start__;
extern const __zero_table_t __zero_table_end__;
for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
for(uint32_t i=0u; i<pTable->wlen; ++i) {
pTable->dest[i] = pTable->src[i];
}
}
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
for(uint32_t i=0u; i<pTable->wlen; ++i) {
pTable->dest[i] = 0u;
}
}
_start();
}
#define __PROGRAM_START __cmsis_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP __StackTop
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT __StackLimit
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Control Register (non-secure)
\details Returns the content of the non-secure Control Register when in secure mode.
\return non-secure Control Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Control Register (non-secure)
\details Writes the given value to the non-secure Control Register when in secure state.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
}
#endif
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Process Stack Pointer (non-secure)
\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Process Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
}
#endif
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Main Stack Pointer (non-secure)
\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Main Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
}
#endif
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Stack Pointer (non-secure)
\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
\return SP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return(result);
}
/**
\brief Set Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
\param [in] topOfStack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
{
__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
}
#endif
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Priority Mask (non-secure)
\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
return(result);
}
#endif
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Priority Mask (non-secure)
\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
{
__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
}
#endif
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Base Priority (non-secure)
\details Returns the current value of the non-secure Base Priority register when in secure state.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
{
__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Base Priority (non-secure)
\details Assigns the given value to the non-secure Base Priority register when in secure state.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
{
__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
}
#endif
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Fault Mask (non-secure)
\details Returns the current value of the non-secure Fault Mask register when in secure state.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Fault Mask (non-secure)
\details Assigns the given value to the non-secure Fault Mask register when in secure state.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
}
#endif
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief Get Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
return result;
#endif
}
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Process Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
return result;
#endif
}
#endif
/**
\brief Set Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Process Stack Pointer (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
#endif
}
#endif
/**
\brief Get Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
return result;
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
return result;
#endif
}
#endif
/**
\brief Set Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
\param [in] MainStackPtrLimit Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
#endif
}
#endif
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#endif
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
#endif
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constraint "l"
* Otherwise, use general registers, specified by constraint "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_RW_REG(r) "+l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_RW_REG(r) "+r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP() __ASM volatile ("nop")
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI() __ASM volatile ("wfi")
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE() __ASM volatile ("wfe")
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV() __ASM volatile ("sev")
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__STATIC_FORCEINLINE void __ISB(void)
{
__ASM volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
}
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return result;
#endif
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return result;
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (int16_t)__builtin_bswap16(value);
#else
int16_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return result;
#endif
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
op2 %= 32U;
if (op2 == 0U)
{
return op1;
}
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
#else
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
}
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
{
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
__builtin_clz(0) is undefined behaviour, so handle this case specially.
This guarantees ARM-compatible results if happening to compile on a non-ARM
target, and ensures the compiler doesn't decide to activate any
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
{
return 32U;
}
return __builtin_clz(value);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
__STATIC_FORCEINLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] ARG1 Value to be saturated
\param [in] ARG2 Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
__extension__ \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] ARG1 Value to be saturated
\param [in] ARG2 Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
}
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
}
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief Load-Acquire (8 bit)
\details Executes a LDAB instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint8_t) result);
}
/**
\brief Load-Acquire (16 bit)
\details Executes a LDAH instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint16_t) result);
}
/**
\brief Load-Acquire (32 bit)
\details Executes a LDA instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
}
/**
\brief Store-Release (8 bit)
\details Executes a STLB instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Store-Release (16 bit)
\details Executes a STLH instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Store-Release (32 bit)
\details Executes a STL instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Load-Acquire Exclusive (8 bit)
\details Executes a LDAB exclusive instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint8_t) result);
}
/**
\brief Load-Acquire Exclusive (16 bit)
\details Executes a LDAH exclusive instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint16_t) result);
}
/**
\brief Load-Acquire Exclusive (32 bit)
\details Executes a LDA exclusive instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
}
/**
\brief Store-Release Exclusive (8 bit)
\details Executes a STLB exclusive instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief Store-Release Exclusive (16 bit)
\details Executes a STLH exclusive instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief Store-Release Exclusive (32 bit)
\details Executes a STL exclusive instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
return(result);
}
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#if 0
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#endif
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#endif /* (__ARM_FEATURE_DSP == 1) */
/*@} end of group CMSIS_SIMD_intrinsics */
#pragma GCC diagnostic pop
#endif /* __CMSIS_GCC_H */
| 62,627 | C | 27.874136 | 143 | 0.598049 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/core_cm23.h | /**************************************************************************//**
* @file core_cm23.h
* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
* @version V5.0.8
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM23_H_GENERIC
#define __CORE_CM23_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M23
@{
*/
#include "cmsis_version.h"
/* CMSIS definitions */
#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
__CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (23U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM23_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM23_H_DEPENDANT
#define __CORE_CM23_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM23_REV
#define __CM23_REV 0x0000U
#warning "__CM23_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#ifndef __ETM_PRESENT
#define __ETM_PRESENT 0U
#warning "__ETM_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MTB_PRESENT
#define __MTB_PRESENT 0U
#warning "__MTB_PRESENT not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M23 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
uint32_t RESERVED0[6U];
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
__IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
__IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration Test FIFO Test Data 0 Register Definitions */
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
/* TPI Integration Test ATB Control Register 2 Register Definitions */
#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
/* TPI Integration Test FIFO Test Data 1 Register Definitions */
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
/* TPI Integration Test ATB Control Register 0 Definitions */
#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
uint32_t RESERVED0[7U];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 1U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#endif
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED4[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
If VTOR is not present address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM23_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| 102,697 | C | 50.426139 | 178 | 0.551087 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/cmsis_armcc.h | /**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */
| 28,132 | C | 30.43352 | 126 | 0.557621 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/tz_context.h | /******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H
| 2,687 | C | 36.859154 | 88 | 0.68329 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/cmsis_iccarm.h | /**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */
| 28,163 | C | 28.185492 | 106 | 0.553457 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/core_cm0.h | /**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| 41,430 | C | 42.474292 | 178 | 0.556384 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/mpu_armv8.h | /******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif
| 11,255 | C | 31.43804 | 130 | 0.668769 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/core_cm3.h | /**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V5.1.0
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM3_H_GENERIC
#define __CORE_CM3_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M3
@{
*/
#include "cmsis_version.h"
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
__CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (3U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM3_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM3_H_DEPENDANT
#define __CORE_CM3_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM3_REV
#define __CM3_REV 0x0200U
#warning "__CM3_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[24U];
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[5U];
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#else
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
#else
uint32_t RESERVED1[1U];
#endif
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
#endif
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED0[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
__IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED1[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
__IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
__IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = (uint32_t )SCB->VTOR;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M3 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = (uint32_t )SCB->VTOR;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM3_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| 109,420 | C | 55.460784 | 178 | 0.531749 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/cmsis_armclang_ltm.h | /**************************************************************************//**
* @file cmsis_armclang_ltm.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
* @version V1.2.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
#ifndef __CMSIS_ARMCLANG_H
#define __CMSIS_ARMCLANG_H
#pragma clang system_header /* treat file as system include file */
#ifndef __ARM_COMPAT_H
#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); see arm_compat.h */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); see arm_compat.h */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Control Register (non-secure)
\details Returns the content of the non-secure Control Register when in secure mode.
\return non-secure Control Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Control Register (non-secure)
\details Writes the given value to the non-secure Control Register when in secure state.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
}
#endif
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Process Stack Pointer (non-secure)
\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Process Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
}
#endif
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Main Stack Pointer (non-secure)
\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Main Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
}
#endif
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Stack Pointer (non-secure)
\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
\return SP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return(result);
}
/**
\brief Set Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
\param [in] topOfStack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
{
__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
}
#endif
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Priority Mask (non-secure)
\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Priority Mask (non-secure)
\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
{
__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
}
#endif
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Base Priority (non-secure)
\details Returns the current value of the non-secure Base Priority register when in secure state.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
{
__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Base Priority (non-secure)
\details Assigns the given value to the non-secure Base Priority register when in secure state.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
{
__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
}
#endif
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Fault Mask (non-secure)
\details Returns the current value of the non-secure Fault Mask register when in secure state.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Fault Mask (non-secure)
\details Assigns the given value to the non-secure Fault Mask register when in secure state.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
}
#endif
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief Get Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
return result;
#endif
}
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Process Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
return result;
#endif
}
#endif
/**
\brief Set Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Process Stack Pointer (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
#endif
}
#endif
/**
\brief Get Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
return result;
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
return result;
#endif
}
#endif
/**
\brief Set Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
\param [in] MainStackPtrLimit Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
#endif
}
#endif
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
#else
#define __get_FPSCR() ((uint32_t)0U)
#endif
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __set_FPSCR __builtin_arm_set_fpscr
#else
#define __set_FPSCR(x) ((void)(x))
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constraint "l"
* Otherwise, use general registers, specified by constraint "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __builtin_arm_nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __builtin_arm_wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __builtin_arm_wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __builtin_arm_sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() __builtin_arm_isb(0xF)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __builtin_arm_dsb(0xF)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __builtin_arm_dmb(0xF)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV(value) __builtin_bswap32(value)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV16(value) __ROR(__REV(value), 16)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REVSH(value) (int16_t)__builtin_bswap16(value)
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
op2 %= 32U;
if (op2 == 0U)
{
return op1;
}
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __builtin_arm_rbit
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
{
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
__builtin_clz(0) is undefined behaviour, so handle this case specially.
This guarantees ARM-compatible results if happening to compile on a non-ARM
target, and ensures the compiler doesn't decide to activate any
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
{
return 32U;
}
return __builtin_clz(value);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB (uint8_t)__builtin_arm_ldrex
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH (uint16_t)__builtin_arm_ldrex
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW (uint32_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB (uint32_t)__builtin_arm_strex
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH (uint32_t)__builtin_arm_strex
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW (uint32_t)__builtin_arm_strex
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __builtin_arm_clrex
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __builtin_arm_ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __builtin_arm_usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
}
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
}
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief Load-Acquire (8 bit)
\details Executes a LDAB instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint8_t) result);
}
/**
\brief Load-Acquire (16 bit)
\details Executes a LDAH instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint16_t) result);
}
/**
\brief Load-Acquire (32 bit)
\details Executes a LDA instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
}
/**
\brief Store-Release (8 bit)
\details Executes a STLB instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Store-Release (16 bit)
\details Executes a STLH instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Store-Release (32 bit)
\details Executes a STL instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Load-Acquire Exclusive (8 bit)
\details Executes a LDAB exclusive instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDAEXB (uint8_t)__builtin_arm_ldaex
/**
\brief Load-Acquire Exclusive (16 bit)
\details Executes a LDAH exclusive instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDAEXH (uint16_t)__builtin_arm_ldaex
/**
\brief Load-Acquire Exclusive (32 bit)
\details Executes a LDA exclusive instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDAEX (uint32_t)__builtin_arm_ldaex
/**
\brief Store-Release Exclusive (8 bit)
\details Executes a STLB exclusive instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEXB (uint32_t)__builtin_arm_stlex
/**
\brief Store-Release Exclusive (16 bit)
\details Executes a STLH exclusive instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEXH (uint32_t)__builtin_arm_stlex
/**
\brief Store-Release Exclusive (32 bit)
\details Executes a STL exclusive instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEX (uint32_t)__builtin_arm_stlex
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#endif /* (__ARM_FEATURE_DSP == 1) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCLANG_H */
| 55,224 | C | 28.188689 | 143 | 0.606312 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/core_sc000.h | /**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup SC000
@{
*/
#include "cmsis_version.h"
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
__SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000U
#warning "__SC000_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154U];
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the SC000 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| 46,407 | C | 44.231969 | 143 | 0.536816 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/core_armv8mbl.h | /**************************************************************************//**
* @file core_armv8mbl.h
* @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
* @version V5.0.8
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_ARMV8MBL_H_GENERIC
#define __CORE_ARMV8MBL_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_ARMv8MBL
@{
*/
#include "cmsis_version.h"
/* CMSIS definitions */
#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
__ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_ARMV8MBL_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_ARMV8MBL_H_DEPENDANT
#define __CORE_ARMV8MBL_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __ARMv8MBL_REV
#define __ARMv8MBL_REV 0x0000U
#warning "__ARMv8MBL_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#ifndef __ETM_PRESENT
#define __ETM_PRESENT 0U
#warning "__ETM_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MTB_PRESENT
#define __MTB_PRESENT 0U
#warning "__MTB_PRESENT not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group ARMv8MBL */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
uint32_t RESERVED0[6U];
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[809U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
uint32_t RESERVED4[4U];
__IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI Periodic Synchronization Control Register Definitions */
#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
/* TPI Software Lock Status Register Definitions */
#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
uint32_t RESERVED0[7U];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 1U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#endif
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED4[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
If VTOR is not present address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| 96,139 | C | 49.020812 | 178 | 0.547239 |
Tbarkin121/GuardDog/stm32/TorquePoleNet/Drivers/CMSIS/Include/cmsis_compiler.h | /**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
| 9,481 | C | 32.387324 | 113 | 0.559224 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/potentiometer.c | /**
******************************************************************************
* @file potentiometer.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides the functions that implement the potentiometer
* component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup Potentiometer
*/
/* Includes ------------------------------------------------------------------*/
#include "potentiometer.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup Potentiometer Linear Potentiometer
* @brief Linear Potentiometer reading component of the Motor Control SDK
*
* The Potentiometer component aims at measuring the voltage set on a linear
* potentiometer. It uses the services of the @ref RCM component to get measures
* from an ADC channel connected to the potentiometer.
*
* The component is designed to take potentiometer measures periodically. It
* computes a moving average on a number of these measures in order to reduce
* the reading noise. This moving average is the potentiometer value produced
* by the component. It is retrieved by calling the POT_GetValue() function.
*
* The measures are taken by the POT_TakeMeasurement() function. This
* function must then be called periodically.
*
* At startup or after a call to the POT_Clear() function, a valid average
* potentiometer value is not immediately available. Enough measures need to be
* taken so that the moving average can be computed. The POT_ValidValueAvailable()
* function can be used to check whether a valid potentiometer value is returned
* when calling the POT_GetValue() function.
*
* The state of a Potentiometer component is maintained in a Potentiometer_Handle_t
* structure. To use the Potentiometer component, a Potentiometer_Handle_t structure
* needs to be instanciated and initialized. The initialization is performed thanks
* to the POT_Init() function. Prior to calling this function, some of the fields of
* this structure need to be given a value. See the Potentiometer_Handle_t and below
* for more details on this.
*
* The Potentiometer component accumulates a number of measures on which it
* computes a moving average. For performance reasons, this number must be a
* power of two. This is set in the Potentiometer_Handle_t::LPFilterBandwidthPOW2
* field of the potentiometer handle structure.
*
* @note In the current version of the Potentiometer component, the periodic ADC
* measures **must** be performed on the Medium Frequency Task. This can be done by using
* the MC_APP_PostMediumFrequencyHook_M1() function of the @ref MCAppHooks service
* for instance.
*
* @{
*/
/* Public functions ----------------------------------------------------------*/
/**
* @brief Initializes a Potentiometer component
*
* This function must be called once before starting to use the component.
*
* @param pHandle Handle on the Potentiometer component to initialize
*/
void POT_Init(Potentiometer_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_POT
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif /* NULL_PTR_CHECK_POT */
/* Potentiometer component init */
pHandle->LPFilterBandwidth = (uint16_t)(1 << pHandle->LPFilterBandwidthPOW2);
POT_Clear(pHandle);
#ifdef NULL_PTR_CHECK_POT
}
#endif /* NULL_PTR_CHECK_POT */
}
/**
* @brief Clears the state of a Potentiometer component
*
* After this function has been called, the potentiometer value
* becomes invalid. See the @ref Potentiometer documentation for more
* details.
*
* @param pHandle Handle on the Potentiometer component
*/
void POT_Clear(Potentiometer_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_POT
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif /* NULL_PTR_CHECK_POT */
for (uint8_t i = 0; i < pHandle->LPFilterBandwidth; i++)
{
pHandle->PotMeasArray[i] = (uint16_t) 0;
}
pHandle->PotValueAccumulator = (uint32_t)0;
pHandle->Index = (uint16_t)0;
pHandle->Valid = (bool) false;
#ifdef NULL_PTR_CHECK_POT
}
#endif /* NULL_PTR_CHECK_POT */
}
/**
* @brief Measures the voltage of the potentiometer of a Potentiometer component
*
* This function needs to be called periodically. See the @ref Potentiometer
* documentation for more details.
*
* @param pHandle Handle on the Potentiometer component
*/
void POT_TakeMeasurement(Potentiometer_Handle_t *pHandle, uint16_t rawValue)
{
#ifdef NULL_PTR_CHECK_POT
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif /* NULL_PTR_CHECK_POT */
/* Update the Accumulator */
pHandle->PotValueAccumulator -= (uint32_t) pHandle->PotMeasArray[pHandle->Index];
pHandle->PotMeasArray[pHandle->Index] = rawValue;
pHandle->PotValueAccumulator += (uint32_t) pHandle->PotMeasArray[pHandle->Index];
/* Update the Index */
pHandle->Index++;
if (pHandle->Index == pHandle->LPFilterBandwidth)
{
pHandle->Index = 0;
/* The Index has reached the end of the measurement array.
* So, the accumulator is only made of actual measure.
* Hence, its value is considered valid. */
pHandle->Valid = true;
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_POT
}
#endif /* NULL_PTR_CHECK_POT */
}
/**
* @brief Returns the current value of a Potentiometer component
*
* @param pHandle Handle on the Potentiometer component
*/
uint16_t POT_GetValue(Potentiometer_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_POT
return ((NULL == pHandle) ? 0U : (uint16_t)(pHandle->PotValueAccumulator >> pHandle->LPFilterBandwidthPOW2));
#else /* NULL_PTR_CHECK_POT */
return ((uint16_t)(pHandle->PotValueAccumulator >> pHandle->LPFilterBandwidthPOW2));
#endif /* NULL_PTR_CHECK_POT */
}
/**
* @brief Returns true if the current value of a Potentiometer component is valid
* and false otherwise
*
* @param pHandle Handle on the Potentiometer component
*/
bool POT_ValidValueAvailable(Potentiometer_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_POT
return ((NULL == pHandle) ? 0U : pHandle->Valid);
#else /* NULL_PTR_CHECK_POT */
return (pHandle->Valid);
#endif /* NULL_PTR_CHECK_POT */
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| 6,915 | C | 32.090909 | 113 | 0.652639 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/gap_gate_driver_ctrl.c | /**
******************************************************************************
* @file gap_gate_driver_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the GAP component of the Motor Control SDK that provides support
* the STGAPxx galvanically isolated gate drivers family.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup GAP_GATE_DRIVER_CTRL
*/
/* Includes ------------------------------------------------------------------*/
#include "gap_gate_driver_ctrl.h"
#include "mc_type.h"
/**
* @addtogroup MCSDK
* @{
*/
/**
* @defgroup GAP_GATE_DRIVER_CTRL STGAP1x controller
* @brief A component to interface with the configuration and diagnostic
* features of STGAP1x gate drivers through SPI
*
* The STGAP1x gate drivers family offers galvanically isolated gate drivers
* for high-power MOSFET and IGBT applications. These devices provide advanced
* configuration and diagnostic features that are accessible through their SPI
* interface. Several STGAP1x devices can be daisy-chained on an SPI bus.
*
* The STGAP1x controller component allows for configuring any number of STGAP1x
* devices daisy-chained on an SPI bus and for accessing their diagnostic
* registers.
*
* The GAP driver configuration is performed at the first steps of the MCboot().
* In a MCSDK project up to seven gate drivers might be configured:
*
* 1 brake STGAP1AS_BRAKE
*
* 3 high and low side PWM signals
STGAP1AS_UH,
STGAP1AS_UL,
STGAP1AS_VH,
STGAP1AS_VL,
STGAP1AS_WH,
STGAP1AS_WL.
*
* More information on STGAP1x can be find on st.com: [Isolated Gate Drivers](https://www.st.com/en/motor-drivers/isolated-gate-drivers.html)
*
* @{
*/
/* Private defines -----------------------------------------------------------*/
#define GAP_STARTCONFIG 0x2A /**< @brief CRC data computation value to start GAP driver configuration. */
#define GAP_STOPCONFIG 0x3A /**< @brief CRC data computation value to stop GAP driver configuration. */
#define GAP_WRITEREG 0x80 /**< @brief CRC data computation value for writing register. */
#define GAP_READREG 0xA0 /**< @brief CRC data computation value for reading register. */
#define GAP_RESETREG 0xC0 /**< @brief CRC data computation value to reset a register. */
#define GAP_RESETSTATUS 0xD0 /**< @brief CRC data computation value to reset a status register. */
#define GAP_GLOBALRESET 0xEA /**< @brief CRC data computation value to reset GAP driver. */
#define GAP_SLPEEP 0xF5 /**< @brief CRC data computation value to set GAP driver in sleep mode. */
#define GAP_NOP 0x00 /**< @brief CRC data computation value for no operation. */
#define GAP_ERROR_CODE_FROM_DEVICE_MASK (uint32_t)(0xFF000000) /**< @brief ERROR code mask */
#define WAITTIME 5000 /**< @brief 860u wait time duration. */
#define WAITTRCHK 50 /**< @brief 8.6u wait time duration. */
#define WAITTSENSECHK 50 /**< @brief 8.6u wait time duration. */
#define WAITTGCHK 50 /**< @brief 8.6u wait time duration. */
#define WAITTDESATCHK 50 /**< @brief 8.6u wait time duration. */
/* Global variables ----------------------------------------------------------*/
static void GAP_SD_Deactivate(GAP_Handle_t *pHandle_t);
static void GAP_SD_Activate(GAP_Handle_t *pHandle_t);
static void GAP_CS_Deactivate(GAP_Handle_t *pHandle_t);
static void GAP_CS_Activate(GAP_Handle_t *pHandle_t);
static uint16_t GAP_SPI_Send(GAP_Handle_t *pHandle_t, uint16_t value);
/**
* @brief Checks errors of GAP devices
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @param errorNow Buffer of returned bitfields containing error flags
* coming from GAP device that are currently active.\n
* The buffer have to be provided from the caller.
* @param errorOccurred Buffer of returned bitfields containing error flags
* coming from GAP device that are over.\n
* The buffer have to be provided from the caller.
* @retval bool It returns false if an error occurs, otherwise return true.
*/
__weak bool GAP_CheckErrors(GAP_Handle_t *pHandle, uint32_t *error_now, uint32_t *error_occurred)
{
bool ret_val = false;
uint32_t errorFromDevices[MAX_DEVICES_NUMBER];
if ((error_now) && (error_occurred))
{
uint8_t index1, index2;
uint8_t ret_read[MAX_DEVICES_NUMBER];
// /* If current error is device not programmable try to re-configure before
// read the status registers */
// if ((pDVars->wGAP_ErrorsNow[0] & GAP_ERROR_CODE_DEVICES_NOT_PROGRAMMABLE) ||
// (pDVars->wGAP_ErrorsNow[0] & GAP_ERROR_CODE_SPI_CRC))
// {
// if (GAP_Configuration(pHandle))
// {
// pDVars->wGAP_ErrorsNow[0] &= ~GAP_ERROR_CODE_DEVICES_NOT_PROGRAMMABLE;
// pDVars->wGAP_ErrorsNow[0] &= ~GAP_ERROR_CODE_SPI_CRC;
// }
// }
index2 = pHandle->DeviceNum;
ret_val = GAP_ReadRegs(pHandle, ret_read, STATUS1);
for (index1 = 0; index1 < index2; index1 ++)
{
errorFromDevices[index1] = (ret_read[index1] << 16);
}
ret_val = GAP_ReadRegs(pHandle, ret_read, STATUS2);
for (index1 = 0; index1 < index2; index1 ++)
{
/* Clear GATE bit from STATUS2 - no error if 1 */
ret_read[index1] &= 0xFE;
errorFromDevices[index1] |= (ret_read[index1] << 8);
}
ret_val = GAP_ReadRegs(pHandle, ret_read, STATUS3);
for (index1 = 0; index1 < index2; index1 ++)
{
errorFromDevices[index1] |= ret_read[index1];
}
for (index1 = 0; index1 < index2; index1 ++)
{
pHandle->GAP_ErrorsNow[index1] &= GAP_ERROR_CODE_FROM_DEVICE_MASK;
pHandle->GAP_ErrorsNow[index1] |= errorFromDevices[index1];
pHandle->GAP_ErrorsOccurred[index1] |= pHandle->GAP_ErrorsNow[index1];
error_now[index1] = pHandle->GAP_ErrorsNow[index1];
error_occurred[index1] = pHandle->GAP_ErrorsOccurred[index1];
}
}
return ret_val;
}
/**
* @brief Clears the fault state of GAP devices.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @retval none.
*/
__weak void GAP_FaultAck(GAP_Handle_t *pHandle)
{
uint8_t index1, index2;
uint16_t value;
GAP_SD_Activate(pHandle);
value = GAP_CRCCalculate(GAP_RESETSTATUS, 0xFF);
GAP_CS_Activate(pHandle);
index2 = pHandle->DeviceNum;
for (index1 = 0; index1 < index2; index1 ++)
{
GAP_SPI_Send(pHandle, value);
}
GAP_CS_Deactivate(pHandle);
GAP_SD_Deactivate(pHandle);
wait(WAITTIME);
for (index1 = 0; index1 < index2; index1 ++)
{
pHandle->GAP_ErrorsOccurred[index1] = GAP_ERROR_CLEAR;
}
}
/**
* @brief Programs the GAP devices with the settled parameters.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @retval bool It returns false if at least one device is not programmable,
* otherwise return true.
*/
__weak bool GAP_Configuration(GAP_Handle_t *pHandle)
{
bool ret_val;
LL_SPI_Enable(pHandle->SPIx);
/* Configure devices with settled parameters */
GAP_DevicesConfiguration(pHandle);
/* Verify if device has been programmed */
ret_val = GAP_IsDevicesProgrammed(pHandle);
if (!ret_val)
{
/* At least one device is not programmable */
pHandle->GAP_ErrorsNow[0] |= GAP_ERROR_CODE_DEVICES_NOT_PROGRAMMABLE;
pHandle->GAP_ErrorsOccurred[0] |= GAP_ERROR_CODE_DEVICES_NOT_PROGRAMMABLE;
}
return ret_val;
}
/**
* @brief Checks if the GAP devices are programmed with the settled parameters.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @retval True if the GAP devices are already programmed with the settled
* parameters.
*/
__weak bool GAP_IsDevicesProgrammed(GAP_Handle_t *pHandle)
{
bool ret_val = true;
uint8_t index1, index2 = pHandle->DeviceNum;
uint8_t read_reg_values[MAX_DEVICES_NUMBER];
GAP_ReadRegs(pHandle, read_reg_values, CFG1);
for (index1 = 0; index1 < index2; index1 ++)
{
if ((pHandle->DeviceParams[index1].CFG1 & CFG1_REG_MASK) != read_reg_values[index1])
{
ret_val = false;
break;
}
}
if (ret_val)
{
GAP_ReadRegs(pHandle, read_reg_values, CFG2);
for (index1 = 0; index1 < index2; index1 ++)
{
if ((pHandle->DeviceParams[index1].CFG2 & CFG2_REG_MASK) != read_reg_values[index1])
{
ret_val = false;
break;
}
}
}
if (ret_val)
{
GAP_ReadRegs(pHandle, read_reg_values, CFG3);
for (index1 = 0; index1 < index2; index1 ++)
{
if ((pHandle->DeviceParams[index1].CFG3 & CFG3_REG_MASK) != read_reg_values[index1])
{
ret_val = false;
break;
}
}
}
if (ret_val)
{
GAP_ReadRegs(pHandle, read_reg_values, CFG4);
for (index1 = 0; index1 < index2; index1 ++)
{
if ((pHandle->DeviceParams[index1].CFG4 & CFG4_REG_MASK) != read_reg_values[index1])
{
ret_val = false;
break;
}
}
}
if (ret_val)
{
GAP_ReadRegs(pHandle, read_reg_values, CFG5);
for (index1 = 0; index1 < index2; index1 ++)
{
if ((pHandle->DeviceParams[index1].CFG5 & CFG5_REG_MASK) != read_reg_values[index1])
{
ret_val = false;
break;
}
}
}
if (ret_val)
{
GAP_ReadRegs(pHandle, read_reg_values, DIAG1);
for (index1 = 0; index1 < index2; index1 ++)
{
if ((pHandle->DeviceParams[index1].DIAG1 & DIAG1_REG_MASK) != read_reg_values[index1])
{
ret_val = false;
break;
}
}
}
if (ret_val)
{
GAP_ReadRegs(pHandle, read_reg_values, DIAG2);
for (index1 = 0; index1 < index2; index1 ++)
{
if ((pHandle->DeviceParams[index1].DIAG2 & DIAG2_REG_MASK) != read_reg_values[index1])
{
ret_val = false;
break;
}
}
}
return ret_val;
}
/**
* @brief Programs the GAP devices with the settled parameters.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @retval bool It returns false if an error occurs, otherwise return true.
*/
__weak bool GAP_DevicesConfiguration(GAP_Handle_t *pHandle)
{
bool ret_val = true;
uint8_t index1, DeviceNum = pHandle->DeviceNum;
uint8_t write_reg_values[MAX_DEVICES_NUMBER];
GAP_StartConfig(pHandle);
/* Global Reset before programming */
GAP_GlobalReset(pHandle);
for (index1 = 0; index1 < DeviceNum; index1 ++)
{
write_reg_values[index1] = pHandle->DeviceParams[index1].CFG1;
}
ret_val = GAP_WriteRegs(pHandle, write_reg_values, CFG1);
if (ret_val)
{
for (index1 = 0; index1 < DeviceNum; index1 ++)
{
write_reg_values[index1] = pHandle->DeviceParams[index1].CFG2;
}
ret_val = GAP_WriteRegs(pHandle, write_reg_values, CFG2);
}
if (ret_val)
{
for (index1 = 0; index1 < DeviceNum; index1 ++)
{
write_reg_values[index1] = pHandle->DeviceParams[index1].CFG3;
}
ret_val = GAP_WriteRegs(pHandle, write_reg_values, CFG3);
}
if (ret_val)
{
for (index1 = 0; index1 < DeviceNum; index1 ++)
{
write_reg_values[index1] = pHandle->DeviceParams[index1].CFG4;
}
ret_val = GAP_WriteRegs(pHandle, write_reg_values, CFG4);
}
if (ret_val)
{
for (index1 = 0; index1 < DeviceNum; index1 ++)
{
write_reg_values[index1] = pHandle->DeviceParams[index1].CFG5;
}
ret_val = GAP_WriteRegs(pHandle, write_reg_values, CFG5);
}
if (ret_val)
{
for (index1 = 0; index1 < DeviceNum; index1 ++)
{
write_reg_values[index1] = pHandle->DeviceParams[index1].DIAG1;
}
ret_val = GAP_WriteRegs(pHandle, write_reg_values, DIAG1);
}
if (ret_val)
{
for (index1 = 0; index1 < DeviceNum; index1 ++)
{
write_reg_values[index1] = pHandle->DeviceParams[index1].DIAG2;
}
ret_val = GAP_WriteRegs(pHandle, write_reg_values, DIAG2);
}
GAP_StopConfig(pHandle);
/* Fault reset */
GAP_FaultAck(pHandle);
return ret_val;
}
/**
* @brief Calculates CRC from data and creates 16bit value with data as MSB and
* CRC as LSB.
* @param data 8bit value used to calculate CRC.
* @retval uint16_t It returns the 16bit value with data as MSB and
* CRC as LSB.
*/
__weak uint16_t GAP_CRCCalculate(uint8_t data, uint8_t crc_initial_value)
{
uint8_t crc = crc_initial_value;
uint8_t poly = 0x07;
uint8_t crc_temp;
uint8_t crctab[8];
uint8_t index1, index2;
uint16_t value;
value = data;
value <<= 8;
for (index2 = 0; index2 < 8; index2 ++)
{
crctab[index2] = (crc >> index2) & 0x1;
}
for (index2 = 0; index2 < 8; index2 ++)
{
crc_temp = (crctab[7] << 7) + (crctab[6] << 6) + (crctab[5] << 5) + (crctab[4] << 4) + (crctab[3] << 3) +
(crctab[2] << 2) + (crctab[1] << 1) + (crctab[0]);
crctab[0] = ((data >> (7 - index2)) & 0x1) ^ crctab[7];
for (index1 = 1; index1 < 8; index1 ++)
{
crctab[index1] = (crctab[0] & ((poly >> index1) & 0x1)) ^ ((crc_temp >> (index1 - 1)) & 0x1);
}
}
crc = (crctab[7] << 7) + (crctab[6] << 6) + (crctab[5] << 5) + (crctab[4] << 4) + (crctab[3] << 3) +
(crctab[2] << 2) + (crctab[1] << 1) + (crctab[0] << 0);
crc ^= 0xFF;
value |= crc;
return value;
}
/**
* @brief Verifies the CRC from dataIn and extracts the 8bit data value (out).
* @param out Reference for the extracted 8bit data value.
* @param dataIn 16bit value with data as MSB and CRC as LSB.
* @retval bool It returns true if CRC is correct, false otherwise.
*/
__weak bool GAP_CRCCheck(uint8_t *out, uint16_t data_in)
{
bool ret_val = false;
uint8_t data = (uint8_t)(data_in >> 8);
uint8_t received_crc = (uint8_t)(data_in);
uint8_t crc = (uint8_t)(GAP_CRCCalculate(data, 0xFF)) ^ 0xFF;
if (crc == received_crc)
{
*out = data;
ret_val = true;
}
return ret_val;
}
/**
* @brief Waits a time interval proportional to count.
* @param count Number of count to be waited.
* @retval none
*/
__weak void wait(uint16_t count)
{
volatile uint16_t wait_cnt;
for (wait_cnt = 0; wait_cnt < count; wait_cnt ++)
{
/* Nothing to do */
}
}
/**
* @brief Returns the register mask starting from it address.
* @param reg Register address GAP_Registers_Handle_t.
* @retval uint8_t Mask to be and-ed bit wise to data to filter it.
*/
__weak uint8_t GAP_RegMask(GAP_Registers_Handle_t reg)
{
uint8_t ret_val;
switch (reg)
{
case CFG1:
{
ret_val = CFG1_REG_MASK;
}
break;
case CFG2:
{
ret_val = CFG2_REG_MASK;
}
break;
case CFG3:
{
ret_val = CFG3_REG_MASK;
}
break;
case CFG4:
{
ret_val = CFG4_REG_MASK;
}
break;
case CFG5:
{
ret_val = CFG5_REG_MASK;
}
break;
case STATUS1:
{
ret_val = STATUS1_REG_MASK;
}
break;
case STATUS2:
{
ret_val = STATUS2_REG_MASK;
}
break;
case STATUS3:
{
ret_val = STATUS3_REG_MASK;
}
break;
case TEST1:
{
ret_val = TEST1_REG_MASK;
}
break;
case DIAG1:
{
ret_val = DIAG1_REG_MASK;
}
break;
case DIAG2:
{
ret_val = DIAG2_REG_MASK;
}
break;
default:
{
ret_val = 0x00;
}
break;
}
return ret_val;
}
/**
* @brief Reads all data in the daisy chain related to register reg.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @param pDataRead Pointer to the buffer in which will be stored the readed
* data. The buffer have to be provided from the caller.
* @param reg Register to be read. It must be one of the register defined in
* GAP_Registers_Handle_t.
* @retval bool It returns false if an error occurs, otherwise return true.
*/
__weak bool GAP_ReadRegs(GAP_Handle_t *pHandle, uint8_t *pDataRead, GAP_Registers_Handle_t reg)
{
bool ret_val = false;
uint8_t index1;
uint8_t device;
uint8_t data;
uint16_t value;
if (pDataRead)
{
value = GAP_CRCCalculate(GAP_READREG | reg, 0xFF);
GAP_CS_Activate(pHandle);
for (index1 = 0; index1 < pHandle->DeviceNum; index1 ++)
{
GAP_SPI_Send(pHandle, value);
}
GAP_CS_Deactivate(pHandle);
wait(WAITTIME);
value = GAP_CRCCalculate(GAP_NOP, 0xFF);
GAP_CS_Activate(pHandle);
ret_val = true;
for (index1 = 0; index1 < pHandle->DeviceNum; index1 ++)
{
device = pHandle->DeviceNum - index1 - 1;
if (pHandle->DeviceParams[device].CFG1 & GAP_CFG1_CRC_SPI)
{
if (GAP_CRCCheck(&data, GAP_SPI_Send(pHandle, value)))
{
pDataRead[device] = data & GAP_RegMask(reg);
}
else
{
pDataRead[device] = 0x00;
pHandle->GAP_ErrorsNow[0] |= GAP_ERROR_CODE_SPI_CRC;
pHandle->GAP_ErrorsOccurred[0] |= GAP_ERROR_CODE_SPI_CRC;
ret_val = false;
}
}
else
{
pDataRead[device] = (uint8_t)(GAP_SPI_Send(pHandle, value) >> 8) & GAP_RegMask(reg);
}
}
GAP_CS_Deactivate(pHandle);
}
return ret_val;
}
/**
* @brief Switches the device to the configuration mode allowing writing configuration values in configuration registers.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @retval none.
*/
__weak void GAP_StartConfig(GAP_Handle_t *pHandle)
{
uint8_t index;
uint16_t value;
GAP_SD_Activate(pHandle);
value = GAP_CRCCalculate(GAP_STARTCONFIG, 0xFF);
GAP_CS_Activate(pHandle);
for (index = 0; index < pHandle->DeviceNum; index ++)
{
GAP_SPI_Send(pHandle, value);
}
GAP_CS_Deactivate(pHandle);
wait(WAITTIME);
}
/**
* @brief Quits the configuration mode and make all changes effective.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @retval none.
*/
__weak void GAP_StopConfig(GAP_Handle_t *pHandle)
{
uint8_t index;
uint16_t value;
value = GAP_CRCCalculate(GAP_STOPCONFIG, 0xFF);
GAP_CS_Activate(pHandle);
for (index = 0; index < pHandle->DeviceNum; index ++)
{
GAP_SPI_Send(pHandle, value);
}
GAP_CS_Deactivate(pHandle);
wait(WAITTIME);
GAP_SD_Deactivate(pHandle);
}
/**
* @brief Writes data in the daisy chain into the register reg.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @param pDataWrite Pointer to the buffer in which are stored the data
* to be written in the register reg. The buffer have to be provided
* from the caller.
* @param reg Register to be write. It must be one of the register defined in
* GAP_Registers_Handle_t.
* @retval bool It returns false if an error occurs, otherwise return true.
*/
__weak bool GAP_WriteRegs(GAP_Handle_t *pHandle, uint8_t *pDataWrite, GAP_Registers_Handle_t reg)
{
bool ret_val = false;
if (pDataWrite)
{
uint8_t crc;
uint8_t index;
uint16_t value;
value = GAP_CRCCalculate(GAP_WRITEREG | reg, 0xFF);
crc = (uint8_t)(value);
GAP_CS_Activate(pHandle);
for (index = 0; index < pHandle->DeviceNum; index ++)
{
GAP_SPI_Send(pHandle, value);
}
GAP_CS_Deactivate(pHandle);
wait(WAITTIME);
GAP_CS_Activate(pHandle);
ret_val = true;
for (index = 0; index < pHandle->DeviceNum; index ++)
{
value = GAP_CRCCalculate(pDataWrite[index], crc ^ 0xFF);
GAP_SPI_Send(pHandle, value);
}
GAP_CS_Deactivate(pHandle);
wait(WAITTIME);
}
return ret_val;
}
/**
* @brief Resets all the registers to the default and releases all the failure flag.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @retval none.
*/
__weak void GAP_GlobalReset(GAP_Handle_t *pHandle)
{
uint8_t index;
uint16_t value;
value = GAP_CRCCalculate(GAP_GLOBALRESET, 0xFF);
GAP_CS_Activate(pHandle);
for (index = 0; index < pHandle->DeviceNum; index ++)
{
GAP_SPI_Send(pHandle, value);
}
GAP_CS_Deactivate(pHandle);
wait(WAITTIME);
}
/**
* @brief Resets selected status register.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @param reg Register to be reset. It must be one of the STATUS register
* defined in GAP_Registers_Handle_t.
* @retval bool It returns false if an error occurs, otherwise return true.
*/
__weak bool GAP_ResetStatus(GAP_Handle_t *pHandle, GAP_Registers_Handle_t reg)
{
bool ret_val = false;
uint8_t index;
uint16_t value;
GAP_SD_Activate(pHandle);
value = GAP_CRCCalculate(GAP_RESETREG | reg, 0xFF);
GAP_CS_Activate(pHandle);
for (index = 0; index < pHandle->DeviceNum; index ++)
{
GAP_SPI_Send(pHandle, value);
}
GAP_CS_Deactivate(pHandle);
GAP_SD_Deactivate(pHandle);
return ret_val;
}
/**
* @brief It performs the selected test on each GAP devices.
* @attention pHandle function should be called just in IDLE state.
* @param pHandle Handle of the GAP component GAP_Handle_t.
* @param testMode Test mode to be executed. It shall be one of the
* test modes present in the GAP_TestMode_t.
* @retval bool It returns true if an error occurs, otherwise return false.
*/
__weak bool GAP_Test(GAP_Handle_t *pHandle, GAP_TestMode_t testMode)
{
bool ret_val = false;
bool invertResult = false;
uint8_t testModeData;
uint8_t clr[MAX_DEVICES_NUMBER];
uint8_t data[MAX_DEVICES_NUMBER];
uint8_t index1, index2 = pHandle->DeviceNum;
uint8_t statusMask;
uint16_t wait_cnt;
switch (testMode)
{
case GOFF_CHK:
{
testModeData = GAP_TEST1_GOFFCHK;
wait_cnt = WAITTGCHK;
statusMask = GAP_STATUS1_DESAT;
}
break;
case GON_CHK:
{
testModeData = GAP_TEST1_GONCHK;
wait_cnt = WAITTGCHK;
statusMask = GAP_STATUS1_TSD;
}
break;
case GAP_TEST1_DESCHK:
{
testModeData = DESAT_CHK;
wait_cnt = WAITTDESATCHK;
statusMask = GAP_STATUS1_DESAT;
invertResult = true;
}
break;
case SENSE_RESISTOR_CHK:
{
testModeData = GAP_TEST1_RCHK;
wait_cnt = WAITTRCHK;
statusMask = GAP_STATUS1_SENSE;
}
break;
case SENSE_COMPARATOR_CHK:
{
testModeData = GAP_TEST1_SNSCHK;
wait_cnt = WAITTSENSECHK;
statusMask = GAP_STATUS1_SENSE;
invertResult = true;
}
break;
default:
{
ret_val = true;
}
break;
}
for (index1 = 0; index1 < index2; index1 ++)
{
data[index1] = testModeData;
clr[index1] = 0x00;
}
GAP_WriteRegs(pHandle, data, TEST1);
wait(wait_cnt);
GAP_ReadRegs(pHandle, data, STATUS1);
/* Clear TEST1 regs */
GAP_WriteRegs(pHandle, clr, TEST1);
/* Clear STATUS1 regs */
GAP_ResetStatus(pHandle, STATUS1);
for (index1 = 0; index1 < index2; index1 ++)
{
if (invertResult)
{
if ((data[index1] & statusMask) == 0)
{
ret_val = true;
}
}
else
{
if ((data[index1] & statusMask) != 0)
{
ret_val = true;
}
}
}
return ret_val;
}
/**
* @brief This function sends a 16bit value through the configured SPI and
* returns the 16-bit value received during communication.
* @param pHandle_t Handle of the GAP component GAP_Handle_t.
* @param value Value to be sent through SPI.
* @retval uint16_t Received 16bit value.
*/
uint16_t GAP_SPI_Send(GAP_Handle_t *pHandle_t, uint16_t value)
{
SPI_TypeDef *SPIx = pHandle_t->SPIx;
/* Wait for SPI Tx buffer empty */
while (LL_SPI_IsActiveFlag_TXE(SPIx) == 0);
/* Send SPI data */
LL_SPI_TransmitData16(SPIx, value);
/* Wait for SPIz data reception */
while (LL_SPI_IsActiveFlag_RXNE(SPIx) == 0);
/* Read SPIz received data */
return LL_SPI_ReceiveData16(SPIx);
}
/**
* @brief Deactivates SD pin.
* @param pHandle_t Handle of the GAP component GAP_Handle_t.
* @retval none.
*/
void GAP_SD_Deactivate(GAP_Handle_t *pHandle_t)
{
LL_GPIO_SetOutputPin(pHandle_t->NSDPort, pHandle_t->NSDPin);
}
/**
* @brief Activates SD pin.
* @param pHandle_t Handle of the GAP component GAP_Handle_t.
* @retval none.
*/
void GAP_SD_Activate(GAP_Handle_t *pHandle_t)
{
LL_GPIO_ResetOutputPin(pHandle_t->NSDPort, pHandle_t->NSDPin);
}
/**
* @brief Deactivates CS pin.
* @param pHandle_t Handle of the GAP component GAP_Handle_t.
* @retval none.
*/
void GAP_CS_Deactivate(GAP_Handle_t *pHandle_t)
{
LL_GPIO_SetOutputPin(pHandle_t->NCSPort, pHandle_t->NCSPin);
}
/**
* @brief Activates CS pin.
* @param pHandle_t Handle of the GAP component GAP_Handle_t.
* @retval none.
*/
void GAP_CS_Activate(GAP_Handle_t *pHandle_t)
{
LL_GPIO_ResetOutputPin(pHandle_t->NCSPort, pHandle_t->NCSPin);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 25,537 | C | 26.971522 | 142 | 0.611309 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pidregdqx_current.c | /**
******************************************************************************
* @file pidregdqx_current.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the PID current regulator component of the Motor Control SDK
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup PIDRegdqx
*/
#include "pidregdqx_current.h"
/** @addtogroup MCSDK
* @{
*/
/**
* @defgroup PIDRegdqx PID current regulator
*
* @brief PID current regulator component of the Motor Control SDK
*
* The PID current regulator component implements the following control functions:
*
* * A proportional-integral controller, implemented by the PIDREGDQX_CURRENT_run() function:
* * A circle limitation feature that limits the output duty vector according to the maximum
* modulation value configured by the user thanks to the function PIDREGDQX_CURRENT_setMaxModulation_squared().
* * A DC bus compensation to mitigate DC bus ripple.
*
* 
*
* * Input:
* * `I_dq_Ref`: currents vector references
* * `I_dq` : currents vector measured
* * Output:
* * `Duty_dq:` Duty vector
*
* If needed the PID current regulator can apply a cross-coupling compensation feature to increase stability at high speed.
*
* 
*
* * Input:
* * `I_dq_Ref`: currents vector references
* * `I_dq` : currents vector measured
* * `?`: Electrical speed from delta angle (low pass filtered)
* * Output:
* * `Duty_dq`: Duty vector
*
* Each of the gain parameters, can be set, at run time and independently, via the PIDREGDQX_CURRENT_setKp_si(),
* PIDREGDQX_CURRENT_setWi_si().
*
* A PID Current Regulator component needs to be initialized before it can be used. This is done with the PIDREGDQX_CURRENT_init()
* function that sets the intergral term to 0 and initializes the component data structure.
*
* To keep the computed values within limits, the component features the possibility to constrain the integral term
* within a range of values bounded by the PIDREGDQX_CURRENT_setOutputLimitsD() and PIDREGDQX_CURRENT_setOutputLimitsQ() functions.
*
* Handling a process with a PID Controller may require some adjustment to cope with specific situations. To that end, the
* PID speed regulator component provides functions to set the integral term (PIDREGDQX_CURRENT_setUiD_pu() and PIDREGDQX_CURRENT_setUiQ_pu()).
* @{
*/
#define PU_FMT (30) /*!< @brief Per unit format, external format */
#define SUM_FTM (24) /*!< @brief Summing format, internal format */
/**
* @brief Initializes PID current regulator component.
* It Should be called during Motor control middleware initialization
* @param pHandle PID current regulator handler
* @param current_scale current scaling factor
* @param voltage_scale voltage scaling factor
* @param pid_freq_hz PID regulator execution frequency
* @param freq_scale_hz frequency scaling factor
* @param duty_limit duty cycle limit
*/
void PIDREGDQX_CURRENT_init(
PIDREGDQX_CURRENT_s * pHandle,
const float current_scale,
const float voltage_scale,
const float pid_freq_hz,
const float freq_scale_hz,
const float duty_limit
)
{
pHandle->crosscompON = false; /* only needed ON when stability at highest speeds is an issue */
pHandle->Kp_fps.value = 0;
pHandle->Kp_fps.fixpFmt = 30;
pHandle->Wi_fps.value = 0;
pHandle->Wi_fps.fixpFmt = 30;
pHandle->maxModulation_squared = FIXP((double)(duty_limit * duty_limit));
pHandle->MaxD = FIXP24(0.7f);
pHandle->MinD = FIXP24(-0.7f);
pHandle->UpD = FIXP24(0.0f);
pHandle->UiD = FIXP24(0.0f);
pHandle->OutD = FIXP30(0.0f);
pHandle->MaxQ = FIXP24(0.7f);
pHandle->MinQ = FIXP24(-0.7f);
pHandle->UpQ = FIXP24(0.0f);
pHandle->UiD = FIXP24(0.0f);
pHandle->compensation = FIXP24(1.0f);
pHandle->current_scale = current_scale;
pHandle->voltage_scale = voltage_scale;
pHandle->freq_scale_hz = freq_scale_hz;
pHandle->pid_freq_hz = pid_freq_hz;
pHandle->wfsT = FIXP((MATH_TWO_PI * (double)freq_scale_hz / (double)pid_freq_hz));
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
/**
* @brief Computes the output of a PID current regulator component, sum of its proportional
* and integral terms
* @param pHandle PID current regulator handler
* @param errD D current error
* @param errQ Q current error
* @param felec_pu motor electrical frequency
*/
void PIDREGDQX_CURRENT_run( PIDREGDQX_CURRENT_s* pHandle, const fixp30_t errD, const fixp30_t errQ, const fixp30_t felec_pu)
{
fixp24_t maxD = pHandle->MaxD;
fixp24_t minD = pHandle->MinD;
fixp24_t maxQ = pHandle->MaxQ;
fixp24_t minQ = pHandle->MinQ;
fixp24_t uiD = pHandle->UiD;
fixp24_t uiQ = pHandle->UiQ;
fixp24_t welecT = FIXP(0.0f);
if(pHandle->crosscompON)
{
welecT = FIXP30_mpy(felec_pu, pHandle->wfsT);
}
/* Error */
pHandle->ErrD = (errD >> (PU_FMT-SUM_FTM));
pHandle->ErrQ = (errQ >> (PU_FMT-SUM_FTM));
/* Proportional term D*/
fixp24_t upD = FIXP_mpyFIXPscaled(pHandle->ErrD, &pHandle->Kp_fps);
upD = FIXP_rsmpy(upD, pHandle->compensation);
/* Proportional term Q*/
fixp24_t upQ = FIXP_mpyFIXPscaled(pHandle->ErrQ, &pHandle->Kp_fps);
upQ = FIXP_rsmpy(upQ, pHandle->compensation);
/* Integral term including cross-term D*/
uiD += FIXP_mpyFIXPscaled(upD, &pHandle->Wi_fps) - FIXP_mpy(upQ,welecT);
pHandle->clippedD = ((uiD <= minD) || (uiD >= maxD));
uiD = FIXP_sat(uiD, maxD, minD);
pHandle->UiD = uiD;
/* Summing term D*/
fixp24_t sumD =FIXP_sat(upD + uiD, maxD, minD);
// Circle limitation based on sumD
fixp24_t d_duty_squared = FIXP_mpy(sumD, sumD);
fixp24_t q_duty_squared = pHandle->maxModulation_squared - d_duty_squared;
maxQ = FIXP24_sqrt(q_duty_squared);
minQ = -maxQ;
pHandle->MaxQ = maxQ;
pHandle->MinQ = minQ;
/* Integral term Q*/
uiQ += FIXP_mpyFIXPscaled(upQ, &pHandle->Wi_fps) + FIXP_mpy(upD,welecT);
pHandle->clippedQ = ((uiQ <= minQ) || (uiQ >= maxQ));
uiQ = FIXP_sat(uiQ, maxQ, minQ);
pHandle->UiQ = uiQ;
/* Summing term Q*/
fixp24_t sumQ =FIXP_sat(upQ + uiQ, maxQ, minQ);
/*back to 30 */
fixp30_t outD = (sumD << (PU_FMT-SUM_FTM));
fixp30_t outQ = (sumQ << (PU_FMT-SUM_FTM));
/* Store DQ values for monitoring */
pHandle->UpD = upD;
pHandle->OutD = outD;
pHandle->UpQ = upQ;
pHandle->OutQ = outQ;
pHandle->clipped = pHandle->clippedD || pHandle->clippedQ;
}
/**
* @brief Gets overall clipping status
* @param pHandle PID current regulator handler
* @retval true if clipped false otherwise
*/
bool PIDREGDQX_CURRENT_getClipped( PIDREGDQX_CURRENT_s* pHandle )
{
return pHandle->clipped;
}
/**
* @brief Gets Kp gain in SI unit
* @param pHandle PID current regulator handler
* @retval Kp in float format
*/
float PIDREGDQX_CURRENT_getKp_si( PIDREGDQX_CURRENT_s* pHandle )
{
float Kp_pu = FIXPSCALED_FIXPscaledToFloat(&pHandle->Kp_fps);
float Kp_si = Kp_pu / pHandle->current_scale * pHandle->voltage_scale;
return Kp_si;
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
/**
* @brief Gets the PID output on D axis
* @param pHandle PID current regulator handler
* @retval outD signal
*/
fixp_t PIDREGDQX_CURRENT_getOutD(PIDREGDQX_CURRENT_s* pHandle)
{
return pHandle->OutD;
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
/**
* @brief Gets the PID output on Q axis
* @param pHandle PID current regulator handler
* @retval outD signal
*/
fixp_t PIDREGDQX_CURRENT_getOutQ(PIDREGDQX_CURRENT_s* pHandle)
{
return pHandle->OutQ;
}
/**
* @brief Gets Ki gain in SI unit
* @param pHandle PID current regulator handler
* @retval Ki gain
*/
float PIDREGDQX_CURRENT_getWi_si( PIDREGDQX_CURRENT_s* pHandle )
{
float Wi_pu = FIXPSCALED_FIXPscaledToFloat(&pHandle->Wi_fps);
float Wi_si = Wi_pu * pHandle->pid_freq_hz;
return Wi_si;
}
/**
* @brief Sets Kp gain expressed in SI unit
* @param pHandle PID current regulator handler
*/
void PIDREGDQX_CURRENT_setKp_si( PIDREGDQX_CURRENT_s* pHandle, const float Kp)
{
// Parameter Kp is in V/A (or Ohm)
/* Convert to per unit, in full scale voltage per full scale current */
float Kp_pu = Kp * pHandle->current_scale / pHandle->voltage_scale;
/* Convert Kp_pu to scaled value, and store */
FIXPSCALED_floatToFIXPscaled(Kp_pu, &pHandle->Kp_fps);
}
/**
* @brief Sets Kp and Ki gain according to Rs and Ls value of the motor
* @param pHandle PID current regulator handler
* @param Rsi motor resistance expressed in Ohm
* @param Lsi motor inductance expressed in Henry
* @param margin margin to apply for Kp computation
*/
void PIDREGDQX_CURRENT_setKpWiRLmargin_si( PIDREGDQX_CURRENT_s* pHandle, const float Rsi, const float Lsi, const float margin)
{
float kp_idq = (2.0f / margin) * Lsi * pHandle->pid_freq_hz; /* using duty_scale=2 unit V/A take gain-margin (margin about 5) */
float wi_idq = (Rsi / Lsi); /* unit rad/s */
pHandle->Kp = kp_idq;
PIDREGDQX_CURRENT_setKp_si(pHandle, kp_idq);
PIDREGDQX_CURRENT_setWi_si(pHandle, wi_idq);
}
/**
* @brief Sets Ki gain in SI unit
* @param pHandle PID current regulator handler
* @param Wi Ki gain expressed in rad/s
*/
void PIDREGDQX_CURRENT_setWi_si( PIDREGDQX_CURRENT_s* pHandle, const float Wi)
{
// Parameter Wi is in 1/s (or rad/s)
// Wi unit is frequency rad/s in series with Kp, dimension of Kp*Wi = V/As (voltage per charge, being 1/Farad)
/* Convert to unit per interrupt frequency */
float Wi_pu = Wi / pHandle->pid_freq_hz;
FIXPSCALED_floatToFIXPscaled(Wi_pu, &pHandle->Wi_fps);
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
/**
* @brief Sets D integral term
* @param pHandle PID current regulator handler
* @param Ui integral term value
*/
void PIDREGDQX_CURRENT_setUiD_pu( PIDREGDQX_CURRENT_s* pHandle, const fixp30_t Ui)
{
// Parameter Ui is in the same unit as the output, per unit duty
// Internally the Ui is stored in a different format
pHandle->UiD = (Ui >> (PU_FMT-SUM_FTM));
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
/**
* @brief Sets Q integral term
* @param pHandle PID current regulator handler
* @param Ui integral term value
*/
void PIDREGDQX_CURRENT_setUiQ_pu( PIDREGDQX_CURRENT_s* pHandle, const fixp30_t Ui)
{
// Parameter Ui is in the same unit as the output, per unit duty
// Internally the Ui is stored in a different format
pHandle->UiQ = (Ui >> (PU_FMT-SUM_FTM));
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
/**
* @brief Sets bus voltage compensation factor
* @param pHandle PID current regulator handler
* @param compensation bus voltage compensation factor
*/
void PIDREGDQX_CURRENT_setCompensation( PIDREGDQX_CURRENT_s* pHandle, const fixp24_t compensation)
{
pHandle->compensation = compensation;
}
/**
* @brief Sets the D upper and lower output limit of a PID component
* @param pHandle PID current regulator handler
* @param max_pu upper limit in per-unit
* @param mix_pu lower limit in per-unit
*/
void PIDREGDQX_CURRENT_setOutputLimitsD( PIDREGDQX_CURRENT_s* pHandle, const fixp30_t max_pu, const fixp30_t min_pu)
{
pHandle->MaxD = (max_pu >> (PU_FMT-SUM_FTM));
pHandle->MinD = (min_pu >> (PU_FMT-SUM_FTM));
}
/**
* @brief Sets the Q upper and lower output limit of a PID component
* @param pHandle PID current regulator handler
* @param max_pu upper limit in per-unit
* @param mix_pu lower limit in per-unit
*/
void PIDREGDQX_CURRENT_setOutputLimitsQ( PIDREGDQX_CURRENT_s* pHandle, const fixp30_t max_pu, const fixp30_t min_pu)
{
pHandle->MaxQ = (max_pu >> (PU_FMT-SUM_FTM));
pHandle->MinQ = (min_pu >> (PU_FMT-SUM_FTM));
}
/**
* @brief Sets squared maximum modulation value
* @param pHandle PID current regulator handler
* @param duty_limit maximum modulation
*/
void PIDREGDQX_CURRENT_setMaxModulation_squared( PIDREGDQX_CURRENT_s* pHandle, const float duty_limit)
{
pHandle->maxModulation_squared = FIXP((double)(duty_limit * duty_limit));
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 13,442 | C | 31.314904 | 144 | 0.672221 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/speed_potentiometer.c | /**
******************************************************************************
* @file speed_potentiometer.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Speed Potentiometer component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 20232 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup SpeedPotentiometer
*/
/* Includes ------------------------------------------------------------------*/
#include "speed_potentiometer.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup Potentiometer
* @{
*/
/** @defgroup SpeedPotentiometer Speed Potentiometer
* @brief Potentiometer reading component that sets the motor
* speed reference from the potentiometer value
*
* The Speed Potentiometer component uses the services of the
* @ref Potentiometer component to read a potentiometer. Values read
* from this potentiometer are used to set the rotation speed reference
* of a motor.
*
* The state of a Speed Potentiometer component is maintained in a
* SpeedPotentiometer_Handle_t structure. To use the Speed Potentiometer component,
* a SpeedPotentiometer_Handle_t structure needs to be instanciated and initialized.
* The initialization is performed thanks to the SPDPOT_Init() function. Prior to
* calling this function, some of the fields of this structure need to be given a
* value. See the Potentiometer_Handle_t and below for more details on this.
*
* A Speed Potentiometer component sets speed references by executing speed ramps
* thanks to the STC_ExecRamp() function. Prior to doing so, the component checks
* if the motor is started (that is: if its state machine has reached the #RUN state)
* and if its control modality is [Speed](@ref MCM_SPEED_MODE). If either of these
* conditions is not met, no speed ramp is executed.
*
* In addition, a speed ramp is executed only if the value of the potentiometer at
* that time differs from the one of the previous ramp that the component filed by
* a configurable amount. This amount is gieven by the
* @ref SpeedPotentiometer_Handle_t::SpeedAdjustmentRange "SpeedAdjustmentRange" field
* of the Handle structure.
*
* The speed range accessible through the potentiometer is bounded by a minimum speed
* and a maximum speed. the minimum speed is stated at compile time in the
* @ref SpeedPotentiometer_Handle_t::MinimumSpeed "MinimumSpeed" field of the Handle
* structure. The maximum speed is deduced from the
* @ref SpeedPotentiometer_Handle_t::ConversionFactor "ConversionFactor" field thanks to
* the following formula:
*
* $$
* MaximumSpeed = \frac{(65536 - MinimumSpeed \times ConversionFactor )}{ConversionFactor}
* $$
*
* where 65536 is the maximum value that the potentiometer (the ADC actually) can produce.
*
* The @ref SpeedPotentiometer_Handle_t::MinimumSpeed "MinimumSpeed" can be set so that when
* the potentiometer is set to its minimum value, the motor stil spins. This is useful when
* the Motor Control application uses a sensorless speed and position sensing algorithm that
* cannot work below a given speed.
*
* The duration of speed ramps is controlled with the @ref SpeedPotentiometer_Handle_t::RampSlope "RampSlope"
* field of the Handle. This field actually sets the acceleration used to change from one speed
* to another.
*
* A potentiometer provides absolute values. A Speed Potentiometer component turns these
* values into either positive or negative speed references depending on the actual speed
* of the motor. So, if a motor is started with a negative speed, the references set by the
* Speed Potentiometer component targetting it will also be negative.
*
* Values measured from the potentiometer are expressed in "u16digits": these are 16-bit values directly
* read from an ADC. They need to be converted to the [speed unit](#SPEED_UNIT) used by the API
* of the motor control library in order to generatethe speed references for the ramps.
*
* @note In the current version of the Speed Potentiometer component, the periodic ADC
* measures **must** be performed on the Medium Frequency Task. This can be done by using
* the MC_APP_PostMediumFrequencyHook_M1() function of the @ref MCAppHooks service
* for instance.
*
* @{
*/
/* Public functions ----------------------------------------------------------*/
/**
* @brief Initializes a Speed Potentiometer component
*
* This function must be called once before the component can be used.
*
* @param pHandle Handle on the Speed Potentiometer component to initialize
*/
void SPDPOT_Init(SpeedPotentiometer_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_POT
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
POT_Init(&pHandle->Pot);
SPDPOT_Clear(pHandle);
#ifdef NULL_PTR_CHECK_SPD_POT
}
#endif /* NULL_PTR_CHECK_SPD_POT */
}
/**
* @brief Clears the state of a Speed Potentiometer component
*
* The state of the @ref Potentiometer component instance used by the
* Speed Potentiometer component is also cleared.
*
* @param pHandle Handle on the Speed Potentiometer component
*/
void SPDPOT_Clear( SpeedPotentiometer_Handle_t * pHandle )
{
#ifdef NULL_PTR_CHECK_SPD_POT
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
POT_Clear((Potentiometer_Handle_t *)pHandle);
pHandle->LastSpeedRefSet = (uint16_t)0;
pHandle->IsRunning = false;
#ifdef NULL_PTR_CHECK_SPD_POT
}
#endif /* NULL_PTR_CHECK_SPD_POT */
}
/**
* @brief Reads the value of the potentiometer of a Speed Potentiometer component and sets
* the rotation speed reference of the motor it targets acordingly
*
* The potentiometer handled by the Speed Potentiometer component is read. If its value
* differs from the one that was last used to set the speed reference of the motor by more
* than @ref SpeedPotentiometer_Handle_t::SpeedAdjustmentRange "SpeedAdjustmentRange", then
* this new value is used to set a new speed reference.
*
* If the motor does not spin (it is not in the #RUN state) or if the current motor control
* modality is not speed (#MCM_SPEED_MODE), nothing is done.
*
* This function needs to be called periodically. See the @ref Potentiometer
* documentation for more details.
* @param pHandle Handle on the Speed Potentiometer component
*/
bool SPDPOT_Run( SpeedPotentiometer_Handle_t *pHandle, uint16_t rawValue)
{
bool retVal = false;
#ifdef NULL_PTR_CHECK_SPD_POT
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
SpeednTorqCtrl_Handle_t *pSTC = pHandle->pMCI->pSTC;
POT_TakeMeasurement((Potentiometer_Handle_t *)pHandle, rawValue);
if (MCM_SPEED_MODE == STC_GetControlMode(pSTC))
{
if (RUN == MCI_GetSTMState(pHandle->pMCI))
{
if (false == pHandle->IsRunning)
{
/* Making sure the potentiometer value is going to be considered */
pHandle->LastSpeedRefSet ^= 65535;
/* Remember that the motor is running */
pHandle->IsRunning = true;
}
else
{
/* Nothing to do */
}
if (POT_ValidValueAvailable((Potentiometer_Handle_t *) pHandle))
{
uint16_t potValue = POT_GetValue((Potentiometer_Handle_t *)pHandle);
if ((potValue <= (pHandle->LastSpeedRefSet - pHandle->SpeedAdjustmentRange)) ||
(potValue >= pHandle->LastSpeedRefSet + pHandle->SpeedAdjustmentRange))
{
SpeednPosFdbk_Handle_t *speedHandle;
uint32_t rampDuration;
int16_t currentSpeed;
int16_t requestedSpeed;
int16_t deltaSpeed;
speedHandle = STC_GetSpeedSensor(pSTC);
currentSpeed = SPD_GetAvrgMecSpeedUnit(speedHandle);
requestedSpeed = (int16_t)((potValue / pHandle->ConversionFactor) + pHandle->MinimumSpeed);
deltaSpeed = (int16_t)requestedSpeed - ((currentSpeed >= 0) ? currentSpeed : -currentSpeed);
if (deltaSpeed < 0)
{
deltaSpeed = - deltaSpeed;
}
else
{
/* Nothing to do */
}
rampDuration = ((uint32_t)deltaSpeed * 1000U) / pHandle->RampSlope;
if (currentSpeed < 0)
{
requestedSpeed = - requestedSpeed;
}
else
{
/* Nothing to do */
}
STC_ExecRamp(pSTC, requestedSpeed, rampDuration);
pHandle->LastSpeedRefSet = potValue;
retVal = true;
}
}
else
{
/* Nothing to do */
}
}
else
{
pHandle->IsRunning = false;
}
}
else
{
pHandle->IsRunning = false;
}
#ifdef NULL_PTR_CHECK_SPD_POT
}
#endif /* NULL_PTR_CHECK_SPD_POT */
return (retVal);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 9,735 | C | 33.524823 | 111 | 0.635747 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pqd_motor_power_measurement.c | /**
******************************************************************************
* @file pqd_motor_power_measurement.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides the functions that implement the features of the
* PQD Motor Power Measurement component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pqd_motorpowermeasurement
*/
/* Includes ------------------------------------------------------------------*/
#include "pqd_motor_power_measurement.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup pqd_motorpowermeasurement PQD Motor Power Measurement
* @brief Motor Power Measurement component using DQ-frame current and voltage values
*
* The PQD Motor Power Measurement component uses @f$I_d@f$, @f$I_q@f$, @f$V_d@f$ and @f$V_q@f$
* to compute the electrical power flowing through the motor.
*
* These values are periodically sampled from the current regulation loop and used to compute
* instantaneous power values. The instantaneous values are then used to compute an average
* power value that is stored. These computations are done with integer operations and the
* average value is store as an integer, in s16 digit format (s16A x s16V unit).
*
* The PQD Motor Power Measurement component provides an interface, PQD_GetAvrgElMotorPowerW()
* that converts the int16_t digit average power into a floating point value expressed in
* Watts.
*
* @{
*/
/**
* @brief Updates the average electrical motor power measure with the latest values
* of the DQ currents and voltages.
*
* This method should be called with Medium Frequency Task periodicity. It computes an
* instantaneous power value using the latest @f$I_{qd}@f$ and @f$V_{qd}@f$ data available
* and uses it to update the average motor power value.
*
* Computations are done on s16A and s16V integer values defined in
* [Current measurement unit](measurement_units.md). The average motor power value is
* computed as an int16_t value.
*
* @param pHandle Handle on the related PQD Motor Power Measurement component instance.
*/
__weak void PQD_CalcElMotorPower(PQD_MotorPowMeas_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_PQD_MOT_POW_MEAS
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wAux;
qd_t Iqd = pHandle->pFOCVars->Iqd;
qd_t Vqd = pHandle->pFOCVars->Vqd;
wAux = ((int32_t)Iqd.q * (int32_t)Vqd.q)
+ ((int32_t)Iqd.d * (int32_t)Vqd.d);
wAux /= 65536;
/* pHandle->hAvrgElMotorPower += (wAux - pHandle->hAvrgElMotorPower) >> 4 */
pHandle->hAvrgElMotorPower += (int16_t)((wAux - (int32_t)pHandle->hAvrgElMotorPower) / 16);
#ifdef NULL_PTR_CHECK_PQD_MOT_POW_MEAS
}
#endif
}
/**
* @brief Clears the int16_t digit average motor power value stored in the handle.
*
* This function should be called before each motor start.
*
* @param pHandle Handle on the related PQD Motor Power Measurement component instance.
*/
__weak void PQD_Clear(PQD_MotorPowMeas_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_MOT_POW_MES
if (MC_NULL == pHandle)
{
/* nothing to do */
}
else
{
#endif
pHandle->hAvrgElMotorPower = 0;
#ifdef NULL_PTR_CHECK_MOT_POW_MES
}
#endif
}
/**
* @brief Returns an average value of the measured motor power expressed in Watts
*
* This function converts the int16_t digit average motor power value stored in the handle
* in a floating point value in Watts.
*
* @param pHandle pointer on the related component instance.
* @retval float_t The average measured motor power expressed in Watts.
*/
__weak float_t PQD_GetAvrgElMotorPowerW(const PQD_MotorPowMeas_Handle_t *pHandle)
{
float_t PowerW = 0.0f;
#ifdef NULL_PTR_CHECK_PQD_MOT_POW_MEAS
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
/* First perform an integer multiplication, then a float one. */
PowerW = ((float_t)pHandle->hAvrgElMotorPower * (float_t)VBS_GetAvBusVoltage_V(pHandle->pVBS)) * pHandle->ConvFact;
#ifdef NULL_PTR_CHECK_PQD_MOT_POW_MEAS
}
#endif
return (PowerW);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 4,818 | C | 30.292208 | 117 | 0.636779 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/digital_output.c | /**
******************************************************************************
* @file digital_output.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the Digital
* Output component of the Motor Control SDK:
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup DigitalOutput
*/
/* Includes ------------------------------------------------------------------*/
#include "digital_output.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup DigitalOutput Digital Output
* @brief Digital output component of the Motor Control SDK
*
* @{
*/
/**
* @brief Accordingly with selected polarity, it sets to active or inactive the
* digital output
* @param pHandle handler address of the digital output component.
* @param State New requested state
*
*/
__weak void DOUT_SetOutputState(DOUT_handle_t *pHandle, DOutputState_t State)
{
#ifdef NULL_PTR_CHECK_DIG_OUT
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (ACTIVE == State)
{
if (pHandle->bDOutputPolarity == DOutputActiveHigh)
{
LL_GPIO_SetOutputPin(pHandle->hDOutputPort, pHandle->hDOutputPin);
}
else
{
LL_GPIO_ResetOutputPin(pHandle->hDOutputPort, pHandle->hDOutputPin);
}
}
else if (pHandle->bDOutputPolarity == DOutputActiveHigh)
{
LL_GPIO_ResetOutputPin(pHandle->hDOutputPort, pHandle->hDOutputPin);
}
else
{
LL_GPIO_SetOutputPin(pHandle->hDOutputPort, pHandle->hDOutputPin);
}
pHandle->OutputState = State;
#ifdef NULL_PTR_CHECK_DIG_OUT
}
#endif
}
/**
* @brief It returns the state of the digital output
* @param pHandle pointer on related component instance
* @retval Digital output state (ACTIVE or INACTIVE)
*/
__weak DOutputState_t DOUT_GetOutputState(DOUT_handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_DIG_OUT
DOutputState_t temp_outputState;
if (MC_NULL == pHandle)
{
temp_outputState = INACTIVE;
}
else
{
temp_outputState = pHandle->OutputState;
}
return (temp_outputState);
#else
return (pHandle->OutputState);
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,871 | C | 24.415929 | 95 | 0.575409 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pwm_common_sixstep.c | /**
******************************************************************************
* @file pwm_common_sixstep.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the following features
* of the six-step PWM component of the Motor Control SDK:
*
* * ADC triggering for sensorless bemf acquisition
* * translation of the electrical angle in step sequence
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pwm_curr_fdbk_6s
*/
/* Includes ------------------------------------------------------------------*/
#include "pwm_common_sixstep.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk
* @{
*/
/** @defgroup pwm_curr_fdbk_6s Six-Step PWM generation
*
* @brief PWM components for Six Step drive
*
* @todo Complete documentation for the pwm_curr_fdbk_6s module
*
* @{
*/
/**
* @brief It is used to clear the variable in CPWMC.
* @param this related object of class CPWMC
* @retval none
*/
void PWMC_Clear(PWMC_Handle_t *pHandle)
{
}
/**
* @brief Switches PWM generation off, inactivating the outputs.
* @param pHandle Handle on the target instance of the PWMC component
*/
__weak void PWMC_SwitchOffPWM( PWMC_Handle_t * pHandle )
{
pHandle->pFctSwitchOffPwm( pHandle );
}
/**
* @brief Switches PWM generation on
* @param pHandle Handle on the target instance of the PWMC component
*/
__weak void PWMC_SwitchOnPWM( PWMC_Handle_t * pHandle )
{
pHandle->pFctSwitchOnPwm( pHandle );
}
/**
* @brief Set the ADC trigger point for bemf acquisition.
* @param pHandle Handle on the target instance of the PWMC component
* @param SamplingPoint pulse value of the timer channel used for ADC triggering
*/
__weak void PWMC_SetADCTriggerChannel( PWMC_Handle_t * pHandle, uint16_t SamplingPoint )
{
pHandle->pFctSetADCTriggerChannel( pHandle, SamplingPoint );
}
/**
* @brief Switches power stage Low Sides transistors on.
*
* This function is meant for charging boot capacitors of the driving
* section. It has to be called on each motor start-up when using high
* voltage drivers.
*
* @param pHandle: handle on the target instance of the PWMC component
*/
__weak void PWMC_TurnOnLowSides( PWMC_Handle_t * pHandle, uint32_t ticks)
{
pHandle->pFctTurnOnLowSides(pHandle, ticks);
}
/**
* @brief It is used to retrieve the satus of TurnOnLowSides action.
* @param pHandle: handler of the current instance of the PWMC component
* @retval bool It returns the state of TurnOnLowSides action:
* true if TurnOnLowSides action is active, false otherwise.
*/
/** @brief Returns the status of the "TurnOnLowSide" action on the power stage
* controlled by the @p pHandle PWMC component: true if it
* is active, false otherwise*/
__weak bool PWMC_GetTurnOnLowSidesAction( PWMC_Handle_t * pHandle )
{
return pHandle->TurnOnLowSidesAction;
}
/**
* @brief It is used to set the align motor flag.
* @param this related object of class CPWMC
* @param flag to be applied in uint8_t, 1: motor is in align stage, 2: motor is not in align stage
* @retval none
*/
void PWMC_SetAlignFlag(PWMC_Handle_t *pHandle, int16_t flag)
{
pHandle->AlignFlag = flag;
}
/**
* @brief Sets the Callback that the PWMC component shall invoke to switch PWM
* generation off.
* @param pCallBack pointer on the callback
* @param pHandle pointer on the handle structure of the PWMC instance
*
*/
__weak void PWMC_RegisterSwitchOffPwmCallBack( PWMC_Generic_Cb_t pCallBack,
PWMC_Handle_t * pHandle )
{
pHandle->pFctSwitchOffPwm = pCallBack;
}
/**
* @brief Sets the Callback that the PWMC component shall invoke to switch PWM
* generation on.
* @param pCallBack pointer on the callback
* @param pHandle pointer on the handle structure of the PWMC instance
*
*/
__weak void PWMC_RegisterSwitchonPwmCallBack( PWMC_Generic_Cb_t pCallBack,
PWMC_Handle_t * pHandle )
{
pHandle->pFctSwitchOnPwm = pCallBack;
}
/**
* @brief Sets the Callback that the PWMC component shall invoke to turn low sides on.
* @param pCallBack pointer on the callback
* @param pHandle pointer on the handle structure of the PWMC instance
*
*/
__weak void PWMC_RegisterTurnOnLowSidesCallBack( PWMC_TurnOnLowSides_Cb_t pCallBack,
PWMC_Handle_t * pHandle )
{
pHandle->pFctTurnOnLowSides = pCallBack;
}
/**
* @brief Sets the Callback that the PWMC component shall invoke to the overcurrent status
* @param pCallBack pointer on the callback
* @param pHandle pointer on the handle structure of the PWMC instance
*
*/
__weak void PWMC_RegisterIsOverCurrentOccurredCallBack( PWMC_OverCurr_Cb_t pCallBack,
PWMC_Handle_t * pHandle )
{
pHandle->pFctIsOverCurrentOccurred = pCallBack;
}
/**
* @brief It forces the Fast Demag interval to the passed value
* @param pHandle: handler of the current instance of the PWM component
* @param uint16_t: period where the fast demagnetization is applied
* @retval none
*/
void PWMC_ForceFastDemagTime(PWMC_Handle_t * pHandle, uint16_t constFastDemagTime )
{
pHandle->DemagCounterThreshold = constFastDemagTime;
}
/**
* @brief It enables/disables the Fast Demag feature at next step change
* @param pHandle: handler of the current instance of the PWM component
* @param uint8_t: 0=disable, 1=enable
* @retval none
*/
void PWMC_SetFastDemagState(PWMC_Handle_t * pHandle, uint8_t State )
{
if (State == 1)
{
pHandle->ModUpdateReq = ENABLE_FAST_DEMAG;
}
else
{
pHandle->ModUpdateReq = DISABLE_FAST_DEMAG;
}
}
/**
* @brief It enables/disables the Qusi Synch feature at next step change
* @param pHandle: handler of the current instance of the PWM component
* @param uint8_t: 0=disable, 1=enable
* @retval none
*/
void PWMC_SetQuasiSynchState(PWMC_Handle_t * pHandle, uint8_t State )
{
if (State == 1)
{
pHandle->ModUpdateReq = ENABLE_QUASI_SYNCH;
}
else
{
pHandle->ModUpdateReq = DISABLE_QUASI_SYNCH;
}
}
/**
* @brief It returns the Fast Demag feature status
* @param pHandle: handler of the current instance of the PWM component
* @retval uint8_t: 0=disabled, 1=enabled
*/
uint8_t PWMC_GetFastDemagState(PWMC_Handle_t * pHandle )
{
return ((MC_NULL == pHandle->pGetFastDemagFlag) ? 0 : pHandle->pGetFastDemagFlag(pHandle));
}
/**
* @brief It returns the Quasi Synch feature status
* @param pHandle: handler of the current instance of the PWM component
* @retval uint8_t: 0=disabled, 1=enabled
*/
uint8_t PWMC_GetQuasiSynchState(PWMC_Handle_t * pHandle )
{
return ((MC_NULL == pHandle->pGetQuasiSynchFlag) ? 0 : pHandle->pGetQuasiSynchFlag(pHandle));
}
/**
* @brief Converts the motor electrical angle to the corresponding step in the six-step sequence
* @param pHandle pointer on the handle structure of the PWMC instance
* @retval calculated step
*/
__weak uint8_t PWMC_ElAngleToStep( PWMC_Handle_t * pHandle )
{
uint8_t Step;
if ((pHandle->hElAngle >= (int16_t)( S16_60_PHASE_SHIFT / 2)) && (pHandle->hElAngle < (int16_t)( S16_60_PHASE_SHIFT + S16_60_PHASE_SHIFT / 2))) Step = STEP_1;
else if ((pHandle->hElAngle >= (int16_t)( S16_60_PHASE_SHIFT + S16_60_PHASE_SHIFT / 2)) && (pHandle->hElAngle < (int16_t)( S16_120_PHASE_SHIFT + S16_60_PHASE_SHIFT / 2))) Step = STEP_2;
else if ((pHandle->hElAngle >= (int16_t)( S16_120_PHASE_SHIFT + S16_60_PHASE_SHIFT / 2)) || (pHandle->hElAngle < (int16_t)( - S16_120_PHASE_SHIFT - S16_60_PHASE_SHIFT / 2))) Step = STEP_3;
else if ((pHandle->hElAngle >= (int16_t)( - S16_120_PHASE_SHIFT - S16_60_PHASE_SHIFT / 2)) && (pHandle->hElAngle < (int16_t)( - S16_60_PHASE_SHIFT - S16_60_PHASE_SHIFT / 2))) Step = STEP_4;
else if ((pHandle->hElAngle >= (int16_t)( - S16_60_PHASE_SHIFT - S16_60_PHASE_SHIFT / 2)) && (pHandle->hElAngle < (int16_t)( - S16_60_PHASE_SHIFT / 2))) Step = STEP_5;
else if ((pHandle->hElAngle >= (int16_t)( - S16_60_PHASE_SHIFT / 2)) && (pHandle->hElAngle < (int16_t)( S16_60_PHASE_SHIFT / 2))) Step = STEP_6;
else {}
return Step;
}
/*
* @brief Checks if an overcurrent occurred since last call.
*
* @param pHdl: Handler of the current instance of the PWM component.
* @retval uint16_t Returns #MC_OVER_CURR if an overcurrent has been
* detected since last method call, #MC_NO_FAULTS otherwise.
*/
__weak uint16_t PWMC_IsFaultOccurred(PWMC_Handle_t *pHandle)
{
uint16_t retVal = MC_NO_FAULTS;
if (true == pHandle->OverVoltageFlag)
{
retVal = MC_OVER_VOLT;
pHandle->OverVoltageFlag = false;
}
else
{
/* Nothing to do */
}
if (true == pHandle->OverCurrentFlag)
{
retVal |= MC_OVER_CURR;
pHandle->OverCurrentFlag = false;
}
else
{
/* Nothing to do */
}
if (true == pHandle->driverProtectionFlag)
{
retVal |= MC_DP_FAULT;
pHandle->driverProtectionFlag = false;
}
else
{
/* Nothing to do */
}
return (retVal);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 9,715 | C | 29.844444 | 191 | 0.652702 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/virtual_speed_sensor.c | /**
******************************************************************************
* @file virtual_speed_sensor.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Virtual Speed Sensor component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup VirtualSpeedSensor
*/
/* Includes ------------------------------------------------------------------*/
#include "virtual_speed_sensor.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup SpeednPosFdbk
* @{
*/
/** @defgroup VirtualSpeedSensor Virtual Speed & Position Feedback
* @brief Virtual Speed Speed & Position Feedback implementation
*
* This component provides a "virtual" implementation of the speed and position feedback features.
* This implementation provides a theoretical estimation of the speed and position of the rotor of
* the motor based on a mechanical acceleration and an initial angle set by the application.
*
* This component is used during the @ref RevUpCtrl "Rev-Up Control" phases of the motor or in an
* @ref OpenLoop "Open Loop Control" configuration in a sensorless subsystem.
*
*
* @{
*/
/**
* @brief Software initialization of VirtualSpeedSensor component.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @retval none
*
* - Calls VSS_Clear.
* - Called at initialization of the whole MC core.
*/
__weak void VSS_Init(VirtualSpeedSensor_Handle_t *pHandle)
{
VSS_Clear(pHandle);
}
/**
* @brief Software initialization of VSS object to be performed at each restart
* of the motor.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @retval none
*/
__weak void VSS_Clear(VirtualSpeedSensor_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->_Super.bSpeedErrorNumber = 0U;
pHandle->_Super.hElAngle = 0;
pHandle->_Super.hMecAngle = 0;
pHandle->_Super.hAvrMecSpeedUnit = 0;
pHandle->_Super.hElSpeedDpp = 0;
pHandle->_Super.hMecAccelUnitP = 0;
pHandle->_Super.bSpeedErrorNumber = 0U;
pHandle->wElAccDppP32 = 0;
pHandle->wElSpeedDpp32 = 0;
pHandle->hRemainingStep = 0U;
pHandle->hElAngleAccu = 0;
pHandle->bTransitionStarted = false;
pHandle->bTransitionEnded = false;
pHandle->hTransitionRemainingSteps = pHandle->hTransitionSteps;
pHandle->bTransitionLocked = false;
pHandle->bCopyObserver = false;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Updates the rotor electrical angle integrating the last settled
* instantaneous electrical speed express in [dpp](measurement_units.md).
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @retval int16_t Measured electrical angle in s16degree format.
*
* - Systematically called after #SPD_GetElAngle that retrieves last computed rotor electrical angle.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t VSS_CalcElAngle(VirtualSpeedSensor_Handle_t *pHandle, int16_t *pInputVars_str)
{
int16_t hRetAngle;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if ((MC_NULL == pHandle) || (MC_NULL == pInputVars_str))
{
hRetAngle = 0;
}
else
{
#endif
int16_t hAngleDiff;
int32_t wAux;
int16_t hAngleCorr;
int16_t hSignCorr = 1;
if (true == pHandle->bCopyObserver)
{
hRetAngle = *(int16_t *)pInputVars_str;
}
else
{
pHandle->hElAngleAccu += pHandle->_Super.hElSpeedDpp;
pHandle->_Super.hMecAngle += (pHandle->_Super.hElSpeedDpp / (int16_t)pHandle->_Super.bElToMecRatio);
if (true == pHandle->bTransitionStarted)
{
if (0 == pHandle->hTransitionRemainingSteps)
{
hRetAngle = *(int16_t *)pInputVars_str;
pHandle->bTransitionEnded = true;
pHandle->_Super.bSpeedErrorNumber = 0U;
}
else
{
pHandle->hTransitionRemainingSteps--;
if (pHandle->_Super.hElSpeedDpp >= 0)
{
hAngleDiff = *(int16_t *)pInputVars_str - pHandle->hElAngleAccu;
}
else
{
hAngleDiff = pHandle->hElAngleAccu - *(int16_t *)pInputVars_str;
hSignCorr = -1;
}
wAux = (int32_t)hAngleDiff * pHandle->hTransitionRemainingSteps;
hAngleCorr = (int16_t)(wAux / pHandle->hTransitionSteps);
hAngleCorr *= hSignCorr;
if (hAngleDiff >= 0)
{
pHandle->bTransitionLocked = true;
hRetAngle = *(int16_t *)pInputVars_str - hAngleCorr;
}
else
{
if (false == pHandle->bTransitionLocked)
{
hRetAngle = pHandle->hElAngleAccu;
}
else
{
hRetAngle = *(int16_t *)pInputVars_str + hAngleCorr;
}
}
}
}
else
{
hRetAngle = pHandle->hElAngleAccu;
}
}
pHandle->_Super.hElAngle = hRetAngle;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
return (hRetAngle);
}
/**
* @brief Computes and stores rotor instantaneous electrical speed (express
* in [dpp](measurement_units.md) considering the measurement frequency) in order to provide it
* to #SPD_GetElAngle.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @param hMecSpeedUnit pointer to int16_t, used to return the rotor average
* mechanical speed [SPEED_UNIT](measurement_units.md).
* @retval bool true = sensor information is reliable and false = sensor information is not reliable.
*
* - Stores and returns through parameter hMecSpeedUnit the rotor average mechanical speed,
* expressed in the unit defined by [SPEED_UNIT](measurement_units.md).
* - Returns the reliability state of the sensor (always true).
* - Called with the same periodicity on which speed control is executed, precisely during START and SWITCH_OVER states
* of the MC tasks state machine or in its RUM state in @ref OpenLoop "Open Loop Control" configuration into
* TSK_MediumFrequencyTask.
*/
__weak bool VSS_CalcAvrgMecSpeedUnit(VirtualSpeedSensor_Handle_t *pHandle, int16_t *hMecSpeedUnit)
{
bool SpeedSensorReliability;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if ((MC_NULL == pHandle) || (MC_NULL == hMecSpeedUnit))
{
SpeedSensorReliability = false;
}
else
{
#endif
if (pHandle->hRemainingStep > 1u)
{
pHandle->wElSpeedDpp32 += pHandle->wElAccDppP32;
#ifndef FULL_MISRA_C_COMPLIANCY_VIRT_SPD_SENS
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
pHandle->_Super.hElSpeedDpp = (int16_t)(pHandle->wElSpeedDpp32 >> 16);
#else
pHandle->_Super.hElSpeedDpp = (int16_t)(pHandle->wElSpeedDpp32 / 65536);
#endif
/* Convert dpp into MecUnit */
*hMecSpeedUnit = (int16_t)((((int32_t)pHandle->_Super.hElSpeedDpp)
* ((int32_t )pHandle->_Super.hMeasurementFrequency) * SPEED_UNIT)
/ (((int32_t)pHandle->_Super.DPPConvFactor) * ((int32_t)pHandle->_Super.bElToMecRatio)));
pHandle->_Super.hAvrMecSpeedUnit = *hMecSpeedUnit;
pHandle->hRemainingStep--;
}
else if (1U == pHandle->hRemainingStep)
{
*hMecSpeedUnit = pHandle->hFinalMecSpeedUnit;
pHandle->_Super.hAvrMecSpeedUnit = *hMecSpeedUnit;
pHandle->_Super.hElSpeedDpp = (int16_t)((((int32_t)*hMecSpeedUnit) * ((int32_t)pHandle->_Super.DPPConvFactor))
/ (((int32_t)SPEED_UNIT) * ((int32_t)pHandle->_Super.hMeasurementFrequency)));
pHandle->_Super.hElSpeedDpp *= ((int16_t)pHandle->_Super.bElToMecRatio);
pHandle->hRemainingStep = 0U;
}
else
{
*hMecSpeedUnit = pHandle->_Super.hAvrMecSpeedUnit;
}
/* If the transition is not done yet, we already know that speed is not reliable */
if (false == pHandle->bTransitionEnded)
{
pHandle->_Super.bSpeedErrorNumber = pHandle->_Super.bMaximumSpeedErrorsNumber;
SpeedSensorReliability = false;
}
else
{
SpeedSensorReliability = SPD_IsMecSpeedReliable(&pHandle->_Super, hMecSpeedUnit);
}
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
return (SpeedSensorReliability);
}
/**
* @brief Sets instantaneous information on VSS mechanical and electrical angle.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @param hMecAngle: instantaneous measure of rotor mechanical angle.
* @retval none
*
* - Called during @ref RevUpCtrl "Rev-Up Control" and
* @ref EncAlignCtrl "Encoder Alignment Controller procedure" initialization.
*/
__weak void VSS_SetMecAngle(VirtualSpeedSensor_Handle_t *pHandle, int16_t hMecAngle)
{
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hElAngleAccu = hMecAngle;
pHandle->_Super.hMecAngle = pHandle->hElAngleAccu / ((int16_t)pHandle->_Super.bElToMecRatio);
pHandle->_Super.hElAngle = hMecAngle;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
}
/**
* @brief Sets the mechanical acceleration of virtual speed sensor.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @param hFinalMecSpeedUnit mechanical speed assumed by
* the virtual speed sensor at the end of the duration. Expressed in the unit defined
* by [SPEED_UNIT](measurement_units.md).
* @param hDurationms: Duration expressed in ms. It can be 0 to apply
* instantaneous the final speed.
* @retval none
*
* - This acceleration is defined starting from current mechanical speed, final mechanical
* speed expressed in [SPEED_UNIT](measurement_units.md) and duration expressed in milliseconds.
* - Called during @ref RevUpCtrl "Rev-Up Control" and
* @ref EncAlignCtrl "Encoder Alignment Controller procedure" initialization.
*/
__weak void VSS_SetMecAcceleration(VirtualSpeedSensor_Handle_t *pHandle, int16_t hFinalMecSpeedUnit,
uint16_t hDurationms)
{
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wMecAccDppP32;
uint16_t hNbrStep;
int16_t hCurrentMecSpeedDpp;
int16_t hFinalMecSpeedDpp;
if (false == pHandle->bTransitionStarted)
{
if (0U == hDurationms)
{
pHandle->_Super.hAvrMecSpeedUnit = hFinalMecSpeedUnit;
pHandle->_Super.hElSpeedDpp = (int16_t)((((int32_t)hFinalMecSpeedUnit)
* ((int32_t)pHandle->_Super.DPPConvFactor))
/ (((int32_t)SPEED_UNIT)
* ((int32_t)pHandle->_Super.hMeasurementFrequency)));
pHandle->_Super.hElSpeedDpp *= ((int16_t)pHandle->_Super.bElToMecRatio);
pHandle->hRemainingStep = 0U;
pHandle->hFinalMecSpeedUnit = hFinalMecSpeedUnit;
}
else
{
hNbrStep = (uint16_t)((((uint32_t)hDurationms) * ((uint32_t)pHandle->hSpeedSamplingFreqHz)) / 1000U);
hNbrStep++;
pHandle->hRemainingStep = hNbrStep;
hCurrentMecSpeedDpp = pHandle->_Super.hElSpeedDpp / ((int16_t)pHandle->_Super.bElToMecRatio);
hFinalMecSpeedDpp = (int16_t)((((int32_t )hFinalMecSpeedUnit) * ((int32_t)pHandle->_Super.DPPConvFactor))
/ (((int32_t )SPEED_UNIT) * ((int32_t)pHandle->_Super.hMeasurementFrequency)));
if (0U == hNbrStep)
{
/* Nothing to do */
}
else
{
wMecAccDppP32 = ((((int32_t)hFinalMecSpeedDpp) - ((int32_t)hCurrentMecSpeedDpp))
* ((int32_t)65536)) / ((int32_t )hNbrStep);
pHandle->wElAccDppP32 = wMecAccDppP32 * ((int16_t)pHandle->_Super.bElToMecRatio);
}
pHandle->hFinalMecSpeedUnit = hFinalMecSpeedUnit;
pHandle->wElSpeedDpp32 = ((int32_t)pHandle->_Super.hElSpeedDpp) * ((int32_t)65536);
}
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
}
/**
* @brief Checks if the ramp executed after a #VSS_SetMecAcceleration command
* has been completed by checking zero value of the Number of steps remaining to reach the final
* speed.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @retval bool: true if the ramp is completed, otherwise false.
*
* - Not used into current implementation.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool VSS_RampCompleted(VirtualSpeedSensor_Handle_t *pHandle)
{
bool retVal = false;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if (MC_NULL == pHandle)
{
/* nothing to do */
}
else
{
#endif
if (0U == pHandle->hRemainingStep)
{
retVal = true;
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
return (retVal);
}
/**
* @brief Gets the final speed of last settled ramp of virtual speed sensor expressed
in [SPEED_UNIT](measurement_units.md).
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @retval none
*
* - Will be call for future dual motor implementation into START state of MC tasks state machine into TSK_MediumFrequencyTask.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t VSS_GetLastRampFinalSpeed(VirtualSpeedSensor_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
return ((MC_NULL == pHandle) ? 0 : pHandle->hFinalMecSpeedUnit);
#else
return (pHandle->hFinalMecSpeedUnit);
#endif
}
/**
* @brief Sets the command to Start the transition phase from Virtual Speed Sensor
* to other Speed Sensor.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @param bool: true to Start the transition phase, false has no effect.
* @retval bool: true if Transition phase is enabled (started or not), false if
* transition has been triggered but it's actually disabled
* (parameter #hTransitionSteps = 0).
*
* - Transition is to be considered ended when Sensor information is
* declared 'Reliable' or if function returned value is false.
* - Called into START state of MC tasks state machine into TSK_MediumFrequencyTask.
*/
__weak bool VSS_SetStartTransition(VirtualSpeedSensor_Handle_t *pHandle, bool bCommand)
{
bool bAux = true;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if (MC_NULL == pHandle)
{
/* nothing to do */
}
else
{
#endif
if (true == bCommand)
{
pHandle->bTransitionStarted = true;
if (0 == pHandle->hTransitionSteps)
{
pHandle->bTransitionEnded = true;
pHandle->_Super.bSpeedErrorNumber = 0U;
bAux = false;
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
return (bAux);
}
/**
* @brief Returns the status of the transition phase by checking the status of the two parameters
* @ref VirtualSpeedSensor_Handle_t::bTransitionStarted "bTransitionStarted" and
* @ref VirtualSpeedSensor_Handle_t::bTransitionEnded "bTransitionEnded".
* @param pHandle: handler of the current instance of the VirtualSpeedSensor components
* @retval bool: true if Transition phase is ongoing, false otherwise.
*
* - Not used into current implementation.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool VSS_IsTransitionOngoing(VirtualSpeedSensor_Handle_t *pHandle)
{
bool retVal = false;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if (MC_NULL == pHandle)
{
/* nothing to do */
}
else
{
#endif
uint16_t hTS = 0U;
uint16_t hTE = 0U;
uint16_t hAux;
if (true == pHandle->bTransitionStarted)
{
hTS = 1U;
}
else
{
/* Nothing to do */
}
if (true == pHandle->bTransitionEnded)
{
hTE = 1U;
}
else
{
/* Nothing to do */
}
hAux = hTS ^ hTE;
if (hAux != 0U)
{
retVal = true;
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
return (retVal);
}
/**
* @brief Returns the ending status of the transition phase by checking the parameter
* @ref VirtualSpeedSensor_Handle_t::bTransitionEnded "bTransitionEnded".
* @param pHandle: handler of the current instance of the VirtualSpeedSensor components
* @retval bool: true if Transition phase ended, false otherwise.
*
* - Called into SWITCH_OVER state of MC tasks state machine into TSK_MediumFrequencyTask.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool VSS_TransitionEnded(VirtualSpeedSensor_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
return ((MC_NULL == pHandle) ? false : pHandle->bTransitionEnded);
#else
return (pHandle->bTransitionEnded);
#endif
}
/**
* @brief Sets instantaneous information on rotor electrical angle same as copied by state observer.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @retval none
*
* - Not used into current implementation.
*/
__weak void VSS_SetCopyObserver(VirtualSpeedSensor_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->bCopyObserver = true;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
}
/**
* @brief Sets instantaneous information on rotor electrical angle.
* @param pHandle: handler of the current instance of the VirtualSpeedSensor component.
* @param hElAngle instantaneous measure of rotor electrical angle in [s16degrees](measurement_units.md).
* @retval none
*
* - Not used into current implementation.
*/
__weak void VSS_SetElAngle(VirtualSpeedSensor_Handle_t *pHandle, int16_t hElAngle)
{
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hElAngleAccu = hElAngle;
pHandle->_Super.hElAngle = hElAngle;
#ifdef NULL_PTR_CHECK_VIR_SPD_SEN
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 19,123 | C | 29.845161 | 128 | 0.638707 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/profiler.c | /**
******************************************************************************
* @file profiler.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement
* the profiler component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup Profiler
*/
/* Includes ------------------------------------------------------------------*/
#include "profiler.h"
#include "drive_parameters.h"
#include "parameters_conversion.h"
/** @addtogroup MCSDK
* @{
*/
/**
* @defgroup Profiler
*
* @brief Profiler component of the Motor Control SDK
*
* This procedure can be used to identify any PMSM.
*
* Once the profiler complete successfully the motor parameters @f$R_s,\ L_s@f$ and motor flux @f$\psi_{mag} @f$ are provided.\n
* The estimated @f$R_s@f$ and @f$L_s@f$ are then used to define the PI settings (@f$K_p,\ K_i@f$) for current controllers.
*
* [Profiler](Profiler.md)
*
* @{
*/
void PROFILER_stateMachine(PROFILER_Handle handle, MOTOR_Handle motor);
/**
* @brief Initializes Profiler component.
* @param handle Profiler handler
* @param pParams pointer on profiler parameters
* @param flashParams pointer on flash parameters handler
*
*/
void PROFILER_init(PROFILER_Handle handle,
PROFILER_Params *pParams,
FLASH_Params_t const *flashParams)
{
PROFILER_DCAC_init(&handle->dcacObj);
PROFILER_FLUXESTIM_init(&handle->fluxestimObj);
pParams->fullScaleFreq_Hz = flashParams->scale.frequency;
pParams->fullScaleCurrent_A = flashParams->scale.current;
pParams->fullScaleVoltage_V = flashParams->scale.voltage;
pParams->PolePairs = flashParams->motor.polePairs;
handle->PolePairs = pParams->PolePairs;
handle->PowerDC_goal_W = pParams->dcac_PowerDC_goal_W;
handle->fullScaleFreq_Hz = pParams->fullScaleFreq_Hz;
handle->fullScaleVoltage_V = pParams->fullScaleVoltage_V;
PROFILER_DCAC_setParams(&handle->dcacObj, pParams);
PROFILER_FLUXESTIM_setParams(&handle->fluxestimObj, pParams);
}
/**
* Resets Profiler to restart new measure
* param pHandle Profiler handler
* param motor handler
*
*/
void PROFILER_reset(PROFILER_Handle handle, MOTOR_Handle motor)
{
handle->state = PROFILER_STATE_Idle;
handle->command = PROFILER_COMMAND_None;
handle->error = PROFILER_ERROR_None;
PROFILER_DCAC_reset(&handle->dcacObj, motor);
PROFILER_FLUXESTIM_reset(&handle->fluxestimObj, motor);
/* Clear result variables */
PROFILER_resetEstimates(handle);
}
/**
* @brief Executes profiler procedure
* @param handle Profiler handler
* @param motor motor handler
*
*/
void PROFILER_run(PROFILER_Handle handle, MOTOR_Handle motor)
{
/* Called from the motor control interrupt */
/* Required because some data can only be calculated in the interrupt (or at least synchronous to isr)
* Slow/demanding calculations are not allowed
*/
switch (handle->state)
{
case PROFILER_STATE_DCandACcheck:
PROFILER_DCAC_run(&handle->dcacObj, motor);
break;
case PROFILER_STATE_FluxEstim:
PROFILER_FLUXESTIM_run(&handle->fluxestimObj, motor);
break;
case PROFILER_STATE_Idle:
/* No break */
case PROFILER_STATE_Complete:
/* No break */
case PROFILER_STATE_Error:
case PROFILER_STATE_DCAC_Error:
case PROFILER_STATE_FluxEstim_Error:
/* Nothing to do in these states */
break;
}
}
/**
* @brief Executes profiling in background task.
* @param handle Profiler handler
* @param motor parameters
*
*/
void PROFILER_runBackground(PROFILER_Handle handle, MOTOR_Handle motor)
{
/* Called from slow control loop, outside of ISR */
/* Does nothing when profiler is not active */
if ((handle->state == PROFILER_STATE_Idle || handle->state == PROFILER_STATE_Complete) &&
(handle->command != PROFILER_COMMAND_Start) && handle->command != PROFILER_COMMAND_Reset) return;
/* Run the profiler top-level state machine */
PROFILER_stateMachine(handle, motor);
/* Run the lower level profilers */
switch(handle->state)
{
case PROFILER_STATE_DCandACcheck:
PROFILER_DCAC_runBackground(&handle->dcacObj, motor);
break;
case PROFILER_STATE_FluxEstim:
PROFILER_FLUXESTIM_runBackground(&handle->fluxestimObj, motor);
break;
case PROFILER_STATE_Complete:
case PROFILER_STATE_Error:
case PROFILER_STATE_DCAC_Error:
case PROFILER_STATE_FluxEstim_Error:
motor->pSPD->zestControl.injectFreq_kHz = FIXP30(80.0f / 1000.0f); // switch to 80Hz injection frequency after profiling;
motor->pSPD->zestControl.injectId_A_pu = 0; // switch to 0 injection after profiling;
motor->pSPD->zestControl.feedbackGainD = 0; // reset gainD after profiling
motor->pSPD->zestControl.feedbackGainQ = 0; // reset gainQ after profiling
motor->pCurrCtrl->Ddq_ref_pu.D = 0 ;
break;
case PROFILER_STATE_Idle:
/* No break */
/* Nothing to do in these states */
break;
}
}
/**
* @brief Set PWM off and disable current controller
* @param handle Profiler handler
* @param motor parameters
*
*/
void PROFILER_setMotorToIdle(PROFILER_Handle handle, MOTOR_Handle motor)
{
motor->pCurrCtrl->forceZeroPwm = true;
motor->pCurrCtrl->currentControlEnabled = false;
}
/**
* @brief Check profiler state before to start profiling procedure
* @param handle Profiler handler
* @param motor parameters
*
*/
PROFILER_Error_e PROFILER_isReadyToStart(PROFILER_Handle handle, MOTOR_Handle motor)
{
// ToDo: Check PWM is active (Requires reference to hardware layer from motorHandle)
/* Must be in control mode 'None' */ // ToDo: Allow Profiler start in more controlModes
if (motor->pFocVars->controlMode != MCM_PROFILING_MODE) return PROFILER_ERROR_NotReady;
// ToDo: Check offset measurement performed (or known-good from EEPROM)
if (motor->pCurrCtrl->forceZeroPwm == false) return PROFILER_ERROR_NotReady; /* Must be in ForceZeroPwm mode */
return PROFILER_ERROR_None;
}
/**
* @brief Profiler top-level state machine
* @param handle Profiler handler
* @param motor parameters
*
*/
void PROFILER_stateMachine(PROFILER_Handle handle, MOTOR_Handle motor)
{
PROFILER_State_e state = handle->state;
PROFILER_State_e newState = state;
PROFILER_Command_e command = handle->command;
handle->command = PROFILER_COMMAND_None;
switch (state)
{
case PROFILER_STATE_Idle:
if (command == PROFILER_COMMAND_Start)
{
PROFILER_Error_e isReadyResult = PROFILER_isReadyToStart(handle, motor);
if (isReadyResult == PROFILER_ERROR_None)
{
handle->error = PROFILER_ERROR_None;
/* Reset sub-profilers */
PROFILER_DCAC_reset(&handle->dcacObj, motor);
PROFILER_FLUXESTIM_reset(&handle->fluxestimObj, motor);
PROFILER_resetEstimates(handle);
/* Set up for DCAC measurement */
handle->dcacObj.PowerDC_goal_W = handle->PowerDC_goal_W;
motor->pFocVars->controlMode = MCM_PROFILING_MODE;
newState = PROFILER_STATE_DCandACcheck;
}
else
{
/* Cannot start profiling now */
handle->error = isReadyResult;
newState = PROFILER_STATE_Error;
}
}
break;
case PROFILER_STATE_DCandACcheck:
if ((handle->dcacObj.state == PROFILER_DCAC_STATE_Complete) || (handle->dcacObj.state == PROFILER_DCAC_STATE_Error))
{
/* Fetch measured Rs and Ls */
handle->PowerDC_W = handle->dcacObj.PowerDC_W;
handle->dutyDC = FIXP30_toF(handle->dcacObj.dc_duty_pu);
handle->Idc_A = FIXP30_toF(handle->dcacObj.Id_dc_ref_pu) * handle->dcacObj.fullScaleCurrent_A;
handle->Rs_dc = handle->dcacObj.Rs_dc;
handle->Rs_ac = handle->dcacObj.Rs_inject;
handle->Ld_H = handle->dcacObj.Ls_inject;
handle->Lq_H = 0.0f; //todo
handle->R_factor = handle->dcacObj.Rs_inject / handle->dcacObj.Rs_dc;
handle->injectFreq_Hz = FIXP30_toF(handle->dcacObj.ac_freqkHz_pu) * 1000.0f;
/* Copy value from DCAC test */
handle->fluxestimObj.Id_ref_pu = handle->dcacObj.Id_dc_ref_pu;
handle->fluxestimObj.ramp_rate_A_pu_per_cycle = FIXP30_mpy(handle->fluxestimObj.Id_ref_pu, handle->fluxestimObj.CurToRamp_sf_pu);
if (handle->dcacObj.state == PROFILER_DCAC_STATE_Error)
{
handle->error = PROFILER_ERROR_DCAC;
newState = PROFILER_STATE_DCAC_Error;
/* Clear profiling mode */
motor->pFocVars->controlMode = MCM_PROFILING_MODE;
}
else
{
newState = PROFILER_STATE_FluxEstim;
}
}
break;
case PROFILER_STATE_FluxEstim:
if ((handle->fluxestimObj.state == PROFILER_FLUXESTIM_STATE_Complete) || (handle->fluxestimObj.state == PROFILER_FLUXESTIM_STATE_Error))
{
/* Fetch measured Flux */
handle->freqEst_Hz = FIXP30_toF(handle->fluxestimObj.freqEst_pu) * handle->fullScaleFreq_Hz;
handle->freqHSO_Hz = FIXP30_toF(handle->fluxestimObj.freqHSO_pu) * handle->fullScaleFreq_Hz;
if (handle->fluxestimObj.state == PROFILER_FLUXESTIM_STATE_Complete)
{
handle->Flux_Wb = FIXP30_toF(handle->fluxestimObj.flux_Wb);
handle->debug_Flux_VpHz = M_TWOPI * handle->Flux_Wb; /* Flux V/Hz, just for check*/
handle->debug_kV = 30.0f / (1.0000f * handle->PolePairs * handle->debug_Flux_VpHz); //rpm per Volt DC (drone motors)
handle->KT_Nm_A = 1.5f * handle->PolePairs * handle->Flux_Wb; /* Torque per Amp (Nm/Apeak) */
handle->Isc_A = handle->Flux_Wb / handle->Ld_H; /* machine's short-circuit current */
/* Update PolePulse parameters */
POLPULSE_setCurrentGoal(motor->pPolpulse, 0.25f*handle->Isc_A);
POLPULSE_setLsd(motor->pPolpulse, handle->Ld_H);
handle->CritFreq_Hz = (handle->Rs_dc * handle->Idc_A) / handle->debug_Flux_VpHz; /* freq where Rs voltage drop would equal emf at used current level */
// suggested Kp_mech = 5 * rated current / rated speed: rated current is about
float FullScaleFlux = handle->fullScaleVoltage_V * (float)(1.0f/TF_REGULATION_RATE);
float RatedFlux_pu = (M_TWOPI * handle->Flux_Wb) / FullScaleFlux;
float oneOverRatedFlux_pu = 1.0f / RatedFlux_pu;
FIXPSCALED_floatToFIXPscaled(oneOverRatedFlux_pu, &motor->pSPD->oneOverFlux_pu_fps);
motor->pFocVars->Kt = (1.0f / (1.5f * handle->PolePairs * handle->Flux_Wb));
motor->pSPD->flagDynamicQgain = false;
newState = PROFILER_STATE_Complete;
}
else /* PROFILER_FLUXESTIM_STATE_Error */
{
handle->Flux_Wb = 0.0;
handle->debug_Flux_VpHz = 0.0;
handle->debug_kV = 0.0;
handle->KT_Nm_A = 0.0;
handle->Isc_A = 0.0;
handle->CritFreq_Hz = 0.0;
handle->error = PROFILER_ERROR_FluxEstim;
newState = PROFILER_STATE_FluxEstim_Error;
}
/* PWM off and related settings */
PROFILER_setMotorToIdle(handle, motor);
/* Next state */
motor->pFocVars->controlMode = MCM_PROFILING_MODE;
}
break;
case PROFILER_STATE_Complete:
{
PROFILER_DCAC_reset(&handle->dcacObj, motor);
PROFILER_FLUXESTIM_reset(&handle->fluxestimObj, motor);
/* Allow starting from Complete state */
if (command == PROFILER_COMMAND_Start)
{
newState = PROFILER_STATE_Idle;
}
}
break;
case PROFILER_STATE_Error:
case PROFILER_STATE_DCAC_Error:
case PROFILER_STATE_FluxEstim_Error:
/* PWM off and related settings */
PROFILER_setMotorToIdle(handle, motor);
break;
}
/* Reset is allowed in any state */
if (command == PROFILER_COMMAND_Reset)
{
PROFILER_reset(handle, motor);
newState = PROFILER_STATE_Idle;
}
if (newState != state)
{
handle->state = newState;
}
}
/* Accessors */
float_t PROFILER_getDcAcMeasurementTime(PROFILER_Handle handle)
{
return PROFILER_DCAC_getMeasurementTime(&handle->dcacObj);
}
/**
* @brief Returns measured flux amplitude (in Weber)
* @param pHandle Handle on the Profiler component
*/
float_t PROFILER_getFlux_Wb(const PROFILER_Handle handle)
{
return handle->Flux_Wb;
}
/**
* @brief Returns estimated flux amplitude (in Hz)
* @param pHandle Handle on the Profiler component
*/
float_t PROFILER_getFluxEstFreq_Hz(const PROFILER_Handle handle)
{
return PROFILER_FLUXESTIM_getFluxEstFreq_Hz(&handle->fluxestimObj);
}
/**
* @brief Returns measurement time allowed to estimate the flux
* @param pHandle Handle on the Profiler component
*/
float_t PROFILER_getFluxEstMeasurementTime(PROFILER_Handle handle)
{
return PROFILER_FLUXESTIM_getMeasurementTime(&handle->fluxestimObj);
}
/**
* @brief Returns estimated inductance (in Henry)
* @param pHandle Handle on the Profiler component
*/
float_t PROFILER_getLd_H(const PROFILER_Handle handle)
{
return handle->Ld_H;
}
/**
* @brief Returns power goal used for DCAC measurement
* @param pHandle Handle on the Profiler component
*/
float_t PROFILER_getPowerGoal_W(const PROFILER_Handle handle)
{
return handle->PowerDC_goal_W;
}
/**
* @brief Returns estimated resistance Rs_ac from AC-duty injection
* @param pHandle Handle on the Profiler component
*/
float_t PROFILER_getRs_ac(const PROFILER_Handle handle)
{
return handle->Rs_ac;
}
/**
* @brief Returns estimated resistance Rs_dc once current ramp-up complete
* @param pHandle Handle on the Profiler component
*/
float_t PROFILER_getRs_dc(const PROFILER_Handle handle)
{
return handle->Rs_dc;
}
/**
* @brief Sets user command to start or reset the profiler
* @param pHandle Handle on the Profiler component
* @param command User command: Start or Reset
*/
void PROFILER_setCommand(PROFILER_Handle handle, const PROFILER_Command_e command)
{
handle->command = command;
}
/**
* @brief Sets measurement time allowed to DCAC steps
* @param pHandle Handle on the Profiler component
* @param time_seconds time in seconds allowed to execute each one of steps: DC, AC measuring
*/
void PROFILER_setDcAcMeasurementTime(PROFILER_Handle handle, const float_t time_seconds)
{
PROFILER_DCAC_setMeasurementTime(&handle->dcacObj, time_seconds);
}
/**
* @brief Sets flux estimation frequency
* @param pHandle Handle on the Profiler component
* @param fluxEstFreq_Hz Flux estimate frequency (speed in Hz)
*/
void PROFILER_setFluxEstFreq_Hz(PROFILER_Handle handle, const float_t fluxEstFreq_Hz)
{
PROFILER_FLUXESTIM_setFluxEstFreq_Hz(&handle->fluxestimObj, fluxEstFreq_Hz);
}
/**
* @brief Sets measurement time allowed for flux estimate step
* @param pHandle Handle on the Profiler component
* @param time_seconds time in seconds allowed to execute the flux measurement step
*/
void PROFILER_setFluxEstMeasurementTime(PROFILER_Handle handle, const float_t time_seconds)
{
PROFILER_FLUXESTIM_setMeasurementTime(&handle->fluxestimObj, time_seconds);
}
/**
* @brief Sets the number of polepairs
* @param pHandle Handle on the Profiler component
* @param polepairs number of polepairs
*/
void PROFILER_setPolePairs(PROFILER_Handle handle, const float_t polepairs)
{
handle->PolePairs = polepairs;
}
/**
* @brief Sets the power goal for DCAC measurement
* @param pHandle Handle on the Profiler component
* @param powerGoal_W Level of power allowed to identify the motor
*/
void PROFILER_setPowerGoal_W(PROFILER_Handle handle, const float_t powerGoal_W)
{
if (handle->state == PROFILER_STATE_Idle || handle->state == PROFILER_STATE_Complete || handle->state == PROFILER_STATE_Error)
{
handle->PowerDC_goal_W = powerGoal_W;
}
}
/**
* @brief Clears result variables before each profiling
* @param pHandle Handle on the Profiler component
*/
void PROFILER_resetEstimates(PROFILER_Handle handle)
{
handle->PowerDC_W = 0.0;
handle->dutyDC = 0.0;
handle->Idc_A = 0.0;
handle->Rs_dc = 0.0;
handle->Rs_ac = 0.0;
handle->Ld_H = 0.0;
handle->Lq_H = 0.0f;
handle->freqEst_Hz = 0.0;
handle->freqHSO_Hz = 0.0;
handle->Flux_Wb = 0.0;
handle->debug_Flux_VpHz = 0.0;
handle->debug_kV = 0.0;
handle->KT_Nm_A = 0.0;
handle->Isc_A = 0.0;
handle->CritFreq_Hz = 0.0;
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 16,941 | C | 30.316081 | 159 | 0.665132 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/ramp_ext_mngr.c | /**
******************************************************************************
* @file ramp_ext_mngr.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Ramp Extended Manager component of the Motor Control SDK:
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "ramp_ext_mngr.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup RampExtMngr Ramp Manager
* @brief Ramp Extended Manager component of the Motor Control SDK
*
* @todo Document the Ramp Extended Manager "module".
*
* @{
*/
/* Private function prototypes -----------------------------------------------*/
uint32_t getScalingFactor(int32_t Target);
/**
* @brief It reset the state variable to zero.
* @param pHandle related Handle of struct RampMngr_Handle_t
* @retval none.
*/
void REMNG_Init(RampExtMngr_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->Ext = 0;
pHandle->TargetFinal = 0;
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
pHandle->ScalingFactor = 1U;
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
}
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Exec the ramp calculations and returns the current value of the
state variable.
It must be called at fixed interval defined in the hExecFreq.
* @param pHandle related Handle of struct RampMngr_Handle_t
* @retval int32_t value of the state variable
*/
__weak int32_t REMNG_Calc(RampExtMngr_Handle_t *pHandle)
{
int32_t ret_val;
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
if (MC_NULL == pHandle)
{
ret_val = 0;
}
else
{
#endif
int32_t current_ref;
current_ref = pHandle->Ext;
/* Update the variable and terminates the ramp if needed */
if (pHandle->RampRemainingStep > 1U)
{
/* Increment/decrement the reference value */
current_ref += pHandle->IncDecAmount;
/* Decrement the number of remaining steps */
pHandle->RampRemainingStep --;
}
else if (1U == pHandle->RampRemainingStep)
{
/* Set the backup value of TargetFinal */
current_ref = pHandle->TargetFinal * ((int32_t)pHandle->ScalingFactor);
pHandle->RampRemainingStep = 0U;
}
else
{
/* Do nothing */
}
pHandle->Ext = current_ref;
ret_val = pHandle->Ext / ((int32_t)pHandle->ScalingFactor);
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
}
#endif
return (ret_val);
}
/**
* @brief Setup the ramp to be executed
* @param pHandle related Handle of struct RampMngr_Handle_t
* @param hTargetFinal (signed 32bit) final value of state variable at the end
* of the ramp.
* @param hDurationms (unsigned 32bit) the duration of the ramp expressed in
* milliseconds. It is possible to set 0 to perform an instantaneous
* change in the value.
* @retval bool It returns true is command is valid, false otherwise
*/
__weak bool REMNG_ExecRamp(RampExtMngr_Handle_t *pHandle, int32_t TargetFinal, uint32_t Durationms)
{
bool retVal = true;
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
if (MC_NULL == pHandle)
{
retVal = false;
}
else
{
#endif
uint32_t aux;
int32_t aux1;
int32_t current_ref;
/* Get current state */
current_ref = pHandle->Ext / ((int32_t)pHandle->ScalingFactor);
if (0U == Durationms)
{
pHandle->ScalingFactor = getScalingFactor(TargetFinal);
pHandle->Ext = TargetFinal * ((int32_t)pHandle->ScalingFactor);
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
}
else
{
uint32_t wScalingFactor = getScalingFactor(TargetFinal - current_ref);
uint32_t wScalingFactor2 = getScalingFactor(current_ref);
uint32_t wScalingFactor3 = getScalingFactor(TargetFinal);
uint32_t wScalingFactorMin;
if (wScalingFactor < wScalingFactor2)
{
if (wScalingFactor < wScalingFactor3)
{
wScalingFactorMin = wScalingFactor;
}
else
{
wScalingFactorMin = wScalingFactor3;
}
}
else
{
if (wScalingFactor2 < wScalingFactor3)
{
wScalingFactorMin = wScalingFactor2;
}
else
{
wScalingFactorMin = wScalingFactor3;
}
}
pHandle->ScalingFactor = wScalingFactorMin;
pHandle->Ext = current_ref * ((int32_t)pHandle->ScalingFactor);
/* Store the TargetFinal to be applied in the last step */
pHandle->TargetFinal = TargetFinal;
/* Compute the (wRampRemainingStep) number of steps remaining to complete the ramp */
aux = Durationms * ((uint32_t)pHandle->FrequencyHz); /* Check for overflow and use prescaler */
aux /= 1000U;
pHandle->RampRemainingStep = aux;
pHandle->RampRemainingStep++;
/* Compute the increment/decrement amount (wIncDecAmount) to be applied to
the reference value at each CalcTorqueReference */
aux1 = (TargetFinal - current_ref) * ((int32_t)pHandle->ScalingFactor);
aux1 /= ((int32_t)pHandle->RampRemainingStep);
pHandle->IncDecAmount = aux1;
}
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
}
#endif
return (retVal);
}
/**
* @brief Returns the current value of the state variable.
* @param pHandle related Handle of struct RampMngr_Handle_t
* @retval int32_t value of the state variable
*/
__weak int32_t REMNG_GetValue(const RampExtMngr_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
return ((MC_NULL == pHandle) ? 0 : (pHandle->Ext / ((int32_t)pHandle->ScalingFactor)));
#else
return (pHandle->Ext / ((int32_t)pHandle->ScalingFactor));
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Check if the settled ramp has been completed.
* @param pHandle related Handle of struct RampMngr_Handle_t.
* @retval bool It returns true if the ramp is completed, false otherwise.
*/
__weak bool REMNG_RampCompleted(const RampExtMngr_Handle_t *pHandle)
{
bool retVal = false;
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (0U == pHandle->RampRemainingStep)
{
retVal = true;
}
else
{
/* nothing to do */
}
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
}
#endif
return (retVal);
}
/**
* @brief Stop the execution of the ramp keeping the last reached value.
* @param pHandle related Handle of struct RampMngr_Handle_t.
* @retval none
*/
__weak void REMNG_StopRamp(RampExtMngr_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
#ifdef NULL_PTR_CHECK_RMP_EXT_MNG
}
#endif
}
/**
* @brief Calculating the scaling factor to maximixe the resolution. It
* perform the 2^int(31-log2(Target)) with an iterative approach.
* It allows to keep Target * Scaling factor inside int32_t type.
* @param Target Input data.
* @retval uint32_t It returns the optimized scaling factor.
*/
__weak uint32_t getScalingFactor(int32_t Target)
{
uint32_t TargetAbs;
int32_t aux;
uint8_t i;
if (Target < 0)
{
aux = -Target;
TargetAbs = (uint32_t)aux;
}
else
{
TargetAbs = (uint32_t)Target;
}
for (i = 1U; i < 32U; i++)
{
uint32_t limit = (((uint32_t)1) << (31U - i));
if (TargetAbs >= limit)
{
break;
}
else
{
/* Nothing to do */
}
}
return (((uint32_t)1) << (i - 1U));
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 8,605 | C | 25 | 101 | 0.607438 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/virtual_bus_voltage_sensor.c | /**
******************************************************************************
* @file virtual_bus_voltage_sensor.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Virtual Bus Voltage Sensor component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup VirtualBusVoltageSensor
*/
/* Includes ------------------------------------------------------------------*/
#include "virtual_bus_voltage_sensor.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup BusVoltageSensor
* @{
*/
/** @defgroup VirtualBusVoltageSensor Virtual Bus Voltage Sensor
* @brief Virtual Bus Voltage Sensor implementation.
*
* @{
*/
/**
* @brief It initializes bus voltage conversion for virtual bus voltage sensor
* (latest value and averaged value) with expected VBus value
* @param pHandle related Handle of VirtualBusVoltageSensor_Handle_t
* @retval none
*/
__weak void VVBS_Init(VirtualBusVoltageSensor_Handle_t *pHandle)
{
pHandle->_Super.FaultState = MC_NO_ERROR;
pHandle->_Super.LatestConv = pHandle->ExpectedVbus_d;
pHandle->_Super.AvBusVoltage_d = pHandle->ExpectedVbus_d;
}
/**
* @brief Empty function (no process and no returned value)
* @param pHandle related Handle of VirtualBusVoltageSensor_Handle_t
* @retval none
*/
__weak void VVBS_Clear(VirtualBusVoltageSensor_Handle_t *pHandle)
{
return;
}
/**
* @brief It returns #MC_NO_ERROR
* @param pHandle related Handle of VirtualBusVoltageSensor_Handle_t
* @retval uint16_t Fault code error: #MC_NO_ERROR
*/
__weak uint16_t VVBS_NoErrors(VirtualBusVoltageSensor_Handle_t *pHandle)
{
return (MC_NO_ERROR);
}
/**
* @}
*/
/**
* @}
*/
/** @} */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,410 | C | 27.034883 | 85 | 0.582988 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/revup_ctrl_sixstep.c | /**
******************************************************************************
* @file revup_ctrl_sixstep.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides the functions that implement the features
* of the Rev-Up Control component for Six-Step drives of the Motor
* Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
* @ingroup RevUpCtrl6S
*/
/* Includes ------------------------------------------------------------------*/
#include "revup_ctrl_sixstep.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup RevUpCtrl
*
* @{
*/
/** @defgroup RevUpCtrl6S Six-Step Rev-Up Control component
* @brief Rev-Up Control component used to start motor driven with the Six-Step technique
*
* @{
*/
/* Private defines -----------------------------------------------------------*/
/**
* @brief Timeout used to reset integral term of PLL.
* It is expressed in ms.
*
*/
#define RUC_OTF_PLL_RESET_TIMEOUT 100u
/* Private functions ----------------------------------------------------------*/
/* Returns the mechanical speed of a selected phase */
static int16_t RUC_GetPhaseFinalMecSpeed01Hz(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase)
{
int16_t hRetVal = 0;
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
hRetVal = pHandle->ParamsData[bPhase].hFinalMecSpeedUnit;
}
return (hRetVal);
}
/**
* @brief Initialize and configure the 6-Step RevUpCtrl Component
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param pSTC: Pointer on speed and torque controller structure.
* @param pVSS: Pointer on virtual speed sensor structure.
*/
__weak void RUC_Init( RevUpCtrl_Handle_t *pHandle,
SpeednTorqCtrl_Handle_t *pSTC,
VirtualSpeedSensor_Handle_t *pVSS)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
RevUpCtrl_PhaseParams_t *pRUCPhaseParams = &pHandle->ParamsData[0];
uint8_t bPhase = 0U;
pHandle->pSTC = pSTC;
pHandle->pVSS = pVSS;
while ((pRUCPhaseParams != MC_NULL) && (bPhase < RUC_MAX_PHASE_NUMBER))
{
/* Dump HF data for now HF data are forced to 16 bits*/
pRUCPhaseParams = (RevUpCtrl_PhaseParams_t * )pRUCPhaseParams->pNext; //cstat !MISRAC2012-Rule-11.5
bPhase++;
}
if (0U == bPhase)
{
/* nothing to do error */
}
else
{
pHandle->ParamsData[bPhase - 1u].pNext = MC_NULL;
pHandle->bPhaseNbr = bPhase;
}
}
}
/*
* @brief Initialize internal 6-Step RevUp controller state.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param hMotorDirection: Rotor rotation direction.
* This parameter must be -1 or +1.
*/
__weak void RUC_Clear(RevUpCtrl_Handle_t *pHandle, int16_t hMotorDirection)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
VirtualSpeedSensor_Handle_t *pVSS = pHandle->pVSS;
SpeednTorqCtrl_Handle_t *pSTC = pHandle->pSTC;
RevUpCtrl_PhaseParams_t *pPhaseParams = pHandle->ParamsData;
pHandle->hDirection = hMotorDirection;
/*Initializes the rev up stages counter.*/
pHandle->bStageCnt = 0U;
/* Calls the clear method of VSS.*/
VSS_Clear(pVSS);
/* Sets the STC in torque mode.*/
STC_SetControlMode(pSTC, MCM_TORQUE_MODE);
/* Sets the mechanical starting angle of VSS.*/
VSS_SetMecAngle(pVSS, pHandle->hStartingMecAngle * hMotorDirection);
/* Sets to zero the starting torque of STC */
(void)STC_ExecRamp(pSTC, STC_GetDutyCycleRef(pSTC), 0U);
/* Gives the first command to STC and VSS.*/
(void)STC_ExecRamp(pSTC, pPhaseParams->hFinalPulse, (uint32_t)(pPhaseParams->hDurationms));
VSS_SetMecAcceleration(pVSS, pPhaseParams->hFinalMecSpeedUnit * hMotorDirection, pPhaseParams->hDurationms );
/* Compute hPhaseRemainingTicks.*/
pHandle->hPhaseRemainingTicks = (uint16_t)((((uint32_t)pPhaseParams->hDurationms)
* ((uint32_t)pHandle->hRUCFrequencyHz))
/ 1000U );
pHandle->hPhaseRemainingTicks++;
/*Set the next phases parameter pointer.*/
pHandle->pCurrentPhaseParams = (RevUpCtrl_PhaseParams_t * )pPhaseParams->pNext; //cstat !MISRAC2012-Rule-11.5
pHandle->EnteredZone1 = false;
}
}
/**
* @brief Update rev-up duty cycle relative to actual Vbus value to be applied
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param BusVHandle: pointer to the bus voltage sensor
*/
__weak void RUC_UpdatePulse(RevUpCtrl_Handle_t *pHandle, BusVoltageSensor_Handle_t *BusVHandle)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
uint16_t tPulseUpdateFactor = 10 * NOMINAL_BUS_VOLTAGE_V
/ VBS_GetAvBusVoltage_V(BusVHandle);
pHandle->PulseUpdateFactor = tPulseUpdateFactor;
}
}
/*
* @brief 6-Step Main revup controller procedure executing overall programmed phases.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to true when entire revup phases have been completed.
*/
__weak bool RUC_Exec(RevUpCtrl_Handle_t *pHandle)
{
bool retVal = true;
if (MC_NULL == pHandle)
{
retVal = false;
}
else
{
if (pHandle->hPhaseRemainingTicks > 0U)
{
/* Decrease the hPhaseRemainingTicks.*/
pHandle->hPhaseRemainingTicks--;
} /* hPhaseRemainingTicks > 0 */
if (0U == pHandle->hPhaseRemainingTicks)
{
if (pHandle->pCurrentPhaseParams != MC_NULL)
{
/* If it becomes zero the current phase has been completed.*/
/* Gives the next command to STC and VSS.*/
uint16_t hPulse = pHandle->pCurrentPhaseParams->hFinalPulse * pHandle->PulseUpdateFactor / 10;
(void)STC_ExecRamp(pHandle->pSTC, hPulse,
(uint32_t)(pHandle->pCurrentPhaseParams->hDurationms));
VSS_SetMecAcceleration(pHandle->pVSS,
pHandle->pCurrentPhaseParams->hFinalMecSpeedUnit * pHandle->hDirection,
pHandle->pCurrentPhaseParams->hDurationms);
/* Compute hPhaseRemainingTicks.*/
pHandle->hPhaseRemainingTicks = (uint16_t)((((uint32_t)pHandle->pCurrentPhaseParams->hDurationms)
* ((uint32_t)pHandle->hRUCFrequencyHz)) / 1000U );
pHandle->hPhaseRemainingTicks++;
/*Set the next phases parameter pointer.*/
pHandle->pCurrentPhaseParams = pHandle->pCurrentPhaseParams->pNext; //cstat !MISRAC2012-Rule-11.5
/*Increases the rev up stages counter.*/
pHandle->bStageCnt++;
}
else
{
retVal = false;
}
}
}
return (retVal);
}
/*
* @brief It is used to check if this stage is used for align motor.
* @param this related object of class CRUC.
* @retval Returns 1 if the alignment is correct otherwise it returns 0
*/
uint8_t RUC_IsAlignStageNow(RevUpCtrl_Handle_t *pHandle)
{
uint8_t align_flag = 0;
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
int16_t speed;
speed = RUC_GetPhaseFinalMecSpeed01Hz(pHandle, pHandle->bStageCnt);
if (0 == speed)
{
align_flag = 1;
}
}
return (align_flag);
}
/*
* @brief Provide current state of revup controller procedure.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to true when entire revup phases have been completed.
*/
__weak bool RUC_Completed(RevUpCtrl_Handle_t *pHandle)
{
bool retVal = false;
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
if (MC_NULL == pHandle->pCurrentPhaseParams)
{
retVal = true;
}
}
return (retVal);
}
/*
* @brief Allow to exit from RevUp process at the current rotor speed.
* @param pHandle: Pointer on Handle structure of RevUp controller.
*/
__weak void RUC_Stop(RevUpCtrl_Handle_t *pHandle)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
VirtualSpeedSensor_Handle_t *pVSS = pHandle->pVSS;
pHandle->pCurrentPhaseParams = MC_NULL;
pHandle->hPhaseRemainingTicks = 0U;
VSS_SetMecAcceleration(pVSS, SPD_GetAvrgMecSpeedUnit(&pVSS->_Super), 0U);
}
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__( ( section ( ".ccmram" ) ) )
#endif
#endif
/*
* @brief Check that alignment and first acceleration stage are completed.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to true when first acceleration stage has been reached.
*/
__weak bool RUC_FirstAccelerationStageReached( RevUpCtrl_Handle_t * pHandle)
{
bool retVal = false;
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
if (pHandle->bStageCnt >= pHandle->bFirstAccelerationStage)
{
retVal = true;
}
}
return (retVal);
}
/*
* @brief Check that minimum rotor speed has been reached.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to true when speed has been reached.
*/
__weak bool RUC_ObserverSpeedReached( RevUpCtrl_Handle_t * pHandle)
{
bool retVal = false;
VirtualSpeedSensor_Handle_t *pVSS = pHandle->pVSS;
int16_t hSpeed;
hSpeed = SPD_GetAvrgMecSpeedUnit(&pVSS->_Super);
if (hSpeed < 0) hSpeed = -hSpeed;
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
if ((false == pHandle->EnteredZone1) && (hSpeed >= pHandle->hMinStartUpValidSpeed))
{
pHandle->EnteredZone1 = true;
retVal = true;
}
}
return (retVal);
}
/*
* @brief Allow to modify duration of a selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase where new duration shall be modified.
* This parameter must be a number between 0 and 6.
* @param hDurationms: new duration value required for associated phase.
* This parameter must be set in millisecond.
*/
__weak void RUC_SetPhaseDurationms(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase, uint16_t hDurationms)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->ParamsData[bPhase].hDurationms = hDurationms;
}
}
/*
* @brief Allow to modify targeted mechanical speed of a selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase where new mechanical speed shall be modified.
* This parameter must be a number between 0 and 6.
* @param hFinalMecSpeedUnit: new targeted mechanical speed.
* This parameter must be expressed in 0.1Hz.
*/
__weak void RUC_SetPhaseFinalMecSpeedUnit(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase, int16_t hFinalMecSpeedUnit)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->ParamsData[bPhase].hFinalMecSpeedUnit = hFinalMecSpeedUnit;
}
}
/**
* @brief Allow to modify targeted PWM counter pulse of a selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase where new the motor torque shall be modified.
* This parameter must be a number between 0 and 6.
* @param hFinalPulse: new targeted motor torque.
*/
__weak void RUC_SetPhaseFinalPulse(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase, uint16_t hFinalPulse)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->ParamsData[bPhase].hFinalPulse = hFinalPulse;
}
}
/*
* @brief Allow to configure a revUp phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Returns boolean set to true
*/
__weak bool RUC_SetPhase(RevUpCtrl_Handle_t *pHandle, uint8_t phaseNumber, RevUpCtrl_PhaseParams_t *phaseData)
{
bool retValue = true;
if ((MC_NULL == pHandle) || (MC_NULL == phaseData))
{
retValue = false;
}
else
{
pHandle->ParamsData[phaseNumber].hFinalPulse = phaseData->hFinalPulse;
pHandle->ParamsData[phaseNumber].hFinalMecSpeedUnit = phaseData->hFinalMecSpeedUnit;
pHandle->ParamsData[phaseNumber].hDurationms = phaseData->hDurationms;
}
return (retValue);
}
/*
* @brief Allow to read duration set in selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase from where duration is read.
* This parameter must be a number between 0 and 6.
* @retval Returns duration used in selected phase.
*/
__weak uint16_t RUC_GetPhaseDurationms(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase)
{
return ((MC_NULL == pHandle) ? 0U : (uint16_t)pHandle->ParamsData[bPhase].hDurationms);
}
/*
* @brief Allow to read targeted rotor speed set in selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase from where targeted rotor speed is read.
* This parameter must be a number between 0 and 6.
* @retval Returns targeted rotor speed set in selected phase.
*/
__weak int16_t RUC_GetPhaseFinalMecSpeedUnit(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase)
{
return ((MC_NULL == pHandle) ? 0 : (int16_t)pHandle->ParamsData[bPhase].hFinalMecSpeedUnit);
}
/**
* @brief Allow to read targeted PWM counter pulse set in selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase from where targeted motor torque is read.
* This parameter must be a number between 0 and 6.
* @retval Returns targeted motor torque set in selected phase.
*/
__weak int16_t RUC_GetPhaseFinalPulse(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase)
{
return ((MC_NULL == pHandle) ? 0 : (int16_t)pHandle->ParamsData[bPhase].hFinalPulse);
}
/*
* @brief Allow to read total number of programmed phases.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Returns number of phases relative to the programmed revup.
*/
__weak uint8_t RUC_GetNumberOfPhases(RevUpCtrl_Handle_t *pHandle)
{
return ((MC_NULL == pHandle) ? 0U : (uint8_t)pHandle->bPhaseNbr);
}
/*
* @brief Allow to read a programmed phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Returns number of phases relative to the programmed revup.
*/
__weak bool RUC_GetPhase(RevUpCtrl_Handle_t *pHandle, uint8_t phaseNumber, RevUpCtrl_PhaseParams_t *phaseData)
{
bool retValue = true;
if ((MC_NULL == pHandle) || (MC_NULL == phaseData))
{
retValue = false;
}
else
{
phaseData->hFinalPulse = (int16_t)pHandle->ParamsData[phaseNumber].hFinalPulse;
phaseData->hFinalMecSpeedUnit = (int16_t)pHandle->ParamsData[phaseNumber].hFinalMecSpeedUnit;
phaseData->hDurationms = (uint16_t)pHandle->ParamsData[phaseNumber].hDurationms;
}
return (retValue);
}
/**
* @brief Allow to read spinning direction of the motor
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Returns direction of the motor.
*/
__weak int16_t RUC_GetDirection(RevUpCtrl_Handle_t *pHandle)
{
return ((MC_NULL == pHandle) ? 0U : (int16_t)pHandle->hDirection);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 17,712 | C | 30.184859 | 114 | 0.656786 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/data_scope.c | /**
******************************************************************************
* @file data_scope.c
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* data_scope.c */
#include "data_scope.h"
#include <string.h> // memset
/* ToDo:
* Conversion and scaling;
* Source is IQ24, IQ15, IQ30 etc.
* Current scaling
* IQ_PU_A to 1V/A, 0.1V/A, 0.01V/A etc.
* User sets preference in some scale that makes sense
* 1V/Nm, 1V/VpHz
*
*/
/* Responsibilities:
* Offset, scale. Compensate for DAC board deviations
* (This module was first developed for DAC output, and this functionality is left in)
* Signal selection
* Whole group select, 4 channels at once
* Individual channel selection
* Scale selection
* 1V/Nm, 0.1V/Nm etc for torques
* 1V/VpHz for flux
* Scale-up, scale-down impulse, like encoder knob on oscilloscope
* Natural scale, not per unit
* Per unit to A, 1V/A etc.
* (1V/<unit> terminology is a legacy of the DAC output)
* Excluded:
* Meta-data
* Is defined in another module, which is application-specific. DATA_SCOPE is a more general module.
*/
/* Implementation:
* _run function
* performs scaling using current offset, scale factors
* uses current input values, pointer to struct parameter input
* does not do floats (?) (maybe FPU on only?)
* choice:
* Should this lookup data in memory? (internal selection?
* Must know data then?
* Or location, type etc of data
* Should this be given data from outside (outside selection)
* Channel select is external then [So No]
*
* Option:
* Channel has
* Source location (void*)
* Numerical type (uint16, int32 etc)
* Data type (A_PU, FLUX_PU, V_PU etc)
* Scaling from internal Per Unit to usable units)
* Data scale (iqFmt)
* Scope scale (1V/U, 10V/U, 0.1V/U etc)
* 1x, 2x, 5x, 10x, 20x, 50x, 100x, 0.5x, 0.2x, 0.1x etc
* Ranges?
*
*/
/* Internal function declarations */
/* Initialization functions */
DATA_SCOPE_Handle DATA_SCOPE_init(void* pMemory, const size_t numWords)
{
DATA_SCOPE_Handle handle = (DATA_SCOPE_Handle) 0;
if (numWords >= sizeof(DATA_SCOPE_Obj))
{
handle = (DATA_SCOPE_Handle) pMemory;
memset(pMemory, 0, numWords);
}
return handle;
} /* end of DATA_SCOPE_init() function */
void DATA_SCOPE_setup(DATA_SCOPE_Handle handle)
{
DATA_SCOPE_Obj* obj = (DATA_SCOPE_Obj*) handle;
DATA_SCOPE_CHANNEL_s* pChannel = 0;
int i;
for (i = 0; i < DATA_SCOPE_NUMCHANNELS; i++)
{
pChannel = &obj->channel[i];
/* Disable channel */
pChannel->enabled = false;
/* Set scale and offset to defaults */
pChannel->dac_scale = FIXP16(0.1);
pChannel->dac_offset = FIXP16(0.5);
pChannel->data_scale_f = 0.0f;
DATA_SCOPE_setChannelDataScale(handle, i, 1.0f);
}
return;
} /* end of DATA_SCOPE_setup() function */
/* Functional */
void DATA_SCOPE_run(DATA_SCOPE_Handle handle)
{
DATA_SCOPE_Obj* obj = (DATA_SCOPE_Obj*) handle;
DATA_SCOPE_CHANNEL_s* pChannel = 0;
int i;
for (i = 0; i < DATA_SCOPE_NUMCHANNELS; i++)
{
pChannel = &obj->channel[i];
if (pChannel->enabled)
{
// Read data from RAM
uint16_t dac_value = 0;
switch (pChannel->datatype)
{
case DATA_DATATYPE_Int32:
{
/* Read value, in native scale unit */
fixp_t value = *((fixp_t*)(pChannel->pData));
/* Multiply by data_scale, which is in FIXP(V/unit) */
value = FIXP_mpyFIXPscaled(value, &pChannel->data_scale_fixps);
// data_qFmt is taken into account in setChannelDataScale
pChannel->data_fixp24_volt = value;
/* Saturate to +/- 5V */
value = FIXP_sat(value, FIXP(5.0), FIXP(-5.0));
/* Scale to DAC scaling */
value = FIXP_mpy(value, pChannel->dac_scale);
/* Adjust for offset */
value -= pChannel->dac_offset;
/* Limit to full scale */
// value = FIXP_sat(value, 0xFFFF, 0);
#warning Issue here is likely that value is signed, and 0xFFFF is unsigned?
dac_value = (uint16_t) value;
}
break;
}
// Store
pChannel->dac_value = dac_value;
}
}
return;
} /* end of DATA_SCOPE_run() function */
uint16_t DATA_SCOPE_getSingleChannelValue(DATA_SCOPE_Handle handle, uint16_t channel)
{
DATA_SCOPE_Obj* obj = (DATA_SCOPE_Obj*) handle;
DATA_SCOPE_CHANNEL_s* pChannel = &obj->channel[channel];
uint16_t value = pChannel->dac_offset;
if (pChannel->enabled) value = pChannel->dac_value;
return (value);
} /* end of DATA_SCOPE_getSingleChannelValue() function */
void DATA_SCOPE_setChannelDacScaleAndOffset(DATA_SCOPE_Handle handle, const uint16_t channel, const fixp15_t scale, const fixp15_t offset)
{
DATA_SCOPE_Obj* obj = (DATA_SCOPE_Obj*) handle;
DATA_SCOPE_CHANNEL_s* pChannel = &obj->channel[channel];
pChannel->dac_scale = scale;
pChannel->dac_offset = offset;
return;
} /* end of DATA_SCOPE_setChannelDacScaleAndOffset() function */
void DATA_SCOPE_setChannelDataScale(DATA_SCOPE_Handle handle, const uint16_t channel, const float dataScale)
{
DATA_SCOPE_Obj* obj = (DATA_SCOPE_Obj*) handle;
DATA_SCOPE_CHANNEL_s* pChannel = &obj->channel[channel];
/* Only update if the data scale has actually changed */
if (pChannel->data_scale_f == dataScale) return;
/* Remember the new data scale */
pChannel->data_scale_f = dataScale;
float ds = 1.0f / dataScale;
FIXPSCALED_calculateScaleFactor(pChannel->data_qFmt, 24, pChannel->data_fullscale, 1.0f, ds, &pChannel->data_scale_fixps);
return;
}
/* Internal functions */
/* end of data_scope.c */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 6,952 | C | 28.841202 | 138 | 0.567319 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pid_regulator.c | /**
******************************************************************************
* @file pid_regulator.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the PID regulator component of the Motor Control SDK.
*
* The PID regulator component provides the functions needed to implement
* a proportional–integral–derivative controller.
*
* See @link PIDRegulator @endlink for more details.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup PIDRegulator
*/
/* Includes ------------------------------------------------------------------*/
#include "pid_regulator.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/**
* @defgroup PIDRegulator PID Regulator
* @brief PID Regulator component of the Motor Control SDK
*
* The PID regulator component implements the following two control functions:
*
* * A simple proportional-integral controller, implemented by the PI_Controller() function:
* @f[
* r(t_k) = K_p \times \epsilon(t_k) + K_i \times \sum_{j=0}^k\epsilon(t_j)
* @f]
* * A complete proportional–integral–derivative controller, implemented by the PID_Controller() function:
* @f[
* r(t_k) = K_p \times \epsilon(t_k) + K_i \times \sum_{j=0}^k\epsilon(t_j) + K_d \times (\epsilon(t_k) - \epsilon(t_{k-1}))
* @f]
*
* The proportional, integral and derivative gains are expressed as rational numbers, with a gain (numerator)
* and a divisor (denominator) parameters:
*
* * Proportional gain: @f$ K_{p} = K_{pg} / K_{pd} @f$
* * Integral gain: @f$ K_{i} = K_{ig} / K_{id} @f$
* * Derivative gain: @f$ K_{d} = K_{dg} / K_{dd} @f$
*
* Each of the gain numerator and divisor parameters, @f$K_{{p}g}@f$, @f$K_{{i}g}@f$, @f$K_{{d}g}@f$, @f$K_{{p}d}@f$,
* @f$K_{id}@f$, @f$K_{dd}@f$, can be set, at run time and independently, via the PID_SetKP(), PID_SetKI(), PID_SetKD(),
* PID_SetKPDivisorPOW2(), PID_SetKIDivisorPOW2() and PID_SetKDDivisorPOW2() functions, respectively.
*
* A PID Regulator component needs to be initialized before it can be used. This is done with the PID_HandleInit()
* function that sets the intergral term and the derivative term base (the previous value of the process error input)
* to 0 and that also resets the numerators of the proportional, integral and derivative gains to their default values.
* These default values are literally written in the code of the application, so they are set at compile time. They
* can be retrieved with the PID_GetDefaultKP(), PID_GetDefaultKI() and PID_GetDefaultKD() functions.
*
* The controller functions implemented by the PI_Controller() and the PID_Controller() functions are based on 16-bit
* integer arithmetics: the gains are expressed as fractional numbers, with 16-bit numerators and denominators. And the
* controller output values returned by these functions are also 16-bit integers. This makes it possible to use this
* component efficiently on all STM2 MCUs.
*
* To keep the computed values within limits, the component features the possibility to constrain the integral term
* within a range of values bounded by the PID_SetLowerIntegralTermLimit() and PID_SetUpperIntegralTermLimit() functions.
*
* The output valud of the controller can also be bounded between a high and a low limit thanks to the
* PID_SetLowerOutputLimit() and PID_SetUpperOutputLimit() functions.
*
* Hanlding a process with a PID Controller may require some adjustment to cope with specific situations. To that end, the
* PID regulator component provides functions to set the integral term (PID_SetIntegralTerm()) or to set the value of the
* previous process error (PID_SetPrevError()).
*
* See the [PID chapter of the User Manual](PID_regulator_theoretical_background.md) for more details on the theoretical
* background of this regulator.
* @{
*/
/**
* @brief Initializes the handle of a PID component
* @param pHandle A Handle on the PID component to initialize
*
* The integral term and the derivative base of the PID component are
* set to zero.
*
* The numerators of the proportional, integral and derivative gains
* are set to their default values. These default values are the ones
* set to the PID_Handle_t::hDefKpGain, PID_Handle_t::hDefKiGain and
* PID_Handle_t::hDefKdGain fields of the PID_Handle_t structure.
*/
__weak void PID_HandleInit(PID_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hKpGain = pHandle->hDefKpGain;
pHandle->hKiGain = pHandle->hDefKiGain;
pHandle->hKdGain = pHandle->hDefKdGain;
pHandle->wIntegralTerm = 0;
pHandle->wPrevProcessVarError = 0;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Sets @f$K_{pg}@f$, the numerator of the proportional gain of a PID component
* @param pHandle Handle on the PID component
* @param hKpGain New @f$K_{pg}@f$ value
*/
__weak void PID_SetKP(PID_Handle_t *pHandle, int16_t hKpGain)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hKpGain = hKpGain;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Sets the @f$K_{ig}@f$, the numrerator of the integral gain of a PID component
* @param pHandle Handle on the PID component
* @param hKiGain new @f$K_{ig}@f$ value
*/
__weak void PID_SetKI(PID_Handle_t *pHandle, int16_t hKiGain)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hKiGain = hKiGain;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Returns @f$K_{pg}@f$, the numerator of the proportional gain of a PID component
* @param pHandle Handle on the PID component
*/
__weak int16_t PID_GetKP(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0 : pHandle->hKpGain);
#else
return (pHandle->hKpGain);
#endif
}
/**
* @brief Returns @f$K_{ig}@f$, the numrerator of the integral gain of a PID component
* @param pHandle Handle on the PID component
*/
__weak int16_t PID_GetKI(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0 : pHandle->hKiGain);
#else
return (pHandle->hKiGain);
#endif
}
/**
* @brief Returns the default @f$K_{pg}@f$ value, the numerator of the proportional
* gain of a PID component
* @param pHandle Handle on the PID component
*
* The default @f$K_{pg}@f$ value is the one that is being used at startup time,
* when the MCU is reset or when the PID_HandleInit() function gets called. When
* any of the last two event occurs, any proportional gain numerator that may
* have been previously set with the PID_SetKP() function is replaced by this
* default value.
*/
__weak int16_t PID_GetDefaultKP(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0 : pHandle->hDefKpGain);
#else
return (pHandle->hDefKpGain);
#endif
}
/**
* @brief Returns the default @f$K_{ig}@f$ value, the numerator of the integral
* gain of a PID component
* @param pHandle Handle on the PID component
*
* The default @f$K_{ig}@f$ value is the one that is being used at startup time,
* when the MCU is reset or when the PID_HandleInit() function gets called. When
* any of the last two event occurs, any gain that may have been previously set
* with the PID_SetKI() function is replaced by this default value.
*/
__weak int16_t PID_GetDefaultKI(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0 : pHandle->hDefKiGain);
#else
return (pHandle->hDefKiGain);
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Sets the value of the integral term of a PID component
* @param pHandle Handle on the PID component
* @param wIntegralTermValue new integral term value multiplied by the divisor
* of the integral gain
*
* If @f$T_{i}@f$ is the target integral term, the @p wIntegralTermValue term is stored
* before the division by @f$K_{id}@f$ to maximize the available dynamics.
*
* @attention @p wIntegralTermValue divided by @f$K_{id}@f$ must fit in a 16-bit signed
* integer value.
*/
__weak void PID_SetIntegralTerm(PID_Handle_t *pHandle, int32_t wIntegralTermValue)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->wIntegralTerm = wIntegralTermValue;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
return;
}
/**
* @brief Returns @f$K_{pd}@f$, the divisor of the proportional gain of a PID component
* @param pHandle Handle on the PID component
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* @sa PID_GetKPDivisorPOW2()
*/
__weak uint16_t PID_GetKPDivisor(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0U : pHandle->hKpDivisor);
#else
return (pHandle->hKpDivisor);
#endif
}
/**
* @brief Returns the power of two that makes @f$K_{pd}@f$, the divisor of the proportional
* gain of a PID component
* @param pHandle Handle on the PID component
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* @sa PID_GetKPDivisor()
*/
__weak uint16_t PID_GetKPDivisorPOW2(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0U : pHandle->hKpDivisorPOW2);
#else
return (pHandle->hKpDivisorPOW2);
#endif
}
/**
* @brief Sets the power of two that makes @f$K_{pd}@f$, the divisor of the proportional gain
* of a PID component
* @param pHandle Handle on the PID component
* @param hKpDivisorPOW2 new @f$K_{pd}@f$ divisor value, expressed as power of 2
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* This function sets @f$K_{pd}@f$ to 2 to the power of @p hKpDivisorPOW2.
*/
__weak void PID_SetKPDivisorPOW2(PID_Handle_t *pHandle, uint16_t hKpDivisorPOW2)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hKpDivisorPOW2 = hKpDivisorPOW2;
pHandle->hKpDivisor = (((uint16_t)1) << hKpDivisorPOW2);
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Returns @f$K_{id}@f$, the divisor of the integral gain of a PID component
* @param pHandle Handle on the PID component
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* @sa PID_GetKIDivisorPOW2()
*/
__weak uint16_t PID_GetKIDivisor(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0U : pHandle->hKiDivisor);
#else
return (pHandle->hKiDivisor);
#endif
}
/**
* @brief Returns the power of two that makes @f$K_{id}@f$, the divisor of the integral
* gain of a PID component
* @param pHandle Handle on the PID component
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* @sa PID_GetKIDivisor()
*/
__weak uint16_t PID_GetKIDivisorPOW2(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0U : pHandle->hKiDivisorPOW2);
#else
return (pHandle->hKiDivisorPOW2);
#endif
}
/**
* @brief Sets the power of two that makes @f$K_{id}@f$, the divisor of the integral gain
* of a PID component
* @param pHandle Handle on the PID component
* @param hKiDivisorPOW2 new @f$K_{id}@f$ divisor value, expressed as power of 2
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* This function sets @f$K_{id}@f$ to 2 to the power of @p hKiDivisorPOW2.
*
* Note that the upper and lower limits of the integral term are also updated to
* accept any 16-bit value. If the limits of the integral term need to be different
* use the PID_SetUpperIntegralTermLimit() and PID_SetLowerIntegralTermLimit() functions
* after this one.
*/
__weak void PID_SetKIDivisorPOW2(PID_Handle_t *pHandle, uint16_t hKiDivisorPOW2)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
uint32_t wKiDiv = (((uint32_t)1) << hKiDivisorPOW2);
pHandle->hKiDivisorPOW2 = hKiDivisorPOW2;
pHandle->hKiDivisor = (uint16_t)wKiDiv;
PID_SetUpperIntegralTermLimit(pHandle, (int32_t)INT16_MAX * (int32_t)wKiDiv);
PID_SetLowerIntegralTermLimit(pHandle, (int32_t)(-INT16_MAX) * (int32_t)wKiDiv);
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Sets the lower limit of the integral term of a PID component
*
* @param pHandle Handle on the PID component
* @param wLowerLimit new lower integral term limit multiplied by the divisor
* of the integral gain
*
* If @f$T_{iL}@f$ is the target lower limit, the @p wLowerLimit parameter must
* be set to @f$T_{iL}\times K_{id}@f$. This is because the limit is checked before
* applying the divisor in the PI_Controller() and PID_Controller() controller
* functions.
*
* When the PI or PID controller is executed, the value of the integral term is floored
* to this value.
*
* @attention @p wLowerLimit divided by @f$K_{id}@f$ must fit in a 16-bit signed
* integer value.
*/
__weak void PID_SetLowerIntegralTermLimit(PID_Handle_t *pHandle, int32_t wLowerLimit)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->wLowerIntegralLimit = wLowerLimit;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Sets the upper limit of the integral term of a PID component
*
* @param pHandle Handle on the PID component
* @param wUpperLimit new upper integral term limit multiplied by the divisor
* of the integral gain
*
* If @f$T_{iU}@f$ is the target upper limit, the @p wUpperLimit parameter must
* be set to @f$T_{iU}\times K_{id}@f$. This is because the limit is checked before
* applying the divisor in the PI_Controller() and PID_Controller() controller
* functions.
*
* When the controller is executed, the value of the integral term is capped to
* this value.
*
* @attention @p wUpperLimit divided by @f$K_{id}@f$ must fit in a 16-bit signed
* integer value.
*/
__weak void PID_SetUpperIntegralTermLimit(PID_Handle_t *pHandle, int32_t wUpperLimit)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->wUpperIntegralLimit = wUpperLimit;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Sets the lower output limit of a PID component
*
* @param pHandle Handle on the PID component
* @param hLowerLimit new lower limit of the output value
*
* When the controller is executed, the value of its output is floored to this value.
*/
__weak void PID_SetLowerOutputLimit(PID_Handle_t *pHandle, int16_t hLowerLimit)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hLowerOutputLimit = hLowerLimit;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Sets the upper output limit of a PID component
*
* @param pHandle Handle on the PID component
* @param hUpperLimit: new upper limit of the output value
*
* When the controller is executed, the value of its output is capped to this value.
*/
__weak void PID_SetUpperOutputLimit(PID_Handle_t *pHandle, int16_t hUpperLimit)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hUpperOutputLimit = hUpperLimit;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Sets the value of the previous process error of a PID component
*
* @param pHandle Handle on the PID component
* @param wPrevProcessVarError new value of the previous error variable
*/
__weak void PID_SetPrevError(PID_Handle_t *pHandle, int32_t wPrevProcessVarError)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->wPrevProcessVarError = wPrevProcessVarError;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
return;
}
/**
* @brief Sets @f$K_{dg}@f$, the numerator of the derivative gain of a PID component
* @param pHandle Handle on the PID component
* @param hKpGain New @f$K_{dg}@f$ value
*/
__weak void PID_SetKD(PID_Handle_t *pHandle, int16_t hKdGain)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hKdGain = hKdGain;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
/**
* @brief Returns @f$K_{dg}@f$, the numerator of the derivative gain of a PID component
* @param pHandle Handle on the PID component
*/
__weak int16_t PID_GetKD(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0 : pHandle->hKdGain);
#else
return (pHandle->hKdGain);
#endif
}
/**
* @brief Returns @f$K_{dd}@f$, the divisor of the derivative gain of a PID component
* @param pHandle Handle on the PID component
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* @sa PID_GetKDDivisorPOW2()
*/
__weak uint16_t PID_GetKDDivisor(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0U : pHandle->hKdDivisor);
#else
return (pHandle->hKdDivisor);
#endif
}
/**
* @brief Returns the power of two that makes @f$K_{dd}@f$, the divisor of the derivative
* gain of a PID component
* @param pHandle Handle on the PID component
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* @sa PID_GetKDDivisor()
*/
__weak uint16_t PID_GetKDDivisorPOW2(PID_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_PID_REG
return ((MC_NULL == pHandle) ? 0U : pHandle->hKdDivisorPOW2);
#else
return (pHandle->hKdDivisorPOW2);
#endif
}
/**
* @brief Sets the power of two that makes @f$K_{dd}@f$, the divisor of the derivative gain
* of a PID component
* @param pHandle Handle on the PID component
* @param hKdDivisorPOW2 new @f$K_{dd}@f$ divisor value, expressed as power of 2
*
* The divisors that make the gains of the @ref PIDRegulator "PID regulator component" are
* powers of two.
*
* This function sets @f$K_{dd}@f$ to 2 to the power of @p hKdDivisorPOW2.
*/
__weak void PID_SetKDDivisorPOW2(PID_Handle_t *pHandle, uint16_t hKdDivisorPOW2)
{
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hKdDivisorPOW2 = hKdDivisorPOW2;
pHandle->hKdDivisor = (((uint16_t)1) << hKdDivisorPOW2);
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Computes the output of a PI Regulator component, sum of its proportional and
* integral terms
*
* @param pHandle Handle on the PID component
* @param wProcessVarError current process variable error (the reference value minus the
* present process variable value)
* @retval computed PI controller output
*
* This function implements the proportional-integral controller function described by the
* @ref PIDRegulator "PID regulator component". The integral term is saturated by the upper
* and lower intergral term limit values before it is added to the proportional term.
*
* The resulting value is then saturated by the upper and lower output limit values before
* being returned.
*/
__weak int16_t PI_Controller(PID_Handle_t *pHandle, int32_t wProcessVarError)
{
int16_t returnValue;
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
returnValue = 0;
}
else
{
#endif
int32_t wProportional_Term;
int32_t wIntegral_Term;
int32_t wOutput_32;
int32_t wIntegral_sum_temp;
int32_t wDischarge = 0;
int16_t hUpperOutputLimit = pHandle->hUpperOutputLimit;
int16_t hLowerOutputLimit = pHandle->hLowerOutputLimit;
/* Proportional term computation*/
wProportional_Term = pHandle->hKpGain * wProcessVarError;
/* Integral term computation */
if (0 == pHandle->hKiGain)
{
pHandle->wIntegralTerm = 0;
}
else
{
wIntegral_Term = pHandle->hKiGain * wProcessVarError;
wIntegral_sum_temp = pHandle->wIntegralTerm + wIntegral_Term;
if (wIntegral_sum_temp < 0)
{
if (pHandle->wIntegralTerm > 0)
{
if (wIntegral_Term > 0)
{
wIntegral_sum_temp = INT32_MAX;
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
}
else
{
if (pHandle->wIntegralTerm < 0)
{
if (wIntegral_Term < 0)
{
wIntegral_sum_temp = -INT32_MAX;
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
}
if (wIntegral_sum_temp > pHandle->wUpperIntegralLimit)
{
pHandle->wIntegralTerm = pHandle->wUpperIntegralLimit;
}
else if (wIntegral_sum_temp < pHandle->wLowerIntegralLimit)
{
pHandle->wIntegralTerm = pHandle->wLowerIntegralLimit;
}
else
{
pHandle->wIntegralTerm = wIntegral_sum_temp;
}
}
#ifndef FULL_MISRA_C_COMPLIANCY_PID_REGULATOR
/* WARNING: the below instruction is not MISRA compliant, user should verify
that Cortex-M3 assembly instruction ASR (arithmetic shift right)
is used by the compiler to perform the shifts (instead of LSR
logical shift right)*/
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
wOutput_32 = (wProportional_Term >> pHandle->hKpDivisorPOW2) + (pHandle->wIntegralTerm >> pHandle->hKiDivisorPOW2);
#else
wOutput_32 = (wProportional_Term / (int32_t)pHandle->hKpDivisor)
+ (pHandle->wIntegralTerm / (int32_t)pHandle->hKiDivisor);
#endif
if (wOutput_32 > hUpperOutputLimit)
{
wDischarge = hUpperOutputLimit - wOutput_32;
wOutput_32 = hUpperOutputLimit;
}
else if (wOutput_32 < hLowerOutputLimit)
{
wDischarge = hLowerOutputLimit - wOutput_32;
wOutput_32 = hLowerOutputLimit;
}
else
{
/* Nothing to do here */
}
pHandle->wIntegralTerm += wDischarge;
returnValue = (int16_t)wOutput_32;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
return (returnValue);
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Computes the output of a PID Regulator component, sum of its proportional,
* integral and derivative terms
*
* @param pHandle Handle on the PID component
* @param wProcessVarError current process variable error (the reference value minus the
* present process variable value)
* @retval computed PID controller output
*
* This function implements the proportional-integral-derivative controller function described
* by the @ref PIDRegulator "PID regulator component". The integral term is saturated by
* the upper and lower intergral term limit values before it is added to the proportional term
* and derivative terms.
*
* The resulting value is then saturated by the upper and lower output limit values before
* being returned.
*/
__weak int16_t PID_Controller(PID_Handle_t *pHandle, int32_t wProcessVarError)
{
int16_t returnValue;
#ifdef NULL_PTR_CHECK_PID_REG
if (MC_NULL == pHandle)
{
returnValue = 0;
}
else
{
#endif
int32_t wDifferential_Term;
int32_t wDeltaError;
int32_t wTemp_output;
if (0 == pHandle->hKdGain) /* derivative terms not used */
{
wTemp_output = PI_Controller(pHandle, wProcessVarError);
}
else
{
wDeltaError = wProcessVarError - pHandle->wPrevProcessVarError;
wDifferential_Term = pHandle->hKdGain * wDeltaError;
#ifndef FULL_MISRA_C_COMPLIANCY_PID_REGULATOR
/* WARNING: the below instruction is not MISRA compliant, user should verify
that Cortex-M3 assembly instruction ASR (arithmetic shift right)
is used by the compiler to perform the shifts (instead of LSR
logical shift right)*/
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
wDifferential_Term >>= pHandle->hKdDivisorPOW2;
#else
wDifferential_Term /= ((int32_t)pHandle->hKdDivisor);
#endif
pHandle->wPrevProcessVarError = wProcessVarError;
wTemp_output = PI_Controller(pHandle, wProcessVarError) + wDifferential_Term;
if (wTemp_output > pHandle->hUpperOutputLimit)
{
wTemp_output = pHandle->hUpperOutputLimit;
}
else if (wTemp_output < pHandle->hLowerOutputLimit)
{
wTemp_output = pHandle->hLowerOutputLimit;
}
else
{
/* Nothing to do */
}
}
returnValue = (int16_t) wTemp_output;
#ifdef NULL_PTR_CHECK_PID_REG
}
#endif
return (returnValue);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 26,857 | C | 29.835821 | 125 | 0.657743 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/mcptl.c | /**
******************************************************************************
* @file mcptl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief
*
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
#include "mcptl.h"
bool MCTL_decodeCRCData(MCTL_Handle_t *pHandle)
{
return (true);
}
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 919 | C | 28.677418 | 80 | 0.452666 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/profiler_fluxestim.c | /**
******************************************************************************
* @file profiler_fluxestim.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions of profiler
* component
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*
*/
/* Includes ------------------------------------------------------------------*/
#include "profiler_fluxestim.h"
void PROFILER_FLUXESTIM_stateMachine(PROFILER_FLUXESTIM_Handle handle, MOTOR_Handle motor);
/**
* @brief todo
*/
void PROFILER_FLUXESTIM_init(PROFILER_FLUXESTIM_Handle handle)
{
handle->state = PROFILER_FLUXESTIM_STATE_Idle;
}
/**
* @brief todo
*/
void PROFILER_FLUXESTIM_setParams(PROFILER_FLUXESTIM_Handle handle, PROFILER_Params* pParams)
{
/* Scaling */
handle->fullScaleVoltage_V = pParams->fullScaleVoltage_V;
handle->fullScaleCurrent_A = pParams->fullScaleCurrent_A;
handle->fullScaleFreq_Hz = pParams->fullScaleFreq_Hz;
/* Number of medium frequency task cycles in the dc measurement time */
handle->background_rate_hz = pParams->background_rate_hz;
PROFILER_FLUXESTIM_setMeasurementTime(handle, pParams->fluxestim_measurement_time_s);
handle->CurToRamp_sf_pu = FIXP30(1.0f / pParams->fluxestim_current_ramping_time_s / pParams->background_rate_hz);
handle->FreqToRamp_sf_pu = FIXP30(1.0f / pParams->fluxestim_speed_ramping_time_s / pParams->background_rate_hz);
/* Current setpoint */
handle->Id_ref_pu = FIXP30(pParams->fluxestim_Idref_A / pParams->fullScaleCurrent_A);
/* Flux estimation frequency */
PROFILER_FLUXESTIM_setFluxEstFreq_Hz(handle, pParams->fluxestim_speed_Hz);
/* Ramp rate */
handle->ramp_rate_freq_pu_per_cycle = FIXP30_mpy(handle->FluxEstFreq_pu, handle->FreqToRamp_sf_pu);
handle->ramp_rate_A_pu_per_cycle = FIXP30_mpy(handle->Id_ref_pu, handle->CurToRamp_sf_pu);
handle->voltagefilterpole_rps = pParams->voltagefilterpole_rps;
handle->glue_dcac_fluxestim_on = pParams->glue_dcac_fluxestim_on;
/* tune fluxEstimPole to 1/7 of measurement time to get 0.999 expectation ratio */
handle->fluxEstimPoleTs = FIXP30(7.0f /(pParams->fluxestim_measurement_time_s * pParams->background_rate_hz));
}
/**
* @brief todo
*/
void PROFILER_FLUXESTIM_run(PROFILER_FLUXESTIM_Handle handle, MOTOR_Handle motor)
{
/* This function is called from the high frequency task / motor control interrupt */
/* After Sensorless and CurrentControl, so the DQ-values are available */
}
/**
* @brief todo
*/
void PROFILER_FLUXESTIM_runBackground(PROFILER_FLUXESTIM_Handle handle, MOTOR_Handle motor)
{
/* This function is called from the medium frequency task */
/* Counter counts down */
if (handle->counter > 0) handle->counter--;
switch (handle->state)
{
case PROFILER_FLUXESTIM_STATE_Idle:
handle->flux_Wb = FIXP30(0.0f); /* clear flux filter before new estimate */
break;
/* Current ramping */
case PROFILER_FLUXESTIM_STATE_RampUpCur:
{
fixp30_t ramp_rate = handle->ramp_rate_A_pu_per_cycle;
fixp30_t delta_pu = handle->Id_ref_pu - motor->pSTC->Idq_ref_pu.D; /* delta = target - current */
motor->pSTC->Idq_ref_pu.D += FIXP_sat(delta_pu, ramp_rate, -ramp_rate);
}
break;
case PROFILER_FLUXESTIM_STATE_RampUpFreq:
{
fixp30_t ramp_rate = handle->ramp_rate_freq_pu_per_cycle;
fixp30_t delta_pu = handle->FluxEstFreq_pu - motor->pSTC->speed_ref_pu; /* delta = target - current */
motor->pSTC->speed_ref_pu += FIXP_sat(delta_pu, ramp_rate, -ramp_rate);
}
break;
case PROFILER_FLUXESTIM_STATE_FluxRefAuto:
{
/* read and filter actual flux amplitude and copy to reference value: equilibrium will be found, use 7tau for accuracy */
handle->flux_Wb += FIXP30_mpy((HSO_getFluxAmpl_Wb(motor->pSPD->pHSO) - handle->flux_Wb), handle->fluxEstimPoleTs);
HSO_setFluxRef_Wb(motor->pSPD->pHSO, handle->flux_Wb);
/* Update user visible rated flux */
motor->pFocVars->Flux_Rated_VpHz = FIXP30_mpy(handle->flux_Wb, FIXP(M_TWOPI));
}
break;
case PROFILER_FLUXESTIM_STATE_RampDownFreq:
{
fixp30_t ramp_rate = handle->ramp_rate_freq_pu_per_cycle;
fixp30_t delta_pu = 0 - motor->pSTC->speed_ref_pu; /* delta = target - present */
motor->pSTC->speed_ref_pu += FIXP_sat(delta_pu, ramp_rate, -ramp_rate);
}
break;
case PROFILER_FLUXESTIM_STATE_RampDownCur:
{
fixp30_t ramp_rate = handle->ramp_rate_A_pu_per_cycle;
fixp30_t delta_pu = 0 - motor->pSTC->Idq_ref_pu.D; /* delta = target - current */
motor->pSTC->Idq_ref_pu.D += FIXP_sat(delta_pu, ramp_rate, -ramp_rate);
}
break;
case PROFILER_FLUXESTIM_STATE_Error:
break;
case PROFILER_FLUXESTIM_STATE_Complete:
break;
}
PROFILER_FLUXESTIM_stateMachine(handle, motor);
}
/**
* @brief todo
*/
void PROFILER_FLUXESTIM_reset(PROFILER_FLUXESTIM_Handle handle, MOTOR_Handle motor)
{
handle->state = PROFILER_FLUXESTIM_STATE_Idle;
handle->error = PROFILER_FLUXESTIM_ERROR_None;
motor->pSTC->Idq_ref_pu.D = 0;
motor->pSTC->Idq_ref_pu.Q = 0;
motor->pSTC->speed_ref_pu = 0;
}
/**
* @brief todo
*/
void PROFILER_FLUXESTIM_stateMachine(PROFILER_FLUXESTIM_Handle handle, MOTOR_Handle motor)
{
PROFILER_FLUXESTIM_State_e state = handle->state;
PROFILER_FLUXESTIM_State_e newState = state;
switch (state)
{
case PROFILER_FLUXESTIM_STATE_Idle:
/* Only called when profiler active */
/* Set motor to required state */
{
/* Open loop current mode */
motor->pSTC->SpeedControlEnabled = false;
motor->pCurrCtrl->currentControlEnabled = true;
motor->pSPD->closedLoopAngleEnabled = false;
motor->pCurrCtrl->forceZeroPwm = false;
if (handle->glue_dcac_fluxestim_on == false)
{
motor->pCurrCtrl->Ddq_ref_pu.D = 0;
}
motor->pCurrCtrl->Ddq_ref_pu.Q = 0;
motor->pSTC->speedref_source = FOC_SPEED_SOURCE_Default;
motor->pSTC->speed_ref_active_pu = 0;
motor->pSTC->speed_ref_ramped_pu = 0;
motor->pSTC->speed_ref_pu = FIXP30(0.0f);
motor->pSPD->zestControl.enableControlUpdate = false; /* Disable MC_ZEST_Control_Update() */
motor->pSPD->flagHsoAngleEqualsOpenLoopAngle = false; /* enable hso to follow EMF */
ZEST_setInjectMode(motor->pSPD->pZeST, ZEST_INJECTMODE_None);
if (handle->glue_dcac_fluxestim_on)
{
motor->pSTC->Idq_ref_pu.D = motor->pCurrCtrl->Idq_in_pu.D; /* Copy present current to reference */
PIDREGDQX_CURRENT_setUiD_pu(&motor->pCurrCtrl->pid_IdIqX_obj,motor->pCurrCtrl->Ddq_ref_pu.D); /* Copy present duty to current controller integrator */
}
}
{
float_t myfreq = 100.0f; /* Set Flux observer cross-over frequency */
HSO_setMinCrossOver_Hz(motor->pSPD->pHSO, myfreq);
HSO_setMaxCrossOver_Hz(motor->pSPD->pHSO, myfreq);
handle->flux_Wb = FIXP30(0.0f); /* Set Ref-flux to zero before speed rampup */
HSO_setFluxRef_Wb(motor->pSPD->pHSO, handle->flux_Wb);
}
newState = PROFILER_FLUXESTIM_STATE_RampUpCur;
break;
case PROFILER_FLUXESTIM_STATE_RampUpCur:
/* open-loop current mode */
if (motor->pSTC->Idq_ref_pu.D == handle->Id_ref_pu)
{
motor->pSTC->I_max_pu = FIXP24_mpy(handle->Id_ref_pu, FIXP24(2.0f));
newState = PROFILER_FLUXESTIM_STATE_RampUpFreq;
}
break;
case PROFILER_FLUXESTIM_STATE_RampUpFreq:
{
Voltages_Uab_t Uab = motor->pPWM->Uab_in_pu;
fixp30_t Umag = FIXP_mag(Uab.A, Uab.B);
/* ramp speed up till set frequency or 50% of available duty */
if ((motor->pSTC->speed_ref_pu == handle->FluxEstFreq_pu) || (Umag > (motor->pVBus->Udcbus_in_pu >> 2)))
{
/* Prepare the Flux measurement */
handle->freqEst_pu = motor->pSTC->speed_ref_pu; //copy actual OL speed
/* set new Flux observer cross-over frequency was 100Hz up to now*/
float_t myfreq = 2 * FIXP30_toF(handle->freqEst_pu) * handle->fullScaleFreq_Hz;
HSO_setMinCrossOver_Hz(motor->pSPD->pHSO, myfreq);
HSO_setMaxCrossOver_Hz(motor->pSPD->pHSO, myfreq);
handle->counter = handle->measurement_counts;
newState = PROFILER_FLUXESTIM_STATE_FluxRefAuto;
}
}
break;
case PROFILER_FLUXESTIM_STATE_FluxRefAuto:
if (handle->counter == 0)
{
handle->freqHSO_pu = HSO_getSpeedLP_pu(motor->pSPD->pHSO); //copy actual HSO speed
fixp30_t freqHSO = FIXP_abs(handle->freqHSO_pu);
fixp30_t freqRef = FIXP_abs(handle->freqEst_pu);
if ((freqHSO < FIXP_mpy(freqRef, FIXP(0.60))) || (freqHSO > FIXP_mpy(freqRef, FIXP(1.50))))
{
handle->error = PROFILER_FLUXESTIM_ERROR_FluxNotValid;
}
newState = PROFILER_FLUXESTIM_STATE_RampDownFreq;
}
break;
case PROFILER_FLUXESTIM_STATE_RampDownFreq:
if (motor->pSTC->speed_ref_pu == FIXP30(0.0f))
{
HSO_setMinCrossOver_Hz(motor->pSPD->pHSO, 20.0f); /* return to previous settings */
HSO_setMaxCrossOver_Hz(motor->pSPD->pHSO, 500.0f);
//set Kp_speed to Imax / speed:(voltage/flux)
newState = PROFILER_FLUXESTIM_STATE_RampDownCur;
}
break;
case PROFILER_FLUXESTIM_STATE_RampDownCur:
// Reduce current reference by ramp rate
if (motor->pSTC->Idq_ref_pu.D == FIXP30(0.0f))
{
/* Done, set motor control back to normal functioning */
ZEST_setInjectMode(motor->pSPD->pZeST, ZEST_INJECTMODE_Auto);
motor->pSPD->flagDisableImpedanceCorrection = false; /* Enable Impedance Correction */
motor->pSPD->zestControl.enableControlUpdate = true; /* Back to default situation */
if (handle->error != PROFILER_FLUXESTIM_ERROR_None)
{
newState = PROFILER_FLUXESTIM_STATE_Error;
}
else
{
newState = PROFILER_FLUXESTIM_STATE_Complete;
}
}
break;
case PROFILER_FLUXESTIM_STATE_Complete:
/* No action */
break;
case PROFILER_FLUXESTIM_STATE_Error:
/* No action */
break;
}
if (state != newState)
{
handle->state = newState;
}
}
/* Accessors */
/**
* @brief todo
*/
float_t PROFILER_FLUXESTIM_getFluxEstFreq_Hz(const PROFILER_FLUXESTIM_Handle handle)
{
return FIXP30_toF(handle->FluxEstFreq_pu) * handle->fullScaleFreq_Hz;
}
/**
* @brief todo
*/
float_t PROFILER_FLUXESTIM_getMeasurementTime(PROFILER_FLUXESTIM_Handle handle)
{
return handle->measurement_time_s;
}
/**
* @brief todo
*/
void PROFILER_FLUXESTIM_setFluxEstFreq_Hz(PROFILER_FLUXESTIM_Handle handle, const float_t fluxEstFreq_Hz)
{
handle->FluxEstFreq_pu = FIXP30(fluxEstFreq_Hz / handle->fullScaleFreq_Hz);
}
/**
* @brief todo
*/
void PROFILER_FLUXESTIM_setMeasurementTime(PROFILER_FLUXESTIM_Handle handle, const float_t time_seconds)
{
handle->measurement_time_s = time_seconds;
handle->measurement_counts = (uint32_t) (time_seconds * handle->background_rate_hz);
}
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 11,111 | C | 32.071428 | 154 | 0.671857 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/sto_cordic_speed_pos_fdbk.c | /**
******************************************************************************
* @file sto_cordic_speed_pos_fdbk.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the State Observer + CORDIC Speed & Position Feedback component of the
* Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "sto_cordic_speed_pos_fdbk.h"
#include "mc_math.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup SpeednPosFdbk
* @{
*/
/** @defgroup STO_CORDIC_SpeednPosFdbk State Observer CORDIC Speed & Position Feedback
* @brief State Observer with CORDIC Speed & Position Feedback implementation
*
* This component uses a State Observer coupled with a CORDIC (COordinate Rotation DIgital
* Computer) to provide an estimation of the speed and the position of the rotor of the motor.
*
* @todo Document the State Observer + CORDIC Speed & Position Feedback "module".
*
* @{
*/
/* Private defines -----------------------------------------------------------*/
#define C6_COMP_CONST1 (int32_t)1043038
#define C6_COMP_CONST2 (int32_t)10430
/* Private functions prototypes ----------------------------------------------*/
static void STO_CR_Store_Rotor_Speed(STO_CR_Handle_t *pHandle, int16_t hRotor_Speed, int16_t hOrRotor_Speed);
static void STO_CR_InitSpeedBuffer(STO_CR_Handle_t *pHandle);
/**
* @brief It initializes the state observer object
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval none
*/
__weak void STO_CR_Init(STO_CR_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wAux;
int16_t htempk;
pHandle->ConsistencyCounter = pHandle->StartUpConsistThreshold;
pHandle->EnableDualCheck = true;
wAux = (int32_t)1;
pHandle->F3POW2 = 0u;
htempk = (int16_t)(C6_COMP_CONST1 / (pHandle->hF2));
while (htempk != 0)
{
htempk /= (int16_t)2;
wAux *= (int32_t)2;
pHandle->F3POW2++;
}
pHandle->hF3 = (int16_t)wAux;
wAux = (int32_t)(pHandle->hF2) * pHandle->hF3;
pHandle->hC6 = (int16_t)(wAux / C6_COMP_CONST2);
STO_CR_Clear(pHandle);
/* Acceleration measurement set to zero */
pHandle->_Super.hMecAccelUnitP = 0;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief This method executes Luenberger state observer equations and calls
* CORDIC with the purpose of computing a new speed estimation and
* updating the estimated electrical angle.
* @param pHandle: handler of the current instance of the STO CORDIC component.
* pInputs pointer to the observer inputs structure.
* @retval int16_t rotor electrical angle (s16Degrees)
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t STO_CR_CalcElAngle(STO_CR_Handle_t *pHandle, Observer_Inputs_t *pInputs)
{
int16_t returnvalue;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if ((NULL == pHandle) || (NULL == pInputs))
{
returnvalue = 0;
}
else
{
#endif
int32_t wAux;
int32_t wDirection;
int32_t wAux_Alpha;
int32_t wAux_Beta;
int32_t wIalfa_est_Next;
int32_t wIbeta_est_Next;
int32_t wBemf_alfa_est_Next;
int32_t wBemf_beta_est_Next;
int16_t hAux;
int16_t hAux_Alfa;
int16_t hAux_Beta;
int16_t hIalfa_err;
int16_t hIbeta_err;
int16_t hRotor_Speed;
int16_t hOrRotor_Speed;
int16_t hRotor_Acceleration;
int16_t hRotor_Angle;
int16_t hValfa;
int16_t hVbeta;
int16_t hPrev_Rotor_Angle = pHandle->_Super.hElAngle;
int16_t hPrev_Rotor_Speed = pHandle->_Super.hElSpeedDpp;
int16_t hMax_Instant_Accel = pHandle->MaxInstantElAcceleration;
if (pHandle->wBemf_alfa_est > ((int32_t)pHandle->hF2 * INT16_MAX))
{
pHandle->wBemf_alfa_est = INT16_MAX * (int32_t)(pHandle->hF2);
}
else if (pHandle->wBemf_alfa_est <= (-INT16_MAX * (int32_t)(pHandle->hF2)))
{
pHandle->wBemf_alfa_est = -INT16_MAX * (int32_t)(pHandle->hF2);
}
else
{
/* Nothing to do */
}
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hAux_Alfa = (int16_t)(pHandle->wBemf_alfa_est >> pHandle->F2LOG);
#else
hAux_Alfa = (int16_t)(pHandle->wBemf_alfa_est / pHandle->hF2);
#endif
if (pHandle->wBemf_beta_est > (INT16_MAX * (int32_t)(pHandle->hF2)))
{
pHandle->wBemf_beta_est = INT16_MAX * (int32_t)(pHandle->hF2);
}
else if (pHandle->wBemf_beta_est <= (-INT16_MAX * (int32_t)(pHandle->hF2)))
{
pHandle->wBemf_beta_est = -INT16_MAX * (int32_t)(pHandle->hF2);
}
else
{
/* Nothing to do */
}
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hAux_Beta = (int16_t)(pHandle->wBemf_beta_est >> pHandle->F2LOG);
#else
hAux_Beta = (int16_t)(pHandle->wBemf_beta_est / pHandle->hF2);
#endif
if (pHandle->Ialfa_est > (INT16_MAX * (int32_t)(pHandle->hF1)))
{
pHandle->Ialfa_est = INT16_MAX * (int32_t)(pHandle->hF1);
}
else if (pHandle->Ialfa_est <= (-INT16_MAX * (int32_t)(pHandle->hF1)))
{
pHandle->Ialfa_est = -INT16_MAX * (int32_t)(pHandle->hF1);
}
else
{
/* Nothing to do */
}
if (pHandle->Ibeta_est > (INT16_MAX * (int32_t)(pHandle->hF1)))
{
pHandle->Ibeta_est = INT16_MAX * (int32_t)(pHandle->hF1);
}
else if (pHandle->Ibeta_est <= (-INT16_MAX * (int32_t)(pHandle->hF1)))
{
pHandle->Ibeta_est = -INT16_MAX * (int32_t)(pHandle->hF1);
}
else
{
/* Nothing to do */
}
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hIalfa_err = (int16_t)(pHandle->Ialfa_est >> pHandle->F1LOG);
#else
hIalfa_err = (int16_t)(pHandle->Ialfa_est / pHandle->hF1);
#endif
hIalfa_err = hIalfa_err - pInputs->Ialfa_beta.alpha;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hIbeta_err = (int16_t)(pHandle->Ibeta_est >> pHandle->F1LOG);
#else
hIbeta_err = (int16_t)(pHandle->Ibeta_est / pHandle->hF1);
#endif
hIbeta_err = hIbeta_err - pInputs->Ialfa_beta.beta;
wAux = (int32_t)(pInputs->Vbus) * pInputs->Valfa_beta.alpha;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
hValfa = (int16_t)(wAux >> 16); //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
hValfa = (int16_t)(wAux / 65536);
#endif
wAux = (int32_t)(pInputs->Vbus) * pInputs->Valfa_beta.beta;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
hVbeta = (int16_t)(wAux >> 16); //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
hVbeta = (int16_t)(wAux / 65536);
#endif
/* Alfa axes observer */
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hAux = (int16_t)(pHandle->Ialfa_est >> pHandle->F1LOG);
#else
hAux = (int16_t)(pHandle->Ialfa_est / pHandle->hF1);
#endif
wAux = (int32_t)(pHandle->hC1) * hAux;
wIalfa_est_Next = pHandle->Ialfa_est - wAux;
wAux = (int32_t)(pHandle->hC2) * hIalfa_err;
wIalfa_est_Next += wAux;
wAux = (int32_t)(pHandle->hC5) * hValfa;
wIalfa_est_Next += wAux;
wAux = (int32_t)(pHandle->hC3) * hAux_Alfa;
wIalfa_est_Next -= wAux;
wAux = (int32_t)(pHandle->hC4) * hIalfa_err;
wBemf_alfa_est_Next = pHandle->wBemf_alfa_est + wAux;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
wAux = (int32_t) hAux_Beta >> pHandle->F3POW2;
#else
wAux = (int32_t)hAux_Beta / pHandle->hF3;
#endif
wAux = wAux * pHandle->hC6;
wAux = hPrev_Rotor_Speed * wAux;
wBemf_alfa_est_Next += wAux;
/* Beta axes observer */
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hAux = (int16_t)(pHandle->Ibeta_est >> pHandle->F1LOG);
#else
hAux = (int16_t)(pHandle->Ibeta_est / pHandle->hF1);
#endif
wAux = (int32_t)(pHandle->hC1) * hAux;
wIbeta_est_Next = pHandle->Ibeta_est - wAux;
wAux = (int32_t)(pHandle->hC2) * hIbeta_err;
wIbeta_est_Next += wAux;
wAux = (int32_t)(pHandle->hC5) * hVbeta;
wIbeta_est_Next += wAux;
wAux = (int32_t)(pHandle->hC3) * hAux_Beta;
wIbeta_est_Next -= wAux;
wAux = (int32_t)(pHandle->hC4) * hIbeta_err;
wBemf_beta_est_Next = pHandle->wBemf_beta_est + wAux;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
wAux = (int32_t) hAux_Alfa >> pHandle->F3POW2;
#else
wAux = (int32_t)hAux_Alfa / pHandle->hF3;
#endif
wAux = wAux * pHandle->hC6;
wAux = hPrev_Rotor_Speed * wAux;
wBemf_beta_est_Next -= wAux;
if (pHandle->Orig_ElSpeedDpp >= 0)
{
wDirection = 1;
}
else
{
wDirection = -1;
}
/* Stores observed b-emfs */
pHandle->hBemf_alfa_est = hAux_Alfa;
pHandle->hBemf_beta_est = hAux_Beta;
/* Calls the CORDIC blockset */
wAux_Alpha = pHandle->wBemf_alfa_est * wDirection;
wAux_Beta = pHandle->wBemf_beta_est * wDirection;
hRotor_Angle = MCM_PhaseComputation(wAux_Alpha, -wAux_Beta);
hOrRotor_Speed = (int16_t)(hRotor_Angle - hPrev_Rotor_Angle);
hRotor_Acceleration = hOrRotor_Speed - hPrev_Rotor_Speed;
hRotor_Speed = hOrRotor_Speed;
if (wDirection == 1)
{
if (hRotor_Speed < 0)
{
hRotor_Speed = 0;
}
else
{
if (hRotor_Acceleration > hMax_Instant_Accel)
{
hRotor_Speed = hPrev_Rotor_Speed + hMax_Instant_Accel;
pHandle->_Super.hElAngle = hPrev_Rotor_Angle + hRotor_Speed;
}
else
{
pHandle->_Super.hElAngle = hRotor_Angle;
}
}
}
else
{
if (hRotor_Speed > 0)
{
hRotor_Speed = 0;
}
else
{
if (hRotor_Acceleration < (-hMax_Instant_Accel))
{
hRotor_Speed = hPrev_Rotor_Speed - hMax_Instant_Accel;
pHandle->_Super.hElAngle = hPrev_Rotor_Angle + hRotor_Speed;
}
else
{
pHandle->_Super.hElAngle = hRotor_Angle;
}
}
}
if (hRotor_Acceleration > hMax_Instant_Accel)
{
hOrRotor_Speed = hPrev_Rotor_Speed + hMax_Instant_Accel;
}
else if (hRotor_Acceleration < (-hMax_Instant_Accel))
{
hOrRotor_Speed = hPrev_Rotor_Speed - hMax_Instant_Accel;
}
else
{
/* Nothing to do */
}
STO_CR_Store_Rotor_Speed(pHandle, hRotor_Speed, hOrRotor_Speed);
/* Storing previous values of currents and bemfs */
pHandle->Ialfa_est = wIalfa_est_Next;
pHandle->wBemf_alfa_est = wBemf_alfa_est_Next;
pHandle->Ibeta_est = wIbeta_est_Next;
pHandle->wBemf_beta_est = wBemf_beta_est_Next;
returnvalue = pHandle->_Super.hElAngle;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
return (returnvalue);
}
/**
* @brief Computes the rotor average mechanical speed in the unit defined by
* #SPEED_UNIT and writes it in pMecSpeedUnit
*
* This method must be called - at least - with the same periodicity
* on which the speed control is executed. It computes and returns - through
* parameter pMecSpeedUnit - the rotor average mechanical speed, expressed in
* the unit defined by #SPEED_UNIT. Average is computed considering a FIFO depth
* equal to STO_CR_Handle_t::SpeedBufferSizeUnit.
*
* Moreover it also computes and returns the reliability state of the sensor,
* measured with reference to parameters STO_CR_Handle_t::Reliability_hysteresys,
* STO_CR_Handle_t::VariancePercentage and STO_CR_Handle_t::SpeedBufferSizeUnit of
* the STO_CR_Handle_t handle.
*
* @param pHandle handler of the current instance of the STO CORDIC component
* @param pMecSpeedUnit pointer to int16_t, used to return the rotor average
* mechanical speed
* @retval true if the sensor information is reliable, false otherwise
*/
__weak bool STO_CR_CalcAvrgMecSpeedUnit(STO_CR_Handle_t *pHandle, int16_t *pMecSpeedUnit)
{
bool bAux = false;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if ((NULL == pHandle) || (NULL == pMecSpeedUnit))
{
/* Nothing to do */
}
else
{
#endif
int32_t wAvrSpeed_dpp = (int32_t)0;
int32_t wError;
int32_t wAux;
int32_t wAvrSquareSpeed;
int32_t wAvrQuadraticError = 0;
int32_t wObsBemf, wEstBemf;
int32_t wObsBemfSq = 0;
int32_t wEstBemfSq = 0;
int32_t wEstBemfSqLo;
uint8_t i;
uint8_t bSpeedBufferSizeUnit = pHandle->SpeedBufferSizeUnit;
bool bIs_Speed_Reliable = false;
bool bIs_Bemf_Consistent = false;
for (i = 0U; i < bSpeedBufferSizeUnit; i++)
{
wAvrSpeed_dpp += (int32_t)(pHandle->Speed_Buffer[i]);
}
if ((uint8_t)0 == bSpeedBufferSizeUnit)
{
/* Nothing to do */
}
else
{
wAvrSpeed_dpp = wAvrSpeed_dpp / (int16_t)bSpeedBufferSizeUnit;
}
/* Value is written during init and computed by MC Workbench and always >= 1 */
//cstat -MISRAC2012-Rule-1.3_d
for (i = 0U; i < bSpeedBufferSizeUnit; i++)
{
wError = (int32_t)(pHandle->Speed_Buffer[i]) - wAvrSpeed_dpp;
wError = (wError * wError);
wAvrQuadraticError += wError;
}
/* It computes the measurement variance */
wAvrQuadraticError = wAvrQuadraticError / (int16_t)bSpeedBufferSizeUnit;
//cstat +MISRAC2012-Rule-1.3_d
/* The maximum variance acceptable is here calculated as a function of average speed */
wAvrSquareSpeed = wAvrSpeed_dpp * wAvrSpeed_dpp;
int64_t lAvrSquareSpeed = (int64_t)(wAvrSquareSpeed) * (int64_t)pHandle->VariancePercentage;
wAvrSquareSpeed = (int32_t)(lAvrSquareSpeed / (int64_t)128);
if (wAvrQuadraticError < wAvrSquareSpeed)
{
bIs_Speed_Reliable = true;
}
else
{
/* Nothing to do */
}
/* Computation of Mechanical speed unit */
wAux = wAvrSpeed_dpp * (int32_t)(pHandle->_Super.hMeasurementFrequency);
wAux = wAux * (int32_t) (pHandle->_Super.SpeedUnit);
wAux = wAux / (int32_t)(pHandle->_Super.DPPConvFactor);
wAux = wAux / (int16_t)(pHandle->_Super.bElToMecRatio);
*pMecSpeedUnit = (int16_t)wAux;
pHandle->_Super.hAvrMecSpeedUnit = (int16_t)wAux;
pHandle->IsSpeedReliable = bIs_Speed_Reliable;
/* Bemf Consistency Check algorithm */
if (true == pHandle->EnableDualCheck) /*do algorithm if it's enabled*/
{
/* wAux abs value */
/* False positive */
wAux = ((wAux < 0) ? (-wAux) : (wAux)); //cstat !MISRAC2012-Rule-14.3_b !RED-cond-never !RED-cmp-never
if (wAux < (int32_t)(pHandle->MaxAppPositiveMecSpeedUnit))
{
/* Computation of Observed back-emf */
wObsBemf = (int32_t)(pHandle->hBemf_alfa_est);
wObsBemfSq = wObsBemf * wObsBemf;
wObsBemf = (int32_t)(pHandle->hBemf_beta_est);
wObsBemfSq += wObsBemf * wObsBemf;
/* Computation of Estimated back-emf */
wEstBemf = (wAux * 32767) / (int16_t)(pHandle->_Super.hMaxReliableMecSpeedUnit);
wEstBemfSq = (wEstBemf * (int32_t)(pHandle->BemfConsistencyGain)) / 64;
wEstBemfSq *= wEstBemf;
/* Computation of threshold */
wEstBemfSqLo = wEstBemfSq - ((wEstBemfSq / 64) * (int32_t)(pHandle->BemfConsistencyCheck));
/* Check */
if (wObsBemfSq > wEstBemfSqLo)
{
bIs_Bemf_Consistent = true;
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
pHandle->IsBemfConsistent = bIs_Bemf_Consistent;
pHandle->Obs_Bemf_Level = wObsBemfSq;
pHandle->Est_Bemf_Level = wEstBemfSq;
}
else
{
bIs_Bemf_Consistent = true;
}
/* Decision making */
if (pHandle->IsAlgorithmConverged == false)
{
bAux = SPD_IsMecSpeedReliable(&pHandle->_Super, pMecSpeedUnit);
}
else
{
if ((pHandle->IsSpeedReliable == false) || (bIs_Bemf_Consistent == false))
{
pHandle->ReliabilityCounter++;
if (pHandle->ReliabilityCounter >= pHandle->Reliability_hysteresys)
{
pHandle->ReliabilityCounter = 0U;
pHandle->_Super.bSpeedErrorNumber = pHandle->_Super.bMaximumSpeedErrorsNumber;
bAux = false;
}
else
{
bAux = SPD_IsMecSpeedReliable (&pHandle->_Super, pMecSpeedUnit);
}
}
else
{
pHandle->ReliabilityCounter = 0U;
bAux = SPD_IsMecSpeedReliable (&pHandle->_Super, pMecSpeedUnit);
}
}
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
return (bAux);
}
/**
* @brief It clears state observer object by re-initializing private variables
* @param pHandle pointer on the component instance to work on.
*/
__weak void STO_CR_Clear(STO_CR_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->Ialfa_est = (int32_t)0;
pHandle->Ibeta_est = (int32_t)0;
pHandle->wBemf_alfa_est = (int32_t)0;
pHandle->wBemf_beta_est = (int32_t)0;
pHandle->_Super.hElAngle = (int16_t)0;
pHandle->_Super.hElSpeedDpp = (int16_t)0;
pHandle->Orig_ElSpeedDpp = (int16_t)0;
pHandle->ConsistencyCounter = 0u;
pHandle->ReliabilityCounter = 0u;
pHandle->IsAlgorithmConverged = false;
pHandle->IsBemfConsistent = false;
pHandle->Obs_Bemf_Level = (int32_t)0;
pHandle->Est_Bemf_Level = (int32_t)0;
pHandle->DppBufferSum = (int32_t)0;
pHandle->DppOrigBufferSum = (int32_t)0;
pHandle->ForceConvergency = false;
pHandle->ForceConvergency2 = false;
STO_CR_InitSpeedBuffer(pHandle);
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
}
/**
* @brief It stores in estimated speed FIFO latest calculated value of motor
* speed
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval none
*/
inline static void STO_CR_Store_Rotor_Speed(STO_CR_Handle_t *pHandle, int16_t hRotor_Speed, int16_t hOrRotor_Speed)
{
uint8_t bBuffer_index = pHandle->Speed_Buffer_Index;
bBuffer_index++;
if (bBuffer_index == pHandle->SpeedBufferSizeUnit)
{
bBuffer_index = 0U;
}
else
{
/* Nothing too do */
}
pHandle->SpeedBufferOldestEl = pHandle->Speed_Buffer[bBuffer_index];
pHandle->OrigSpeedBufferOldestEl = pHandle->Orig_Speed_Buffer[bBuffer_index];
pHandle->Speed_Buffer[bBuffer_index] = hRotor_Speed;
pHandle->Orig_Speed_Buffer[bBuffer_index] = hOrRotor_Speed;
pHandle->Speed_Buffer_Index = bBuffer_index;
}
/**
* @brief It clears the estimated speed buffer
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval none
*/
static void STO_CR_InitSpeedBuffer(STO_CR_Handle_t *pHandle)
{
uint8_t b_i;
uint8_t bSpeedBufferSizeUnit = pHandle->SpeedBufferSizeUnit;
/*init speed buffer*/
for (b_i = 0U; b_i < bSpeedBufferSizeUnit; b_i++)
{
pHandle->Speed_Buffer[b_i] = (int16_t)0;
pHandle->Orig_Speed_Buffer[b_i] = (int16_t)0;
}
pHandle->Speed_Buffer_Index = 0u;
pHandle->SpeedBufferOldestEl = (int16_t)0;
pHandle->OrigSpeedBufferOldestEl = (int16_t)0;
}
/**
* @brief Returns true if the Observer has converged or false otherwise.
*
* Internally performs a set of checks necessary to state whether
* the state observer algorithm has converged or not.
*
* This function is to be periodically called during the motor rev-up procedure
* at the same frequency as the *_CalcElAngle() functions.
*
* It returns true if the estimated angle and speed can be considered reliable,
* false otherwise.
*
* @param pHandle pointer on the component instance
* @param hForcedMecSpeedUnit Mechanical speed as forced by VSS, in the unit defined by #SPEED_UNIT
*/
__weak bool STO_CR_IsObserverConverged(STO_CR_Handle_t *pHandle, int16_t hForcedMecSpeedUnit)
{
bool bAux = false;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wAux;
int32_t wtemp;
int16_t hEstimatedSpeedUnit;
int16_t hUpperThreshold;
int16_t hLowerThreshold;
int16_t lForcedMecSpeedUnit;
if (pHandle->ForceConvergency2 == true)
{
lForcedMecSpeedUnit = pHandle->_Super.hAvrMecSpeedUnit;
}
else
{
lForcedMecSpeedUnit = hForcedMecSpeedUnit;
}
if (pHandle->ForceConvergency == true)
{
bAux = true;
pHandle->IsAlgorithmConverged = true;
pHandle->_Super.bSpeedErrorNumber = 0U;
}
else
{
hEstimatedSpeedUnit = pHandle->_Super.hAvrMecSpeedUnit;
wtemp = (int32_t)hEstimatedSpeedUnit * (int32_t)lForcedMecSpeedUnit;
if (wtemp > 0)
{
if (hEstimatedSpeedUnit < 0)
{
hEstimatedSpeedUnit = -hEstimatedSpeedUnit;
}
else
{
/* Nothing to do */
}
if (lForcedMecSpeedUnit < 0)
{
lForcedMecSpeedUnit = -lForcedMecSpeedUnit;
}
else
{
/* Nothing to do */
}
wAux = (int32_t) (lForcedMecSpeedUnit) * (int16_t)pHandle->SpeedValidationBand_H;
hUpperThreshold = (int16_t)(wAux / (int32_t)16);
wAux = (int32_t) (lForcedMecSpeedUnit) * (int16_t)pHandle->SpeedValidationBand_L;
hLowerThreshold = (int16_t)(wAux / (int32_t)16);
/* If the variance of the estimated speed is low enough... */
if (true == pHandle->IsSpeedReliable)
{
if ((uint16_t)hEstimatedSpeedUnit > pHandle->MinStartUpValidSpeed)
{
/* ...and the estimated value is quite close to the expected value... */
if (hEstimatedSpeedUnit >= hLowerThreshold)
{
if (hEstimatedSpeedUnit <= hUpperThreshold)
{
pHandle->ConsistencyCounter++;
/* ...for hConsistencyThreshold consecutive times... */
if (pHandle->ConsistencyCounter >= pHandle->StartUpConsistThreshold)
{
/* The algorithm converged */
bAux = true;
pHandle->IsAlgorithmConverged = true;
pHandle->_Super.bSpeedErrorNumber = 0U;
}
}
else
{
pHandle->ConsistencyCounter = 0U;
}
}
else
{
pHandle->ConsistencyCounter = 0U;
}
}
else
{
pHandle->ConsistencyCounter = 0U;
}
}
else
{
pHandle->ConsistencyCounter = 0U;
}
}
}
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
return (bAux);
}
/* false positive */
//cstat -MISRAC2012-Rule-2.2_b
/**
* @brief It exports estimated Bemf alpha-beta in qd_t format
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval alphabeta_t Bemf alpha-beta
*/
//cstat !MISRAC2012-Rule-8.13
__weak alphabeta_t STO_CR_GetEstimatedBemf(STO_CR_Handle_t *pHandle)
{
alphabeta_t Vaux;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
Vaux.alpha = 0;
Vaux.beta = 0;
}
else
{
#endif
Vaux.alpha = pHandle->hBemf_alfa_est;
Vaux.beta = pHandle->hBemf_beta_est;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
return (Vaux);
}
/**
* @brief It exports the stator current alpha-beta as estimated by state
* observer
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval alphabeta_t State observer estimated stator current Ialpha-beta
*/
//cstat !MISRAC2012-Rule-8.13
__weak alphabeta_t STO_CR_GetEstimatedCurrent(STO_CR_Handle_t *pHandle)
{
alphabeta_t Iaux;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
Iaux.alpha = 0;
Iaux.beta = 0;
}
else
{
#endif
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
Iaux.alpha = (int16_t)(pHandle->Ialfa_est >> pHandle->F1LOG);
#else
Iaux.alpha = (int16_t)(pHandle->Ialfa_est / (pHandle->hF1));
#endif
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
Iaux.beta = (int16_t)(pHandle->Ibeta_est >> pHandle->F1LOG);
#else
Iaux.beta = (int16_t)(pHandle->Ibeta_est / (pHandle->hF1));
#endif
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
return (Iaux);
}
//cstat +MISRAC2012-Rule-2.2_b
/**
* @brief It exports current observer gains through parameters hhC2 and hhC4
* @param pHandle: handler of the current instance of the STO CORDIC component
* @param phC2 pointer to int16_t used to return parameters hhC2
* @param phC4 pointer to int16_t used to return parameters hhC4
* @retval none
*/
__weak void STO_CR_GetObserverGains(STO_CR_Handle_t *pHandle, int16_t *phC2, int16_t *phC4)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if ((NULL == pHandle) || (NULL == phC2) || (NULL == phC4))
{
/* Nothing to do */
}
else
{
#endif
*phC2 = pHandle->hC2;
*phC4 = pHandle->hC4;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
}
/**
* @brief It allows setting new values for observer gains
* @param pHandle: handler of the current instance of the STO CORDIC component
* @param wK1 new value for observer gain hhC1
* @param wK2 new value for observer gain hhC2
* @retval none
*/
__weak void STO_CR_SetObserverGains(STO_CR_Handle_t *pHandle, int16_t hhC1, int16_t hhC2)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hC2 = hhC1;
pHandle->hC4 = hhC2;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief This method must be called - at least - with the same periodicity
* on which speed control is executed. It computes and update object
* variable hElSpeedDpp that is estimated average electrical speed
* expressed in dpp used for instance in observer equations.
* Average is computed considering a FIFO depth equal to
* bSpeedBufferSizedpp.
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval none
*/
__weak void STO_CR_CalcAvrgElSpeedDpp(STO_CR_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wSum = pHandle->DppBufferSum;
int32_t wSumOrig = pHandle->DppOrigBufferSum;
int32_t wAvrSpeed_dpp;
int16_t hSpeedBufferSizedpp = (int16_t)(pHandle->SpeedBufferSizedpp);
int16_t hSpeedBufferSizeUnit = (int16_t)(pHandle->SpeedBufferSizeUnit);
int16_t hBufferSizeDiff;
int16_t hIndexNew = (int16_t)pHandle->Speed_Buffer_Index;
int16_t hIndexOld;
int16_t hIndexOldTemp;
hBufferSizeDiff = hSpeedBufferSizeUnit - hSpeedBufferSizedpp;
if (0 == hBufferSizeDiff)
{
wSum = wSum + pHandle->Speed_Buffer[hIndexNew] - pHandle->SpeedBufferOldestEl;
wSumOrig = wSumOrig + pHandle->Orig_Speed_Buffer[hIndexNew] - pHandle->OrigSpeedBufferOldestEl;
}
else
{
hIndexOldTemp = hIndexNew + hBufferSizeDiff;
if (hIndexOldTemp >= hSpeedBufferSizeUnit)
{
hIndexOld = hIndexOldTemp - hSpeedBufferSizeUnit;
}
else
{
hIndexOld = hIndexOldTemp;
}
wSum = wSum + pHandle->Speed_Buffer[hIndexNew] - pHandle->Speed_Buffer[hIndexOld];
wSumOrig = wSumOrig + pHandle->Orig_Speed_Buffer[hIndexNew] - pHandle->Orig_Speed_Buffer[hIndexOld];
}
#ifndef FULL_MISRA_C_COMPLIANCY_STO_CORDIC
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
wAvrSpeed_dpp = (int32_t)(wSum >> pHandle->SpeedBufferSizedppLOG);
pHandle->_Super.hElSpeedDpp = (int16_t)wAvrSpeed_dpp;
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
wAvrSpeed_dpp = (int32_t)(wSumOrig >> pHandle->SpeedBufferSizedppLOG);
#else
if (hSpeedBufferSizedpp != 0)
{
wAvrSpeed_dpp = wSum / hSpeedBufferSizedpp;
pHandle->_Super.hElSpeedDpp = (int16_t)wAvrSpeed_dpp;
wAvrSpeed_dpp = wSumOrig / hSpeedBufferSizedpp;
}
else
{
wAvrSpeed_dpp = (int32_t)0;
}
#endif
pHandle->Orig_ElSpeedDpp = (int16_t)wAvrSpeed_dpp;
pHandle->DppBufferSum = wSum;
pHandle->DppOrigBufferSum = wSumOrig;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
}
/**
* @brief It exports estimated Bemf squared level
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval int32_t
*/
__weak int32_t STO_CR_GetEstimatedBemfLevel(const STO_CR_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
return ((NULL == pHandle) ? 0 : pHandle->Est_Bemf_Level);
#else
return (pHandle->Est_Bemf_Level);
#endif
}
/**
* @brief It exports observed Bemf squared level
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval int32_t
*/
__weak int32_t STO_CR_GetObservedBemfLevel(const STO_CR_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
return ((NULL == pHandle) ? 0 : pHandle->Obs_Bemf_Level);
#else
return (pHandle->Obs_Bemf_Level);
#endif
}
/**
* @brief It enables/disables the bemf consistency check
* @param pHandle: handler of the current instance of the STO CORDIC component
* @param bSel boolean; true enables check; false disables check
*/
__weak void STO_CR_BemfConsistencyCheckSwitch(STO_CR_Handle_t *pHandle, bool bSel)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
/* Noything to do */
}
else
{
#endif
pHandle->EnableDualCheck = bSel;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
}
/**
* @brief It returns the result of the Bemf consistency check
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval bool Bemf consistency state
*/
__weak bool STO_CR_IsBemfConsistent(const STO_CR_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
return ((NULL == pHandle) ? false : pHandle->IsBemfConsistent);
#else
return (pHandle->IsBemfConsistent);
#endif
}
/**
* @brief This method returns the reliability of the speed sensor
* @param pHandle: handler of the current instance of the STO CORDIC component
* @retval bool speed sensor reliability, measured with reference to parameters
* bReliability_hysteresys, hVariancePercentage and bSpeedBufferSize
* true = sensor information is reliable
* false = sensor information is not reliable
*/
__weak bool STO_CR_IsSpeedReliable(const STO_Handle_t *pHandle)
{
bool returnbool;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
returnbool = false;
}
else
{
#endif
const STO_CR_Handle_t *pHdl = (STO_CR_Handle_t *)pHandle->_Super; //cstat !MISRAC2012-Rule-11.3
returnbool = pHdl->IsSpeedReliable;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
return (returnbool);
}
/* @brief It forces the state-observer to declare converged
* @param pHandle: handler of the current instance of the STO CORDIC component
*/
__weak void STO_CR_ForceConvergency1(STO_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
STO_CR_Handle_t *pHdl = (STO_CR_Handle_t *)pHandle->_Super; //cstat !MISRAC2012-Rule-11.3
pHdl->ForceConvergency = true;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
}
/* @brief It forces the state-observer to declare converged
* @param pHandle: handler of the current instance of the STO CORDIC component
*/
__weak void STO_CR_ForceConvergency2(STO_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
STO_CR_Handle_t *pHdl = (STO_CR_Handle_t *)pHandle->_Super; //cstat !MISRAC2012-Rule-11.3
pHdl->ForceConvergency2 = true;
#ifdef NULL_PTR_CHECK_STO_COR_SPD_POS_FDB
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/** @} */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 35,354 | C | 28.810287 | 115 | 0.639136 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/speed_ctrl.c | /*
******************************************************************************
* @file speed_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the following features
* of the Speed Control component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "speed_ctrl.h"
#include "speed_pos_fdbk.h"
#include "mc_type.h"
#define CHECK_BOUNDARY
/** @addtogroup MCSDK
* @{
*/
/** @defgroup SpeednTorqCtrl Speed Control
* @brief Speed Control component of the Motor Control SDK
*
* @todo Document the Speed Control "module".
*
* @{
*/
/**
* @brief Initializes all the object variables, usually it has to be called
* once right after object creation.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @param pPI the PI object used as controller for the speed regulation.
* @param SPD_Handle the speed sensor used to perform the speed regulation.
* @retval none.
*/
__weak void STC_Init( SpeednTorqCtrl_Handle_t * pHandle, PID_Handle_t * pPI, SpeednPosFdbk_Handle_t * SPD_Handle )
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->PISpeed = pPI;
pHandle->SPD = SPD_Handle;
pHandle->Mode = pHandle->ModeDefault;
pHandle->SpeedRefUnitExt = ((int32_t)pHandle->MecSpeedRefUnitDefault) * 65536;
pHandle->DutyCycleRef = ((uint32_t)pHandle->DutyCycleRefDefault) * 65536;
pHandle->TargetFinal = 0;
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
}
}
/**
* @brief It sets in real time the speed sensor utilized by the STC.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @param SPD_Handle Speed sensor component to be set.
* @retval none
*/
__weak void STC_SetSpeedSensor( SpeednTorqCtrl_Handle_t * pHandle, SpeednPosFdbk_Handle_t * SPD_Handle )
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->SPD = SPD_Handle;
}
}
/**
* @brief It returns the speed sensor utilized by the FOC.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval SpeednPosFdbk_Handle_t speed sensor utilized by the FOC.
*/
__weak SpeednPosFdbk_Handle_t * STC_GetSpeedSensor( SpeednTorqCtrl_Handle_t * pHandle )
{
return ((MC_NULL == pHandle) ? MC_NULL : pHandle->SPD);
}
/**
* @brief It should be called before each motor restart. If STC is set in
speed mode, this method resets the integral term of speed regulator.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval none.
*/
__weak void STC_Clear( SpeednTorqCtrl_Handle_t * pHandle )
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
if (MCM_SPEED_MODE == pHandle->Mode)
{
PID_SetIntegralTerm(pHandle->PISpeed, 0);
}
pHandle->DutyCycleRef = ((uint32_t)pHandle->DutyCycleRefDefault) * 65536;
}
}
/**
* @brief Get the current mechanical rotor speed reference.
* Expressed in the unit defined by SPEED_UNIT.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval int16_t current mechanical rotor speed reference.
* Expressed in the unit defined by SPEED_UNIT.
*/
__weak int16_t STC_GetMecSpeedRefUnit( SpeednTorqCtrl_Handle_t * pHandle )
{
#ifdef NO_FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
return ((MC_NULL == pHandle) ? 0 : (int16_t)(pHandle->SpeedRefUnitExt >> 16));
#else
return ((MC_NULL == pHandle) ? 0 : (int16_t)(pHandle->SpeedRefUnitExt / 65536));
#endif
}
/**
* @brief Get the current motor dutycycle reference. This value represents
* actually the dutycycle reference expressed in digit.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval uint16_t current dutycycle reference. This value is actually expressed in digit.
*/
__weak uint16_t STC_GetDutyCycleRef(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NO_FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
return ((MC_NULL == pHandle) ? 0 : (uint16_t)(pHandle->DutyCycleRef >> 16));
#else
return ((MC_NULL == pHandle) ? 0 : (uint16_t)(pHandle->DutyCycleRef / 65536));
#endif
}
/**
* @brief Set the modality of the speed controller. Two modality
* are available Torque mode and Speed mode.
* In Torque mode is possible to set directly the dutycycle
* reference or execute a motor dutycycle ramp. This value represents
* actually the reference expressed in digit.
* In Speed mode is possible to set the mechanical rotor speed
* reference or execute a speed ramp. The required motor dutycycle is
* automatically calculated by the STC.
* This command interrupts the execution of any previous ramp command
* maintaining the last value of dutycycle.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @param bMode modality of STC. It can be one of these two settings:
* MCM_TORQUE_MODE to enable the Torque mode or MCM_SPEED_MODE to
* enable the Speed mode.
* @retval none
*/
__weak void STC_SetControlMode( SpeednTorqCtrl_Handle_t * pHandle, MC_ControlMode_t bMode )
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->Mode = bMode;
pHandle->RampRemainingStep = 0u; /* Interrupts previous ramp. */
}
}
/**
* @brief Get the modality of the speed controller.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval MC_ControlMode_t It returns the modality of STC. It can be one of
* these two values: MCM_TORQUE_MODE or MCM_SPEED_MODE.
*/
__weak MC_ControlMode_t STC_GetControlMode( SpeednTorqCtrl_Handle_t * pHandle )
{
return ((MC_NULL == pHandle) ? MCM_TORQUE_MODE : pHandle->Mode);
}
/**
* @brief Starts the execution of a ramp using new target and duration. This
* command interrupts the execution of any previous ramp command.
* The generated ramp will be in the modality previously set by
* STC_SetControlMode method.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @param hTargetFinal final value of command. This is different accordingly
* the STC modality.
* hTargetFinal is the value of mechanical rotor speed reference at the end
* of the ramp.Expressed in the unit defined by SPEED_UNIT
* @param hDurationms the duration of the ramp expressed in milliseconds. It
* is possible to set 0 to perform an instantaneous change in the value.
* @retval bool It return false if the absolute value of hTargetFinal is out of
* the boundary of the application (Above max application speed or below min
* application speed in this case the command is ignored and the
* previous ramp is not interrupted, otherwise it returns true.
*/
__weak bool STC_ExecRamp(SpeednTorqCtrl_Handle_t *pHandle, int16_t hTargetFinal, uint32_t hDurationms)
{
bool allowedRange = true;
if (MC_NULL == pHandle)
{
allowedRange = false;
}
else
{
uint32_t wAux;
int32_t wAux1;
int16_t hCurrentReference;
/* Check if the hTargetFinal is out of the bound of application. */
if (MCM_TORQUE_MODE == pHandle->Mode)
{
hCurrentReference = STC_GetDutyCycleRef(pHandle);
#ifdef CHECK_BOUNDARY
if ((int32_t)hTargetFinal > (int32_t)pHandle->MaxPositiveDutyCycle)
{
allowedRange = false;
}
#endif
}
else
{
#ifdef NO_FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hCurrentReference = (int16_t)(pHandle->SpeedRefUnitExt >> 16);
#else
hCurrentReference = (int16_t)(pHandle->SpeedRefUnitExt / 65536);
#endif
#ifdef CHECK_BOUNDARY
if ((int32_t)hTargetFinal > (int32_t)pHandle->MaxAppPositiveMecSpeedUnit)
{
allowedRange = false;
}
else if (hTargetFinal < pHandle->MinAppNegativeMecSpeedUnit)
{
allowedRange = false;
}
else if ((int32_t)hTargetFinal < (int32_t)pHandle->MinAppPositiveMecSpeedUnit)
{
if (hTargetFinal > pHandle->MaxAppNegativeMecSpeedUnit)
{
allowedRange = false;
}
}
else
{
/* Nothing to do */
}
#endif
}
if (true == allowedRange)
{
/* Interrupts the execution of any previous ramp command */
if (0U == hDurationms)
{
if (MCM_SPEED_MODE == pHandle->Mode)
{
pHandle->SpeedRefUnitExt = ((int32_t)hTargetFinal) * 65536;
}
else
{
pHandle->DutyCycleRef = ((int32_t)hTargetFinal) * 65536;
}
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
}
else
{
/* Store the hTargetFinal to be applied in the last step */
pHandle->TargetFinal = hTargetFinal;
/* Compute the (wRampRemainingStep) number of steps remaining to complete
the ramp. */
wAux = ((uint32_t)hDurationms) * ((uint32_t)pHandle->STCFrequencyHz);
wAux /= 1000U;
pHandle->RampRemainingStep = wAux;
pHandle->RampRemainingStep++;
/* Compute the increment/decrement amount (wIncDecAmount) to be applied to
the reference value at each CalcSpeedReference. */
wAux1 = (((int32_t)hTargetFinal) - ((int32_t)hCurrentReference)) * 65536;
wAux1 /= ((int32_t)pHandle->RampRemainingStep);
pHandle->IncDecAmount = wAux1;
}
}
}
return (allowedRange);
}
/**
* @brief This command interrupts the execution of any previous ramp command.
* The last value of mechanical rotor speed reference is maintained.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval none
*/
__weak void STC_StopRamp(SpeednTorqCtrl_Handle_t *pHandle)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
}
}
/**
* @brief It is used to compute the new value of motor speed reference. It
* must be called at fixed time equal to hSTCFrequencyHz. It is called
* passing as parameter the speed sensor used to perform the speed
* regulation.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval int16_t motor dutycycle reference. This value represents actually the
* dutycycle expressed in digit.
*/
__weak uint16_t STC_CalcSpeedReference(SpeednTorqCtrl_Handle_t *pHandle)
{
uint16_t hDutyCycleReference;
if (MC_NULL == pHandle)
{
hDutyCycleReference = 0;
}
else
{
int32_t wCurrentReference;
int16_t hMeasuredSpeed;
int16_t hTargetSpeed;
int16_t hError;
if (MCM_TORQUE_MODE == pHandle->Mode)
{
wCurrentReference = pHandle->DutyCycleRef;
}
else
{
wCurrentReference = pHandle->SpeedRefUnitExt;
}
/* Update the speed reference or the torque reference according to the mode
and terminates the ramp if needed. */
if (pHandle->RampRemainingStep > 1U)
{
/* Increment/decrement the reference value. */
wCurrentReference += pHandle->IncDecAmount;
/* Decrement the number of remaining steps */
pHandle->RampRemainingStep--;
}
else if (1U == pHandle->RampRemainingStep)
{
/* Set the backup value of hTargetFinal. */
wCurrentReference = ((int32_t)pHandle->TargetFinal) * 65536;
pHandle->RampRemainingStep = 0U;
}
else
{
/* Do nothing. */
}
if (MCM_SPEED_MODE == pHandle->Mode)
{
/* Run the speed control loop */
/* Compute speed error */
#ifdef NO_FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hTargetSpeed = (int16_t)(wCurrentReference >> 16);
#else
hTargetSpeed = (int16_t)(wCurrentReference / 65536);
#endif
hMeasuredSpeed = SPD_GetAvrgMecSpeedUnit(pHandle->SPD);
if (hTargetSpeed < 0) hError = hMeasuredSpeed - hTargetSpeed;
else hError = hTargetSpeed - hMeasuredSpeed;
hDutyCycleReference = PI_Controller(pHandle->PISpeed, (int32_t)hError);
pHandle->SpeedRefUnitExt = wCurrentReference;
pHandle->DutyCycleRef = ((int32_t)hDutyCycleReference) * 65536;
}
else
{
pHandle->DutyCycleRef = wCurrentReference;
#ifdef NO_FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hDutyCycleReference = (int16_t)(wCurrentReference >> 16);
#else
hDutyCycleReference = (int16_t)(wCurrentReference / 65536);
#endif
}
}
return (hDutyCycleReference);
}
/**
* @brief Get the Default mechanical rotor speed reference.
* Expressed in the unit defined by #SPEED_UNIT.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval int16_t It returns the Default mechanical rotor speed.
* Expressed in the unit defined by #SPEED_UNIT
*/
__weak int16_t STC_GetMecSpeedRefUnitDefault(SpeednTorqCtrl_Handle_t *pHandle)
{
return ((MC_NULL == pHandle) ? 0 : pHandle->MecSpeedRefUnitDefault);
}
/**
* @brief Returns the Application maximum positive value of rotor speed. Expressed in the unit defined by #SPEED_UNIT.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
*/
__weak uint16_t STC_GetMaxAppPositiveMecSpeedUnit(SpeednTorqCtrl_Handle_t *pHandle)
{
return ((MC_NULL == pHandle) ? 0U : pHandle->MaxAppPositiveMecSpeedUnit);
}
/**
* @brief Returns the Application minimum negative value of rotor speed. Expressed in the unit defined by #SPEED_UNIT.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
*/
__weak int16_t STC_GetMinAppNegativeMecSpeedUnit(SpeednTorqCtrl_Handle_t *pHandle)
{
return ((MC_NULL == pHandle) ? 0 : pHandle->MinAppNegativeMecSpeedUnit);
}
/**
* @brief Check if the settled speed ramp has been completed.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval bool It returns true if the ramp is completed, false otherwise.
*/
__weak bool STC_RampCompleted(SpeednTorqCtrl_Handle_t *pHandle)
{
bool retVal = false;
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
if (0U == pHandle->RampRemainingStep)
{
retVal = true;
}
}
return (retVal);
}
/**
* @brief Stop the execution of speed ramp.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval bool It returns true if the command is executed, false otherwise.
*/
__weak bool STC_StopSpeedRamp(SpeednTorqCtrl_Handle_t *pHandle)
{
bool retVal = false;
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
if (MCM_SPEED_MODE == pHandle->Mode)
{
pHandle->RampRemainingStep = 0u;
retVal = true;
}
}
return (retVal);
}
/**
* @brief Force the speed reference to the curren speed. It is used
* at the START_RUN state to initialize the speed reference.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component
* @retval none
*/
__weak void STC_ForceSpeedReferenceToCurrentSpeed(SpeednTorqCtrl_Handle_t *pHandle)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->SpeedRefUnitExt = ((int32_t)SPD_GetAvrgMecSpeedUnit(pHandle->SPD)) * (int32_t)65536;
}
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 16,565 | C | 31.042553 | 120 | 0.652883 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/revup_ctrl.c | /**
******************************************************************************
* @file revup_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Rev-Up Control component of the Motor Control SDK:
*
* * Main Rev-Up procedure to execute programmed phases
* * On the Fly (OTF)
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
* @ingroup RevUpCtrlFOC
*/
/* Includes ------------------------------------------------------------------*/
#include "revup_ctrl.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup RevUpCtrl Rev-Up Control
* @brief Rev-Up Control component of the Motor Control SDK
*
* Used to start up the motor with a set of pre-programmed phases.
*
* The number of phases of the Rev-Up procedure range is from 0 to 5.
* The Rev-Up controller must be called at speed loop frequency.
*
* @{
*/
/** @defgroup RevUpCtrlFOC FOC Rev-Up Control component
* @brief Rev-Up control component used to start motor driven with
* the Field Oriented Control technique
*
* @{
*/
/* Private defines -----------------------------------------------------------*/
/**
* @brief Timeout used to reset integral term of PLL.
* It is expressed in ms.
*
*/
#define RUC_OTF_PLL_RESET_TIMEOUT 100u
/* Private functions ----------------------------------------------------------*/
/* Returns the mechanical speed of a selected phase */
//cstat !MISRAC2012-Rule-8.13
static int16_t RUC_GetPhaseFinalMecSpeed01Hz(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase)
{
return (pHandle->ParamsData[bPhase].hFinalMecSpeedUnit);
}
/**
* @brief Initialize and configure the FOC RevUpCtrl Component
* @param pHandle: Pointer on Handle structure of FOC RevUp controller.
* @param pSTC: Pointer on speed and torque controller structure.
* @param pVSS: Pointer on virtual speed sensor structure.
* @param pSNSL: Pointer on sensorless state observer structure.
* @param pPWM: Pointer on the PWM structure.
*/
__weak void RUC_Init(RevUpCtrl_Handle_t *pHandle,
SpeednTorqCtrl_Handle_t *pSTC,
VirtualSpeedSensor_Handle_t *pVSS,
STO_Handle_t *pSNSL,
PWMC_Handle_t *pPWM)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
RevUpCtrl_PhaseParams_t *pRUCPhaseParams = &pHandle->ParamsData[0];
uint8_t bPhase = 0U;
pHandle->pSTC = pSTC;
pHandle->pVSS = pVSS;
pHandle->pSNSL = pSNSL;
pHandle->pPWM = pPWM;
pHandle->OTFSCLowside = false;
pHandle->EnteredZone1 = false;
while ((pRUCPhaseParams != MC_NULL) && (bPhase < RUC_MAX_PHASE_NUMBER))
{
/* Dump HF data for now HF data are forced to 16 bits */
pRUCPhaseParams = (RevUpCtrl_PhaseParams_t *)pRUCPhaseParams->pNext; //cstat !MISRAC2012-Rule-11.5
bPhase++;
}
if (0U == bPhase)
{
/* nothing to do error */
}
else
{
pHandle->ParamsData[bPhase - 1u].pNext = MC_NULL;
pHandle->bPhaseNbr = bPhase;
pHandle->bResetPLLTh = (uint8_t)((RUC_OTF_PLL_RESET_TIMEOUT * pHandle->hRUCFrequencyHz) / 1000U);
}
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
}
/**
* @brief Initialize internal FOC RevUp controller state.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param hMotorDirection: Rotor rotation direction.
* This parameter must be -1 or +1.
*/
__weak void RUC_Clear(RevUpCtrl_Handle_t *pHandle, int16_t hMotorDirection)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
VirtualSpeedSensor_Handle_t *pVSS = pHandle->pVSS;
SpeednTorqCtrl_Handle_t *pSTC = pHandle->pSTC;
RevUpCtrl_PhaseParams_t *pPhaseParams = pHandle->ParamsData;
pHandle->hDirection = hMotorDirection;
pHandle->EnteredZone1 = false;
/* Initializes the rev up stages counter */
pHandle->bStageCnt = 0U;
pHandle->bOTFRelCounter = 0U;
pHandle->OTFSCLowside = false;
/* Calls the clear method of VSS */
VSS_Clear(pVSS);
/* Sets the STC in torque mode */
STC_SetControlMode(pSTC, MCM_TORQUE_MODE);
/* Sets the mechanical starting angle of VSS */
VSS_SetMecAngle(pVSS, pHandle->hStartingMecAngle * hMotorDirection);
/* Sets to zero the starting torque of STC */
(void)STC_ExecRamp(pSTC, 0, 0U);
/* Gives the first command to STC and VSS */
(void)STC_ExecRamp(pSTC, pPhaseParams->hFinalTorque * hMotorDirection, (uint32_t)(pPhaseParams->hDurationms));
VSS_SetMecAcceleration(pVSS, pPhaseParams->hFinalMecSpeedUnit * hMotorDirection, pPhaseParams->hDurationms);
/* Compute hPhaseRemainingTicks */
pHandle->hPhaseRemainingTicks = (uint16_t)((((uint32_t)pPhaseParams->hDurationms)
* ((uint32_t)pHandle->hRUCFrequencyHz))
/ 1000U );
pHandle->hPhaseRemainingTicks++;
/* Set the next phases parameter pointer */
pHandle->pCurrentPhaseParams = (RevUpCtrl_PhaseParams_t *)pPhaseParams->pNext; //cstat !MISRAC2012-Rule-11.5
/* Timeout counter for PLL reset during OTF */
pHandle->bResetPLLCnt = 0U;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
}
/**
* @brief FOC Main Rev-Up controller procedure executing overall programmed phases and
* on-the-fly startup handling.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to false when entire Rev-Up phases have been completed.
*/
__weak bool RUC_OTF_Exec(RevUpCtrl_Handle_t *pHandle)
{
bool retVal = true;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
bool IsSpeedReliable;
bool condition = false;
if (pHandle->hPhaseRemainingTicks > 0u)
{
/* Decrease the hPhaseRemainingTicks */
pHandle->hPhaseRemainingTicks--;
/* OTF start-up */
if (0U == pHandle->bStageCnt)
{
if (false == pHandle->EnteredZone1)
{
if (pHandle->pSNSL->pFctStoOtfResetPLL != MC_NULL)
{
pHandle->bResetPLLCnt++;
if (pHandle->bResetPLLCnt > pHandle->bResetPLLTh)
{
pHandle->pSNSL->pFctStoOtfResetPLL(pHandle->pSNSL);
pHandle->bOTFRelCounter = 0U;
pHandle->bResetPLLCnt = 0U;
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
IsSpeedReliable = pHandle->pSNSL->pFctSTO_SpeedReliabilityCheck(pHandle->pSNSL);
if (IsSpeedReliable)
{
if (pHandle->bOTFRelCounter < 127U)
{
pHandle->bOTFRelCounter++;
}
else
{
/* Nothing to do */
}
}
else
{
pHandle->bOTFRelCounter = 0U;
}
if (pHandle->pSNSL->pFctStoOtfResetPLL != MC_NULL)
{
if (pHandle->bOTFRelCounter == (pHandle->bResetPLLTh >> 1))
{
condition = true;
}
else
{
/* Nothing to do */
}
}
else
{
if (127U == pHandle->bOTFRelCounter)
{
condition = true;
}
else
{
/* Nothing to do */
}
}
if (true == condition)
{
bool bCollinearSpeed = false;
int16_t hObsSpeedUnit = SPD_GetAvrgMecSpeedUnit(pHandle->pSNSL->_Super);
int16_t hObsSpeedUnitAbsValue =
((hObsSpeedUnit < 0) ? (-hObsSpeedUnit) : (hObsSpeedUnit)); /* hObsSpeedUnit absolute value */
if (pHandle->hDirection > 0)
{
if (hObsSpeedUnit > 0)
{
bCollinearSpeed = true; /* Actual and reference speed are collinear */
}
else
{
/* Nothing to do */
}
}
else
{
if (hObsSpeedUnit < 0)
{
bCollinearSpeed = true; /* Actual and reference speed are collinear */
}
else
{
/* Nothing to do */
}
}
if (false == bCollinearSpeed)
{
/*reverse speed management*/
pHandle->bOTFRelCounter = 0U;
}
else /* Speeds are collinear */
{
if ((uint16_t)(hObsSpeedUnitAbsValue) > pHandle->hMinStartUpValidSpeed)
{
/* Startup end, go to run */
pHandle->pSNSL->pFctForceConvergency1(pHandle->pSNSL);
pHandle->EnteredZone1 = true;
}
else if ((uint16_t)(hObsSpeedUnitAbsValue) > pHandle->hMinStartUpFlySpeed)
{
/* Synch with startup */
/* Nearest phase search */
int16_t hOldFinalMecSpeedUnit = 0;
int16_t hOldFinalTorque = 0;
int32_t wDeltaSpeedRevUp;
int32_t wDeltaTorqueRevUp;
bool bError = false;
VSS_SetCopyObserver(pHandle->pVSS);
pHandle->pSNSL->pFctForceConvergency2(pHandle->pSNSL);
if (MC_NULL == pHandle->pCurrentPhaseParams)
{
bError = true;
pHandle->hPhaseRemainingTicks = 0U;
}
else
{
while (pHandle->pCurrentPhaseParams->hFinalMecSpeedUnit < hObsSpeedUnitAbsValue)
{
if (pHandle->pCurrentPhaseParams->pNext == MC_NULL)
{
/* Sets for Revup fail error */
bError = true;
pHandle->hPhaseRemainingTicks = 0U;
break;
}
else
{
/* Skips this phase */
hOldFinalMecSpeedUnit = pHandle->pCurrentPhaseParams->hFinalMecSpeedUnit;
hOldFinalTorque = pHandle->pCurrentPhaseParams->hFinalTorque;
//cstat !MISRAC2012-Rule-11.5
pHandle->pCurrentPhaseParams = (RevUpCtrl_PhaseParams_t *)pHandle->pCurrentPhaseParams->pNext;
pHandle->bStageCnt++;
}
}
}
if (false == bError)
{
/* Calculation of the transition phase from OTF to standard revup */
int16_t hTorqueReference;
wDeltaSpeedRevUp = ((int32_t)(pHandle->pCurrentPhaseParams->hFinalMecSpeedUnit))
- ((int32_t)(hOldFinalMecSpeedUnit));
wDeltaTorqueRevUp = ((int32_t)(pHandle->pCurrentPhaseParams->hFinalTorque))
- ((int32_t)(hOldFinalTorque));
if ((int32_t)0 == wDeltaSpeedRevUp)
{
/* Nothing to do */
}
else
{
hTorqueReference = (int16_t)((((int32_t)hObsSpeedUnit) * wDeltaTorqueRevUp) / wDeltaSpeedRevUp)
+ hOldFinalTorque;
(void)STC_ExecRamp(pHandle->pSTC, pHandle->hDirection * hTorqueReference, 0U);
}
pHandle->hPhaseRemainingTicks = 1U;
pHandle->pCurrentPhaseParams = &pHandle->OTFPhaseParams;
pHandle->bStageCnt = 6U;
} /* No MC_NULL error */
} /* Speed > MinStartupFly */
else
{
/* Nothing to do */
}
} /* Speeds are collinear */
} /* Speed is reliable */
}/* EnteredZone1 1 is false */
else
{
pHandle->pSNSL->pFctForceConvergency1(pHandle->pSNSL);
}
} /* Stage 0 */
} /* hPhaseRemainingTicks > 0 */
if (0U == pHandle->hPhaseRemainingTicks)
{
if (pHandle->pCurrentPhaseParams != MC_NULL)
{
if (0U == pHandle->bStageCnt)
{
/* End of OTF */
PWMC_SwitchOffPWM(pHandle->pPWM);
pHandle->OTFSCLowside = true;
PWMC_TurnOnLowSides(pHandle->pPWM, 0u);
pHandle->bOTFRelCounter = 0U;
}
else if (1U == pHandle->bStageCnt)
{
PWMC_SwitchOnPWM(pHandle->pPWM);
pHandle->OTFSCLowside = false;
}
else
{
/* Nothing to do */
}
/* If it becomes zero the current phase has been completed */
/* Gives the next command to STC and VSS */
(void)STC_ExecRamp(pHandle->pSTC, pHandle->pCurrentPhaseParams->hFinalTorque * pHandle->hDirection,
(uint32_t)(pHandle->pCurrentPhaseParams->hDurationms));
VSS_SetMecAcceleration(pHandle->pVSS,
pHandle->pCurrentPhaseParams->hFinalMecSpeedUnit * pHandle->hDirection,
pHandle->pCurrentPhaseParams->hDurationms);
/* Compute hPhaseRemainingTicks */
pHandle->hPhaseRemainingTicks = (uint16_t)((((uint32_t)pHandle->pCurrentPhaseParams->hDurationms)
* (uint32_t)pHandle->hRUCFrequencyHz) / 1000U);
pHandle->hPhaseRemainingTicks++;
/* Set the next phases parameter pointer */
pHandle->pCurrentPhaseParams = pHandle->pCurrentPhaseParams->pNext; //cstat !MISRAC2012-Rule-11.5
/* Increases the rev up stages counter */
pHandle->bStageCnt++;
}
else
{
if (pHandle->bStageCnt == (pHandle->bPhaseNbr - (uint8_t)1)) /* End of user programmed revup */
{
retVal = false;
}
else if (7U == pHandle->bStageCnt) /* End of first OTF runs */
{
pHandle->bStageCnt = 0U; /* Breaking state */
pHandle->hPhaseRemainingTicks = 0U;
}
else
{
/* Nothing to do */
}
}
}
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
return (retVal);
}
/**
* @brief FOC Main Rev-Up controller procedure executing overall programmed phases.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to false when entire Rev-Up phases have been completed.
*/
__weak bool RUC_Exec(RevUpCtrl_Handle_t *pHandle)
{
bool retVal = true;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
retVal = false;
}
else
{
#endif
if (pHandle->hPhaseRemainingTicks > 0U)
{
/* Decrease the hPhaseRemainingTicks */
pHandle->hPhaseRemainingTicks--;
} /* hPhaseRemainingTicks > 0 */
else
{
/* Nothing to do */
}
if (0U == pHandle->hPhaseRemainingTicks)
{
if (pHandle->pCurrentPhaseParams != MC_NULL)
{
/* If it becomes zero the current phase has been completed */
/* Gives the next command to STC and VSS */
(void)STC_ExecRamp(pHandle->pSTC, pHandle->pCurrentPhaseParams->hFinalTorque * pHandle->hDirection,
(uint32_t)(pHandle->pCurrentPhaseParams->hDurationms));
VSS_SetMecAcceleration(pHandle->pVSS,
pHandle->pCurrentPhaseParams->hFinalMecSpeedUnit * pHandle->hDirection,
pHandle->pCurrentPhaseParams->hDurationms);
/* Compute hPhaseRemainingTicks */
pHandle->hPhaseRemainingTicks = (uint16_t)((((uint32_t)pHandle->pCurrentPhaseParams->hDurationms)
* ((uint32_t)pHandle->hRUCFrequencyHz)) / 1000U );
pHandle->hPhaseRemainingTicks++;
/* Set the next phases parameter pointer */
pHandle->pCurrentPhaseParams = pHandle->pCurrentPhaseParams->pNext; //cstat !MISRAC2012-Rule-11.5
/* Increases the rev up stages counter */
pHandle->bStageCnt++;
}
else
{
retVal = false;
}
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
return (retVal);
}
/**
* @brief It checks if this stage is used for align motor.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Returns 1 if the alignment is correct otherwise it returns 0
*/
//cstat !MISRAC2012-Rule-8.13
uint8_t RUC_IsAlignStageNow(RevUpCtrl_Handle_t *pHandle)
{
uint8_t align_flag = 0;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int16_t speed;
speed = RUC_GetPhaseFinalMecSpeed01Hz(pHandle, pHandle->bStageCnt);
if (0 == speed)
{
align_flag = 1;
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
return (align_flag);
}
/**
* @brief Provide current state of Rev-Up controller procedure.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to true when entire Rev-Up phases have been completed.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool RUC_Completed(RevUpCtrl_Handle_t *pHandle)
{
bool retVal = false;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (MC_NULL == pHandle->pCurrentPhaseParams)
{
retVal = true;
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
return (retVal);
}
/**
* @brief Allow to exit from Rev-Up process at the current rotor speed.
* @param pHandle: Pointer on Handle structure of RevUp controller.
*/
__weak void RUC_Stop(RevUpCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
VirtualSpeedSensor_Handle_t *pVSS = pHandle->pVSS;
pHandle->pCurrentPhaseParams = MC_NULL;
pHandle->hPhaseRemainingTicks = 0U;
VSS_SetMecAcceleration(pVSS, SPD_GetAvrgMecSpeedUnit(&pVSS->_Super), 0U);
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Check that alignment and first acceleration stage are completed.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to true when first acceleration stage has been reached.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool RUC_FirstAccelerationStageReached(RevUpCtrl_Handle_t *pHandle)
{
bool retVal = false;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (pHandle->bStageCnt >= pHandle->bFirstAccelerationStage)
{
retVal = true;
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
return (retVal);
}
/**
* @brief Allow to modify duration of a selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase where new duration shall be modified.
* This parameter must be a number between 0 and 6.
* @param hDurationms: new duration value required for associated phase.
* This parameter must be set in millisecond.
*/
__weak void RUC_SetPhaseDurationms(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase, uint16_t hDurationms)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->ParamsData[bPhase].hDurationms = hDurationms;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
}
/**
* @brief Allow to modify targeted mechanical speed of a selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase where new mechanical speed shall be modified.
* This parameter must be a number between 0 and 6.
* @param hFinalMecSpeedUnit: new targeted mechanical speed.
* This parameter must be expressed in 0.1Hz.
*/
__weak void RUC_SetPhaseFinalMecSpeedUnit(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase, int16_t hFinalMecSpeedUnit)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->ParamsData[bPhase].hFinalMecSpeedUnit = hFinalMecSpeedUnit;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
}
/**
* @brief Allow to modify targeted the motor torque of a selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase where new the motor torque shall be modified.
* This parameter must be a number between 0 and 6.
* @param hFinalTorque: new targeted motor torque.
*/
__weak void RUC_SetPhaseFinalTorque(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase, int16_t hFinalTorque)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->ParamsData[bPhase].hFinalTorque = hFinalTorque;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
}
/**
* @brief Allow to configure a Rev-Up phase.
* @param pHandle: Pointer on Handle structure of Rev-Up controller.
* @param phaseNumber : number of phases relative to the programmed Rev-Up
* @param phaseData:
* - RevUp phase where new motor torque shall be modified.
* This parameter must be a number between 0 and 6.
* - RevUp phase where new mechanical speed shall be modified.
* This parameter must be a number between 0 and 6.
* - New duration value required for associated phase in ms unit.
* @retval Boolean set to true
*/
__weak bool RUC_SetPhase(RevUpCtrl_Handle_t *pHandle, uint8_t phaseNumber, RevUpCtrl_PhaseParams_t *phaseData)
{
bool retValue = true;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if ((MC_NULL == pHandle) || (MC_NULL == phaseData))
{
retValue = false;
}
else
{
#endif
pHandle->ParamsData[phaseNumber].hFinalTorque = phaseData->hFinalTorque;
pHandle->ParamsData[phaseNumber].hFinalMecSpeedUnit = phaseData->hFinalMecSpeedUnit;
pHandle->ParamsData[phaseNumber].hDurationms = phaseData->hDurationms;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
return (retValue);
}
/**
* @brief Allow to read duration set in selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase from where duration is read.
* This parameter must be a number between 0 and 6.
* @retval Returns duration used in selected phase in ms unit.
*/
//cstat !MISRAC2012-Rule-8.13
__weak uint16_t RUC_GetPhaseDurationms(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
return ((MC_NULL == pHandle) ? 0U : (uint16_t)pHandle->ParamsData[bPhase].hDurationms);
#else
return ((uint16_t)pHandle->ParamsData[bPhase].hDurationms);
#endif
}
/**
* @brief Allow to read targeted rotor speed set in selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase from where targeted rotor speed is read.
* This parameter must be a number between 0 and 6.
* @retval Returns targeted rotor speed set for a selected phase.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t RUC_GetPhaseFinalMecSpeedUnit(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
return ((MC_NULL == pHandle) ? 0 : (int16_t)pHandle->ParamsData[bPhase].hFinalMecSpeedUnit);
#else
return ((int16_t)pHandle->ParamsData[bPhase].hFinalMecSpeedUnit);
#endif
}
/**
* @brief Allow to read targeted motor torque set in selected phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param bPhase: RevUp phase from where targeted motor torque is read.
* This parameter must be a number between 0 and 6.
* @retval Returns targeted motor torque set for a selected phase.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t RUC_GetPhaseFinalTorque(RevUpCtrl_Handle_t *pHandle, uint8_t bPhase)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
return ((MC_NULL == pHandle) ? 0 : (int16_t)pHandle->ParamsData[bPhase].hFinalTorque);
#else
return ((int16_t)pHandle->ParamsData[bPhase].hFinalTorque);
#endif
}
/**
* @brief Allow to read total number of programmed phases.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Returns number of phases relative to the programmed Rev-Up.
*
*/
//cstat !MISRAC2012-Rule-8.13
__weak uint8_t RUC_GetNumberOfPhases(RevUpCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
return ((MC_NULL == pHandle) ? 0U : (uint8_t)pHandle->bPhaseNbr);
#else
return ((uint8_t)pHandle->bPhaseNbr);
#endif
}
/**
* @brief Allow to read a programmed phase.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @param phaseNumber : number of phases relative to the programmed Rev-Up
* @param phaseData:
* - RevUp phase from where targeted rotor speed is read.
* This parameter must be a number between 0 and 6.
* - RevUp phase from where targeted motor torque is read.
* This parameter must be a number between 0 and 6.
* - Duration set in selected phase in ms unit.
* @retval Returns Boolean set to true value.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool RUC_GetPhase(RevUpCtrl_Handle_t *pHandle, uint8_t phaseNumber, RevUpCtrl_PhaseParams_t *phaseData)
{
bool retValue = true;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
if ((MC_NULL == pHandle) || (MC_NULL == phaseData))
{
retValue = false;
}
else
{
#endif
phaseData->hFinalTorque = (int16_t)pHandle->ParamsData[phaseNumber].hFinalTorque;
phaseData->hFinalMecSpeedUnit = (int16_t)pHandle->ParamsData[phaseNumber].hFinalMecSpeedUnit;
phaseData->hDurationms = (uint16_t)pHandle->ParamsData[phaseNumber].hDurationms;
#ifdef NULL_PTR_CHECK_REV_UP_CTL
}
#endif
return (retValue);
}
/**
* @brief Allow to read status of On The Fly (OTF) feature.
* @param pHandle: Pointer on Handle structure of RevUp controller.
* @retval Boolean set to true at the end of OTF processing.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool RUC_Get_SCLowsideOTF_Status(RevUpCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_REV_UP_CTL
return ((MC_NULL == pHandle) ? false : pHandle->OTFSCLowside);
#else
return (pHandle->OTFSCLowside);
#endif
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 29,303 | C | 30.68 | 116 | 0.601884 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/cos_sin.c | /**
******************************************************************************
* @file cos_sin.c
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
//
#include "math_defs.h"
// Needed for printf(), etc.
// #include <stdio.h>
//
// Assumes a normalized angle: 0 <= th/(2*pi) <= 1.
// Fast poly z = cos(th) + j*sin(th) int32 precision,
// for any value of th using 10th order polynomial
// approximations, absolute error = |e| < 10^-5. See:
// Abramowitz and Stegun, "Handbook of Mathematical
// Functions", p. 76. Polynomial coeffs. in cordicx.h
//
// cos_sin_poly_L(&zi);
//
void cos_sin_poly_L(DQL zi) {
//
// Cos, Sin coeffs.
static long long ccsi[_CSSN], csni[_CSSN];
static long long pi2, pi, hpi, one;
static int ob, n = 0;
// Misc. variables.
int b, bb, hth, i, quad;
long long th, th2, cs, sn;
// Number of bits.
b = zi->b;
// Convert coefficients?
if (b != ob) {
// Difference bits.
bb = _MNB - b;
ob = b;
// Move & scale cos,sin coeffs.
for (i = 0; i < _CSSN; i++) {
// Scale coeffs.
ccsi[i] = _ccsl[i] >> bb;
csni[i] = _csnl[i] >> bb;
// Both coefs. zero?
if (ccsi[i] == 0LL && csni[i] == 0LL)
break;
}
// Last non-zero coefficients.
n = i;
// Constants.
pi2 = _PII2 >> bb;
pi = _PII >> bb;
hpi = _HPII >> bb;
one = _ONEI >> bb;
}
// th = thr/(2*pi).
th = (zi->thr*pi) >> (zi->b - 1);
// |th| > pi?
if (th > pi)
th -= pi2;
else if (th < -pi)
th += pi2;
// Get quadrant.
if (th > _ZERO) {
if (th > hpi) {
th -= hpi;
quad = 1;
}
else
quad = 0;
}
else {
if (th < -hpi) {
th += hpi;
quad = 2;
}
else
quad = 3;
}
// 1/2 Angle avoids overflow.
hth = (int) (llabs(th) > one) ? 1:0;
if (hth) {
th = th >> 1;
}
// Angle squared.
th2 = (th*th) >> b;
// Initialize.
cs = ccsi[n-1];
sn = csni[n-1];
// Nested polynomial evaluation.
for (i = n-2; i >= 0; i--) {
cs = ((cs*th2) >> b) + ccsi[i];
sn = ((sn*th2) >> b) + csni[i];
}
// Complete Sin.
sn = (sn*th) >> b;
// Half angle conversion?
if (hth) {
// sin(x) = 2*cos(x/2)*sin(x/2).
sn = (cs*sn) >> (b - 1);
// cos(x) = 2*cos(x/2)*cos(x/2) - 1.
cs = ((cs*cs) >> (b - 1)) - one;
}
// Quadrant conversion.
switch (quad) {
case 0:
zi->x = (long) cs;
zi->y = (long) sn;
return;
case 1:
zi->x = (long) -sn;
zi->y = (long) cs;
return;
case 2:
zi->x = (long) sn;
zi->y = (long) -cs;
return;
case 3:
zi->x = (long) cs;
zi->y = (long) sn;
default:
return;
}
}
//
// Assumes a normalized angle: 0 <= th/(2*pi) <= 1.
// Fast table z = cos(th) + j*sin(th) (long) precision,
// for any value of th using m+1 entry cos table + Taylor
// extrapolation or linear interpolation, absolute.
//
// cos_sin_tabl_L(&zi, m);
//
void cos_sin_tabl_L(DQL zi, int m) {
//
static long dth, dthi, sixi, pi, pi2, hpi, one;
static int tpk, bb, ob = 0, om = 0;
//
long th, ths, thf, thr, thr2, cs, sn, dcs, dsn;
int i, k, b, mk, quad;
// Number of bits.
b = zi->b;
// Fill table?
if (_cstl[0] == 0LL || b != ob || m != om) {
// Find tpk, m = 2^tpk.
tpk = log2i(m);
om = m;
// Difference bits.
bb = _MNB - b;
ob = b;
// Constants scaled to b.
one = _ONEI >> bb;
dthi = _HPIII >> bb;
hpi = _HPII >> bb;
pi = _PII >> bb;
pi2 = _PII2 >> bb;
sixi = _SIXII >> bb;
// Theta increment 2^-tpk.
dth = (long ) (one >> (tpk + 2));
(void) dth; /* Suppress warning not used */
th = 0LL;
// Save old value.
ths = zi->thr;
// 1st and last entries.
_cstl[0] = one;
_cstl[m] = _ZERO;
mk = _MTL >> tpk;
#if 0
// Use poly to fill cos table.
for (k = 1; k < m; k++) {
// Fraction of pi/2.
th += dth;
zi->thr = (long)th;
// Int Cos,sin poly.
cos_sin_poly_L(zi);
// Cos only for table.
_cstl[k] = zi->x;
}
#else
// Scaled subset cos table entries.
for (i = 1, k = mk; k < _MTL; k += mk, i++)
_cstl[i] = _cst_128[k] >> bb;
#endif
// Restore old value.
zi->thr = ths;
}
// th = |thr|/(2*pi).
th = (llabs(zi->thr)*hpi) >> (b - 2);
// |th| > pi?
if (th > pi)
th -= pi2;
// Get quadrant.
if (th > _ZERO) {
if (th > hpi) {
th -= pi;
quad = 1;
}
else
quad = 0;
}
else {
if (th < -hpi) {
th += pi;
quad = 2;
}
else
quad = 3;
}
// ths = |th|*(2/pi).
ths = (labs(th)*dthi) >> (b - tpk);
// k = ths/m, 0 <= k < m.
k = (int) (ths >> b);
// thf = (ths - k*m).
// Note use of bit ops.
thf = ths & ~(k << b);
// Table Cos, Sin.
cs = _cstl[k];
mk = m - k;
sn = _cstl[mk];
// Extrapolation method?
if (m <= 16) {
// thr = (ths - k)*((pi/2)/m).
thr = (thf*hpi) >> (b + tpk);
// thr2 = thr*thr.
thr2 = (thr*thr) >> b;
// dcs = 1 - (thr*thr/2).
dcs = one - (thr2 >> 1);
// dsn = thr*(1 - thr*thr/6).
dsn = (thr*(one - ((thr2*sixi) >> b)) >> b);
// Rotate Cos, Sin.
th = (dcs*cs - dsn*sn) >> b;
sn = (dcs*sn + dsn*cs) >> b;
cs = th;
}
// Linear interpolation.
else if (k < m) {
// Secant approximation.
cs += (((_cstl[k + 1] - cs)*thf) >> b);
sn += (((_cstl[mk - 1] - sn)*thf) >> b);
}
// Quadrant conversion.
switch (quad) {
case 0:
zi->x = (long) cs;
zi->y = (long) sn;
return;
case 1:
zi->x = (long) -cs;
zi->y = (long) sn;
return;
case 2:
zi->x = (long) -cs;
zi->y = (long) -sn;
return;
case 3:
zi->x = (long) cs;
zi->y = (long) -sn;
default:
return;
}
}
//
// Assumes a normalized angle: 0 <= th/(2*pi) < 1.
// Fast table z = cos(th) + j*sin(th) (long) precision,
// for a value of th using 4*m+2 entry cos table + Taylor
// extrapolation or linear interpolation, absolute.
//
// cos_sin_tabl_LX(&zi, m);
//
void cos_sin_tabl_LX(DQL zi, int m) {
//
static long dth, hpi;
static long one, sixth;
static int tpk, bb, ob = 0, om = 0;
(void) dth; /* Suppress warning not used */
//
long th, ths, thf, thr, thr2, cs, sn, dcs, dsn;
int i, k, b, mk, m4;
// Number of bits.
b = zi->b;
// Table length * 4.
m4 = m << 2;
// Fill table?
if (_cstl[0] == 0L || b != ob || m4 != om) {
// Find tpk, m = 2^tpk.
tpk = log2i(m);
om = m4;
// Difference bits.
bb = _MNB - b;
ob = b;
// Constants scaled to b.
one = (long) (_ONEI >> bb);
sixth = (long) (_SIXII >> bb);
hpi = (long) (_HPII >> bb);
// Decimation factor.
mk = _MTL >> tpk;
// Quadrant = 0 cos.
for (i = 0, k = 0; k <= _MTL; k += mk, i++) {
_cstl[i] = _cst_128[k] >> bb;
// Next lower 2 bits.
ths = _cst_128[k] >> (bb - 2);
// Next 2 lower bits on?
if ((ths & 3) == 3)
// Round up.
_cstl[i] += 1;
}
// Quadrant = 1 cos.
for (k = i, i = 0; i <= m; i++)
_cstl[i+m] = -_cstl[--k];
// Quadrants = 2, 3 cos.
for (i += m, k = i-1; i <= m4; i++)
_cstl[i] = _cstl[--k];
// Extra point.
_cstl[i] = _cstl[i-1];
}
// th = |thr|.
th = labs(zi->thr);
// ths = |th|*m*4.
ths = labs(th) << (tpk + 2);
// k = ths/m, 0 <= k < m.
k = (int) (ths >> b);
// thf = (ths - k*m).
// Note use of bit ops.
thf = ths & ~(k << b);
// Cos value.
cs = _cstl[k];
// Modulo m4 index.
mk = m + k;
if (mk > m4)
mk -= m4;
// Sin value.
sn = -_cstl[mk];
// Extrapolation method?
if (m <= 16) {
// thr = (ths - k)*((pi/2)/m).
thr = (thf*hpi) >> (b + tpk);
// thr2 = thr*thr.
thr2 = (thr*thr) >> b;
// dcs = 1 - (thr*thr/2).
dcs = one - (thr2 >> 1);
// dsn = thr*(1 - thr*thr/6).
dsn = (thr*(one - ((thr2*sixth) >> b)) >> b);
// Rotate Cos, Sin.
th = (dcs*cs - dsn * sn) >> b;
sn = (dcs*sn + dsn * cs) >> b;
cs = th;
}
// Linear interpolation.
else {
cs += (((_cstl[k + 1] - cs)*thf) >> b);
sn -= (((_cstl[mk + 1] + sn)*thf) >> b);
}
// Save results.
zi->x = cs;
zi->y = sn;
}
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 8,399 | C | 18.090909 | 94 | 0.477081 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/profiler_impedest.c | /**
******************************************************************************
* @file profiler_dcac.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions of profiler DC/AC
* component
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*
*/
/* Includes ------------------------------------------------------------------*/
#include "profiler_impedest.h"
/**
* @brief todo
*
*/
void PROFILER_IMPEDEST_init(PROFILER_IMPEDEST_Handle handle)
{
handle->flag_inject = false;
}
/**
* @brief todo
*
*/
void PROFILER_IMPEDEST_setParams(PROFILER_IMPEDEST_Obj *obj, PROFILER_Params *pParams)
{
obj->isrPeriod_ms = FIXP30(1000.0f / pParams->isrFreq_Hz);
obj->fullScaleCurrent_A = pParams->fullScaleCurrent_A;
obj->fullScaleVoltage_V = pParams->fullScaleVoltage_V;
float_t inject_freq_hz = 80.0f;
obj->injectFreqKhz = FIXP30(inject_freq_hz / 1000.0f);
obj->flag_inject = false;
obj->inject_ref = 0;
float_t filt_freq_radps = inject_freq_hz / 10.0f * M_TWOPI;
obj->filt = FIXP30(filt_freq_radps / pParams->isrFreq_Hz);
obj->angle_inject_pu = 0;
obj->inject_out = 0;
obj->dither = 0;
}
/**
* @brief todo
*
*/
void PROFILER_IMPEDEST_run(PROFILER_IMPEDEST_Obj *obj, fixp30_t Ua_pu, fixp30_t Ia_pu)
{
if (obj->flag_inject)
{
/* Rotate angle */
fixp30_t angle_inject_pu = obj->angle_inject_pu;
angle_inject_pu += FIXP30_mpy(obj->injectFreqKhz, obj->isrPeriod_ms);
angle_inject_pu = angle_inject_pu & (FIXP30(1.0f) - 1);
obj->angle_inject_pu = angle_inject_pu;
/* Generate inject signal */
FIXP_CosSin_t cossin;
FIXP30_CosSinPU(angle_inject_pu, &cossin);
obj->inject_out = FIXP30_mpy(obj->inject_ref, cossin.cos);
/* Dithering */
fixp30_t dither = obj->dither;
dither = dither ^ 1;
obj->dither = dither;
Ua_pu += dither;
Ia_pu += dither;
/* Demodulate U */
Vector_dq_t demod;
demod.D = FIXP30_mpy(Ua_pu, cossin.cos);
demod.Q = FIXP30_mpy(Ua_pu, cossin.sin);
/* Filter U */
fixp30_t filt = obj->filt;
obj->U_demod_lp1.D += FIXP30_mpy((demod.D - obj->U_demod_lp1.D), filt);
obj->U_demod_lp1.Q += FIXP30_mpy((demod.Q - obj->U_demod_lp1.Q), filt);
obj->U_demod_lp2.D += FIXP30_mpy((obj->U_demod_lp1.D - obj->U_demod_lp2.D), filt);
obj->U_demod_lp2.Q += FIXP30_mpy((obj->U_demod_lp1.Q - obj->U_demod_lp2.Q), filt);
/* Demodulate I */
demod.D = FIXP30_mpy(Ia_pu, cossin.cos);
demod.Q = FIXP30_mpy(Ia_pu, cossin.sin);
/* Filter I */
obj->I_demod_lp1.D += FIXP30_mpy((demod.D - obj->I_demod_lp1.D), filt);
obj->I_demod_lp1.Q += FIXP30_mpy((demod.Q - obj->I_demod_lp1.Q), filt);
obj->I_demod_lp2.D += FIXP30_mpy((obj->I_demod_lp1.D - obj->I_demod_lp2.D), filt);
obj->I_demod_lp2.Q += FIXP30_mpy((obj->I_demod_lp1.Q - obj->I_demod_lp2.Q), filt);
}
}
/**
* @brief todo
*
*/
void PROFILER_IMPEDEST_calculate(PROFILER_IMPEDEST_Obj *obj)
{
/* Determine angle and magnitude of demodulated current vector */
fixp30_t I_angle_pu, I_magn_pu;
FIXP30_polar(obj->I_demod_lp2.D, obj->I_demod_lp2.Q, &I_angle_pu, &I_magn_pu);
/* Rotate demodulated voltage vector to align current vector with real axis */
FIXP_CosSin_t cossin;
Vector_dq_t U_demod_aligned_lp;
FIXP30_CosSinPU(I_angle_pu, &cossin);
U_demod_aligned_lp.D = FIXP30_mpy(obj->U_demod_lp2.D, cossin.cos) + FIXP30_mpy(obj->U_demod_lp2.Q, cossin.sin);
U_demod_aligned_lp.Q = FIXP30_mpy(obj->U_demod_lp2.Q, cossin.cos) - FIXP30_mpy(obj->U_demod_lp2.D, cossin.sin);
/* Calculate R and L */
float_t I_magn_A = FIXP30_toF(I_magn_pu) * obj->fullScaleCurrent_A;
float_t tc = 1.0f / (FIXP30_toF(obj->injectFreqKhz) * 1000.0f * M_TWOPI);
obj->Rs = (FIXP30_toF(U_demod_aligned_lp.D) * obj->fullScaleVoltage_V) / I_magn_A;
obj->Ls = -(FIXP30_toF(U_demod_aligned_lp.Q) * obj->fullScaleVoltage_V) / I_magn_A * tc;
}
/* Accessors */
/* Getters */
/**
* @brief todo
*
*/
fixp30_t PROFILER_IMPEDEST_getInject(PROFILER_IMPEDEST_Obj *obj)
{
return obj->inject_out;
}
/**
* @brief todo
*
*/
float_t PROFILER_IMPEDEST_getLs(PROFILER_IMPEDEST_Obj *obj)
{
return obj->Ls;
}
/**
* @brief todo
*
*/
float_t PROFILER_IMPEDEST_getRs(PROFILER_IMPEDEST_Obj *obj)
{
return obj->Rs;
}
/* Setters */
/**
* @brief todo
*
*/
void PROFILER_IMPEDEST_setFlagInject(PROFILER_IMPEDEST_Obj *obj, const bool value)
{
obj->flag_inject = value;
if (obj->flag_inject == false)
{
obj->angle_inject_pu = 0;
obj->inject_out = 0;
}
}
/**
* @brief todo
*
*/
void PROFILER_IMPEDEST_setInjectFreq_kHz(PROFILER_IMPEDEST_Obj *obj, const fixp30_t value)
{
obj->injectFreqKhz = value;
}
/**
* @brief todo
*
*/
void PROFILER_IMPEDEST_setInjectRef(PROFILER_IMPEDEST_Obj *obj, const fixp30_t value)
{
obj->inject_ref = value;
}
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,352 | C | 25.369458 | 112 | 0.608931 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/esc.c | /**
******************************************************************************
* @file esc.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features of
* the esc component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "motorcontrol.h"
#include "esc.h"
/* Define --------------------------------------------------------------------*/
#define STOP_DURATION_SEC 2
#define USER_TIMEBASE_FREQUENCY_HZ 400
#define STOP_DURATION (STOP_DURATION_SEC * USER_TIMEBASE_FREQUENCY_HZ)
#define USER_TIMEBASE_OCCURENCE_TICKS (SYS_TICK_FREQUENCY/USER_TIMEBASE_FREQUENCY_HZ)-1u
#define USER_TIMEBASE_FREQUENCY_HZ_BEEP 400
#define USER_TIMEBASE_OCCURENCE_TICKS_BEEP (SYS_TICK_FREQUENCY/USER_TIMEBASE_FREQUENCY_HZ_BEEP)-1u
#define BEEP_FREQ_ARR 65000
#define BEEP_FREQ_ARR1 62000
#define BEEP_FREQ_ARR2 55000
#define BEEP_TIME_MAX 100
#define BEEP_TIME_MAX_CHECK 100
#define BEEP_DUTY 3000
static uint32_t esc_capture_filter(ESC_Handle_t * pHandle, uint32_t capture_value);
static void esc_reset_pwm_ch(ESC_Handle_t * pHandle);
#ifdef ESC_BEEP_FEATURE
static bool esc_beep_loop(ESC_Handle_t * pHandle, uint16_t number_beep);
static bool esc_phase_check(ESC_Handle_t * pHandle);
#endif
extern MCI_Handle_t * pMCI[NBR_OF_MOTORS];
/**
* @brief Boot function to initialize the ESC board.
* @retval none.
*/
void esc_boot(ESC_Handle_t * pHandle)
{
TIM_TypeDef * TIMx = pHandle->pESC_params->Command_TIM;
/*##- Start the Input Capture in interrupt mode ##########################*/
LL_TIM_CC_EnableChannel (TIMx, LL_TIM_CHANNEL_CH2);
LL_TIM_EnableIT_CC1 (TIMx);
LL_TIM_CC_EnableChannel (TIMx, LL_TIM_CHANNEL_CH1);
LL_TIM_EnableCounter(TIMx);
#ifdef ESC_BEEP_FEATURE
pHandle->beep_state = SM_BEEP_1;
pHandle->phase_check_status = false;
#endif
}
void esc_pwm_stop(ESC_Handle_t * pHandle)
{
MCI_StopMotor( pMCI[pHandle->pESC_params->motor] );
pHandle->sm_state = ESC_ARMING;
pHandle->restart_delay = STOP_DURATION;
pHandle->arming_counter = 0;
}
ESC_State_t esc_pwm_run(ESC_Handle_t * pHandle)
{
uint32_t new_speed;
ESC_Params_t const * pESC_params = pHandle->pESC_params;
bool cmd_status;
ESC_State_t ESC_Fault_Occured = ESC_NOERROR;
{
/* First we detect that we still receive signal from PWM input */
if(pHandle->watchdog_counter == pHandle->watchdog_counter_prev)
{
if(pHandle->pwm_timeout == 0)
{
/* Ton_Value is not updated anymore, set to 0 for safety*/
pHandle->Ton_value = 0;
ESC_Fault_Occured = ESC_NOSIGNAL;
}
else
{
pHandle->pwm_timeout--;
}
}
else
{
pHandle->pwm_timeout = pESC_params->PWM_TURNOFF_MAX;
pHandle->watchdog_counter_prev = pHandle->watchdog_counter;
esc_reset_pwm_ch(pHandle);
}
/* User defined code */
switch (pHandle->sm_state)
{
case ESC_ARMING:
{
if((pHandle->Ton_value >= pESC_params->Ton_arming) && (pHandle->Ton_value < pESC_params->Ton_min))
{
pHandle->arming_counter++;
if(pHandle->arming_counter > pESC_params->ARMING_TIME)
{
pHandle->sm_state = ESC_ARMED;
pHandle->arming_counter = 0;
pHandle->pwm_timeout = pESC_params->PWM_TURNOFF_MAX;
pHandle->watchdog_counter = 0;
pHandle->watchdog_counter_prev = 0;
}
}
else
{
pHandle->sm_state = ESC_ARMING;
pHandle->arming_counter = 0;
}
}
break;
case ESC_ARMED:
{
if (pHandle->Ton_value >= pESC_params->Ton_min)
{
/* Next state */
/* This command sets what will be the first speed ramp after the
MC_StartMotor1 command. It requires as first parameter the
target mechanical speed in thenth of Hz and as
second parameter the speed ramp duration in milliseconds. */
MCI_ExecSpeedRamp( pMCI[pESC_params->motor], (pESC_params->speed_min_valueRPM/6), 0 );
/* This is a user command used to start the motor. The speed ramp shall be
pre programmed before the command.*/
cmd_status = MCI_StartMotor( pMCI[pESC_params->motor] );
/* It verifies if the command "MCI_StartMotor" is successfully executed
otherwise it tries to restart the procedure */
if(cmd_status==false)
{
pHandle->sm_state = ESC_ARMING; // Command NOT executed
}
else
{
pHandle->sm_state = ESC_POSITIVE_RUN; // Command executed
/* From this point the motor is spinning and stop and restart requires STOP_DURATION delay*/
pHandle->restart_delay = STOP_DURATION;
}
pHandle->restart_delay = STOP_DURATION;
}
else
{
if (pHandle->Ton_value < pESC_params->Ton_arming)
{
pHandle->sm_state = ESC_ARMING;
pHandle->arming_counter = 0;
}
else
{
/* Nothing to do stay in ARMED state waiting for TON > TON_MIN*/
}
}
}
break;
case ESC_POSITIVE_RUN:
{
if( pHandle->Ton_value < pESC_params->Ton_min)
{
pHandle->turnoff_delay --;
if(pHandle->turnoff_delay <= 0)
{
pHandle->sm_state = ESC_STOP;
pHandle->turnoff_delay = pESC_params->TURNOFF_TIME_MAX;
/* This is a user command to stop the motor */
MCI_StopMotor( pMCI[pESC_params->motor] );
}
}
else
{
pHandle->turnoff_delay = pESC_params->TURNOFF_TIME_MAX;
if(pHandle->Ton_value <= pESC_params->Ton_max)
{
new_speed = ((pHandle->Ton_value-pESC_params->Ton_min) * (pESC_params->speed_max_valueRPM - pESC_params->speed_min_valueRPM) / pESC_params->delta_Ton_max) + pESC_params->speed_min_valueRPM;
}
else
{
new_speed = pESC_params->speed_max_valueRPM;
}
if (MC_GetSTMStateMotor1() == RUN)
{
MCI_ExecSpeedRamp( pMCI[pESC_params->motor], (new_speed/6), 50 );
}
}
}
break;
case ESC_STOP:
{
/* After the time "STOP_DURATION" the motor will be restarted */
if (pHandle->restart_delay == 0)
{
/* Next state */
pHandle->sm_state = ESC_ARMING;
pHandle->Ton_value = 0;
pHandle->arming_counter = 0;
pHandle->buffer_completed = false;
pHandle->index_filter = 0;
pHandle->pwm_accumulator = 0;
}
else
{
pHandle->restart_delay--;
}
}
break;
}
}
return (ESC_Fault_Occured);
}
/**
* @brief This is the main function to use in the main.c in order to start the current example
* @param None
* @retval None
*/
void esc_pwm_control(ESC_Handle_t * pHandle)
{
ESC_State_t ESC_Fault_Occured;
#ifdef ESC_BEEP_FEATURE
if ( pHandle->phase_check_status == false)
{
pHandle->phase_check_status = esc_phase_check (pHandle);
}
else
#endif
{
if (MC_GetSTMStateMotor1() == FAULT_OVER)
{
#ifdef ESC_BEEP_FEATURE
if (MC_GetOccurredFaultsMotor1() == MC_UNDER_VOLT)
{
pHandle->phase_check_status = false;
pHandle->start_check_flag = false;
}
#endif
MC_AcknowledgeFaultMotor1();
pHandle->sm_state = ESC_ARMING;
pHandle->arming_counter = 0;
}
ESC_Fault_Occured = esc_pwm_run(pHandle);
if (ESC_Fault_Occured == ESC_NOSIGNAL && pHandle->sm_state == ESC_ARMING)
{
#ifdef ESC_BEEP_FEATURE
esc_beep_loop(pHandle, 1);
#endif
}
else
{
/* Nothing to do */
}
}
}
static uint32_t esc_capture_filter(ESC_Handle_t * pHandle, uint32_t capture_value)
{
uint32_t pwm_filtered;
uint32_t pwm_max =0;
if(pHandle->buffer_completed == false)
{
pHandle->pwm_accumulator += capture_value;
pHandle->pwm_buffer[pHandle->index_filter] = capture_value;
pHandle->index_filter++;
pwm_filtered = pHandle->pwm_accumulator/pHandle->index_filter;
if(pHandle->index_filter >= ESC_FILTER_DEEP)
{
pHandle->index_filter = 0;
pHandle->buffer_completed = true;
}
}
else
{
/* We compute moving average, index_filter is the first data to remove*/
pHandle->pwm_accumulator -= pHandle->pwm_buffer[pHandle->index_filter];
pHandle->pwm_buffer[pHandle->index_filter] = capture_value;
pHandle->pwm_accumulator += capture_value;
for (uint8_t i =0; i< ESC_FILTER_DEEP; i++)
{
pwm_max = (pHandle->pwm_buffer[i] > pwm_max) ? pHandle->pwm_buffer[i] : pwm_max ;
}
pHandle->index_filter++;
if(pHandle->index_filter >= ESC_FILTER_DEEP)
{
pHandle->index_filter = 0;
}
/* Remove the max pwm input from the average computation*/
pwm_filtered = (pHandle->pwm_accumulator - pwm_max ) / (ESC_FILTER_DEEP -1);
}
pwm_filtered = (pwm_filtered==0) ? 1 : pwm_filtered ;
return(pwm_filtered);
}
#ifdef ESC_BEEP_FEATURE
static bool esc_beep_loop(ESC_Handle_t * pHandle, uint16_t number_beep)
{
TIM_TypeDef * TIMx = pHandle->pESC_params->Motor_TIM;
bool ESC_Beep_loop_STATUS = false;
/* TIMx Peripheral Configuration -------------------------------------------*/
if( pHandle-> start_check_flag == false)
{
pHandle-> start_check_flag = true;
ESC_Beep_loop_STATUS = false;
/* Set the Output State */
LL_TIM_SetAutoReload (TIMx, BEEP_FREQ_ARR);
LL_TIM_CC_DisableChannel (TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2
| LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH1N
| LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3N);
LL_TIM_CC_EnableChannel (TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2
| LL_TIM_CHANNEL_CH3 );
LL_TIM_EnableAllOutputs (TIMx);
}
{
/* User defined code */
switch (pHandle->beep_state)
{
case SM_BEEP_1:
{
if(pHandle->beep_counter == 0)
{
LL_TIM_OC_SetCompareCH1 (TIMx,BEEP_DUTY);
LL_TIM_OC_SetCompareCH2 (TIMx,BEEP_FREQ_ARR);
LL_TIM_OC_SetCompareCH3 (TIMx,BEEP_FREQ_ARR);
LL_TIM_CC_DisableChannel (TIMx,LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH3 );
LL_TIM_CC_EnableChannel (TIMx, (LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3N
| LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N));
}
pHandle->beep_counter++;
if(pHandle->beep_counter > BEEP_TIME_MAX)
{
if(number_beep == 1)
{
pHandle->beep_stop_time = 570;
pHandle->beep_state = SM_BEEP_4;
}
if(number_beep == 2)
{
pHandle->beep_num ++;
if(pHandle->beep_num <= 2)
{
LL_TIM_OC_SetCompareCH1 (TIMx,0);
pHandle->beep_state = SM_BEEP_3;
}
else
{
pHandle->beep_stop_time = 410;
pHandle->beep_state = SM_BEEP_4;
pHandle->beep_num = 1;
}
}
if(number_beep == 3)
{
pHandle->beep_num ++;
if(pHandle->beep_num <= 3)
{
LL_TIM_OC_SetCompareCH1 (TIMx,0);
pHandle->beep_state = SM_BEEP_3;
}
else
{
pHandle->beep_stop_time = 270;
pHandle->beep_state = SM_BEEP_4;
pHandle->beep_num = 1;
}
}
pHandle->beep_counter = 0;
}
}
break;
case SM_BEEP_3:
{
if(pHandle->beep_counter == 0)
{
LL_TIM_OC_SetCompareCH1 (TIMx,0);
}
pHandle->beep_counter++;
if(pHandle->beep_counter > 50)
{
pHandle->beep_state = SM_BEEP_1;
pHandle->beep_counter = 0;
}
}
break;
case SM_BEEP_4:
{
if(pHandle->beep_counter == 0)
{
LL_TIM_OC_SetCompareCH1 (TIMx,0);
LL_TIM_OC_SetCompareCH2 (TIMx,0);
LL_TIM_OC_SetCompareCH3 (TIMx,0);
}
pHandle->beep_counter++;
if(pHandle->beep_counter > pHandle->beep_stop_time)
{
pHandle->beep_state = SM_BEEP_1;
pHandle->beep_counter = 0;
esc_reset_pwm_ch(pHandle);
pHandle-> start_check_flag = false;
ESC_Beep_loop_STATUS = true;
}
}
break;
case SM_BEEP_2:
default:
break;
}
}
return (ESC_Beep_loop_STATUS);
}
static bool esc_phase_check(ESC_Handle_t * pHandle)
{
TIM_TypeDef * TIMx = pHandle->pESC_params->Motor_TIM;
bool ESC_phase_check_status = false;
/* TIMx Peripheral Configuration -------------------------------------------*/
if(pHandle-> start_check_flag == false)
{
pHandle-> start_check_flag = true;
/* Set the Output State */
ESC_phase_check_status = false;
LL_TIM_SetAutoReload (TIMx, BEEP_FREQ_ARR);
LL_TIM_CC_DisableChannel (TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2
| LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH1N
| LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3N);
LL_TIM_CC_EnableChannel (TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2
| LL_TIM_CHANNEL_CH3 );
LL_TIM_EnableAllOutputs (TIMx);
pHandle->beep_state = SM_BEEP_1;
pHandle->beep_counter = 0;
}
{
/* User defined code */
switch (pHandle->beep_state)
{
case SM_BEEP_1:
{
if(pHandle->beep_counter == 0)
{
LL_TIM_OC_SetCompareCH3 (TIMx,BEEP_DUTY);
LL_TIM_OC_SetCompareCH2 (TIMx,BEEP_FREQ_ARR);
LL_TIM_OC_SetCompareCH1 (TIMx,BEEP_FREQ_ARR);
LL_TIM_CC_DisableChannel (TIMx,LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2 );
LL_TIM_CC_EnableChannel (TIMx, (LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2N
| LL_TIM_CHANNEL_CH3N | LL_TIM_CHANNEL_CH3));
}
pHandle->beep_counter++;
if(pHandle->beep_counter > BEEP_TIME_MAX_CHECK)
{
pHandle->beep_state = SM_BEEP_2;
pHandle->beep_counter = 0;
LL_TIM_OC_SetCompareCH2 (TIMx,BEEP_DUTY);
LL_TIM_SetAutoReload (TIMx, BEEP_FREQ_ARR1);
}
}
break;
case SM_BEEP_2:
{
if(pHandle->beep_counter == 0)
{
LL_TIM_OC_SetCompareCH2 (TIMx,BEEP_DUTY);
LL_TIM_OC_SetCompareCH1 (TIMx,BEEP_FREQ_ARR1);
LL_TIM_OC_SetCompareCH3 (TIMx,BEEP_FREQ_ARR1);
LL_TIM_CC_DisableChannel (TIMx,LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH1 );
LL_TIM_CC_EnableChannel (TIMx, (LL_TIM_CHANNEL_CH3N | LL_TIM_CHANNEL_CH1N
| LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N));
}
pHandle->beep_counter++;
if(pHandle->beep_counter > BEEP_TIME_MAX_CHECK)
{
pHandle->beep_state = SM_BEEP_3;
pHandle->beep_counter = 0;
LL_TIM_OC_SetCompareCH1 (TIMx,BEEP_DUTY);
LL_TIM_SetAutoReload (TIMx, BEEP_FREQ_ARR2);
}
}
break;
case SM_BEEP_3:
{
if(pHandle->beep_counter == 0)
{
LL_TIM_OC_SetCompareCH1 (TIMx,BEEP_DUTY);
LL_TIM_OC_SetCompareCH2 (TIMx,BEEP_FREQ_ARR2);
LL_TIM_OC_SetCompareCH3 (TIMx,BEEP_FREQ_ARR2);
LL_TIM_CC_DisableChannel (TIMx,LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH3 );
LL_TIM_CC_EnableChannel (TIMx, (LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3N
| LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N));
}
pHandle->beep_counter++;
if(pHandle->beep_counter > BEEP_TIME_MAX_CHECK)
{
pHandle->beep_state = SM_BEEP_4;
pHandle->beep_counter = 0;
}
}
break;
case SM_BEEP_4:
{
if(pHandle->beep_counter == 0)
{
LL_TIM_OC_SetCompareCH1 (TIMx,0);
LL_TIM_OC_SetCompareCH2 (TIMx,0);
LL_TIM_OC_SetCompareCH3 (TIMx,0);
}
pHandle->beep_counter++;
if(pHandle->beep_counter > 1000)
{
pHandle->beep_state = SM_BEEP_1;
pHandle->beep_counter = 0;
esc_reset_pwm_ch(pHandle);
pHandle-> start_check_flag = false;
ESC_phase_check_status = true;
}
}
break;
}
}
return(ESC_phase_check_status);
}
#endif // ESC_BEEP_FEATURE
static void esc_reset_pwm_ch(ESC_Handle_t * pHandle)
{
TIM_TypeDef * TIMx = TIM1;
LL_TIM_CC_DisableChannel (TIMx, (LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2
| LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH1N
| LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3N ) );
LL_TIM_SetAutoReload (TIMx, ((PWM_PERIOD_CYCLES) / 2));
/* Set the Output State */
LL_TIM_CC_EnableChannel (TIMx, (LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2
| LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH1N
| LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3N ));
}
/**
* @brief This function handles TIM2 global interrupt request.
* @param None
* @retval None
*/
void TIM2_IRQHandler(void)
{
/* Clear TIM1 Capture compare interrupt pending bit */
LL_TIM_ClearFlag_CC1 (TIM2);
/* Get Pulse width and low pass filter it to remove spurious informations */
ESC_M1.Ton_value = esc_capture_filter(&ESC_M1, LL_TIM_OC_GetCompareCH2(TIM2));
/* Fail safe mechanism: stops the motor is the PWM input is disabled */
ESC_M1.watchdog_counter++;
if(ESC_M1.watchdog_counter == 0)
ESC_M1.watchdog_counter = 1;
}
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 18,518 | C | 29.609917 | 201 | 0.55411 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/speed_pos_fdbk.c | /**
******************************************************************************
* @file speed_pos_fdbk.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Speed & Position Feedback component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "speed_pos_fdbk.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup SpeednPosFdbk Speed & Position Feedback
*
* @brief Speed & Position Feedback components of the Motor Control SDK
*
* These components provide the speed and the angular position of the rotor of a motor (both
* electrical and mechanical). These informations are expressed in units defined into [measurement units](measurement_units.md).
*
* Several implementations of the Speed and Position Feedback feature are provided by the Motor
* to account for the specificities of the motor used on the application:
*
* - @ref hall_speed_pos_fdbk "Hall Speed & Position Feedback" for motors with Hall effect sensors.
* - @ref Encoder "Encoder Speed & Position Feedback" for motors with a quadrature encoder.
* - Two general purpose sensorless implementations are provided:
* @ref SpeednPosFdbk_STO "State Observer with PLL" and
* @ref STO_CORDIC_SpeednPosFdbk "State Observer with CORDIC"
* - A @ref VirtualSpeedSensor "Virtual Speed & Position Feedback" implementation used during the
* @ref RevUpCtrl "Rev-Up Control" phases of the motor in a sensorless subsystem.
* - @ref In the future a High Frequency Injection for anisotropic I-PMSM motors will be supported.
*
* For more information see the user manual [Speed position and sensorless BEMF reconstruction](speed_pos_sensorless_bemf_reconstruction.md).
* @{
*/
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Returns the last computed rotor electrical angle, expressed in [s16degrees](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
* @retval int16_t rotor electrical angle.
*/
__weak int16_t SPD_GetElAngle(const SpeednPosFdbk_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
return ((MC_NULL == pHandle) ? 0 : pHandle->hElAngle);
#else
return (pHandle->hElAngle);
#endif
}
/**
* @brief Returns the last computed rotor mechanical angle, expressed in [s16degrees](measurement_units.md).
* @note Both Hall sensor and Sensor-less application do not implement either mechanical angle computation or
* acceleration computation.
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
* @retval int16_t rotor mechanical angle.
*
* - Mechanical angle frame is based on parameter @ref SpeednPosFdbk_Handle_t::bElToMecRatio "bElToMecRatio"
* and, if occasionally provided through Encoder function of a measured mechanical angle, on information computed
* thereof.
* - Called to set a mechanical position ot the rotor.
*/
__weak int32_t SPD_GetMecAngle(const SpeednPosFdbk_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
return ((MC_NULL == pHandle) ? 0 : pHandle->wMecAngle);
#else
return (pHandle->wMecAngle);
#endif
}
/**
* @brief Returns the last computed average mechanical speed, expressed in
* the unit defined by [SPEED_UNIT](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
*/
__weak int16_t SPD_GetAvrgMecSpeedUnit(const SpeednPosFdbk_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
return ((MC_NULL == pHandle) ? 0 : pHandle->hAvrMecSpeedUnit);
#else
return (pHandle->hAvrMecSpeedUnit);
#endif
}
/**
* @brief Returns the last computed electrical speed, expressed in [dpp](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
* @retval int16_t rotor electrical speed ([dpp](measurement_units.md)).
*
* - The control period is the period on which the rotor electrical angle is computed thanks
* to HALL effect sensor functions.
* - Called during feed-forward controller computation and during Motor profiling.
*/
__weak int16_t SPD_GetElSpeedDpp(const SpeednPosFdbk_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
return ((MC_NULL == pHandle) ? 0 : pHandle->hElSpeedDpp);
#else
return (pHandle->hElSpeedDpp);
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Returns the last instantaneous computed electrical speed, expressed in [dpp](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
* @retval int16_t rotor instantaneous electrical speed ([dpp](measurement_units.md)).
*
* - The control period is the period on which the rotor electrical angle is computed thanks to HALL effect sensor
* functions.
* - Called during FOC drive control for Iqd currents regulation.
*/
__weak int16_t SPD_GetInstElSpeedDpp(const SpeednPosFdbk_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
return ((MC_NULL == pHandle) ? 0 : pHandle->InstantaneousElSpeedDpp);
#else
return (pHandle->InstantaneousElSpeedDpp);
#endif
}
/**
* @brief Returns the result of the last reliability check performed.
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
* @retval bool sensor reliability state.
*
* - Reliability is measured with reference to parameters
* @ref SpeednPosFdbk_Handle_t::hMaxReliableMecSpeedUnit "hMaxReliableMecSpeedUnit",
* @ref SpeednPosFdbk_Handle_t::hMinReliableMecSpeedUnit "hMaxReliableMecSpeedUnit",
* @ref SpeednPosFdbk_Handle_t::bMaximumSpeedErrorsNumber "bMaximumSpeedErrorsNumber".
* - If the number of time the average mechanical speed is not valid matches the
* maximum value of not valid speed measurements, sensor information is not reliable.
* - Embedded into construction of the MC_GetSpeedSensorReliabilityMotor API.
* - The return value is a boolean that expresses:\n
* -- true = sensor information is reliable.\n
* -- false = sensor information is not reliable.
*/
__weak bool SPD_Check(const SpeednPosFdbk_Handle_t *pHandle)
{
bool SpeedSensorReliability = true;
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
if ((MC_NULL == pHandle) || (pHandle->bSpeedErrorNumber == pHandle->bMaximumSpeedErrorsNumber))
#else
if (pHandle->bSpeedErrorNumber == pHandle->bMaximumSpeedErrorsNumber)
#endif
{
SpeedSensorReliability = false;
}
else
{
/* Nothing to do */
}
return (SpeedSensorReliability);
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Computes and returns through parameter @ref SpeednPosFdbk_Handle_t::pMecSpeedUnit "pMecSpeedUnit",
* the rotor average mechanical speed, expressed in the unit defined by
* @ref SpeednPosFdbk_Handle_t::SpeedUnit "SpeedUnit".
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
* @param pMecSpeedUnit: pointer to int16_t, used to return the rotor average
* mechanical speed (expressed in the unit defined by [SPEED_UNIT](measurement_units.md).
* @retval none
*
* - Computes and returns the reliability state of the sensor. Reliability is measured with
* reference to parameters @ref SpeednPosFdbk_Handle_t::hMinReliableMecSpeedUnit "hMinReliableMecSpeedUnit",
* @ref SpeednPosFdbk_Handle_t::hMaxReliableMecSpeedUnit "hMaxReliableMecSpeedUnit",
* @ref SpeednPosFdbk_Handle_t::bMaximumSpeedErrorsNumber "bMaximumSpeedErrorsNumber"\n
* -- true = sensor information is reliable.\n
* -- false = sensor information is not reliable.\n
* - Called at least with the same periodicity on which speed control is executed.
* -
*/
__weak bool SPD_IsMecSpeedReliable(SpeednPosFdbk_Handle_t *pHandle, const int16_t *pMecSpeedUnit)
{
bool SpeedSensorReliability = true;
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
if ((MC_NULL == pHandle) || (MC_NULL == pMecSpeedUnit))
{
SpeedSensorReliability = false;
}
else
{
#endif
uint16_t hAbsMecSpeedUnit;
uint16_t hAbsMecAccelUnitP;
int16_t hAux;
uint8_t bSpeedErrorNumber;
uint8_t bMaximumSpeedErrorsNumber = pHandle->bMaximumSpeedErrorsNumber;
bool SpeedError = false;
bSpeedErrorNumber = pHandle->bSpeedErrorNumber;
/* Compute absoulte value of mechanical speed */
if (*pMecSpeedUnit < 0)
{
hAux = -(*pMecSpeedUnit);
hAbsMecSpeedUnit = (uint16_t)hAux;
}
else
{
hAbsMecSpeedUnit = (uint16_t)(*pMecSpeedUnit);
}
if (hAbsMecSpeedUnit > pHandle->hMaxReliableMecSpeedUnit)
{
SpeedError = true;
}
else
{
/* Nothing to do */
}
if (hAbsMecSpeedUnit < pHandle->hMinReliableMecSpeedUnit)
{
SpeedError = true;
}
else
{
/* Nothing to do */
}
/* Compute absoulte value of mechanical acceleration */
if (pHandle->hMecAccelUnitP < 0)
{
hAux = -(pHandle->hMecAccelUnitP);
hAbsMecAccelUnitP = (uint16_t)hAux;
}
else
{
hAbsMecAccelUnitP = (uint16_t)pHandle->hMecAccelUnitP;
}
if (hAbsMecAccelUnitP > pHandle->hMaxReliableMecAccelUnitP)
{
SpeedError = true;
}
else
{
/* Nothing to do */
}
if (true == SpeedError)
{
if (bSpeedErrorNumber < bMaximumSpeedErrorsNumber)
{
bSpeedErrorNumber++;
}
else
{
/* Nothing to do */
}
}
else
{
if (bSpeedErrorNumber < bMaximumSpeedErrorsNumber)
{
bSpeedErrorNumber = 0u;
}
else
{
/* Nothing to do */
}
}
if (bSpeedErrorNumber == bMaximumSpeedErrorsNumber)
{
SpeedSensorReliability = false;
}
else
{
/* Nothing to do */
}
pHandle->bSpeedErrorNumber = bSpeedErrorNumber;
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
}
#endif
return (SpeedSensorReliability);
}
/**
* @brief Returns the average mechanical rotor speed expressed in [S16Speed](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednPosFdbk component
* @retval int16_t The average mechanical rotor speed.
*
* - The value equals:\n
* -- zero when the average mechanical speed is equal zero,\n
* -- INT16_MAX when the average mechanical speed is equal to
* @ref SpeednPosFdbk_Handle_t::hMaxReliableMecSpeedUnit "hMaxReliableMecSpeedUnit" ,\n
* - Called for speed monitoring through MotorPilote.
*/
__weak int16_t SPD_GetS16Speed(const SpeednPosFdbk_Handle_t *pHandle)
{
int16_t tempValue;
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
if (MC_NULL == pHandle)
{
tempValue = 0;
}
else
{
#endif
int32_t wAux = (int32_t)pHandle->hAvrMecSpeedUnit;
wAux *= INT16_MAX;
wAux /= (int16_t)pHandle->hMaxReliableMecSpeedUnit;
tempValue = (int16_t)wAux;
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
}
#endif
return (tempValue);
}
/**
* @brief Returns the coefficient used to transform electrical to
* mechanical quantities and viceversa. It usually coincides with motor
* pole pairs number.
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
* @retval uint8_t The motor pole pairs number.
*
* - Called by motor profiling functions and for monitoring through motorPilote.
*/
__weak uint8_t SPD_GetElToMecRatio(const SpeednPosFdbk_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
return ((MC_NULL == pHandle) ? 0U : pHandle->bElToMecRatio);
#else
return (pHandle->bElToMecRatio);
#endif
}
/**
* @brief Sets the coefficient used to transform electrical to
* mechanical quantities and viceversa. It usually coincides with motor
* pole pairs number.
* @param pHandle: handler of the current instance of the SpeednPosFdbk component.
* @param bPP The motor pole pairs number to be set.
*
* - Called only for monitoring through motorPilote.
*/
__weak void SPD_SetElToMecRatio(SpeednPosFdbk_Handle_t *pHandle, uint8_t bPP)
{
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->bElToMecRatio = bPP;
#ifdef NULL_PTR_CHECK_SPD_POS_FBK
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 13,307 | C | 31.859259 | 144 | 0.680243 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/speed_torq_ctrl.c | /**
******************************************************************************
* @file speed_torq_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the following features
* of the Speed & Torque Control component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup SpeednTorqCtrlClassic
*/
/* Includes ------------------------------------------------------------------*/
#include "speed_torq_ctrl.h"
#include "speed_pos_fdbk.h"
#include "mc_type.h"
#define CHECK_BOUNDARY
/** @addtogroup MCSDK
* @{
*/
/** @defgroup SpeednTorqCtrl Speed & Torque Control
* @brief Speed & Torque Control component of the Motor Control SDK
*
* The MCSDK is able to control the motor in torque or in speed Mode.
* This component is used to manage torque or speed references and
* torque or speed ramps.
*
* @{
*/
/** @defgroup SpeednTorqCtrlClassic Classic Speed & Torque Control
* @brief Speed & Torque Control component for the classic FOC drive
*
* This component provides the Speed and Torque feature to the Classic
* FOC drive.
* @{
*/
/**
* @brief Initializes all the object variables.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @param pPI: the PI object used as controller for the speed regulation.
* It can be equal to #MC_NULL if the STC is initialized in torque mode
* and it will never be configured in speed mode.
* @param SPD_Handle: the speed sensor used to perform the speed regulation.
* It can be equal to #MC_NULL if the STC is used only in torque mode.
* @retval none.
*
* - Called once right after object creation at initialization of the whole MC core.
*/
__weak void STC_Init(SpeednTorqCtrl_Handle_t *pHandle, PID_Handle_t *pPI, SpeednPosFdbk_Handle_t *SPD_Handle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->PISpeed = pPI;
pHandle->SPD = SPD_Handle;
pHandle->Mode = pHandle->ModeDefault;
pHandle->SpeedRefUnitExt = ((int32_t)pHandle->MecSpeedRefUnitDefault) * 65536;
pHandle->TorqueRef = ((int32_t)pHandle->TorqueRefDefault) * 65536;
pHandle->TargetFinal = 0;
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
}
/**
* @brief Sets in real time the speed sensor utilized by the STC.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @param SPD_Handle Speed sensor component to be set.
* @retval none
*
* - Called during tasks execution of the MC state machine into MediumFrequencyTask.
*/
__weak void STC_SetSpeedSensor(SpeednTorqCtrl_Handle_t *pHandle, SpeednPosFdbk_Handle_t *SPD_Handle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->SPD = SPD_Handle;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
}
/**
* @brief Returns the speed sensor utilized by the FOC.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval SpeednPosFdbk_Handle_t speed sensor utilized by the FOC.
*
* - Called as soon as component parameters are required by MC FW.
*/
//cstat !MISRAC2012-Rule-8.13
__weak SpeednPosFdbk_Handle_t *STC_GetSpeedSensor(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
return ((MC_NULL == pHandle) ? MC_NULL : pHandle->SPD);
#else
return (pHandle->SPD);
#endif
}
/**
* @brief Resets the integral term of speed regulator if STC is set in speed mode.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval none.
*
* - Called before each motor restart.
*/
__weak void STC_Clear(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (MCM_SPEED_MODE == pHandle->Mode)
{
PID_SetIntegralTerm(pHandle->PISpeed, 0);
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
}
/**
* @brief Gets the current mechanical rotor speed reference
* @ref SpeednTorqCtrl_Handle_t::SpeedRefUnitExt "SpeedRefUnitExt" expressed in the unit
* defined by [SPEED_UNIT](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval int16_t current mechanical rotor speed reference expressed in
* the unit defined by [SPEED_UNIT](measurement_units.md).
*
* - Called at MC boot procedure and for speed monitoring through MotorPilote.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t STC_GetMecSpeedRefUnit(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifndef FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
return ((MC_NULL == pHandle) ? 0 : (int16_t)(pHandle->SpeedRefUnitExt >> 16));
#else
return ((int16_t)(pHandle->SpeedRefUnitExt >> 16));
#endif
#else
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
return ((MC_NULL == pHandle) ? 0 : (int16_t)(pHandle->SpeedRefUnitExt / 65536));
#else
return ((int16_t)(pHandle->SpeedRefUnitExt / 65536));
#endif
#endif
}
/**
* @brief Gets the current motor torque reference
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval int16_t current motor torque reference. This value represents
* actually the Iq current expressed in digit.
*
* - @ref SpeednTorqCtrl_Handle_t::TorqueRef "TorqueRef" represents
* actually the Iq current reference expressed in digit.
* - To convert current expressed in digit to current expressed in Amps
* is possible to use the formula:\n
* Current(Amp) = [Current(digit) * Vdd micro] / [65536 * Rshunt * Aop]
* - Called during #STC_ExecRamp execution.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t STC_GetTorqueRef(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifndef FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
return ((MC_NULL == pHandle) ? 0 : (int16_t)(pHandle->TorqueRef >> 16));
#else
return ((int16_t)(pHandle->TorqueRef >> 16));
#endif
#else
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
return ((MC_NULL == pHandle) ? 0 : (int16_t)(pHandle->TorqueRef / 65536));
#else
return ((int16_t)(pHandle->TorqueRef / 65536));
#endif
#endif
}
/**
* @brief Sets the modality of the speed and torque controller
* @ref SpeednTorqCtrl_Handle_t::Mode "Mode".
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @param bMode: modality of STC. It can be one of these two settings:
* MCM_TORQUE_MODE to enable the Torque mode or MCM_SPEED_MODE to
* enable the Speed mode.
* @retval none
*
* - Two modality are available Torque mode and Speed mode.\n
* -- In Torque mode is possible to set directly the motor torque
* reference or execute a motor torque ramp. This value represents
* actually the Iq current reference expressed in digit.\n
* -- In Speed mode is possible to set the mechanical rotor speed
* reference or execute a speed ramp. The required motor torque is
* automatically calculated by the STC.\n
* - Interrupts the execution of any previous ramp command
* maintaining the last value of Iq by clearing
* @ref SpeednTorqCtrl_Handle_t::RampRemainingStep "RampRemainingStep".
* - Called generally before Starting the execution of a ramp.
*/
__weak void STC_SetControlMode(SpeednTorqCtrl_Handle_t *pHandle, MC_ControlMode_t bMode)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->Mode = bMode;
pHandle->RampRemainingStep = 0u; /* Interrupts previous ramp */
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
}
/**
* @brief Gets the modality of the speed and torque controller
* @ref SpeednTorqCtrl_Handle_t::Mode "Mode".
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval MC_ControlMode_t modality of STC. It can be one of
* these two values: MCM_TORQUE_MODE or MCM_SPEED_MODE.
*
* - Called by @ref SpeedRegulatorPotentiometer Speed potentiometer component to manage new speed reference.
*/
//cstat !MISRAC2012-Rule-8.13
__weak MC_ControlMode_t STC_GetControlMode(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
return ((MC_NULL == pHandle) ? MCM_TORQUE_MODE : pHandle->Mode);
#else
return (pHandle->Mode);
#endif
}
/**
* @brief Starts the execution of a ramp using new target and duration.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @param hTargetFinal: final value of command. This is different accordingly
* the STC modality.
* If STC is in Torque mode hTargetFinal is the value of motor torque
* reference at the end of the ramp. This value represents actually the
* Iq current expressed in digit.
* To convert current expressed in Amps to current expressed in digit
* is possible to use the formula:\n
* Current(digit) = [Current(Amp) * 65536 * Rshunt * Aop] / Vdd micro\n
* If STC is in Speed mode hTargetFinal is the value of mechanical
* rotor speed reference at the end of the ramp expressed in the unit
* defined by [SPEED_UNIT](measurement_units.md).
* @param hDurationms: the duration of the ramp expressed in milliseconds. It
* is possible to set 0 to perform an instantaneous change in the value.
* @retval bool returning false if the absolute value of hTargetFinal is out of
* the boundary of the application (Above max application speed or max
* application torque or below min application speed depending on
* current modality of TSC) in this case the command is ignored and the
* previous ramp is not interrupted, otherwise it returns true.
*
* - This command interrupts the execution of any previous ramp command.
* The generated ramp will be in the modality previously set by
* #STC_SetControlMode method.
* - Called during @ref motor profiling, @ref RevUpCtrl "Rev-Up Control" phase,
* @ref EncAlignCtrl "Encoder Alignment Control",
* @ref PositionControl "Position Control" loop or
* speed regulation with @ref SpeedRegulatorPotentiometer Speed potentiometer.
*/
__weak bool STC_ExecRamp(SpeednTorqCtrl_Handle_t *pHandle, int16_t hTargetFinal, uint32_t hDurationms)
{
bool allowedRange = true;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
allowedRange = false;
}
else
{
#endif
uint32_t wAux;
int32_t wAux1;
int16_t hCurrentReference;
/* Check if the hTargetFinal is out of the bound of application */
if (MCM_TORQUE_MODE == pHandle->Mode)
{
hCurrentReference = STC_GetTorqueRef(pHandle);
#ifdef CHECK_BOUNDARY
if ((int32_t)hTargetFinal > (int32_t)pHandle->MaxPositiveTorque)
{
allowedRange = false;
}
else
{
/* Nothing to do */
}
if ((int32_t)hTargetFinal < (int32_t)pHandle->MinNegativeTorque)
{
allowedRange = false;
}
else
{
/* Nothing to do */
}
#endif
}
else
{
#ifndef FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hCurrentReference = (int16_t)(pHandle->SpeedRefUnitExt >> 16);
#else
hCurrentReference = (int16_t)(pHandle->SpeedRefUnitExt / 65536);
#endif
#ifdef CHECK_BOUNDARY
if ((int32_t)hTargetFinal > (int32_t)pHandle->MaxAppPositiveMecSpeedUnit)
{
allowedRange = false;
}
else if (hTargetFinal < pHandle->MinAppNegativeMecSpeedUnit)
{
allowedRange = false;
}
else if ((int32_t)hTargetFinal < (int32_t)pHandle->MinAppPositiveMecSpeedUnit)
{
if (hTargetFinal > pHandle->MaxAppNegativeMecSpeedUnit)
{
allowedRange = false;
}
}
else
{
/* Nothing to do */
}
#endif
}
if (true == allowedRange)
{
/* Interrupts the execution of any previous ramp command */
if (0U == hDurationms)
{
if (MCM_SPEED_MODE == pHandle->Mode)
{
pHandle->SpeedRefUnitExt = ((int32_t)hTargetFinal) * 65536;
}
else
{
pHandle->TorqueRef = ((int32_t)hTargetFinal) * 65536;
}
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
}
else
{
/* Store the hTargetFinal to be applied in the last step */
pHandle->TargetFinal = hTargetFinal;
/* Compute the (wRampRemainingStep) number of steps remaining to complete the ramp */
wAux = ((uint32_t)hDurationms) * ((uint32_t)pHandle->STCFrequencyHz);
wAux /= 1000U;
pHandle->RampRemainingStep = wAux;
pHandle->RampRemainingStep++;
/* Compute the increment/decrement amount (wIncDecAmount) to be applied to
the reference value at each CalcTorqueReference */
wAux1 = (((int32_t)hTargetFinal) - ((int32_t)hCurrentReference)) * 65536;
wAux1 /= ((int32_t)pHandle->RampRemainingStep);
pHandle->IncDecAmount = wAux1;
}
}
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
return (allowedRange);
}
/**
* @brief Interrupts the execution of any previous ramp command in particular by clearing
* the number of steps remaining to complete the ramp
* @ref SpeednTorqCtrl_Handle_t::RampRemainingStep "RampRemainingStep".
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval none
*
* - If STC has been set in Torque mode the last value of Iq is maintained.\n
* - If STC has been set in Speed mode the last value of mechanical
* rotor speed reference is maintained.
* - Called by MCI_StopSpeedRamp execution command.
*/
__weak void STC_StopRamp(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->RampRemainingStep = 0U;
pHandle->IncDecAmount = 0;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
}
/**
* @brief Computes the new value of motor torque reference.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval int16_t motor torque reference. This value represents actually the
* Iq current expressed in digit.
* To convert current expressed in Amps to current expressed in digit
* is possible to use the formula:\n
* Current(digit) = [Current(Amp) * 65536 * Rshunt * Aop] / Vdd micro
*
* - Must be called at fixed time equal to hSTCFrequencyHz. It is called
* passing as parameter the speed sensor used to perform the speed regulation.
* - Called during START and ALIGNEMENT states of the MC state machine into MediumFrequencyTask.
*/
__weak int16_t STC_CalcTorqueReference(SpeednTorqCtrl_Handle_t *pHandle)
{
int16_t hTorqueReference;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
hTorqueReference = 0;
}
else
{
#endif
int32_t wCurrentReference;
int16_t hMeasuredSpeed;
int16_t hTargetSpeed;
int16_t hError;
if (MCM_TORQUE_MODE == pHandle->Mode)
{
wCurrentReference = pHandle->TorqueRef;
}
else
{
wCurrentReference = pHandle->SpeedRefUnitExt;
}
/* Update the speed reference or the torque reference according to the mode
and terminates the ramp if needed */
if (pHandle->RampRemainingStep > 1U)
{
/* Increment/decrement the reference value */
wCurrentReference += pHandle->IncDecAmount;
/* Decrement the number of remaining steps */
pHandle->RampRemainingStep--;
}
else if (1U == pHandle->RampRemainingStep)
{
/* Set the backup value of hTargetFinal */
wCurrentReference = ((int32_t)pHandle->TargetFinal) * 65536;
pHandle->RampRemainingStep = 0U;
}
else
{
/* Do nothing */
}
if (MCM_SPEED_MODE == pHandle->Mode)
{
/* Run the speed control loop */
/* Compute speed error */
#ifndef FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hTargetSpeed = (int16_t)(wCurrentReference >> 16);
#else
hTargetSpeed = (int16_t)(wCurrentReference / 65536);
#endif
hMeasuredSpeed = SPD_GetAvrgMecSpeedUnit(pHandle->SPD);
hError = hTargetSpeed - hMeasuredSpeed;
hTorqueReference = PI_Controller(pHandle->PISpeed, (int32_t)hError);
pHandle->SpeedRefUnitExt = wCurrentReference;
pHandle->TorqueRef = ((int32_t)hTorqueReference) * 65536;
}
else
{
pHandle->TorqueRef = wCurrentReference;
#ifndef FULL_MISRA_C_COMPLIANCY_SPD_TORQ_CTRL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hTorqueReference = (int16_t)(wCurrentReference >> 16);
#else
hTorqueReference = (int16_t)(wCurrentReference / 65536);
#endif
}
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
return (hTorqueReference);
}
/**
* @brief Gets the Default mechanical rotor speed reference
* @ref SpeednTorqCtrl_Handle_t::MecSpeedRefUnitDefault "MecSpeedRefUnitDefault" expressed in
* the unit defined by [SPEED_UNIT](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval int16_t Default mechanical rotor speed.
*
* - It is the first command to STC after the start of speed ramp execution.
* - Called during the boot phase of the MC process.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t STC_GetMecSpeedRefUnitDefault(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
return ((MC_NULL == pHandle) ? 0 : pHandle->MecSpeedRefUnitDefault);
#else
return (pHandle->MecSpeedRefUnitDefault);
#endif
}
/**
* @brief Returns the Application maximum positive value of rotor speed
* @ref SpeednTorqCtrl_Handle_t::MaxAppPositiveMecSpeedUnit "MaxAppPositiveMecSpeedUnit".
* Expressed in the unit defined by [SPEED_UNIT](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
*
* - Not used into current implementation.
*/
//cstat !MISRAC2012-Rule-8.13
__weak uint16_t STC_GetMaxAppPositiveMecSpeedUnit(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
return ((MC_NULL == pHandle) ? 0U : pHandle->MaxAppPositiveMecSpeedUnit);
#else
return (pHandle->MaxAppPositiveMecSpeedUnit);
#endif
}
/**
* @brief Returns the Application minimum negative value of rotor speed
* @ref SpeednTorqCtrl_Handle_t::MinAppNegativeMecSpeedUnit "MinAppNegativeMecSpeedUnit".
* Expressed in the unit defined by [SPEED_UNIT](measurement_units.md).
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
*
* - Not used into current implementation.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t STC_GetMinAppNegativeMecSpeedUnit(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
return ((MC_NULL == pHandle) ? 0 : pHandle->MinAppNegativeMecSpeedUnit);
#else
return (pHandle->MinAppNegativeMecSpeedUnit);
#endif
}
/**
* @brief Checks if the settled speed or torque ramp has been completed by checking zero value of
* @ref SpeednTorqCtrl_Handle_t::RampRemainingStep "RampRemainingStep".
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval bool returning true if the ramp is completed, false otherwise.
*
* - Called during motor profiler tuning of HALL sensor.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool STC_RampCompleted(SpeednTorqCtrl_Handle_t *pHandle)
{
bool retVal = false;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (0U == pHandle->RampRemainingStep)
{
retVal = true;
}
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
return (retVal);
}
/**
* @brief Stops the execution of speed ramp by clearing the number of steps remaining to complete the ramp.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval bool returning true if the command is executed, false otherwise.
*
* - Not used into current implementation.
*/
__weak bool STC_StopSpeedRamp(SpeednTorqCtrl_Handle_t *pHandle)
{
bool retVal = false;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (MCM_SPEED_MODE == pHandle->Mode)
{
pHandle->RampRemainingStep = 0u;
retVal = true;
}
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
return (retVal);
}
/**
* @brief Returns the default values of Iqdref.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval default values of Iqdref.
*
* - Called during the boot phase of the MC process.
*/
//cstat !MISRAC2012-Rule-8.13
__weak qd_t STC_GetDefaultIqdref(SpeednTorqCtrl_Handle_t *pHandle)
{
qd_t IqdRefDefault;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
IqdRefDefault.q = 0;
IqdRefDefault.d = 0;
}
else
{
#endif
IqdRefDefault.q = pHandle->TorqueRefDefault;
IqdRefDefault.d = pHandle->IdrefDefault;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
return (IqdRefDefault);
}
/**
* @brief Changes the nominal current by setting new values of
* @ref SpeednTorqCtrl_Handle_t::MaxPositiveTorque "MaxPositiveTorque" and
* @ref SpeednTorqCtrl_Handle_t::MinNegativeTorque "MinNegativeTorque".
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @param hNominalCurrent: represents actually the maximum Iq current expressed in digit.
* @retval none
*
* - Not used into current implementation.
*/
__weak void STC_SetNominalCurrent(SpeednTorqCtrl_Handle_t *pHandle, uint16_t hNominalCurrent)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->MaxPositiveTorque = hNominalCurrent;
pHandle->MinNegativeTorque = -(int16_t)hNominalCurrent;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
}
/**
* @brief Forces the speed reference
* @ref SpeednTorqCtrl_Handle_t::SpeedRefUnitExt "SpeedRefUnitExt" to the current speed.
* @param pHandle: handler of the current instance of the SpeednTorqCtrl component.
* @retval none
*
* - Called during the CHARGE_BOOT_CAP, SWITCH_OVER and WAIT_STOP_MOTOR states of the MC state machine
* into MediumFrequencyTask to initialize the speed reference.
*/
__weak void STC_ForceSpeedReferenceToCurrentSpeed(SpeednTorqCtrl_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->SpeedRefUnitExt = ((int32_t)SPD_GetAvrgMecSpeedUnit(pHandle->SPD)) * (int32_t)65536;
#ifdef NULL_PTR_CHECK_SPD_TRQ_CTL
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 24,016 | C | 31.151272 | 109 | 0.671386 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pidreg_speed.c | /**
******************************************************************************
* @file pidreg_speed.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the PID speed regulator component of the Motor Control SDK
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup PIDRegSpeed
*/
#include "pidreg_speed.h"
/** @addtogroup MCSDK
* @{
*/
/**
* @defgroup PIDRegSpeed PID speed regulator
*
* @brief PID speed regulator component of the Motor Control SDK
*
* The PID speed regulator component implements the following control functions:
*
* * A proportional-integral controller, implemented by the PIDREG_SPEED2_run() function:
*
* 
*
* * Input:
* * `Speed_user_ref`: Electrical reference speed (in Hz) from user
* * `?`: Electrical speed from delta angle (low pass filtered)
* * `?Emf`: Electrical speed from angular speed minus correction signal (low pass filtered)
* * Output:
* * `I_q_ref`: Iq current reference
*
* Note:
* Input `err` represents the speed error without zest-correction and is used for proportional gain Kp only. Without zest-correction in the feedback signal, higher proportional gains can be used while keeping the system stable.
* Input `errIncSpd` is the discrete derivative of the estimated angle that also includes the zest-correction. While standing still, zest will do something to compensate for any system imperfections and offsets, hence `err` will
* contain a non-zero signal that represents a non-zero speed. Hence a corrected angle is required for integral speed (position) control, otherwise position-drift will occur.
* In case a Ki is commanded, the shaft should act as a mechanical torsional spring. Standstill should result in a fixed position without drift at any constant load. Hence `errIncSpd` is used for the integration part.
*
* Each of the gain parameters, can be set, at run time and independently, via the PIDREG_SPEED_setKp_si(),
* PIDREG_SPEED_setKp_si().
*
* A PID Speed Regulator component needs to be initialized before it can be used. This is done with the PIDREG_SPEED_init()
* function that sets the intergral term to 0 and initializes the component data structure.
*
* To keep the computed values within limits, the component features the possibility to constrain the integral term
* within a range of values bounded by the PIDREG_SPEED_setOutputLimits() function.
*
* Handling a process with a PID Controller may require some adjustment to cope with specific situations. To that end, the
* PID speed regulator component provides functions to set the integral term (PIDREG_SPEED_setUi_pu()).
*
*
* @{
*/
#define PU_FMT (30) /*!< @brief Per unit format, external format */
#define SUM_FTM (24) /*!< @brief Summing format, internal format */
#define HALF_BIT ((1L << (PU_FMT-SUM_FTM-1))-1) /*!< @brief equal to 2^(PU_FMT-SUM_FTM -1) -1 = 32-1 = 31 in standard case*/
/**
* @brief Initializes PID speed regulator component.
*
* It Should be called during Motor control middleware initialization.
* @param pHandle PID current regulator handler
* @param current_scale current scaling factor
* @param frequency_scale frequency scaling factor
* @param pid_freq_PID regulator execution frequency
*/
void PIDREG_SPEED_init(
PIDREG_SPEED_s* pHandle,
const float current_scale,
const float frequency_scale,
const float pid_freq_hz
)
{
pHandle->Kp_fps.value = 0;
pHandle->Kp_fps.fixpFmt = 30;
pHandle->Ki_fps.value = 0;
pHandle->Ki_fps.fixpFmt = 30;
pHandle->Max = FIXP24(0.7f);
pHandle->Min = FIXP24(-0.7f);
pHandle->Up = FIXP24(0.0f);
pHandle->Ui = FIXP24(0.0f);
pHandle->Out = FIXP30(0.0f);
pHandle->dither = 0;
pHandle->current_scale = current_scale;
pHandle->frequency_scale = frequency_scale;
pHandle->pid_freq_hz = pid_freq_hz;
}
/**
* @brief Computes the output of a PID speed regulator component, sum of its proportional
* and integral terms
* @param pHandle PID current regulator handler
* @param err speed error
*/
fixp30_t PIDREG_SPEED_run( PIDREG_SPEED_s* pHandle, const fixp30_t err )
{
fixp24_t max = pHandle->Max;
fixp24_t min = pHandle->Min;
fixp24_t ui = pHandle->Ui;
/* Error */
fixp24_t err_24 = (err >> (PU_FMT-SUM_FTM));
/* Proportional term */
fixp24_t up = FIXP_mpyFIXPscaled(err_24, &pHandle->Kp_fps);
/* Integral term */
ui += FIXP_mpyFIXPscaled(err_24, &pHandle->Ki_fps);
ui = FIXP_sat(ui, max, min);
pHandle->Ui = ui;
fixp24_t sum = FIXP_sat(up + ui, max, min);
fixp30_t out = (sum << (PU_FMT-SUM_FTM));
/* Store values for monitoring */
pHandle->Err = err_24;
pHandle->Up = up;
pHandle->Out = out;
return (out);
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
/**
* @brief Computes the output of a PID speed regulator component, sum of its proportional
* and integral terms
* @param pHandle PID current regulator handler
* @param err speed error
* @param err speed error
*/
fixp30_t PIDREG_SPEED2_run( PIDREG_SPEED_s* pHandle, const fixp30_t err, const fixp30_t errIncSpd)
{
fixp24_t max = pHandle->Max;
fixp24_t min = pHandle->Min;
fixp24_t ui = pHandle->Ui;
/* Error */
fixp24_t err_24 = ((err + HALF_BIT) >> (PU_FMT-SUM_FTM));
fixp24_t errIncSpd_24 = ((errIncSpd + HALF_BIT) >> (PU_FMT-SUM_FTM));
/* Proportional term */
fixp24_t up = FIXP_mpyFIXPscaled(err_24, &pHandle->Kp_fps);
/* Integral term */
pHandle->dither = (pHandle->dither + 1) & 1;
ui += FIXP_mpyFIXPscaled(errIncSpd_24, &pHandle->Ki_fps) + pHandle->dither;
pHandle->clipped = ((ui <= min) || (ui >= max));
ui = FIXP_sat(ui, max, min);
pHandle->Ui = ui;
fixp24_t sum = FIXP_sat(up + ui, max, min);
fixp30_t out = (sum << (PU_FMT-SUM_FTM));
/* Store values for monitoring */
pHandle->Err = err_24;
pHandle->Up = up;
pHandle->Out = out;
return (out);
}
/**
* @brief Gets overall clipping status
* @param pHandle PID current regulator handler
* @retval bool clipping status
*/
bool PIDREG_SPEED_getClipped( PIDREG_SPEED_s* pHandle )
{
return pHandle->clipped;
}
/* end of PIDREG_SPEED_getClipped( PIDREG_SPEED_s* pHandle )*/
/**
* @brief Gets Kp gain in SI unit
* @param pHandle PID speed regulator handler
* @retval float Kp gain in SI unit
*/
float PIDREG_SPEED_getKp_si( PIDREG_SPEED_s* pHandle )
{
float Kp_pu = FIXPSCALED_FIXPscaledToFloat(&pHandle->Kp_fps);
float Kp_si = Kp_pu / pHandle->frequency_scale * pHandle->current_scale;
return Kp_si;
}
/**
* @brief Gets Ki gain in SI unit
* @param pHandle PID speed regulator handler
* @retval float Ki gain in SI unit
*/
float PIDREG_SPEED_getKi_si( PIDREG_SPEED_s* pHandle )
{
float Ki_pu = FIXPSCALED_FIXPscaledToFloat(&pHandle->Ki_fps);
float Ki_si = Ki_pu / pHandle->frequency_scale * pHandle->current_scale * pHandle->pid_freq_hz;
return Ki_si;
}
/**
* @brief Sets Kp gain in SI unit
* @param pHandle PID current regulator handler
* @param Kp Kp gain
*/
void PIDREG_SPEED_setKp_si( PIDREG_SPEED_s* pHandle, const float Kp)
{
// Parameter Kp is in current per speed, A/Hz (electrical)
// User may want to set using different scale, like A/rad*s^-1, that is done external to this function
/* Convert to per unit, in full scale current per full scale frequency */
float Kp_pu = Kp * pHandle->frequency_scale / pHandle->current_scale;
/* Convert Kp_pu to scaled value, and store */
FIXPSCALED_floatToFIXPscaled(Kp_pu, &pHandle->Kp_fps);
}
/**
* @brief Sets Ki gain in SI unit
* @param pHandle PID current regulator handler
* @param Ki Ki gain
*/
void PIDREG_SPEED_setKi_si( PIDREG_SPEED_s* pHandle, const float Ki)
{
/* Parameter Ki is in current per angle, A/rad; */
/* Convert to per unit, in full scale voltage per full scale current per pid_freq_hz */
float Ki_pu = Ki * pHandle->frequency_scale / pHandle->current_scale / pHandle->pid_freq_hz;
FIXPSCALED_floatToFIXPscaled(Ki_pu, &pHandle->Ki_fps);
}
/**
* @brief Sets integral term
* @param pHandle PID current regulator handler
* @param Ui integral term
*/
void PIDREG_SPEED_setUi_pu( PIDREG_SPEED_s* pHandle, const fixp30_t Ui)
{
// Parameter Ui is in the same unit as the output, per unit duty
// Internally the Ui is stored in a different format
pHandle->Ui = (Ui >> (PU_FMT-SUM_FTM));
}
/**
* @brief Sets PID regulator output limits
* @param pHandle PID current regulator handler
* @param max_pu upper limit in per-unit
* @param mix_pu lower limit in per unit
*/
void PIDREG_SPEED_setOutputLimits(PIDREG_SPEED_s* pHandle, const fixp30_t max_pu, const fixp30_t min_pu)
{
pHandle->Max = (max_pu >> (PU_FMT-SUM_FTM));
pHandle->Min = (min_pu >> (PU_FMT-SUM_FTM));
}
/**
* @brief Gets PID regulator maximum output limits
* @param pHandle PID current regulator handler
* @retval fixp30_t maximum output limits
*/
fixp30_t PIDREG_SPEED_getOutputLimitMax(PIDREG_SPEED_s* pHandle)
{
return ((pHandle->Max) << (PU_FMT-SUM_FTM));
}
/**
* @brief Gets PID regulator minimum output limits
* @param pHandle PID current regulator handler
* @retval fixp30_t minimum output limits
*/
fixp30_t PIDREG_SPEED_getOutputLimitMin(PIDREG_SPEED_s* pHandle)
{
return ((pHandle->Min) << (PU_FMT-SUM_FTM));
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 10,194 | C | 31.78135 | 229 | 0.662841 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/flux_weakening_ctrl.c | /**
******************************************************************************
* @file flux_weakening_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implements the Flux Weakening
* Control component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup FluxWeakeningCtrl
*/
/* Includes ------------------------------------------------------------------*/
#include "flux_weakening_ctrl.h"
#include "mc_math.h"
#include "mc_type.h"
#include "pid_regulator.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup FluxWeakeningCtrl Flux Weakening Control
* @brief Flux Weakening (FW) Control component of the Motor Control SDK
*
* The Flux Weakening Control component modifies Idq reference to reach a speed higher than rated one.
* To do so it uses its own PID controller to control the current reference and acts also on the PID speed controller.
*
* Flux Weakening Control component needs to be initialized before it can be used. This is done with the FW_Init()
* function. Ensure that PID speed has been correctly initialized prior to use flux weakiening component.
*
* The controller functions implemented by the FW_CalcCurrRef() functions is based on 16-bit integer arithmetics
* The controller output values returned by this functions is also 16-bit integers. This makes it possible to use this
* component efficiently on all STM2 MCUs.
*
* For more information, please refer to [Flux Weakening documentation](flux_weakening_control.md)
*
* @{
*/
/**
* @brief Initializes flux weakening component handler, it should be called
* once during Motor Control initialization.
* @param pHandle pointer to flux weakening component handler.
* @param pPIDSpeed pointer to speed PID strutcture.
* @param PIDFluxWeakeningHandle pointer to FW PID strutcture.
*/
__weak void FW_Init(FW_Handle_t *pHandle, PID_Handle_t *pPIDSpeed, PID_Handle_t *pPIDFluxWeakeningHandle)
{
#ifdef NULL_PTR_CHECK_FLUX_WEAK
if (NULL == pHandle)
{
/* Mothing to do */
}
else
{
#endif
pHandle->hFW_V_Ref = pHandle->hDefaultFW_V_Ref;
pHandle->pFluxWeakeningPID = pPIDFluxWeakeningHandle;
pHandle->pSpeedPID = pPIDSpeed;
#ifdef NULL_PTR_CHECK_FLUX_WEAK
}
#endif
}
/**
* @brief Clears the Flux weakening internal variables except the target
* voltage (hFW_V_Ref). It should be called before each motor restart
* @param pHandle pointer to flux weakening component handler.
*/
__weak void FW_Clear(FW_Handle_t *pHandle)
{
qd_t V_null = {(int16_t)0, (int16_t)0};
#ifdef NULL_PTR_CHECK_FLUX_WEAK
if (NULL == pHandle)
{
/* Mothing to do */
}
else
{
#endif
PID_SetIntegralTerm(pHandle->pFluxWeakeningPID, (int32_t)0);
pHandle->AvVolt_qd = V_null;
pHandle->AvVoltAmpl = (int16_t)0;
pHandle->hIdRefOffset = (int16_t)0;
#ifdef NULL_PTR_CHECK_FLUX_WEAK
}
#endif
}
/**
* @brief Computes Iqdref according to the flux weakening algorithm.
* As soon as the speed increases beyond the nominal one, flux weakening
* algorithm takes place and handles Idref value. Finally, accordingly
* with new Idref, a new Iqref saturation value is also computed and
* put into speed PI. this routine should be called during background task.
* @param pHandle pointer to flux weakening component handler.
* @param Iqdref current reference that will be
* modified, if needed, by the flux weakening algorithm.
* @retval qd_t Computed Iqdref.
*/
__weak qd_t FW_CalcCurrRef(FW_Handle_t *pHandle, qd_t Iqdref)
{
qd_t IqdrefRet;
#ifdef NULL_PTR_CHECK_FLUX_WEAK
if (NULL == pHandle)
{
IqdrefRet.d = 0;
IqdrefRet.q = 0;
}
else
{
#endif
int32_t wIdRef;
int32_t wIqSatSq;
int32_t wIqSat;
int32_t wAux1;
int16_t Aux2;
uint32_t wVoltLimit_Ref;
int16_t hId_fw;
/* Computation of the Id contribution coming from flux weakening algorithm */
wVoltLimit_Ref = ((uint32_t)(pHandle->hFW_V_Ref) * pHandle->hMaxModule) / 1000U;
Aux2 = MCM_Modulus( pHandle->AvVolt_qd.q, pHandle->AvVolt_qd.d );
pHandle->AvVoltAmpl = Aux2;
hId_fw = PI_Controller(pHandle->pFluxWeakeningPID, (int32_t)wVoltLimit_Ref - (int32_t)Aux2);
/* If the Id coming from flux weakening algorithm (Id_fw) is positive, keep
unchanged Idref, otherwise sum it to last Idref available when Id_fw was
zero */
if (hId_fw >= (int16_t)0)
{
pHandle->hIdRefOffset = Iqdref.d;
wIdRef = (int32_t)Iqdref.d;
}
else
{
wIdRef = (int32_t)pHandle->hIdRefOffset + hId_fw;
}
/* Saturate new Idref to prevent the rotor from being demagnetized */
if (wIdRef < pHandle->hDemagCurrent)
{
wIdRef = pHandle->hDemagCurrent;
}
else
{
/* Nothing to do */
}
IqdrefRet.d = (int16_t)wIdRef;
/* New saturation for Iqref */
wIqSatSq = pHandle->wNominalSqCurr - (wIdRef * wIdRef);
wIqSat = MCM_Sqrt(wIqSatSq);
/* Iqref saturation value used for updating integral term limitations of speed PI */
wAux1 = wIqSat * (int32_t)PID_GetKIDivisor(pHandle->pSpeedPID);
PID_SetLowerIntegralTermLimit(pHandle->pSpeedPID, -wAux1);
PID_SetUpperIntegralTermLimit(pHandle->pSpeedPID, wAux1);
/* Iqref saturation value used for updating integral term limitations of speed PI */
if (Iqdref.q > wIqSat)
{
IqdrefRet.q = (int16_t)wIqSat;
}
else if (Iqdref.q < -wIqSat)
{
IqdrefRet.q = -(int16_t)wIqSat;
}
else
{
IqdrefRet.q = Iqdref.q;
}
#ifdef NULL_PTR_CHECK_FLUX_WEAK
}
#endif
return (IqdrefRet);
}
//cstat #ATH-shift-bounds
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Applies a low-pass filter on both Vqd voltage components. Filter
* bandwidth depends on hVqdLowPassFilterBW parameter. It shall
* be called during current controller task.
* @param pHandle pointer to flux weakening component handler.
* @param Vqd Voltage componets to be averaged.
*/
__weak void FW_DataProcess(FW_Handle_t *pHandle, qd_t Vqd)
{
#ifdef NULL_PTR_CHECK_FLUX_WEAK
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wAux;
int32_t lowPassFilterBW = (int32_t)(pHandle->hVqdLowPassFilterBW) - (int32_t)1 ;
#ifndef FULL_MISRA_C_COMPLIANCY_FLUX_WEAK
wAux = (int32_t)(pHandle->AvVolt_qd.q) * lowPassFilterBW;
wAux += Vqd.q;
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
pHandle->AvVolt_qd.q = (int16_t)(wAux >> pHandle->hVqdLowPassFilterBWLOG);
wAux = (int32_t)(pHandle->AvVolt_qd.d) * lowPassFilterBW;
wAux += Vqd.d;
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
pHandle->AvVolt_qd.d = (int16_t)(wAux >> pHandle->hVqdLowPassFilterBWLOG);
#else
wAux = (int32_t)(pHandle->AvVolt_qd.q) * lowPassFilterBW;
wAux += Vqd.q;
pHandle->AvVolt_qd.q = (int16_t)(wAux / (int32_t)(pHandle->hVqdLowPassFilterBW));
wAux = (int32_t)(pHandle->AvVolt_qd.d) * lowPassFilterBW;
wAux += Vqd.d;
pHandle->AvVolt_qd.d = (int16_t)(wAux / (int32_t)pHandle->hVqdLowPassFilterBW);
#endif
#ifdef NULL_PTR_CHECK_FLUX_WEAK
}
#endif
}
/**
* @brief Sets a new value for the voltage reference used by
* flux weakening algorithm.
* @param pHandle pointer to flux weakening component handler.
* @param hNewVref New target voltage value, expressed in tenth of percentage
* points of available voltage.
*/
__weak void FW_SetVref(FW_Handle_t *pHandle, uint16_t hNewVref)
{
#ifdef NULL_PTR_CHECK_FLUX_WEAK
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hFW_V_Ref = hNewVref;
#ifdef NULL_PTR_CHECK_FLUX_WEAK
}
#endif
}
/**
* @brief Returns the present value of target voltage used by flux
* weakening algorihtm.
* @param pHandle pointer to flux weakening component handler.
* @retval int16_t Present target voltage value expressed in tenth of
* percentage points of available voltage.
*/
__weak uint16_t FW_GetVref(FW_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_FLUX_WEAK
return ((NULL == pHandle) ? 0U : pHandle->hFW_V_Ref);
#else
return (pHandle->hFW_V_Ref);
#endif
}
/**
* @brief Returns the present value of voltage actually used by flux
* weakening algorihtm.
* @param pHandle pointer to flux weakening component handler.
* @retval int16_t Present averaged phase stator voltage value, expressed
* in s16V (0-to-peak), where
* PhaseVoltage(V) = [PhaseVoltage(s16A) * Vbus(V)] /[sqrt(3) *32767].
*/
__weak int16_t FW_GetAvVAmplitude(FW_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_FLUX_WEAK
return ((NULL == pHandle) ? 0 : pHandle->AvVoltAmpl);
#else
return (pHandle->AvVoltAmpl);
#endif
}
/**
* @brief Returns the present voltage actually used by flux
* weakening algorihtm as percentage of available voltage.
* @param pHandle pointer to flux weakening component handler.
* @retval uint16_t Present averaged phase stator voltage value, expressed in
* tenth of percentage points of available voltage.
*/
__weak uint16_t FW_GetAvVPercentage(FW_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_FLUX_WEAK
return ((NULL == pHandle) ? 0U
: (uint16_t)((uint32_t)(pHandle->AvVoltAmpl) * 1000U / (uint32_t)(pHandle->hMaxModule)));
#else
return ((uint16_t)((uint32_t)(pHandle->AvVoltAmpl) * 1000U / (uint32_t)(pHandle->hMaxModule)));
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 10,436 | C | 30.627273 | 121 | 0.650537 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pwm_common.c | /**
******************************************************************************
* @file pwm_common.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement common features
* of the PWM & Current Feedback component of the Motor Control SDK:
*
* * start timers (main and auxiliary) synchronously
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pwm_curr_fdbk
*/
/* Includes ------------------------------------------------------------------*/
#include "pwm_common.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk
* @{
*/
#ifdef TIM2
/**
* @brief Performs the start of all the timers required by the control.
*
* Uses TIM2 as a temporary timer to achieve synchronization between PWM signals.
* When this function is called, TIM1 and/or TIM8 must be in a frozen state
* with CNT, ARR, REP RATE and trigger correctly set (these settings are
* usually performed in the Init method accordingly with the configuration)
*/
__weak void startTimers(void)
{
uint32_t isTIM2ClockOn;
uint32_t trigOut;
isTIM2ClockOn = LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2);
if ((uint32_t)0 == isTIM2ClockOn)
{
/* Temporary Enable TIM2 clock if not already on */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
LL_TIM_GenerateEvent_UPDATE(TIM2);
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2);
}
else
{
trigOut = LL_TIM_ReadReg(TIM2, CR2) & TIM_CR2_MMS;
LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_UPDATE);
LL_TIM_GenerateEvent_UPDATE(TIM2);
LL_TIM_SetTriggerOutput(TIM2, trigOut);
}
}
#endif
/**
* @brief Waits for the end of the polarization.
*
* If the polarization exceeds the number of needed PWM cycles, it reports an error.
*
* @param TIMx Timer used to generate PWM.
* @param SWerror Variable used to report a SW error.
* @param repCnt Repetition counter value.
* @param cnt Polarization counter value.
*/
//cstat !MISRAC2012-Rule-8.13
__weak void waitForPolarizationEnd(TIM_TypeDef *TIMx, uint16_t *SWerror, uint8_t repCnt, volatile uint8_t *cnt)
{
#ifdef NULL_PTR_CHECK_POW_COM
if ((MC_NULL == cnt) || (MC_NULL == SWerror))
{
/* Nothing to do */
}
else
{
#endif
uint16_t hCalibrationPeriodCounter;
uint16_t hMaxPeriodsNumber;
hMaxPeriodsNumber = ((uint16_t)2 * NB_CONVERSIONS) * (((uint16_t)repCnt + 1U) >> 1);
/* Wait for NB_CONVERSIONS to be executed */
LL_TIM_ClearFlag_CC1(TIMx);
hCalibrationPeriodCounter = 0u;
while (*cnt < NB_CONVERSIONS)
{
if ((uint32_t)ERROR == LL_TIM_IsActiveFlag_CC1(TIMx))
{
LL_TIM_ClearFlag_CC1(TIMx);
hCalibrationPeriodCounter++;
if (hCalibrationPeriodCounter >= hMaxPeriodsNumber)
{
if (*cnt < NB_CONVERSIONS)
{
*SWerror = 1u;
break;
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
}
#ifdef NULL_PTR_CHECK_POW_COM
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 3,844 | C | 26.66187 | 112 | 0.567378 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/trajectory_ctrl.c | /**
******************************************************************************
* @file trajectory_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implements the Position Control
* component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup PositionControl
*/
/* Includes ------------------------------------------------------------------*/
#include "trajectory_ctrl.h"
#include "speed_pos_fdbk.h"
/** @addtogroup MCSDK
* @{
*/
/**
* @defgroup PositionControl Position Control
*
* @brief Position Control component of the Motor Control SDK
* The Position Control component allows to control the movement of the motor in two different ways:
*
* * Trajectory control mode, implemented by the TC_MoveCommand() function: allows to move the motor to a specified
* target mechanical position in a settled time (duration) following a programmed trajectory composed of three phases:
* 1- acceleration, 2- rotation at constant speed and 3- deceleration.
* * Follow mode, implemented by the TC_FollowCommand() function: This mode is for instance useful when the trajectory is
* computed by an external controller, or by an algorithm defined by the user.
* The user can send at fixed rate, different target positions according to a required trajectory and the position control
* algorithm computes the intermediate points to reach (follow) the target with a smooth movement.
*
* The position controller uses a PID (with a proportional, integral and derivative action) to regulate the angular position.
*
* @{
*/
/**
* @brief Initializes the handle of position control.
* @param pHandle handler of the current instance of the Position Control component.
* @param pPIDPosReg pointer on the handler of the current instance of PID used for the position regulation.
* @param pSTC pointer on the handler of the current instance of the SpeednTorqCtrl component.
* @param pENC handler of the current instance of the EncAlignCtrl component.
*/
void TC_Init(PosCtrl_Handle_t *pHandle, PID_Handle_t *pPIDPosReg, SpeednTorqCtrl_Handle_t *pSTC, ENCODER_Handle_t *pENC)
{
pHandle->MovementDuration = 0.0f;
pHandle->AngleStep = 0.0f;
pHandle->SubStep[0] = 0.0f;
pHandle->SubStep[1] = 0.0f;
pHandle->SubStep[2] = 0.0f;
pHandle->SubStep[3] = 0.0f;
pHandle->SubStep[4] = 0.0f;
pHandle->SubStep[5] = 0.0f;
pHandle->SubStepDuration = 0;
pHandle->Jerk = 0.0f;
pHandle->CruiseSpeed = 0.0f;
pHandle->Acceleration = 0.0f;
pHandle->Omega = 0.0f;
pHandle->OmegaPrev = 0.0f;
pHandle->Theta = 0.0f;
pHandle->ThetaPrev = 0.0f;
pHandle->ReceivedTh = 0.0f;
pHandle->TcTick = 0;
pHandle->ElapseTime = 0.0f;
pHandle->PositionControlRegulation = DISABLE;
pHandle->PositionCtrlStatus = TC_READY_FOR_COMMAND;
pHandle->pENC = pENC;
pHandle->pSTC = pSTC;
pHandle->PIDPosRegulator = pPIDPosReg;
pHandle->MecAngleOffset = 0;
}
/**
* @brief Configures the trapezoidal speed trajectory.
* @param pHandle handler of the current instance of the Position Control component.
* @param startingAngle Current mechanical position.
* @param angleStep Target mechanical position.
* @param movementDuration Duration to reach the final position (in seconds).
* @retval ConfigurationStatus set to true when Trajectory command is programmed
* otherwise not yet ready for a new trajectory configuration.
*
* This function implements the Trajectory Control mode. When fDuration is different from 0,
* the trajectory of the movement, and therefore its acceleration and speed, are computed.
*
*/
bool TC_MoveCommand(PosCtrl_Handle_t *pHandle, float startingAngle, float angleStep, float movementDuration)
{
bool RetConfigStatus = false;
float fMinimumStepDuration;
if ((pHandle->PositionCtrlStatus == TC_FOLLOWING_ON_GOING) && (movementDuration > 0))
{
/* Back to Move command as the movement duration is different from 0 */
pHandle->PositionCtrlStatus = TC_READY_FOR_COMMAND;
}
else
{
/* Nothing to do */
}
if ((pHandle->PositionCtrlStatus == TC_READY_FOR_COMMAND) && (movementDuration > 0))
{
pHandle->PositionControlRegulation = ENABLE;
fMinimumStepDuration = (9.0f * pHandle->SamplingTime);
/* WARNING: Movement duration value is rounded to the nearest valid value
[(DeltaT/9) / SamplingTime]: shall be an integer value */
pHandle->MovementDuration = (float)((int)(movementDuration / fMinimumStepDuration)) * fMinimumStepDuration;
pHandle->StartingAngle = startingAngle;
pHandle->AngleStep = angleStep;
pHandle->FinalAngle = startingAngle + angleStep;
/* SubStep duration = DeltaT/9 (DeltaT represents the total duration of the programmed movement) */
pHandle->SubStepDuration = pHandle->MovementDuration / 9.0f;
/* Sub step of acceleration phase */
pHandle->SubStep[0] = 1 * pHandle->SubStepDuration; /* Sub-step 1 of acceleration phase */
pHandle->SubStep[1] = 2 * pHandle->SubStepDuration; /* Sub-step 2 of acceleration phase */
pHandle->SubStep[2] = 3 * pHandle->SubStepDuration; /* Sub-step 3 of acceleration phase */
/* Sub step of deceleration Phase */
pHandle->SubStep[3] = 6 * pHandle->SubStepDuration; /* Sub-step 1 of deceleration phase */
pHandle->SubStep[4] = 7 * pHandle->SubStepDuration; /* Sub-step 2 of deceleration phase */
pHandle->SubStep[5] = 8 * pHandle->SubStepDuration; /* Sub-step 3 of deceleration phase */
/* Jerk (J) to be used by the trajectory calculator to integrate (step by step) the target position.
J = DeltaTheta/(12 * A * A * A) => DeltaTheta = final position and A = Sub-Step duration */
pHandle->Jerk = pHandle->AngleStep / (12 * pHandle->SubStepDuration * pHandle->SubStepDuration * pHandle->SubStepDuration);
/* Speed cruiser = 2*J*A*A) */
pHandle->CruiseSpeed = 2 * pHandle->Jerk * pHandle->SubStepDuration * pHandle->SubStepDuration;
pHandle->ElapseTime = 0.0f;
pHandle->Omega = 0.0f;
pHandle->Acceleration = 0.0f;
pHandle->Theta = startingAngle;
pHandle->PositionCtrlStatus = TC_MOVEMENT_ON_GOING; /* new trajectory has been programmed */
RetConfigStatus = true;
}
else
{
/* Nothing to do */
}
return (RetConfigStatus);
}
/**
* @brief Follows an angular position command.
* @param pHandle handler of the current instance of the Position Control component.
* @param Angle Target mechanical position.
*
* This function implements the Follow mode. When the duration is set to zero, the user can send at
* fixed rate different target positions according to a required trajectory and the position control
* algorithm computes the intermediate points to reach (follow) the target with a smooth movement.
* This mode is for instance useful when the trajectory is computed by an external controller, or by
* an algorithm defined by the user and executed by the same microcontroller.
*
*/
void TC_FollowCommand(PosCtrl_Handle_t *pHandle, float Angle)
{
float omega = 0, acceleration = 0, dt = 0;
/* Estimate speed */
if (pHandle->ReceivedTh > 0)
{
/* Calculate dt */
dt = pHandle->TcTick * pHandle->SysTickPeriod;
pHandle->TcTick = 0;
if (dt > 0)
{
omega = (Angle - pHandle->ThetaPrev) / dt;
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
/* Estimated acceleration */
if (pHandle->ReceivedTh > 1)
{
if (dt > 0)
{
acceleration = (omega - pHandle->OmegaPrev) / dt;
}
else
{
/* nothing to do */
}
}
else
{
/* Nothing to do */
}
/* Update state variable */
pHandle->ThetaPrev = Angle;
pHandle->OmegaPrev = omega;
if (pHandle->ReceivedTh < 2)
{
pHandle->ReceivedTh++;
}
else
{
/* Nothing to do */
}
pHandle->Acceleration = acceleration;
pHandle->Omega = omega;
pHandle->Theta = Angle;
pHandle->PositionCtrlStatus = TC_FOLLOWING_ON_GOING; /* follow mode has been programmed */
pHandle->MovementDuration = 0;
}
/**
* @brief Proceeds on the position control loop.
* @param pHandle: handler of the current instance of the Position Control component.
*/
void TC_PositionRegulation(PosCtrl_Handle_t *pHandle)
{
int32_t wMecAngleRef;
int32_t wMecAngle;
int32_t wError;
int32_t hTorqueRef_Pos;
if (pHandle->PositionCtrlStatus == TC_MOVEMENT_ON_GOING)
{
TC_MoveExecution(pHandle);
}
else
{
/* Nothing to do */
}
if (pHandle->PositionCtrlStatus == TC_FOLLOWING_ON_GOING)
{
TC_FollowExecution(pHandle);
}
else
{
/* Nothing to do */
}
if (pHandle->PositionControlRegulation == ENABLE)
{
wMecAngleRef = (int32_t)(pHandle->Theta * RADTOS16);
wMecAngle = SPD_GetMecAngle(STC_GetSpeedSensor(pHandle->pSTC));
wError = wMecAngleRef - wMecAngle;
hTorqueRef_Pos = PID_Controller(pHandle->PIDPosRegulator, wError);
STC_SetControlMode(pHandle->pSTC, MCM_TORQUE_MODE);
STC_ExecRamp(pHandle->pSTC, hTorqueRef_Pos, 0);
}
else
{
/* Nothing to do */
}
}
/**
* @brief Executes the programmed trajectory movement.
* @param pHandle handler of the current instance of the Position Control component.
*/
void TC_MoveExecution(PosCtrl_Handle_t *pHandle)
{
float jerkApplied = 0;
if (pHandle->ElapseTime < pHandle->SubStep[0]) /* 1st Sub-Step interval time of acceleration phase */
{
jerkApplied = pHandle->Jerk;
}
else if (pHandle->ElapseTime < pHandle->SubStep[1]) /* 2nd Sub-Step interval time of acceleration phase */
{
}
else if (pHandle->ElapseTime < pHandle->SubStep[2]) /* 3rd Sub-Step interval time of acceleration phase */
{
jerkApplied = -(pHandle->Jerk);
}
else if (pHandle->ElapseTime < pHandle->SubStep[3]) /* Speed Cruise phase (after acceleration and before
deceleration phases) */
{
pHandle->Acceleration = 0.0f;
pHandle->Omega = pHandle->CruiseSpeed;
}
else if (pHandle->ElapseTime < pHandle->SubStep[4]) /* 1st Sub-Step interval time of deceleration phase */
{
jerkApplied = -(pHandle->Jerk);
}
else if (pHandle->ElapseTime < pHandle->SubStep[5]) /* 2nd Sub-Step interval time of deceleration phase */
{
}
else if (pHandle->ElapseTime < pHandle->MovementDuration) /* 3rd Sub-Step interval time of deceleration phase */
{
jerkApplied = pHandle->Jerk;
}
else
{
pHandle->Theta = pHandle->FinalAngle;
pHandle->PositionCtrlStatus = TC_TARGET_POSITION_REACHED;
}
if (TC_MOVEMENT_ON_GOING == pHandle->PositionCtrlStatus)
{
pHandle->Acceleration += jerkApplied * pHandle->SamplingTime;
pHandle->Omega += pHandle->Acceleration * pHandle->SamplingTime;
pHandle->Theta += pHandle->Omega * pHandle->SamplingTime;
}
else
{
/* Nothing to do */
}
pHandle->ElapseTime += pHandle->SamplingTime;
if (TC_RampCompleted(pHandle))
{
if (TC_ZERO_ALIGNMENT_START == pHandle->AlignmentStatus)
{
/* Ramp is used to search the zero index, if completed there is no z signal */
pHandle->AlignmentStatus = TC_ALIGNMENT_ERROR;
}
else
{
/* Nothing to do */
}
pHandle->ElapseTime = 0;
pHandle->PositionCtrlStatus = TC_READY_FOR_COMMAND;
}
else
{
/* Nothing to do */
}
}
/**
* @brief Updates the angular position.
* @param pHandle handler of the current instance of the Position Control component.
*/
void TC_FollowExecution(PosCtrl_Handle_t *pHandle)
{
pHandle->Omega += pHandle->Acceleration * pHandle->SamplingTime;
pHandle->Theta += pHandle->Omega * pHandle->SamplingTime;
}
/**
* @brief Handles the alignment phase at starting before any position commands.
* @param pHandle: handler of the current instance of the Position Control component.
*/
void TC_EncAlignmentCommand(PosCtrl_Handle_t *pHandle)
{
int32_t wMecAngleRef;
if (TC_ALIGNMENT_COMPLETED == pHandle->AlignmentStatus)
{
pHandle->PositionCtrlStatus = TC_READY_FOR_COMMAND;
/* Do nothing - EncAlignment must be done only one time after the power on */
}
else
{
if (pHandle->AlignmentCfg == TC_ABSOLUTE_ALIGNMENT_SUPPORTED)
{
/* If index is supported start the search of the zero */
pHandle->EncoderAbsoluteAligned = false;
wMecAngleRef = SPD_GetMecAngle(STC_GetSpeedSensor(pHandle->pSTC));
TC_MoveCommand(pHandle, (float)(wMecAngleRef) / RADTOS16, Z_ALIGNMENT_NB_ROTATION, Z_ALIGNMENT_DURATION);
pHandle->AlignmentStatus = TC_ZERO_ALIGNMENT_START;
}
else
{
/* If index is not supprted set the alignment angle as zero reference */
pHandle->pENC->_Super.wMecAngle = 0;
pHandle->AlignmentStatus = TC_ALIGNMENT_COMPLETED;
pHandle->PositionCtrlStatus = TC_READY_FOR_COMMAND;
pHandle->PositionControlRegulation = ENABLE;
}
}
}
/**
* @brief It controls if time allowed for movement is completed.
* @param pHandle: handler of the current instance of the Position Control component.
* @retval Status return true when the programmed trajectory movement is completed
* false when the trajectory movement execution is still ongoing.
*/
bool TC_RampCompleted(PosCtrl_Handle_t *pHandle)
{
bool retVal = false;
/* Check that entire sequence (Acceleration - Cruise - Deceleration) is completed */
if (pHandle->ElapseTime > pHandle->MovementDuration + pHandle->SamplingTime)
{
retVal = true;
}
else
{
/* Nothing to do */
}
return (retVal);
}
/**
* @brief Set the absolute zero mechanical position.
* @param pHandle: handler of the current instance of the Position Control component.
*/
void TC_EncoderReset(PosCtrl_Handle_t *pHandle)
{
if ((!pHandle->EncoderAbsoluteAligned) && (pHandle->AlignmentStatus == TC_ZERO_ALIGNMENT_START))
{
pHandle->MecAngleOffset = pHandle->pENC->_Super.hMecAngle;
pHandle->pENC->_Super.wMecAngle = 0;
pHandle->EncoderAbsoluteAligned = true;
pHandle->AlignmentStatus = TC_ALIGNMENT_COMPLETED;
pHandle->PositionCtrlStatus = TC_READY_FOR_COMMAND;
pHandle->Theta = 0.0f;
ENC_SetMecAngle(pHandle->pENC, pHandle->MecAngleOffset);
}
else
{
/* Nothing to do */
}
}
/**
* @brief Returns the current rotor mechanical angle, expressed in radiant.
* @param pHandle: handler of the current instance of the Position Control component.
* @retval current mechanical position
*/
float TC_GetCurrentPosition(PosCtrl_Handle_t *pHandle)
{
return ((float)((SPD_GetMecAngle(STC_GetSpeedSensor(pHandle->pSTC))) / RADTOS16));
}
/**
* @brief Returns the target rotor mechanical angle, expressed in radiant.
* @param pHandle: handler of the current instance of the Position Control component.
* @retval Target mechanical position
*/
float TC_GetTargetPosition(PosCtrl_Handle_t *pHandle)
{
return (pHandle->FinalAngle);
}
/**
* @brief Returns the duration used to execute the movement, expressed in seconds.
* @param pHandle handler of the current instance of the Position Control component.
* @retval Duration of programmed movement
*/
float TC_GetMoveDuration(PosCtrl_Handle_t *pHandle)
{
return (pHandle->MovementDuration);
}
/**
* @brief Returns the status of the position control execution.
* @param pHandle: handler of the current instance of the Position Control component.
* @retval Position Control Status
*/
PosCtrlStatus_t TC_GetControlPositionStatus(PosCtrl_Handle_t *pHandle)
{
return (pHandle->PositionCtrlStatus);
}
/**
* @brief Returns the status after the rotor alignment phase.
* @param pHandle handler of the current instance of the Position Control component.
*/
AlignStatus_t TC_GetAlignmentStatus(PosCtrl_Handle_t *pHandle)
{
return (pHandle->AlignmentStatus);
}
/**
* @brief Increments Tick counter used in follow mode.
* @param pHandle handler of the current instance of the Position Control component.
*/
void TC_IncTick(PosCtrl_Handle_t *pHandle)
{
pHandle->TcTick++;
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 16,855 | C | 30.803774 | 127 | 0.670958 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pwmc_3pwm.c | /**
******************************************************************************
* @file pwmc_3pwm.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides the firmware functions that implement the
* pwmc_3pwm component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pwmc_3pwm
*/
/* Includes ------------------------------------------------------------------*/
#include "pwmc_3pwm.h"
#include "pwm_common_sixstep.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk_6s
* @{
*/
/**
* @defgroup pwmc_3pwm Six-Step, 3 signals PWM generation
*
* @brief PWM generation implementation for Six-Step drive with 3 PWM duty cycles
*
* This implementation only drives the high sides of the bridges. The low sides are
* automatically driven by the gate driver that inserts the dead time.
*
* Three additional signals are generated to enable or disable the PWM output of each
* phase.
*
* @todo: Complete documentation.
* @{
*/
/* Private defines -----------------------------------------------------------*/
#define TIMxCCER_MASK_CH123 (LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH3)
/* Private function prototypes -----------------------------------------------*/
void ThreePwm_ResetEnablePins( PWMC_ThreePwm_Handle_t * pHandle );
/**
* @brief It initializes TIMx and NVIC
* @param pHdl: handler of the current instance of the PWM component
* @retval none
*/
__weak void ThreePwm_Init( PWMC_ThreePwm_Handle_t * pHandle )
{
if ( ( uint32_t )pHandle == ( uint32_t )&pHandle->_Super )
{
/* Enable the CCS */
LL_RCC_HSE_EnableCSS();
/* Peripheral clocks enabling END ----------------------------------------*/
/* Clear TIMx break flag. */
LL_TIM_ClearFlag_BRK( pHandle->pParams_str->TIMx );
LL_TIM_EnableIT_BRK( pHandle->pParams_str->TIMx );
LL_TIM_ClearFlag_UPDATE( pHandle->pParams_str->TIMx );
/* disable ADC source trigger */
LL_TIM_SetTriggerOutput(pHandle->pParams_str->TIMx, LL_TIM_TRGO_RESET);
/* Enable PWM channel */
LL_TIM_CC_EnableChannel( pHandle->pParams_str->TIMx, TIMxCCER_MASK_CH123 );
/* Clear the flags */
pHandle->_Super.OverVoltageFlag = false;
pHandle->_Super.OverCurrentFlag = false;
pHandle->_Super.driverProtectionFlag = false;
pHandle->FastDemagUpdated = true;
pHandle->_Super.hElAngle = 0;
LL_TIM_EnableCounter( pHandle->pParams_str->TIMx );
if (pHandle->pParams_str->OCPolarity == LL_TIM_OCPOLARITY_HIGH)
{
pHandle->NegOCPolarity = LL_TIM_OCPOLARITY_LOW;
}
else
{
pHandle->NegOCPolarity = LL_TIM_OCPOLARITY_HIGH;
}
}
}
/**
* @brief It updates the stored duty cycle variable.
* @param pHandle Pointer on the target component instance.
* @param new duty cycle value.
* @retval none
*/
__weak void PWMC_SetPhaseVoltage( PWMC_Handle_t * pHandle, uint16_t DutyCycle )
{
pHandle->CntPh = DutyCycle;
}
/**
* @brief It writes the duty cycle into timer shadow registers.
* @param pHandle Pointer on the target component instance.
* @retval none
*/
__weak void ThreePwm_LoadNextStep( PWMC_ThreePwm_Handle_t * pHandle, int16_t Direction )
{
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.NextStep = PWMC_ElAngleToStep(&(pHandle->_Super));
if (pHandle->_Super.Step != pHandle->_Super.NextStep)
{
pHandle->DemagCounter = 0;
if (pHandle->_Super.ModUpdateReq == ENABLE_FAST_DEMAG)
{
pHandle->FastDemag = true;
pHandle->_Super.ModUpdateReq = NO_REQUEST;
}
if (pHandle->_Super.ModUpdateReq == DISABLE_FAST_DEMAG)
{
ThreePwm_ResetOCPolarity(pHandle);
LL_TIM_GenerateEvent_COM( TIMx );
pHandle->FastDemag = false;
pHandle->_Super.ModUpdateReq = NO_REQUEST;
}
}
/* Fast demagnetization */
if (( pHandle->FastDemag == true ) && ( pHandle->DemagCounter < (pHandle->_Super.DemagCounterThreshold)))
{
uint16_t CWFastDemagPulse, CCWFastDemagPulse;
uint32_t CWFastDemagPolarity, CCWFastDemagPolarity;
pHandle->FastDemagUpdated = false;
if (Direction > 0)
{
CWFastDemagPulse = pHandle->_Super.CntPh;
CCWFastDemagPulse = 0;
CWFastDemagPolarity = pHandle->NegOCPolarity;
CCWFastDemagPolarity = pHandle->pParams_str->OCPolarity;
}
else
{
CWFastDemagPulse = 0;
CCWFastDemagPulse = pHandle->_Super.CntPh;
CWFastDemagPolarity = pHandle->pParams_str->OCPolarity;
CCWFastDemagPolarity = pHandle->NegOCPolarity;
}
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetCompareCH2 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, CWFastDemagPolarity);
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, CCWFastDemagPolarity);
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetCompareCH3 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, CWFastDemagPolarity);
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetCompareCH2 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, CCWFastDemagPolarity);
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, CWFastDemagPolarity);
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetCompareCH3 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, CCWFastDemagPolarity);
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
}
}
/* Alignment between two adjacent steps, CW direction*/
else if ( pHandle->_Super.AlignFlag == 1 )
{
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
}
}
/* Alignment between two adjacent steps, CCW direction*/
else if ( pHandle->_Super.AlignFlag == -1 )
{
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
}
}
/* standard configuration */
else
{
if (pHandle->DemagCounter >= pHandle->_Super.DemagCounterThreshold )
{
pHandle->FastDemagUpdated = true;
ThreePwm_ResetOCPolarity(pHandle);
LL_TIM_GenerateEvent_COM( TIMx );
}
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
break;
}
}
}
/**
* @brief It uploads the values into registers.
* @param pHandle Pointer on the target component instance.
* @retval bool Registers have been updated
*/
__weak bool ThreePwm_ApplyNextStep( PWMC_ThreePwm_Handle_t * pHandle )
{
bool retVal = false;
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
if (pHandle->_Super.Step != pHandle->_Super.NextStep)
{
LL_TIM_GenerateEvent_COM( TIMx );
LL_TIM_GenerateEvent_UPDATE( TIMx );
pHandle->_Super.Step = pHandle->_Super.NextStep;
retVal = true;
}
return retVal;
}
/**
* @brief It checks whether the fastdemag configuration has been updated.
* @param pHandle Pointer on the target component instance.
* @retval bool FastDemag configuration has been updated
*/
__weak bool ThreePwm_IsFastDemagUpdated( PWMC_ThreePwm_Handle_t * pHandle )
{
return (pHandle->FastDemagUpdated);
}
/**
* @brief It resets the polarity of the timer PWM channel outputs to default.
* @param pHandle Pointer on the target component instance.
* @retval none
*/
__weak void ThreePwm_ResetOCPolarity( PWMC_ThreePwm_Handle_t * pHandle )
{
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, pHandle->pParams_str->OCPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, pHandle->pParams_str->OCPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, pHandle->pParams_str->OCPolarity);
}
/**
* @brief It turns on low sides switches. This function is intended to be
* used for charging boot capacitors of driving section. It has to be
* called each motor start-up when using high voltage drivers
* @param pHdl: handler of the current instance of the PWM component
* @retval none
*/
__weak void ThreePwm_TurnOnLowSides( PWMC_Handle_t * pHdl, uint32_t ticks)
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_ThreePwm_Handle_t * pHandle = ( PWMC_ThreePwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.TurnOnLowSidesAction = true;
/* Clear Update Flag */
LL_TIM_ClearFlag_UPDATE( TIMx );
/*Turn on the three low side switches */
LL_TIM_OC_SetCompareCH1(TIMx, 0u);
LL_TIM_OC_SetCompareCH2(TIMx, 0u);
LL_TIM_OC_SetCompareCH3(TIMx, 0u);
ThreePwm_ResetOCPolarity( pHandle );
LL_TIM_GenerateEvent_COM( TIMx );
/* Main PWM Output Enable */
LL_TIM_EnableAllOutputs(TIMx);
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_SetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
/**
* @brief This function enables the PWM outputs
* @param pHdl: handler of the current instance of the PWM component
* @retval none
*/
__weak void ThreePwm_SwitchOnPWM( PWMC_Handle_t * pHdl )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_ThreePwm_Handle_t * pHandle = ( PWMC_ThreePwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.TurnOnLowSidesAction = false;
pHandle->DemagCounter = 0;
LL_TIM_EnableIT_UPDATE( pHandle->pParams_str->TIMx );
/* Select the Capture Compare preload feature */
LL_TIM_CC_EnablePreload( TIMx );
/* Select the Commutation event source */
LL_TIM_CC_SetUpdate( TIMx, LL_TIM_CCUPDATESOURCE_COMG_ONLY );
LL_TIM_OC_SetCompareCH1(TIMx, 0u);
LL_TIM_OC_SetCompareCH2(TIMx, 0u);
LL_TIM_OC_SetCompareCH3(TIMx, 0u);
LL_TIM_OC_SetMode( TIMx, LL_TIM_CHANNEL_CH1, LL_TIM_OCMODE_PWM1 );
LL_TIM_OC_SetMode( TIMx, LL_TIM_CHANNEL_CH2, LL_TIM_OCMODE_PWM1 );
LL_TIM_OC_SetMode( TIMx, LL_TIM_CHANNEL_CH3, LL_TIM_OCMODE_PWM1 );
ThreePwm_ResetOCPolarity( pHandle );
LL_TIM_GenerateEvent_COM( TIMx );
/* Main PWM Output Enable */
TIMx->BDTR |= LL_TIM_OSSI_ENABLE;
LL_TIM_EnableAllOutputs(TIMx);
if (true == pHandle->Oversampling )
{
LL_TIM_SetTriggerOutput(TIMx, LL_TIM_TRGO_UPDATE);
}
else
{
LL_TIM_SetTriggerOutput(TIMx, LL_TIM_TRGO_OC4REF);
}
}
/**
* @brief This function sets the capcture compare of the timer channel
* used for ADC triggering
* @param pHdl: handler of the current instance of the PWM component
* @param SamplingPoint: trigger point
* @retval none
*/
__weak void ThreePwm_SetADCTriggerChannel( PWMC_Handle_t * pHdl, uint16_t SamplingPoint )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_ThreePwm_Handle_t * pHandle = ( PWMC_ThreePwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.ADCTriggerCnt = SamplingPoint;
LL_TIM_OC_SetCompareCH4(TIMx, pHandle->_Super.ADCTriggerCnt);
}
/**
* @brief It disables PWM generation on the proper Timer peripheral acting on
* MOE bit and reset the TIM status
* @param pHdl: handler of the current instance of the PWM component
* @retval none
*/
__weak void ThreePwm_SwitchOffPWM( PWMC_Handle_t * pHdl )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_ThreePwm_Handle_t * pHandle = ( PWMC_ThreePwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.TurnOnLowSidesAction = false;
ThreePwm_ResetEnablePins ( pHandle );
/* Main PWM Output Disable */
LL_TIM_DisableAllOutputs(TIMx);
LL_TIM_OC_SetCompareCH1(TIMx, 0u);
LL_TIM_OC_SetCompareCH2(TIMx, 0u);
LL_TIM_OC_SetCompareCH3(TIMx, 0u);
pHandle->_Super.CntPh = 0;
LL_TIM_DisableIT_UPDATE( pHandle->pParams_str->TIMx );
LL_TIM_SetTriggerOutput(pHandle->pParams_str->TIMx, LL_TIM_TRGO_RESET);
return;
}
/**
* @brief It contains the Break event interrupt
* @param pHandle: handler of the current instance of the PWM component
* @retval none
*/
__weak void * ThreePwm_BRK_IRQHandler( PWMC_ThreePwm_Handle_t * pHandle )
{
pHandle->_Super.OverCurrentFlag = true;
LL_TIM_DisableIT_UPDATE( pHandle->pParams_str->TIMx );
LL_TIM_ClearFlag_UPDATE( pHandle->pParams_str->TIMx );
return MC_NULL;
}
void ThreePwm_ResetEnablePins( PWMC_ThreePwm_Handle_t * pHandle )
{
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_u_port, pHandle->pParams_str->pwm_en_u_pin );
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_v_port, pHandle->pParams_str->pwm_en_v_pin );
LL_GPIO_ResetOutputPin( pHandle->pParams_str->pwm_en_w_port, pHandle->pParams_str->pwm_en_w_pin );
}
/**
* @brief It is used to return the fast demagnetization flag.
* @param pHdl: handler of the current instance of the PWM component
* @retval uint16_t It returns 1 whether fast demag is active.
*/
__weak uint8_t ThreePwm_FastDemagFlag( PWMC_Handle_t * pHdl )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_ThreePwm_Handle_t * pHandle = ( PWMC_ThreePwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
return (pHandle->FastDemag);
}
/**
* @brief This function updates the demagnetization counter
* @param pHandle: handler of the current instance of the PWM component
* @retval none
*/
__weak void ThreePwm_UpdatePwmDemagCounter( PWMC_ThreePwm_Handle_t * pHandle )
{
pHandle->DemagCounter += LL_TIM_GetRepetitionCounter(TIM1) + 1;
LL_TIM_EnableIT_UPDATE(TIM1);
}
/**
* @brief This function disable the update of the demagnetization counter in the update event
* @param pHandle: handler of the current instance of the PWM component
* @retval none
*/
__weak void ThreePwm_DisablePwmDemagCounter( PWMC_ThreePwm_Handle_t * pHandle )
{
LL_TIM_DisableIT_UPDATE(TIM1);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 28,077 | C | 39.341954 | 138 | 0.637105 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/inrush_current_limiter.c | /**
******************************************************************************
* @file inrush_current_limiter.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions implementing the
* Inrush Current Limiter feature of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup ICL
*/
/* Includes ------------------------------------------------------------------*/
#include "inrush_current_limiter.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup ICL Inrush Current Limiter
* @brief Inrush Current Limiter component of the Motor Control SDK
*
* Inrush current limiter acts on the NTC bypass relay according to the DC bus level in
* order to limit the current when charging DC bulk capacitor.
* In order to work properly, it needs to point on the Vbus and digital output handlers
* to measure the DC bus and control the NTC bypass relay. Inrush current limiter has
* its own state machine described below:
*
* 
*
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief Initializes all the needed ICL component variables.
* It shall be called only once during Motor Control initialization.
* @param pHandle: handler of the current instance of the ICL component
* @param pVBS the bus voltage sensor used by the ICL.
* @param pDOUT the digital output used by the ICL.
*/
__weak void ICL_Init(ICL_Handle_t *pHandle, BusVoltageSensor_Handle_t *pVBS, DOUT_handle_t *pDOUT)
{
pHandle->pVBS = pVBS;
pHandle->pDOUT = pDOUT;
DOUT_SetOutputState(pDOUT, ACTIVE);
}
/**
* @brief Executes the inrush current limiter state machine and shall be
* called during background task.
* @param pHandle handler of the current instance of the ICL component
* @retval ICLState_t returns the current ICL state machine
*/
__weak ICL_State_t ICL_Exec(ICL_Handle_t *pHandle)
{
/* ICL actions.*/
switch (pHandle->ICLstate)
{
case ICL_ACTIVATION:
{
/* ICL activation: counting the step before pass in ICL_ACTIVE */
if (pHandle->hICLTicksCounter == 0u)
{
pHandle->ICLstate = ICL_ACTIVE;
pHandle->hICLTicksCounter = pHandle->hICLChargingDelayTicks;
}
else
{
pHandle->hICLTicksCounter--;
}
}
break;
case ICL_DEACTIVATION:
{
/* ICL deactivation: counting the step before pass in ICL_INACTIVE.*/
if (pHandle->hICLTicksCounter == 0u)
{
pHandle->ICLstate = ICL_INACTIVE;
}
else
{
pHandle->hICLTicksCounter--;
}
}
break;
case ICL_ACTIVE:
{
/* ICL is active: if bus is present and capacitor charging time elapsed*/
if (pHandle->hICLTicksCounter == 0u)
{
if (VBS_GetAvBusVoltage_d(pHandle->pVBS) > pHandle->hICLVoltageThreshold){
DOUT_SetOutputState(pHandle->pDOUT, INACTIVE);
pHandle->ICLstate = ICL_DEACTIVATION;
pHandle->hICLTicksCounter = pHandle->hICLSwitchDelayTicks;
}
}
else
{
pHandle->hICLTicksCounter--;
}
}
break;
case ICL_INACTIVE:
{
/* ICL is inactive: if bus is not present activate the ICL */
if (VBS_CheckVbus(pHandle->pVBS) == MC_UNDER_VOLT)
{
DOUT_SetOutputState(pHandle->pDOUT, ACTIVE);
pHandle->ICLstate = ICL_ACTIVATION;
pHandle->hICLTicksCounter = pHandle->hICLSwitchDelayTicks;
}
}
break;
case ICL_IDLE:
default:
{
}
break;
}
return pHandle->ICLstate;
}
/**
* @brief Returns the current state of the ICL state machine.
* @param pHandle: handler of the current instance of the ICL component
* @retval ICLState_t returns the current ICL state machine
*/
__weak ICL_State_t ICL_GetState(ICL_Handle_t *pHandle)
{
return pHandle->ICLstate;
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,024 | C | 28.910714 | 98 | 0.552747 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/mathlib.c | /**
******************************************************************************
* @file mathlib.c
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* mathlib.c */
#include "mathlib.h"
#include <math.h>
#include <stdlib.h>
#include <stdbool.h>
/* defines */
#define CST_LEN 128
#define _MTL (CST_LEN) // Max Cos table _MTL = 2^k, Actual length = _MTL+1.
#define COSSIN_TABLESIZE _MTL
#define COSSIN_FORMAT 15
#define _MNB 30 // Position of binary point.
#define _BITS 24 // Maximum bits of precision.
#define _MAXI _BITS+1 // Maximum number of Cordic iterations.
#ifndef M_TWOPI
#define M_TWOPI 6.28318530717958647f
#endif
/* Fixed point macros */
#define __CFIXPn(A, n) (int32_t) ((A) * powf(2.0f, n))
#define __CFIXPnmpy(a, b, n) ( (int32_t)(((int64_t) (a) * (b)) >> (n)) )
#define __CFIXPntoF(A, n) ((float_t)(((float_t) (A)) / powf(2.0f, n)))
/* types */
typedef struct _DQL
{
int b; // bit precision.
int tpk; // number of bits required to index length m table (m=128 -> s_tpk=7)
int tablesize; // source table size (RAM table is (4xtablesize)+2 long)
} dql, *DQL;
// Int DQ structure prototype.
typedef struct _DQI
{
// Cordic consts.
int g;
// pi/2, pi and 1.
int hpi, pi, one;
// Cordic tables.
int atan[_MAXI];
// Cordic & bit precision.
int n, b;
} dqi, *DQI;
/* variables */
/* RAM table */
// _cstl[k] = _RNDL(csti[k]*((float) _MPL)).
// Extra point need for sin interpolation.
long _cstl[4*_MTL+2];
dql cossin_instance =
{
.b = COSSIN_FORMAT /* fixp_t<n> format angle and output */
};
dqi cordic_instance =
{
.n = 15, /* cordic_iterations */
.b = 30 /* cordic_bits */
};
// Cos table: _RNDL(cos(i*pi/(2*_MTL))*(2 << _MNB))
long _cst_128[CST_LEN+1] = {
1073741824, 1073660973, 1073418433, 1073014240, 1072448455,
1071721163, 1070832474, 1069782521, 1068571464, 1067199483,
1065666786, 1063973603, 1062120190, 1060106826, 1057933813,
1055601479, 1053110176, 1050460278, 1047652185, 1044686319,
1041563127, 1038283080, 1034846671, 1031254418, 1027506862,
1023604567, 1019548121, 1015338134, 1010975242, 1006460100,
1001793390, 996975812, 992008094, 986890984, 981625251,
976211688, 970651112, 964944360, 959092290, 953095785,
946955747, 940673101, 934248793, 927683790, 920979082,
914135678, 907154608, 900036924, 892783698, 885396022,
877875009, 870221790, 862437520, 854523370, 846480531,
838310216, 830013654, 821592095, 813046808, 804379079,
795590213, 786681534, 777654384, 768510122, 759250125,
749875788, 740388522, 730789757, 721080937, 711263525,
701339000, 691308855, 681174602, 670937767, 660599890,
650162530, 639627258, 628995660, 618269338, 607449906,
596538995, 585538248, 574449320, 563273883, 552013618,
540670223, 529245404, 517740883, 506158392, 494499676,
482766489, 470960600, 459083786, 447137835, 435124548,
423045732, 410903207, 398698801, 386434353, 374111709,
361732726, 349299266, 336813204, 324276419, 311690799,
299058239, 286380643, 273659918, 260897982, 248096755,
235258165, 222384147, 209476638, 196537583, 183568930,
170572633, 157550647, 144504935, 131437462, 118350194,
105245103, 92124163, 78989349, 65842639, 52686014,
39521455, 26350943, 13176464, 0 };
/* function declarations */
void cos_sin_tabl_init(void);
void cordic_initi(DQI zi);
/* functions */
static inline int log2i(int m)
{
int p2 = 0, k = 1;
// Find p2, m <= 2^p2.
while (k < m)
{
p2++;
k <<= 1;
}
return p2;
} /* end of log2i() */
void cos_sin_tabl_init()
{
/* Not optimized, since we will be converting to a static table, pre-compiled */
DQL zi = &cossin_instance;
int tablesize = COSSIN_TABLESIZE;
int b = zi->b;
int m4 = tablesize << 2;
zi->tablesize = tablesize;
// Find tpk, m = 2^tpk.
zi->tpk = log2i(tablesize); /* number of bits required to index length m table. m=128 -> 7 */
// Difference bits.
int bb = _MNB - b;
// Decimation factor.
int mk;
mk = _MTL >> zi->tpk;
// Quadrant = 0 cos.
int i;
int k;
for (i = 0, k = 0; k <= _MTL; k += mk, i++)
{
_cstl[i] = _cst_128[k] >> bb;
// Next lower 2 bits.
long ths;
ths = _cst_128[k] >> (bb - 2);
// Next 2 lower bits on?
if ((ths & 3) == 3)
{
// Round up.
_cstl[i] += 1;
}
}
// Quadrant = 1 cos.
for (k = i, i = 0; i <= tablesize; i++)
{
_cstl[i+tablesize] = -_cstl[--k];
}
// Quadrants = 2, 3 cos.
for (i += tablesize, k = i-1; i <= m4; i++)
{
_cstl[i] = _cstl[--k];
}
// Extra point.
_cstl[i] = _cstl[i-1];
} /* end of cos_sin_tabl_init() */
// Assumes a normalized angle: 0 <= th/(2*pi) < 1.
// Fast table z = cos(th) + j*sin(th) (long) precision,
// for a value of th using 4*m+2 entry cos table + Taylor
// extrapolation or linear interpolation, absolute.
Vector_cossin_s MATHLIB_cossin(int32_t angle_pu)
{
/* scale of data is fixp_t<m> format, 15 is working, 30 is not.
*
* inputs:
* thr angle theta in per unit (0 = 0 degrees, 1 = 360 degrees)
*
* outputs:
* x cosine
* y sine
*
* tables:
* _cst_128 128 long cosine table, source data, could be in rom
* _cstl 4*_MTL+2 = up to 514 long, derived table, in ram
*
*/
DQL zi = &cossin_instance;
// Number of bits.
int b = zi->b;
// table size
int tablesize = zi->tablesize;
// ths = |th|*m*4.
/* shift left (multiply by 2^n) by tpk (7) + 2 = 9 */
/* ths = fixp15_t(0.999f) << 9, giving fixp24_t(0.999f) */
/* This causes fixp30_t angle to fail */
/* tpk comes from needing log2(m) bits to index the table */
/* the 2 comes from having 1/4 of a rotation in the table */
long ths = labs(angle_pu) << (zi->tpk + 2);
// k = ths/m, 0 <= k < m.
/* shift right by b=15, k is fixp9_t (for tablesize = 128), i.e. k becomes the index for the cosine value but ... */
/* fixp9_t(1.0f) = 512, the table is 1/4 of that. The 2 extra bits */
int k = (int) (ths >> b);
/* k could be calculated in one step; */
/* k = _iq<b>toiq<s_tpk+2> = _iq15toiq9 */
/* k = th >> () */ // _q15 << (s_tkp + 2) >> b == _q15 << (7 + 2) >> 15 == _q15 >> 6 == conversion to _q9
// thf = (ths - k*m).
// Note use of bit ops.
long thf = ths & ~(k << b);
/* used in linear interpolation / extrapolation */
/* k = index, top bits of angle */
/* k << b = top bits back in top bits place */
/* ~ is bitwise NOT, turning those bits off */
/* & masks the index bits off */
/* remainder after removing the k*m part */
// Cos value.
long cs = _cstl[k];
// Modulo m4 index.
/* sine table is cosine table + offset, values inverted? */
int mk = tablesize + k; /* sine index = tablesize + cosine index */
int m4 = tablesize << 2; // Table length * 4.
if (mk > m4) /* wrap sine index (could be bit operation?) */
{
mk -= m4;
}
// Sin value.
long sn = -_cstl[mk]; /* mk is sine index, value is negated because sine table is -cosine table, with an offset? */
// Linear interpolation.
cs += (((_cstl[k + 1] - cs) * thf) >> b);
sn -= (((_cstl[mk + 1] + sn) * thf) >> b);
/* linear interpolation for better, smoother result */
/* k+1 and mk+1 point to the next entry in the table
* (_cstl[k+1]-cs) = delta to next (sine variant uses inverse values)
* * thf multiplies with a fixp_t<b> format number (?), giving fixp_t<2*b> intermediate, >> b shifts back to fixp_t<b> format
* (this limits the function to (1/2 * fixp32_t format), approx)
*
* cs += delta_next * thf
*
* thf must be linear factor dx/step
*/
Vector_cossin_s result;
result.cos = cs;
result.sin = sn;
return result;
} /* end of cos_sin_tabl_LX() */
//
// zi->K factor & atanti for zi->n iterations.
// Note: Should be called first for init.
//
void cordic_initi(DQI zi)
{
int k; /* Loop variable */
int g; /* term for gain[] calculation */
// Convert pi/2, pi, 3*pi/2, 2*pi and one.
zi->one = __CFIXPn(1.0f, zi->b);
/* Per unit angles */
zi->hpi = __CFIXPn(0.25f, zi->b); /* 1/2 PI, 90 degrees, 0.25f per unit */
zi->pi = __CFIXPn(0.5f, zi->b); /* PI, 180 degrees, 0.5f per unit */
// Initialize.
g = zi->one;
// Cordic tables & constants.
for (k = 0; k < zi->n; k++)
{
// Cordic atan tables.
/* floating point calculated variant */
{
float_t slope = powf(2, -k);
zi->atan[k] = __CFIXPn((atanf(slope) / M_TWOPI), zi->b);
}
// Gain table.
if (k < 7)
{
g += (g >> 2*(k + 1));
}
}
// nth constants.
float_t g_flt = __CFIXPntoF(g, zi->b); /* Convert g to floating point */
float_t gain_flt = 1.0f / sqrtf(g_flt); /* Calculate 1/sqrt(g) */
zi->g = __CFIXPn(gain_flt, zi->b); /* Convert result back to fixed point */
} /* end of cordic_initi() */
// Integer precision (int) version
// to b bits of precision, b = zi->b.
// Cordic algorithm to convert complex
// cartesian to polar form. The input
// is complex pair {x, y} where w = x + j*y
// and the phase angle th = atan2(y, x).
// Applies n iterations of Cordic algorithm
// to rotate w to w' such that imag(w') = 0
// and thus |w'| = real(w'). The result is
// multiplied by the Cordic gain g. Pass
// address &zi of dqi data structure.
//
// Input: x = zi->x, y = zi->y, n = zi->n,
// b = zi->b, and g = zi->g.
// Output: th = zi->th, r = zi->r.
//
// cordic_cpoli(&zi);
//
void MATHLIB_polar(const int32_t x, const int32_t y, int32_t *angle_pu, int32_t *magnitude)
{
DQI zi = &cordic_instance;
// Get |components|.
int ax = abs(x);
int ay = abs(y);
// Swap x & y?
bool swapped = false;
if (ay > ax)
{
int temp = ax;
ax = ay;
ay = temp;
swapped = true;
}
// Rotate y to zero.
int sx;
int sy;
int th = 0;
int k;
for (k = 1; k < zi->n; k++)
{
// Cordic increment.
sy = ay >> k;
sx = ax >> k;
// Cordic rotation.
if (ay >= 0)
{
ax += sy;
ay -= sx;
th += zi->atan[k];
}
else
{
ax -= sy;
ay += sx;
th -= zi->atan[k];
}
}
if (swapped) th = zi->hpi - th; /* x/y swapped */
if (x < 0) th = zi->pi - th; /* left half plane */
if (y < 0) th = zi->one - th; /* lower half plane */
*angle_pu = th;
// Normalized magnitude.
*magnitude = __CFIXPnmpy(ax, zi->g, zi->b); /* r = x*g */
} /* end of MATHLIB_polar() */
void MATHLIB_init()
{
/* Initialize cosine/sine table/object */
cos_sin_tabl_init();
/* Initialize cordic table/object */
cordic_initi(&cordic_instance);
} /* end of MATHLIB_init() */
/* end of mathlib.c */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 11,000 | C | 25.444711 | 126 | 0.592727 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/encoder_speed_pos_fdbk.c | /**
******************************************************************************
* @file encoder_speed_pos_fdbk.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the following features
* of the Encoder component of the Motor Control SDK:
* - computes and stores average mechanical speed
* - computes and stores average mechanical acceleration
* - computes and stores the instantaneous electrical speed
* - calculates the rotor electrical and mechanical angle
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup Encoder
*/
/* Includes ------------------------------------------------------------------*/
#include "encoder_speed_pos_fdbk.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup SpeednPosFdbk
* @{
*/
/** @defgroup Encoder Encoder Speed & Position Feedback
* @brief Quadrature Encoder based Speed & Position Feedback implementation
*
* This component is used in applications controlling a motor equipped with a quadrature encoder.
*
* This component uses the output of a quadrature encoder to provide a measure of the speed and
* the motor rotor position.
*
* More detail in [Encoder Speed & Position Feedback module](rotor_speed_pos_feedback_qenc.md).
*
* @{
*/
/* Private defines -----------------------------------------------------------*/
/**
* @brief It initializes the hardware peripherals
required for the speed position sensor management using ENCODER
sensors.
* @param pHandle: handler of the current instance of the encoder component
*/
__weak void ENC_Init(ENCODER_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
TIM_TypeDef *TIMx = pHandle->TIMx;
uint8_t bufferSize;
uint8_t index;
#ifdef TIM_CNT_UIFCPY
LL_TIM_EnableUIFRemap(TIMx);
#define ENC_MAX_OVERFLOW_NB ((uint16_t)2048) /* 2^11*/
#else
#define ENC_MAX_OVERFLOW_NB (1)
#endif
/* Reset counter */
LL_TIM_SetCounter(TIMx, 0);
/*Calculations of convenience*/
pHandle->U32MAXdivPulseNumber = UINT32_MAX / ((uint32_t) pHandle->PulseNumber);
pHandle->SpeedSamplingFreqUnit = ((uint32_t)pHandle->SpeedSamplingFreqHz * (uint32_t)SPEED_UNIT);
/* Set IC filter for both channel 1 & 2 */
LL_TIM_IC_SetFilter(TIMx, LL_TIM_CHANNEL_CH1, ((uint32_t)pHandle->ICx_Filter));
LL_TIM_IC_SetFilter(TIMx, LL_TIM_CHANNEL_CH2, ((uint32_t)pHandle->ICx_Filter));
LL_TIM_ClearFlag_UPDATE(TIMx);
LL_TIM_EnableIT_UPDATE(TIMx);
/* Enable the counting timer */
LL_TIM_EnableCounter(TIMx);
/* Erase speed buffer */
bufferSize = pHandle->SpeedBufferSize;
for (index = 0U; index < bufferSize; index++)
{
pHandle->DeltaCapturesBuffer[index] = 0;
}
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
}
#endif
}
/**
* @brief Clear software FIFO where the captured rotor angle variations are stored.
* This function must be called before starting the motor to initialize
* the speed measurement process.
* @param pHandle: handler of the current instance of the encoder component
*/
__weak void ENC_Clear(ENCODER_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
uint8_t index;
for (index = 0u; index < pHandle->SpeedBufferSize; index++)
{
pHandle->DeltaCapturesBuffer[index] = 0;
}
pHandle->SensorIsReliable = true;
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
}
#endif
}
/**
* @brief It calculates the rotor electrical and mechanical angle, on the basis
* of the instantaneous value of the timer counter.
* @param pHandle: handler of the current instance of the encoder component
* @retval Measured electrical angle in [s16degree](measurement_units.md) format.
*/
__weak int16_t ENC_CalcAngle(ENCODER_Handle_t *pHandle)
{
int16_t elAngle; /* s16degree format */
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
if (NULL == pHandle)
{
elAngle = 0;
}
else
{
#endif
int16_t mecAngle; /* s16degree format */
uint32_t uwtemp1;
int32_t wtemp1;
/* PR 52926 We need to keep only the 16 LSB, bit 31 could be at 1
if the overflow occurs just after the entry in the High frequency task */
uwtemp1 = (LL_TIM_GetCounter(pHandle->TIMx) & 0xffffU) * (pHandle->U32MAXdivPulseNumber);
#ifndef FULL_MISRA_C_COMPLIANCY_ENC_SPD_POS
wtemp1 = (int32_t)uwtemp1 >> 16U; //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
wtemp1 = (int32_t)uwtemp1 / 65536;
#endif
/* Computes and stores the rotor mechanical angle */
mecAngle = (int16_t)wtemp1;
int16_t hMecAnglePrev = pHandle->_Super.hMecAngle;
pHandle->_Super.hMecAngle = mecAngle;
/* Computes and stores the rotor electrical angle */
elAngle = mecAngle * (int16_t)(pHandle->_Super.bElToMecRatio);
pHandle->_Super.hElAngle = elAngle;
int16_t hMecSpeedDpp = mecAngle - hMecAnglePrev;
pHandle->_Super.wMecAngle += ((int32_t)hMecSpeedDpp);
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
}
#endif
/*Returns rotor electrical angle*/
return (elAngle);
}
/**
* @brief This method must be called with the periodicity defined by parameter
* SpeedSamplingFreqUnit. The method generates a capture event on
* a channel, computes and stores average mechanical speed expressed in the unit
* defined by #SPEED_UNIT (on the basis of the buffer filled by Medium Frequency Task),
* computes and stores average mechanical acceleration expressed in #SPEED_UNIT/SpeedSamplingFreq,
* computes and stores the instantaneous electrical speed in Digit Per control Period
* unit [dpp](measurement_units.md), updates the index of the
* speed buffer, then checks, stores and returns the reliability state
* of the sensor.
* @param pHandle: handler of the current instance of the encoder component
* @param pMecSpeedUnit pointer used to return the rotor average mechanical speed
* expressed in the unit defined by #SPEED_UNIT
* @retval true = sensor information is reliable. false = sensor information is not reliable
*/
__weak bool ENC_CalcAvrgMecSpeedUnit(ENCODER_Handle_t *pHandle, int16_t *pMecSpeedUnit)
{
bool bReliability;
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
if ((NULL == pHandle) || (NULL == pMecSpeedUnit))
{
bReliability = false;
}
else
{
#endif
int32_t wtemp1;
int32_t wtemp2;
uint32_t OverflowCntSample;
uint32_t CntCapture;
uint32_t directionSample;
int32_t wOverallAngleVariation = 0;
TIM_TypeDef *TIMx = pHandle->TIMx;
uint8_t bBufferSize = pHandle->SpeedBufferSize;
uint8_t bBufferIndex;
#ifdef TIM_CNT_UIFCPY
uint8_t OFbit;
#else
uint8_t OFbit = 0U;
#endif
#ifdef TIM_CNT_UIFCPY
/* disable Interrupt generation */
LL_TIM_DisableIT_UPDATE(TIMx);
#endif
CntCapture = LL_TIM_GetCounter(TIMx);
OverflowCntSample = pHandle->TimerOverflowNb;
pHandle->TimerOverflowNb = 0;
directionSample = LL_TIM_GetDirection(TIMx);
#ifdef TIM_CNT_UIFCPY
OFbit = __LL_TIM_GETFLAG_UIFCPY(CntCapture);
if (0U == OFbit)
{
/* Nothing to do */
}
else
{
/* If OFbit is set, overflow has occured since IT has been disabled.
We have to take this overflow into account in the angle computation,
but we must not take it into account a second time in the accmulator,
so we have to clear the pending flag. If the OFbit is not set, it does not mean
that an Interrupt has not occured since the last read, but it has not been taken
into accout, we must not clear the interrupt in order to accumulate it */
LL_TIM_ClearFlag_UPDATE(TIMx);
}
LL_TIM_EnableIT_UPDATE(TIMx);
CLEAR_BIT(CntCapture, TIM_CNT_UIFCPY);
#endif
/* If UIFCPY is not present, OverflowCntSample can not be used safely for
speed computation, but we still use it to check that we do not exceed one overflow
(sample frequency not less than mechanical motor speed */
if ((OverflowCntSample + OFbit) > ENC_MAX_OVERFLOW_NB)
{
pHandle->TimerOverflowError = true;
}
else
{
/* Nothing to do */
}
/* Calculation of delta angle */
if (LL_TIM_COUNTERDIRECTION_DOWN == directionSample)
{
/* Encoder timer down-counting */
/* If UIFCPY not present Overflow counter can not be safely used -> limitation to 1 OF */
#ifndef TIM_CNT_UIFCPY
OverflowCntSample = (CntCapture > pHandle->PreviousCapture) ? 1 : 0;
#endif
pHandle->DeltaCapturesBuffer[pHandle->DeltaCapturesIndex] =
((int32_t)CntCapture) - ((int32_t)pHandle->PreviousCapture)
- ((((int32_t)OverflowCntSample) + (int32_t)OFbit) * ((int32_t)pHandle->PulseNumber));
}
else
{
/* Encoder timer up-counting */
/* If UIFCPY not present Overflow counter can not be safely used -> limitation to 1 OF */
#ifndef TIM_CNT_UIFCPY
OverflowCntSample = (CntCapture < pHandle->PreviousCapture) ? 1 : 0;
#endif
pHandle->DeltaCapturesBuffer[pHandle->DeltaCapturesIndex] =
((int32_t)CntCapture) - ((int32_t)pHandle->PreviousCapture)
+ ((((int32_t)OverflowCntSample) + (int32_t)OFbit) * ((int32_t)pHandle->PulseNumber));
}
/* Computes & returns average mechanical speed */
for (bBufferIndex = 0U; bBufferIndex < bBufferSize; bBufferIndex++)
{
wOverallAngleVariation += pHandle->DeltaCapturesBuffer[bBufferIndex];
}
wtemp1 = wOverallAngleVariation * ((int32_t)pHandle->SpeedSamplingFreqUnit);
wtemp2 = ((int32_t)pHandle->PulseNumber) * ((int32_t)pHandle->SpeedBufferSize);
wtemp1 = ((0 == wtemp2) ? wtemp1 : (wtemp1 / wtemp2));
*pMecSpeedUnit = (int16_t)wtemp1;
/* Computes & stores average mechanical acceleration */
pHandle->_Super.hMecAccelUnitP = (int16_t)(wtemp1 - pHandle->_Super.hAvrMecSpeedUnit);
/* Stores average mechanical speed */
pHandle->_Super.hAvrMecSpeedUnit = (int16_t)wtemp1;
/* Computes & stores the instantaneous electrical speed [dpp], var wtemp1 */
wtemp1 = pHandle->DeltaCapturesBuffer[pHandle->DeltaCapturesIndex] * ((int32_t)pHandle->SpeedSamplingFreqHz)
* ((int32_t)pHandle->_Super.bElToMecRatio);
wtemp1 /= ((int32_t)pHandle->PulseNumber);
wtemp1 *= ((int32_t)pHandle->_Super.DPPConvFactor);
wtemp1 /= ((int32_t)pHandle->_Super.hMeasurementFrequency);
pHandle->_Super.hElSpeedDpp = (int16_t)wtemp1;
/* Last captured value update */
pHandle->PreviousCapture = (CntCapture >= (uint32_t)65535) ? 65535U : (uint16_t)CntCapture;
/*Buffer index update*/
pHandle->DeltaCapturesIndex++;
if (pHandle->DeltaCapturesIndex >= pHandle->SpeedBufferSize)
{
pHandle->DeltaCapturesIndex = 0U;
}
else
{
/* Nothing to do */
}
/* Checks the reliability status, then stores and returns it */
if (pHandle->TimerOverflowError)
{
bReliability = false;
pHandle->SensorIsReliable = false;
pHandle->_Super.bSpeedErrorNumber = pHandle->_Super.bMaximumSpeedErrorsNumber;
}
else
{
bReliability = SPD_IsMecSpeedReliable(&pHandle->_Super, pMecSpeedUnit);
}
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
}
#endif
return (bReliability);
}
/**
* @brief It set instantaneous rotor mechanical angle.
* As a consequence, timer counter is computed and updated.
* @param pHandle: handler of the current instance of the encoder component
* @param hMecAngle new value of rotor mechanical angle in [s16degree](measurement_units.md) format.
*/
__weak void ENC_SetMecAngle(ENCODER_Handle_t *pHandle, int16_t hMecAngle)
{
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
TIM_TypeDef *TIMx = pHandle->TIMx;
uint16_t hAngleCounts;
uint16_t hMecAngleuint;
int16_t localhMecAngle = hMecAngle;
pHandle->_Super.hMecAngle = localhMecAngle;
pHandle->_Super.hElAngle = localhMecAngle * (int16_t)pHandle->_Super.bElToMecRatio;
if (localhMecAngle < 0)
{
localhMecAngle *= -1;
hMecAngleuint = ((uint16_t)65535 - ((uint16_t)localhMecAngle));
}
else
{
hMecAngleuint = (uint16_t)localhMecAngle;
}
hAngleCounts = (uint16_t)((((uint32_t)hMecAngleuint) * ((uint32_t)pHandle->PulseNumber)) / 65535U);
TIMx->CNT = (uint16_t)hAngleCounts;
#ifdef NULL_PTR_CHECK_ENC_SPD_POS_FDB
}
#endif
}
/**
* @brief TIMER ENCODER Overflow interrupt counter update
* @param pHandleVoid: handler of the current instance of the encoder component
*/
__weak void *ENC_IRQHandler(void *pHandleVoid)
{
ENCODER_Handle_t *pHandle = (ENCODER_Handle_t *)pHandleVoid; //cstat !MISRAC2012-Rule-11.5
/* Updates the number of overflows occurred */
/* The handling of overflow error is done in ENC_CalcAvrgMecSpeedUnit */
pHandle->TimerOverflowNb += 1U;
return (MC_NULL);
}
/**
* @}
*/
/**
* @}
*/
/** @} */
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 13,748 | C | 31.735714 | 112 | 0.654204 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pwmc_6pwm.c | /**
******************************************************************************
* @file pwmc_6pwm.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides the firmware functions that implement the
* pwmc_6pwm component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pwmc_6pwm
*/
/* Includes ------------------------------------------------------------------*/
#include "pwmc_6pwm.h"
#include "pwm_common_sixstep.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk_6s
* @{
*/
/**
* @defgroup pwmc_6pwm Six-Step, 6 signals PWM generation
*
* @brief PWM generation implementation for Six-Step drive with 6 PWM duty cycles
*
* This implementation drives both the high sides and the low sides of the bridges.
*
* @todo: Complete documentation.
* @{
*/
/* Private defines -----------------------------------------------------------*/
#define TIMxCCER_MASK_CH123 (LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH3 )
#define TIMxCCER_MASK_CH1N2N3N (LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3N)
/* Private function prototypes -----------------------------------------------*/
/**
* @brief It initializes TIMx, DMA1 and NVIC
* @param pHdl: handler of the current instance of the PWM component
* @retval none
*/
__weak void SixPwm_Init( PWMC_SixPwm_Handle_t * pHandle )
{
if ( ( uint32_t )pHandle == ( uint32_t )&pHandle->_Super )
{
/* Enable the CCS */
LL_RCC_HSE_EnableCSS();
/* Peripheral clocks enabling END ----------------------------------------*/
/* Clear TIMx break flag. */
LL_TIM_ClearFlag_BRK( pHandle->pParams_str->TIMx );
LL_TIM_EnableIT_BRK( pHandle->pParams_str->TIMx );
LL_TIM_ClearFlag_UPDATE( pHandle->pParams_str->TIMx );
/* disable ADC source trigger */
LL_TIM_SetTriggerOutput(pHandle->pParams_str->TIMx, LL_TIM_TRGO_RESET);
/* Enable PWM channel */
LL_TIM_CC_EnableChannel( pHandle->pParams_str->TIMx, TIMxCCER_MASK_CH123 | TIMxCCER_MASK_CH1N2N3N );
/* Clear the flags */
pHandle->_Super.OverVoltageFlag = false;
pHandle->_Super.OverCurrentFlag = false;
pHandle->_Super.driverProtectionFlag = false;
pHandle->FastDemagUpdated = true;
pHandle->_Super.hElAngle = 0;
LL_TIM_EnableCounter( pHandle->pParams_str->TIMx );
if (pHandle->pParams_str->OCPolarity == LL_TIM_OCPOLARITY_HIGH)
{
pHandle->NegOCPolarity = LL_TIM_OCPOLARITY_LOW;
}
else
{
pHandle->NegOCPolarity = LL_TIM_OCPOLARITY_HIGH;
}
if (pHandle->pParams_str->OCNPolarity == LL_TIM_OCPOLARITY_HIGH)
{
pHandle->NegOCNPolarity = LL_TIM_OCPOLARITY_LOW;
}
else
{
pHandle->NegOCNPolarity = LL_TIM_OCPOLARITY_HIGH;
}
}
}
/**
* @brief It updates the stored duty cycle variable.
* @param pHandle Pointer on the target component instance.
* @param new duty cycle value.
* @retval none
*/
__weak void PWMC_SetPhaseVoltage( PWMC_Handle_t * pHandle, uint16_t DutyCycle )
{
pHandle->CntPh = DutyCycle;
}
/**
* @brief It writes the duty cycle into timer shadow registers.
* @param pHandle Pointer on the target component instance.
* @retval none
*/
__weak void SixPwm_LoadNextStep( PWMC_SixPwm_Handle_t * pHandle, int16_t Direction )
{
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.NextStep = PWMC_ElAngleToStep(&(pHandle->_Super));
if (pHandle->_Super.Step != pHandle->_Super.NextStep)
{
pHandle->DemagCounter = 0;
if (pHandle->_Super.ModUpdateReq == ENABLE_FAST_DEMAG)
{
pHandle->FastDemag = true;
pHandle->_Super.ModUpdateReq = NO_REQUEST;
}
if (pHandle->_Super.ModUpdateReq == DISABLE_FAST_DEMAG)
{
SixPwm_ResetOCPolarity(pHandle);
LL_TIM_GenerateEvent_COM( TIMx );
pHandle->FastDemag = false;
pHandle->_Super.ModUpdateReq = NO_REQUEST;
}
if (pHandle->_Super.ModUpdateReq == ENABLE_QUASI_SYNCH)
{
pHandle->QuasiSynchDecay = true;
pHandle->_Super.ModUpdateReq = NO_REQUEST;
}
if (pHandle->_Super.ModUpdateReq == DISABLE_QUASI_SYNCH)
{
pHandle->QuasiSynchDecay = false;
pHandle->_Super.ModUpdateReq = NO_REQUEST;
}
}
/* Quasi-synchronous rectification */
if ( pHandle->QuasiSynchDecay == true)
{
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N | LL_TIM_CHANNEL_CH1N);
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH1N);
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2N);
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N | LL_TIM_CHANNEL_CH2N);
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH3);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3N);
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH3N);
}
break;
}
}
/* Fast demagnetization */
else if (( pHandle->FastDemag == true ) && ( pHandle->DemagCounter < (pHandle->_Super.DemagCounterThreshold )))
{
uint16_t CWFastDemagPulse, CCWFastDemagPulse;
uint32_t CWFastDemagPolarity, CWFastDemagNPolarity, CCWFastDemagPolarity, CCWFastDemagNPolarity;
pHandle->FastDemagUpdated = false;
if (Direction > 0)
{
CWFastDemagPulse = pHandle->_Super.CntPh;
CCWFastDemagPulse = 0;
CWFastDemagPolarity = pHandle->NegOCPolarity;
CWFastDemagNPolarity = pHandle->NegOCNPolarity;
CCWFastDemagPolarity = pHandle->pParams_str->OCPolarity;
CCWFastDemagNPolarity = pHandle->pParams_str->OCNPolarity;
}
else
{
CWFastDemagPulse = 0;
CCWFastDemagPulse = pHandle->_Super.CntPh;
CWFastDemagPolarity = pHandle->pParams_str->OCPolarity;
CWFastDemagNPolarity = pHandle->pParams_str->OCNPolarity;
CCWFastDemagPolarity = pHandle->NegOCPolarity;
CCWFastDemagNPolarity = pHandle->NegOCNPolarity;
}
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetCompareCH2 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1N, CWFastDemagNPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2N, CWFastDemagNPolarity);
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1N, CCWFastDemagNPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3N, CCWFastDemagNPolarity);
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N );
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetCompareCH3 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2N, CWFastDemagNPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3N, CWFastDemagNPolarity);
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N );
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetCompareCH2 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1N, CCWFastDemagNPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2N, CCWFastDemagNPolarity);
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, CWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1N, CWFastDemagNPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3N, CWFastDemagNPolarity);
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N );
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, CCWFastDemagPulse );
LL_TIM_OC_SetCompareCH3 ( TIMx, CWFastDemagPulse );
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, CCWFastDemagPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2N, CCWFastDemagNPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3N, CCWFastDemagNPolarity);
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N );
}
break;
}
}
/* Alignment between two adjacent steps, CW direction*/
else if ( pHandle->_Super.AlignFlag == 1 )
{
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
}
break;
}
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N);
}
/* Alignment between two adjacent steps, CCW direction*/
else if ( pHandle->_Super.AlignFlag == -1 )
{
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
}
break;
}
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N);
}
/* standard configuration */
else
{
if (pHandle->DemagCounter >= pHandle->_Super.DemagCounterThreshold )
{
pHandle->FastDemagUpdated = true;
SixPwm_ResetOCPolarity(pHandle);
LL_TIM_GenerateEvent_COM( TIMx );
}
switch ( pHandle->_Super.NextStep )
{
case STEP_1:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N);
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
}
break;
case STEP_2:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N );
}
break;
case STEP_3:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N );
}
break;
case STEP_4:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_OC_SetCompareCH3 ( TIMx, 0 );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
}
break;
case STEP_5:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N );
}
break;
case STEP_6:
{
LL_TIM_OC_SetCompareCH1 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH2 ( TIMx, 0 );
LL_TIM_OC_SetCompareCH3 ( TIMx, (uint32_t)pHandle->_Super.CntPh );
LL_TIM_CC_EnableChannel( TIMx, LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N );
LL_TIM_CC_DisableChannel( TIMx, LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N );
}
break;
}
}
}
/**
* @brief It uploads the values into registers.
* @param pHandle Pointer on the target component instance.
* @retval bool Registers have been updated
*/
__weak bool SixPwm_ApplyNextStep( PWMC_SixPwm_Handle_t * pHandle )
{
bool retVal = false;
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
if (pHandle->_Super.Step != pHandle->_Super.NextStep)
{
LL_TIM_GenerateEvent_COM( TIMx );
LL_TIM_GenerateEvent_UPDATE( TIMx );
pHandle->_Super.Step = pHandle->_Super.NextStep;
retVal = true;
}
return retVal;
}
/**
* @brief It checks whether the fastdemag configuration has been updated.
* @param pHandle Pointer on the target component instance.
* @retval bool FastDemag configuration has been updated
*/
__weak bool SixPwm_IsFastDemagUpdated( PWMC_SixPwm_Handle_t * pHandle )
{
return (pHandle->FastDemagUpdated);
}
/**
* @brief It resets the polarity of the timer PWM channel outputs to default.
* @param pHandle Pointer on the target component instance.
* @retval none
*/
__weak void SixPwm_ResetOCPolarity( PWMC_SixPwm_Handle_t * pHandle )
{
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1, pHandle->pParams_str->OCPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH1N, pHandle->pParams_str->OCNPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2, pHandle->pParams_str->OCPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH2N, pHandle->pParams_str->OCNPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3, pHandle->pParams_str->OCPolarity);
LL_TIM_OC_SetPolarity( TIMx, LL_TIM_CHANNEL_CH3N, pHandle->pParams_str->OCNPolarity);
}
/**
* @brief It turns on low sides switches. This function is intended to be
* used for charging boot capacitors of driving section. It has to be
* called each motor start-up when using high voltage drivers
* @param pHdl: handler of the current instance of the PWM component
* @retval none
*/
__weak void SixPwm_TurnOnLowSides( PWMC_Handle_t * pHdl, uint32_t ticks)
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_SixPwm_Handle_t * pHandle = ( PWMC_SixPwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.TurnOnLowSidesAction = true;
/* Clear Update Flag */
LL_TIM_ClearFlag_UPDATE( TIMx );
/*Turn on the three low side switches */
LL_TIM_OC_SetCompareCH1(TIMx, 0u);
LL_TIM_OC_SetCompareCH2(TIMx, 0u);
LL_TIM_OC_SetCompareCH3(TIMx, 0u);
SixPwm_ResetOCPolarity(pHandle);
LL_TIM_GenerateEvent_COM( TIMx );
/* Main PWM Output Enable */
LL_TIM_EnableAllOutputs(TIMx);
}
/**
* @brief This function enables the PWM outputs
* @param pHdl: handler of the current instance of the PWM component
* @retval none
*/
__weak void SixPwm_SwitchOnPWM( PWMC_Handle_t * pHdl )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_SixPwm_Handle_t * pHandle = ( PWMC_SixPwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.TurnOnLowSidesAction = false;
pHandle->DemagCounter = 0;
LL_TIM_EnableIT_UPDATE( pHandle->pParams_str->TIMx );
/* Select the Capture Compare preload feature */
LL_TIM_CC_EnablePreload( TIMx );
/* Select the Commutation event source */
LL_TIM_CC_SetUpdate( TIMx, LL_TIM_CCUPDATESOURCE_COMG_ONLY );
LL_TIM_OC_SetCompareCH1(TIMx, 0u);
LL_TIM_OC_SetCompareCH2(TIMx, 0u);
LL_TIM_OC_SetCompareCH3(TIMx, 0u);
LL_TIM_OC_SetMode( TIMx, LL_TIM_CHANNEL_CH1, LL_TIM_OCMODE_PWM1 );
LL_TIM_OC_SetMode( TIMx, LL_TIM_CHANNEL_CH2, LL_TIM_OCMODE_PWM1 );
LL_TIM_OC_SetMode( TIMx, LL_TIM_CHANNEL_CH3, LL_TIM_OCMODE_PWM1 );
SixPwm_ResetOCPolarity( pHandle );
LL_TIM_GenerateEvent_COM( TIMx );
/* Main PWM Output Enable */
TIMx->BDTR |= LL_TIM_OSSI_ENABLE;
LL_TIM_EnableAllOutputs(TIMx);
if (true == pHandle->Oversampling )
{
LL_TIM_SetTriggerOutput(TIMx, LL_TIM_TRGO_UPDATE);
}
else
{
LL_TIM_SetTriggerOutput(TIMx, LL_TIM_TRGO_OC4REF);
}
}
/**
* @brief This function sets the capcture compare of the timer channel
* used for ADC triggering
* @param pHdl: handler of the current instance of the PWM component
* @param SamplingPoint: trigger point
* @retval none
*/
__weak void SixPwm_SetADCTriggerChannel( PWMC_Handle_t * pHdl, uint16_t SamplingPoint )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_SixPwm_Handle_t * pHandle = ( PWMC_SixPwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.ADCTriggerCnt = SamplingPoint;
LL_TIM_OC_SetCompareCH4(TIMx, pHandle->_Super.ADCTriggerCnt);
}
/**
* @brief It disables PWM generation on the proper Timer peripheral acting on
* MOE bit and reset the TIM status
* @param pHdl: handler of the current instance of the PWM component
* @retval none
*/
__weak void SixPwm_SwitchOffPWM( PWMC_Handle_t * pHdl )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_SixPwm_Handle_t * pHandle = ( PWMC_SixPwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
TIM_TypeDef * TIMx = pHandle->pParams_str->TIMx;
pHandle->_Super.TurnOnLowSidesAction = false;
/* Main PWM Output Disable */
LL_TIM_DisableAllOutputs(TIMx);
LL_TIM_OC_SetCompareCH1(TIMx, 0u);
LL_TIM_OC_SetCompareCH2(TIMx, 0u);
LL_TIM_OC_SetCompareCH3(TIMx, 0u);
pHandle->_Super.CntPh = 0;
LL_TIM_DisableIT_UPDATE( pHandle->pParams_str->TIMx );
LL_TIM_SetTriggerOutput(pHandle->pParams_str->TIMx, LL_TIM_TRGO_RESET);
return;
}
/**
* @brief It contains the Break event interrupt
* @param pHandle: handler of the current instance of the PWM component
* @retval none
*/
__weak void * SixPwm_BRK_IRQHandler( PWMC_SixPwm_Handle_t * pHandle )
{
pHandle->_Super.OverCurrentFlag = true;
LL_TIM_DisableIT_UPDATE( pHandle->pParams_str->TIMx );
LL_TIM_ClearFlag_UPDATE( pHandle->pParams_str->TIMx );
return MC_NULL;
}
/**
* @brief It is used to return the fast demagnetization flag.
* @param pHdl: handler of the current instance of the PWM component
* @retval uint16_t It returns 1 whether fast demag is active.
*/
__weak uint8_t SixPwm_FastDemagFlag( PWMC_Handle_t * pHdl )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_SixPwm_Handle_t * pHandle = ( PWMC_SixPwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
return (pHandle->FastDemag);
}
/**
* @brief It is used to return the quasi-synchronous rectification flag.
* @param pHdl: handler of the current instance of the PWM component
* @retval uint16_t It returns 1 whether quasi-synch feature is active.
*/
__weak uint8_t SixPwm_QuasiSynchFlag( PWMC_Handle_t * pHdl )
{
#if defined (__ICCARM__)
#pragma cstat_disable = "MISRAC2012-Rule-11.3"
#endif
PWMC_SixPwm_Handle_t * pHandle = ( PWMC_SixPwm_Handle_t * )pHdl;
#if defined (__ICCARM__)
#pragma cstat_restore = "MISRAC2012-Rule-11.3"
#endif
return (pHandle->QuasiSynchDecay);
}
/**
* @brief This function updates the demagnetization counter
* @param pHandle: handler of the current instance of the PWM component
* @retval none
*/
__weak void SixPwm_UpdatePwmDemagCounter( PWMC_SixPwm_Handle_t * pHandle )
{
pHandle->DemagCounter += LL_TIM_GetRepetitionCounter(TIM1) + 1;
LL_TIM_EnableIT_UPDATE(TIM1);
}
/**
* @brief This function disable the update of the demagnetization counter in the update event
* @param pHandle: handler of the current instance of the PWM component
* @retval none
*/
__weak void SixPwm_DisablePwmDemagCounter( PWMC_SixPwm_Handle_t * pHandle )
{
LL_TIM_DisableIT_UPDATE(TIM1);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 28,163 | C | 36.552 | 165 | 0.620708 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/profiler_dcac.c | /**
******************************************************************************
* @file profiler_dcac.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions of profiler DC/AC
* component
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*
*/
/* Includes ------------------------------------------------------------------*/
#include "profiler_dcac.h"
#include "mc_math.h"
void PROFILER_DCAC_stateMachine(PROFILER_DCAC_Handle handle, MOTOR_Handle motor);
/**
* @brief todo
*/
void PROFILER_DCAC_init(PROFILER_DCAC_Handle handle)
{
handle->state = PROFILER_DCAC_STATE_Idle;
}
/**
* @brief todo
*/
void PROFILER_DCAC_setParams(PROFILER_DCAC_Handle handle, PROFILER_Params* pParams)
{
handle->background_rate_hz = pParams->background_rate_hz;
/* Number of medium frequency task cycles in the dc measurement time */
PROFILER_DCAC_setMeasurementTime(handle, pParams->dcac_measurement_time_s);
handle->CurToRamp_sf_pu = FIXP30(1.0f / pParams->dcac_current_ramping_time_s / pParams->background_rate_hz);
/* duty setpoint */
handle->duty_maxgoal_pu = FIXP30(pParams->dcac_duty_maxgoal);
handle->ac_freqkHz_pu = FIXP30(pParams->dcac_ac_freq_Hz / 1000.0f);
handle->dc_duty_pu = FIXP30(0.0f);
handle->ac_duty_pu = FIXP30(0.0f);
handle->PowerDC_goal_W = pParams->dcac_PowerDC_goal_W;
/* Current setpoint */
handle->Id_dc_max_pu = FIXP30(pParams->dcac_DCmax_current_A / pParams->fullScaleCurrent_A);
/* Ramp rate */
handle->ramp_rate_duty_per_cycle = FIXP30(pParams->dcac_duty_maxgoal / pParams->dcac_duty_ramping_time_s / pParams->background_rate_hz);
handle->fullScaleVoltage_V = pParams->fullScaleVoltage_V;
handle->fullScaleCurrent_A = pParams->fullScaleCurrent_A;
handle->voltagefilterpole_rps = pParams->voltagefilterpole_rps;
handle->CurToRamp_sf_pu = FIXP30(1.0f / pParams->fullScaleCurrent_A / pParams->dcac_current_ramping_time_s / pParams->background_rate_hz);
handle->glue_dcac_fluxestim_on = pParams->glue_dcac_fluxestim_on;
}
/**
* @brief todo
*/
void PROFILER_DCAC_run(PROFILER_DCAC_Handle handle, MOTOR_Handle motor)
{
/* This function is called from the high frequency task / motor control interrupt */
/* After Sensorless and CurrentControl, so the DQ-values are available */
{
/* Calculate filtered voltages and currents */
Voltages_Udq_t Udq = motor->pCurrCtrl->Udq_in_pu;
Currents_Idq_t Idq = motor->pCurrCtrl->Idq_in_pu;
/* Run filters with wLP = fs/(2^filtshift) (rad/sec) */
int filtshift = 10;
handle->UdqLP.D += (Udq.D - handle->UdqLP.D) >> filtshift;
handle->UdqLP.Q += (Udq.Q - handle->UdqLP.Q) >> filtshift;
handle->IdqLP.D += (Idq.D - handle->IdqLP.D) >> filtshift;
handle->IdqLP.Q += (Idq.Q - handle->IdqLP.Q) >> filtshift;
}
switch (handle->state)
{
case PROFILER_DCAC_STATE_AC_Measuring:
{
/* During AC Measuring state, use the ZEST injection as a duty injection */
Duty_Ddq_t Ddq;
ZEST_getIdq_ref_inject_pu(motor->pSPD->pZeST, &Ddq); /* AC component for injection */
motor->pCurrCtrl->Ddq_ref_pu.D = handle->dc_duty_pu + Ddq.D;
}
break;
default:
/* Nothing to do */
break;
}
}
/**
* @brief todo
*/
void PROFILER_DCAC_runBackground(PROFILER_DCAC_Handle handle, MOTOR_Handle motor)
{
/* This function is called from the medium frequency task */
/* Counter counts down */
if (handle->counter > 0) handle->counter--;
switch (handle->state)
{
/* Duty ramping */
case PROFILER_DCAC_STATE_RampUp:
{
fixp30_t ramp_rate = handle->ramp_rate_duty_per_cycle;
fixp30_t delta_pu = handle->duty_maxgoal_pu - handle->dc_duty_pu; /* delta = target - current */
handle->dc_duty_pu += FIXP_sat(delta_pu, ramp_rate, -ramp_rate);
motor->pCurrCtrl->Ddq_ref_pu.D = handle->dc_duty_pu;
}
break;
case PROFILER_DCAC_STATE_DC_Measuring:
motor->pCurrCtrl->Ddq_ref_pu.D = handle->dc_duty_pu;
break;
case PROFILER_DCAC_STATE_AC_Measuring:
/* update duty performed in PROFILER_DCAC_run() function */
break;
case PROFILER_DCAC_STATE_DConly:
motor->pCurrCtrl->Ddq_ref_pu.D = handle->dc_duty_pu;
break;
case PROFILER_DCAC_STATE_RampDown:
{
fixp30_t ramp_rate = handle->ramp_rate_duty_per_cycle;
fixp30_t delta_pu = 0 - handle->dc_duty_pu; /* delta = target - current */
handle->dc_duty_pu += FIXP_sat(delta_pu, ramp_rate, -ramp_rate);
motor->pCurrCtrl->Ddq_ref_pu.D = handle->dc_duty_pu;
}
break;
case PROFILER_DCAC_STATE_Idle:
/* No break */
case PROFILER_DCAC_STATE_Complete:
/* No break */
case PROFILER_DCAC_STATE_Error:
/* Nothing to do in these states */
break;
}
PROFILER_DCAC_stateMachine(handle, motor);
}
/**
* @brief todo
*/
void PROFILER_DCAC_reset(PROFILER_DCAC_Handle handle, MOTOR_Handle motor)
{
/* This is called before starting the DCAC process, and when the user aborts the Profiling */
/* Reset the DCAC state */
handle->state = PROFILER_DCAC_STATE_Idle;
handle->error = PROFILER_DCAC_ERROR_None;
/* Stop any ongoing actions */
motor->pSPD->zestControl.enableControlUpdate = true;
motor->pSPD->flagHsoAngleEqualsOpenLoopAngle = false;
motor->pCurrCtrl->Ddq_ref_pu.D = 0;
motor->pCurrCtrl->Ddq_ref_pu.Q = 0;
/* Reset duty reached */
handle->dc_duty_pu = 0;
}
/**
* @brief todo
*/
void PROFILER_DCAC_stateMachine(PROFILER_DCAC_Handle handle, MOTOR_Handle motor)
{
PROFILER_DCAC_State_e state = handle->state;
PROFILER_DCAC_State_e newState = state;
switch (state)
{
case PROFILER_DCAC_STATE_Idle:
/* Only called when profiler active */
/* Set motor to required state */
{
/* Open loop angle, using duty reference Ddq_ref_pu */
//motor->flagEnableClosedLoopAngle = false;
motor->pSTC->SpeedControlEnabled = false;
motor->pCurrCtrl->forceZeroPwm = false;
motor->pSPD->OpenLoopAngle = FIXP30(0.0f);
motor->pCurrCtrl->Ddq_ref_pu.D = 0;
motor->pCurrCtrl->Ddq_ref_pu.Q = 0;
motor->pSTC->speedref_source = FOC_SPEED_SOURCE_Default;
motor->pSTC->speed_ref_active_pu = 0;
motor->pSTC->speed_ref_ramped_pu = 0;
motor->pSTC->speed_ref_pu = FIXP30(0.0f);
motor->pSPD->zestControl.enableControlUpdate = false; /* Disable MC_ZEST_Control_Update() */
motor->pSPD->flagHsoAngleEqualsOpenLoopAngle = true; /* theta, cosTh and sinTh of HSO equal to openloopAngle */
ZEST_setInjectMode(motor->pSPD->pZeST, ZEST_INJECTMODE_Auto);
motor->pSPD->flagDisableImpedanceCorrection = true;
IMPEDCORR_setRs(motor->pSPD->pImpedCorr, 0, 20); //set R and L to zero
IMPEDCORR_setLs(motor->pSPD->pImpedCorr, 0, 20);
handle->dc_duty_pu = 0;
handle->ac_duty_pu = 0;
handle->Id_dc_ref_pu = handle->Id_dc_max_pu; //reset initial current setpoint to max.
handle->PowerDC_goal_pu = FIXP30(1.0f/1.5f * handle->PowerDC_goal_W / (handle->fullScaleCurrent_A * handle->fullScaleVoltage_V));
}
newState = PROFILER_DCAC_STATE_RampUp;
break;
case PROFILER_DCAC_STATE_RampUp:
{
Currents_Idq_t Idq = motor->pCurrCtrl->Idq_in_pu;
FIXP_CosSin_t cossin_park;
FIXP30_CosSinPU(motor->pCurrCtrl->angle_park_pu, &cossin_park);
Voltages_Udq_t Udq = MCM_Park_Voltage(motor->pPWM->Uab_in_pu, &cossin_park);
fixp30_t Umag = FIXP_mag(Udq.D, Udq.Q);
fixp30_t Imag = FIXP_mag(Idq.D, Idq.Q);
fixp30_t Pmag = FIXP30_mpy(Umag, Imag);
handle->PowerDC_W = 1.5f * FIXP30_toF(Umag) * handle->fullScaleVoltage_V * FIXP30_toF(Imag) * handle->fullScaleCurrent_A;
if ((Imag > handle->Id_dc_ref_pu) || (Pmag > handle->PowerDC_goal_pu) || (handle->dc_duty_pu == handle->duty_maxgoal_pu))
{
/* Current ramp-up complete. Actual duty in dc_duty_pu, prepare for the next phase */
if (handle->dc_duty_pu == handle->duty_maxgoal_pu) /* motor with high resistance and low current, use filtered values */
{
handle->Id_dc_ref_pu = FIXP_mag(handle->IdqLP.D, handle->IdqLP.Q);
}
else
{
handle->Id_dc_ref_pu = FIXP_mag(Idq.D, Idq.Q); //make positive reference always
}
/* Set timer counter */
handle->counter = handle->measurement_counts;
newState = PROFILER_DCAC_STATE_DC_Measuring;
}
}
break;
case PROFILER_DCAC_STATE_DC_Measuring:
// if measurement time is done, save values and move on
if (handle->counter == 0)
{
/* Calculate resistance value from filtered values */
fixp30_t Umag = FIXP_mag(handle->UdqLP.D, handle->UdqLP.Q);
fixp30_t Imag = FIXP_mag(handle->IdqLP.D, handle->IdqLP.Q);
if (Imag != 0)
{
handle->Rs_dc = (Umag * handle->fullScaleVoltage_V) / (Imag * handle->fullScaleCurrent_A);
}
handle->Umag_pu = Umag;
handle->Imag_pu = Imag;
handle->PowerDC_W = 1.5f * FIXP30_toF(Umag) * handle->fullScaleVoltage_V * FIXP30_toF(Imag) * handle->fullScaleCurrent_A;
/* Start the AC measurement based on DC effective duty (keeping dead-time out of equation) */
float_t dutyDC = 2 * FIXP30_toF(handle->Umag_pu) / FIXP30_toF(motor->pVBus->Udcbus_in_pu);
handle->ac_duty_pu = FIXP30(dutyDC * 0.5f);
handle->counter = handle->measurement_counts;
ZEST_setFreqInjectkHz(motor->pSPD->pZeST, handle->ac_freqkHz_pu); //inject AC frequency
ZEST_setIdInject_pu(motor->pSPD->pZeST, handle->ac_duty_pu); //inject duty as if it was current...
ZEST_setThresholdInjectActiveCurrent_A(motor->pSPD->pZeST, 0.0f); //remove threshold based on maxmotorcurrent
newState = PROFILER_DCAC_STATE_AC_Measuring;
}
break;
case PROFILER_DCAC_STATE_AC_Measuring:
{
if (handle->counter == 0)
{
handle->Rs_inject = ZEST_getR(motor->pSPD->pZeST);
handle->Ls_inject = ZEST_getL(motor->pSPD->pZeST);
fixp20_t Rsdc = FIXP20(handle->Rs_dc);
fixp20_t Rsinject = FIXP20(handle->Rs_inject);
fixp30_t Lsinject = FIXP30(handle->Ls_inject);
/* Check AC and DC resistance to match */
if ((Rsinject < FIXP_mpy(Rsdc, FIXP(0.8f))) || (Rsinject > FIXP_mpy(Rsdc, FIXP(1.4f))))
{
handle->error = PROFILER_DCAC_ERROR_ResistanceAC;
}
/* Check Ls: negative Ls can result at too low injection levels */
if (Lsinject <= FIXP(0.0f))
{
handle->error = PROFILER_DCAC_ERROR_Inductance;
}
if (handle->error != PROFILER_DCAC_ERROR_None)
{
newState = PROFILER_DCAC_STATE_Error;
}
else
{
/* Set correct currentcontroller-parameters */
PIDREGDQX_CURRENT_setKpWiRLmargin_si(&motor->pCurrCtrl->pid_IdIqX_obj, handle->Rs_inject, handle->Ls_inject, 5.0f);
/* Set correct ImpedanceCorrection-parameters */
PROFILER_DCAC_setImpedCorr_RsLs(handle, motor);
ZEST_setIdInject_pu(motor->pSPD->pZeST, FIXP30(0.0f)); //stop injection.
ZEST_setThresholdInjectActiveCurrent_A(motor->pSPD->pZeST, 0.02 * handle->Rs_dc); //set threshold to intended level
if (handle->glue_dcac_fluxestim_on)
{
handle->counter = 20;
newState = PROFILER_DCAC_STATE_DConly;
}
else
{
/* Start the ramp-down */
newState = PROFILER_DCAC_STATE_RampDown;
}
}
}
}
break;
case PROFILER_DCAC_STATE_DConly:
if (handle->counter == 0)
{
newState = PROFILER_DCAC_STATE_Complete;
}
break;
case PROFILER_DCAC_STATE_RampDown:
// Reduce current reference by ramp rate
if (handle->dc_duty_pu == FIXP30(0.0f))
{
newState = PROFILER_DCAC_STATE_Complete;
}
break;
case PROFILER_DCAC_STATE_Complete:
/* No action */
break;
case PROFILER_DCAC_STATE_Error:
/* No action */
break;
}
if (state != newState)
{
handle->state = newState;
}
}
/* Accessors */
/**
* @brief todo
*/
float_t PROFILER_DCAC_getMeasurementTime(PROFILER_DCAC_Handle handle)
{
return handle->measurement_time_sec;
}
/**
* @brief todo
*/
void PROFILER_DCAC_setIdDCMax(PROFILER_DCAC_Handle handle, const float_t id_dc_max)
{
handle->Id_dc_max_pu = FIXP30(id_dc_max / handle->fullScaleCurrent_A);
}
/**
* @brief todo
*/
void PROFILER_DCAC_setImpedCorr_RsLs(PROFILER_DCAC_Handle handle, MOTOR_Handle motor)
{
{
/* write estimated values of R and L to impedance correction */
IMPEDCORR_setRs_si(motor->pSPD->pImpedCorr, handle->Rs_dc);
RSEST_setRsRatedOhm(motor->pSPD->pRsEst, handle->Rs_dc);
IMPEDCORR_setLs_si(motor->pSPD->pImpedCorr, handle->Ls_inject);
}
{
/* Set other inductance variables */
float_t Ls_pu_flt = handle->Ls_inject * handle->voltagefilterpole_rps * handle->fullScaleCurrent_A / handle->fullScaleVoltage_V;
FIXPSCALED_floatToFIXPscaled(Ls_pu_flt, &motor->pFocVars->Ls_Rated_pu_fps);
FIXPSCALED_floatToFIXPscaled(Ls_pu_flt, &motor->pSPD->Ls_Active_pu_fps);
fixp24_t Ls_henry_fixp24 = FIXP24(handle->Ls_inject);
motor->pFocVars->Ls_Rated_H = Ls_henry_fixp24;
motor->pFocVars->Ls_Active_H = Ls_henry_fixp24;
}
}
/**
* @brief todo
*/
void PROFILER_DCAC_setMeasurementTime(PROFILER_DCAC_Handle handle, const float_t time_seconds)
{
handle->measurement_time_sec = time_seconds;
handle->measurement_counts = (uint32_t) (time_seconds * handle->background_rate_hz);
}
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 13,501 | C | 31.613526 | 146 | 0.660766 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/enc_align_ctrl.c | /**
******************************************************************************
* @file enc_align_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Encoder Alignment Control component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup EncAlignCtrl
*/
/* Includes ------------------------------------------------------------------*/
#include "enc_align_ctrl.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup EncAlignCtrl Encoder Alignment Controller
* @brief Encoder Alignment Controller component of the Motor Control SDK
*
* Initial encoder calibration which comprises a rotor alignment in a given position
* necessary to make the information coming from a quadrature encoder absolute.
* @{
*/
/**
* @brief It initializes the handle
* @param pHandle: handler of the current instance of the EncAlignCtrl component.
* @param pSTC: Pointer to Speed and Torque Controller structure used by the EAC.
* @param pVSS: Pointer to Virtual Speed Sensor structure used by the EAC.
* @param pENC: Pointer to ENCoder structure used by the EAC.
*/
__weak void EAC_Init(EncAlign_Handle_t *pHandle, SpeednTorqCtrl_Handle_t *pSTC, VirtualSpeedSensor_Handle_t *pVSS,
ENCODER_Handle_t *pENC)
{
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->pSTC = pSTC;
pHandle->pVSS = pVSS;
pHandle->pENC = pENC;
pHandle->EncAligned = false;
pHandle->EncRestart = false;
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
}
#endif
}
/**
* @brief It starts the encoder alignment procedure.
* It configures the VSS (Virtual Speed Sensor) with the required angle and sets the
* STC (Speed and Torque Controller) to execute the required torque ramp.
* @param pHandle: handler of the current instance of the EncAlignCtrl component.
*/
__weak void EAC_StartAlignment(EncAlign_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
uint32_t wAux;
/* Set pVSS mechanical speed to zero */
VSS_SetMecAcceleration(pHandle->pVSS, 0, 0U);
/* Set pVSS mechanical angle */
VSS_SetMecAngle(pHandle->pVSS, pHandle->hElAngle);
/* Set pSTC in MCM_TORQUE_MODE */
STC_SetControlMode(pHandle->pSTC, MCM_TORQUE_MODE);
/* Set starting torque to Zero */
(void)STC_ExecRamp(pHandle->pSTC, 0, 0U);
/* Execute the torque ramp */
(void)STC_ExecRamp(pHandle->pSTC, pHandle->hFinalTorque, (uint32_t)pHandle->hDurationms);
/* Compute hRemainingTicks, the number of thick of alignment phase */
wAux = ((uint32_t)pHandle->hDurationms) * ((uint32_t)pHandle->hEACFrequencyHz);
wAux /= 1000U;
pHandle->hRemainingTicks = (uint16_t)wAux;
pHandle->hRemainingTicks++;
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
}
#endif
}
/**
* @brief It executes the encoder alignment controller and must be called with a
* frequency equal to the one settled in the parameters
* hEACFrequencyHz. Calling this method the EAC is able to verify
* if the alignment duration has been finished. At the end of alignment
* the encoder is set to the defined mechanical angle.
* Note: STC and VSS are not called by EAC_Exec.
* @param pHandle: handler of the current instance of the EncAlignCtrl component.
* @retval bool It returns true when the programmed alignment has been
* completed.
*/
__weak bool EAC_Exec(EncAlign_Handle_t *pHandle)
{
bool retVal = true;
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
if (NULL == pHandle)
{
retVal = false;
}
else
{
#endif
if (pHandle->hRemainingTicks > 0U)
{
pHandle->hRemainingTicks--;
if (0U == pHandle->hRemainingTicks)
{
/* At the end of Alignment procedure, we set the encoder mechanical angle to the alignement angle */
ENC_SetMecAngle(pHandle->pENC, pHandle->hElAngle / ((int16_t)pHandle->bElToMecRatio));
pHandle->EncAligned = true;
retVal = true;
}
else
{
retVal = false;
}
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
}
#endif
return (retVal);
}
/**
* @brief It returns true if the encoder has been aligned at least
* one time, false if hasn't been never aligned.
* @param pHandle: handler of the current instance of the EncAlignCtrl component.
* @retval bool Encoder Aligned flag
*/
__weak bool EAC_IsAligned(EncAlign_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
return ((NULL == pHandle) ? false : pHandle->EncAligned);
#else
return (pHandle->EncAligned);
#endif
}
/**
* @brief It sets handler ENCrestart variable according to restart parameter
* @param pHandle: handler of the current instance of the EncAlignCtrl component.
* @param restart: Equal to true if a restart is programmed else false.
*/
__weak void EAC_SetRestartState(EncAlign_Handle_t *pHandle, bool restart)
{
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->EncRestart = restart;
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
}
#endif
}
/**
* @brief Returns true if a restart after an encoder alignment has been requested.
* @param pHandle: handler of the current instance of the EncAlignCtrl component.
* @retval bool Encoder Alignment restart order flag
*/
__weak bool EAC_GetRestartState(EncAlign_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_ENC_ALI_CTRL
return ((NULL == pHandle) ? false : pHandle->EncRestart);
#else
return (pHandle->EncRestart);
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 6,473 | C | 28.972222 | 114 | 0.636336 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/r_divider_bus_voltage_sensor.c | /**
******************************************************************************
* @file r_divider_bus_voltage_sensor.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Resistor Divider Bus Voltage Sensor component of the Motor
* Control SDK:
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup RDividerBusVoltageSensor
*/
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
#include "r_divider_bus_voltage_sensor.h"
#include "regular_conversion_manager.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup BusVoltageSensor
* @{
*/
/** @defgroup RDividerBusVoltageSensor Resistor Divider Bus Voltage Sensor
* @brief Resistor Divider Bus Voltage Sensor implementation.
*
* @{
*/
/**
* @brief It initializes bus voltage conversion (ADC, ADC channel, conversion time.
It must be called only after PWM_Init.
* @param pHandle related RDivider_Handle_t
*/
__weak void RVBS_Init(RDivider_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_RDIV_BUS_VLT_SNS
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
/* Check */
RVBS_Clear(pHandle);
#ifdef NULL_PTR_CHECK_RDIV_BUS_VLT_SNS
}
#endif
}
/**
* @brief It clears bus voltage FW variable containing average bus voltage
* value.
* @param pHandle related RDivider_Handle_t
*/
__weak void RVBS_Clear(RDivider_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_RDIV_BUS_VLT_SNS
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
uint16_t aux;
uint16_t index;
aux = (pHandle->OverVoltageThreshold + pHandle->UnderVoltageThreshold) / 2U;
for (index = 0U; index < pHandle->LowPassFilterBW; index++)
{
pHandle->aBuffer[index] = aux;
}
pHandle->_Super.LatestConv = aux;
pHandle->_Super.AvBusVoltage_d = aux;
pHandle->index = 0U;
#ifdef NULL_PTR_CHECK_RDIV_BUS_VLT_SNS
}
#endif
}
/**
* @brief It actually performes the Vbus ADC conversion and updates averaged
* value for all STM32 families except STM32F3 in u16Volt format.
* @param pHandle related RDivider_Handle_t
* @retval uint16_t Fault code error
*/
__weak uint16_t RVBS_CalcAvVbus(RDivider_Handle_t *pHandle, uint16_t rawValue)
{
uint16_t tempValue;
#ifdef NULL_PTR_CHECK_RDIV_BUS_VLT_SNS
if (MC_NULL == pHandle)
{
tempValue = 0U;
}
else
{
#endif
uint32_t wtemp;
uint16_t hAux;
uint8_t i;
hAux = rawValue;
if (0xFFFFU == hAux)
{
/* Nothing to do */
}
else
{
/* Store latest value on buffer */
pHandle->aBuffer[pHandle->index] = hAux;
wtemp = 0u;
for (i = 0U; i < (uint8_t)pHandle->LowPassFilterBW; i++)
{
wtemp += pHandle->aBuffer[i];
}
wtemp /= pHandle->LowPassFilterBW;
/* Averaging done over the buffer stored values */
pHandle->_Super.AvBusVoltage_d = (uint16_t)wtemp;
pHandle->_Super.LatestConv = hAux;
if ((uint16_t)pHandle->index < (pHandle->LowPassFilterBW - 1U))
{
pHandle->index++;
}
else
{
pHandle->index = 0U;
}
}
pHandle->_Super.FaultState = RVBS_CheckFaultState(pHandle);
tempValue = pHandle->_Super.FaultState;
#ifdef NULL_PTR_CHECK_RDIV_BUS_VLT_SNS
}
#endif
return (tempValue);
}
/**
* @brief It returns #MC_OVER_VOLT, #MC_UNDER_VOLT or #MC_NO_ERROR depending on
* bus voltage and protection threshold values
* @param pHandle related RDivider_Handle_t
* @retval uint16_t Fault code error
*/
__weak uint16_t RVBS_CheckFaultState(RDivider_Handle_t *pHandle)
{
uint16_t fault;
#ifdef NULL_PTR_CHECK_RDIV_BUS_VLT_SNS
if (MC_NULL == pHandle)
{
fault = MC_SW_ERROR;
}
else
{
#endif
/* If both thresholds are equal, single threshold feature is used */
if (pHandle->OverVoltageThreshold == pHandle->OverVoltageThresholdLow)
{
if (pHandle->_Super.AvBusVoltage_d > pHandle->OverVoltageThreshold)
{
fault = MC_OVER_VOLT;
}
else if (pHandle->_Super.AvBusVoltage_d < pHandle->UnderVoltageThreshold)
{
fault = MC_UNDER_VOLT;
}
else
{
fault = MC_NO_ERROR;
}
}
else
{
/* If both thresholds are different, hysteresis feature is used (Brake mode) */
if (pHandle->_Super.AvBusVoltage_d < pHandle->UnderVoltageThreshold)
{
fault = MC_UNDER_VOLT;
}
else if ( false == pHandle->OverVoltageHysteresisUpDir )
{
if (pHandle->_Super.AvBusVoltage_d < pHandle->OverVoltageThresholdLow)
{
pHandle->OverVoltageHysteresisUpDir = true;
fault = MC_NO_ERROR;
}
else{
fault = MC_OVER_VOLT;
}
}
else
{
if (pHandle->_Super.AvBusVoltage_d > pHandle->OverVoltageThreshold)
{
pHandle->OverVoltageHysteresisUpDir = false;
fault = MC_OVER_VOLT;
}
else{
fault = MC_NO_ERROR;
}
}
}
#ifdef NULL_PTR_CHECK_RDIV_BUS_VLT_SNS
}
#endif
return (fault);
}
/**
* @}
*/
/**
* @}
*/
/** @} */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,846 | C | 23.464435 | 85 | 0.578857 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/current_ref_ctrl.c | /**
******************************************************************************
* @file current_ref_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the
* six-step current mode current reference PWM generation component of
* the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "current_ref_ctrl.h"
/** @addtogroup MCSDK
* @{
*/
/**
* @defgroup current_ref_ctrl Six-Step, current mode, PWM generation for current reference
*
* @brief PWM generation of the current reference for Six-Step drive with current mode
*
* This implementation exploits a timer to generate a PWM as reference to limit the current
* peak by means an external comparator
*
* @{
*/
/**
* @brief It initializes TIMx
* @param pHandle: handler of instance of the CRM component
* @retval none
*/
__weak void CRM_Init(CurrentRef_Handle_t *pHandle)
{
switch (pHandle->pParams_str->RefTimerChannel)
{
case LL_TIM_CHANNEL_CH1:
{
LL_TIM_OC_SetCompareCH1(pHandle->pParams_str->TIMx, pHandle->StartCntPh);
break;
}
case LL_TIM_CHANNEL_CH2:
{
LL_TIM_OC_SetCompareCH2(pHandle->pParams_str->TIMx, pHandle->StartCntPh);
break;
}
case LL_TIM_CHANNEL_CH3:
{
LL_TIM_OC_SetCompareCH3(pHandle->pParams_str->TIMx, pHandle->StartCntPh);
break;
}
case LL_TIM_CHANNEL_CH4:
{
LL_TIM_OC_SetCompareCH4(pHandle->pParams_str->TIMx, pHandle->StartCntPh);
break;
}
default:
{
LL_TIM_OC_SetCompareCH1(pHandle->pParams_str->TIMx, pHandle->StartCntPh);
break;
}
}
LL_TIM_EnableCounter(pHandle->pParams_str->TIMx);
LL_TIM_CC_EnableChannel(pHandle->pParams_str->TIMx, pHandle->pParams_str->RefTimerChannel);
LL_TIM_EnableAllOutputs(pHandle->pParams_str->TIMx);
}
/**
* @brief It clears TIMx counter and resets start-up duty cycle
* @param pHandle: handler of instance of the CRM component
* @retval none
*/
__weak void CRM_Clear(CurrentRef_Handle_t *pHandle)
{
LL_TIM_SetCounter(pHandle->pParams_str->TIMx, 0u);
pHandle->Cnt = pHandle->StartCntPh;
switch (pHandle->pParams_str->RefTimerChannel)
{
case LL_TIM_CHANNEL_CH1:
{
LL_TIM_OC_SetCompareCH1(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
case LL_TIM_CHANNEL_CH2:
{
LL_TIM_OC_SetCompareCH2(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
case LL_TIM_CHANNEL_CH3:
{
LL_TIM_OC_SetCompareCH3(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
case LL_TIM_CHANNEL_CH4:
{
LL_TIM_OC_SetCompareCH4(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
default:
{
LL_TIM_OC_SetCompareCH1(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
}
}
/**
* @brief It updates current reference value
* @param pHandle: handler of instance of the CRM component
* @param hCnt: new reference value
* @retval none
*/
__weak void CRM_SetReference(CurrentRef_Handle_t *pHandle, uint16_t hCnt)
{
pHandle->Cnt = hCnt;
switch (pHandle->pParams_str->RefTimerChannel)
{
case LL_TIM_CHANNEL_CH1:
{
LL_TIM_OC_SetCompareCH1(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
case LL_TIM_CHANNEL_CH2:
{
LL_TIM_OC_SetCompareCH2(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
case LL_TIM_CHANNEL_CH3:
{
LL_TIM_OC_SetCompareCH3(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
case LL_TIM_CHANNEL_CH4:
{
LL_TIM_OC_SetCompareCH4(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
default:
{
LL_TIM_OC_SetCompareCH1(pHandle->pParams_str->TIMx, pHandle->Cnt);
break;
}
}
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 4,564 | C | 24.361111 | 93 | 0.588738 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/bus_voltage_sensor.c | /**
******************************************************************************
* @file bus_voltage_sensor.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the BusVoltageSensor component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup BusVoltageSensor
*/
/* Includes ------------------------------------------------------------------*/
#include "bus_voltage_sensor.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup BusVoltageSensor Bus Voltage Sensing
* @brief Bus Voltage Sensor components of the Motor Control SDK
*
* Two Bus Voltage Sensor implementations are provided (selection done according to BUS_VOLTAGE_READING definition):
*
* - The @ref RDividerBusVoltageSensor "Resistor Divider Bus Voltage Sensor" operates as the name suggests
* - The @ref VirtualBusVoltageSensor "Virtual Bus Voltage Sensor" does not make measurement but rather
* returns an application fixed defined value (expected VBus value).
*
* Two formats are used to return VBus measurement:
* - Volt
* - u16Volt that represents the ADC converted signal measuring the voltage at sensing network attenuation output
* @f[
* u16Volt = (ADC\_REFERENCE\_VOLTAGE / VBUS\_PARTITIONING\_FACTOR) / 65536
* @f]
*
* @{
*/
/**
* @brief It return latest Vbus conversion result expressed in u16Volt format
* @param pHandle related Handle of BusVoltageSensor_Handle_t
* @retval uint16_t Latest Vbus conversion result in u16Volt format
*/
__weak uint16_t VBS_GetBusVoltage_d(const BusVoltageSensor_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_BUS_VOLT
uint16_t temp_latestConv;
if (MC_NULL == pHandle)
{
temp_latestConv = 0;
}
else
{
temp_latestConv = pHandle->LatestConv;
}
return (temp_latestConv);
#else
return (pHandle->LatestConv);
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief It return latest averaged Vbus measurement expressed in u16Volt format
* @param pHandle related Handle of BusVoltageSensor_Handle_t
* @retval uint16_t Latest averaged Vbus measurement in u16Volt format
*/
__weak uint16_t VBS_GetAvBusVoltage_d(const BusVoltageSensor_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_BUS_VOLT
uint16_t temp_avBusVoltage_d;
if (MC_NULL == pHandle)
{
temp_avBusVoltage_d = 0U;
}
else
{
temp_avBusVoltage_d = pHandle->AvBusVoltage_d;
}
return (temp_avBusVoltage_d);
#else
return (pHandle->AvBusVoltage_d);
#endif
}
/**
* @brief It return latest averaged Vbus measurement expressed in Volt format
* @param pHandle related Handle of BusVoltageSensor_Handle_t
* @retval uint16_t Latest averaged Vbus measurement in Volt format
*/
__weak uint16_t VBS_GetAvBusVoltage_V(const BusVoltageSensor_Handle_t *pHandle)
{
uint32_t temp;
#ifdef NULL_PTR_CHECK_BUS_VOLT
if (MC_NULL == pHandle)
{
temp = 0U;
}
else
{
#endif
temp = (uint32_t)(pHandle->AvBusVoltage_d);
temp *= pHandle->ConversionFactor;
temp /= 65536U;
#ifdef NULL_PTR_CHECK_BUS_VOLT
}
#endif
return ((uint16_t)temp);
}
/**
* @brief It returns #MC_OVER_VOLT, #MC_UNDER_VOLT or #MC_NO_ERROR depending on
* bus voltage and protection threshold values
* @param pHandle related Handle of BusVoltageSensor_Handle_t
* @retval uint16_t Fault code error
*/
__weak uint16_t VBS_CheckVbus(const BusVoltageSensor_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_BUS_VOLT
uint16_t temp_faultState;
if (MC_NULL == pHandle)
{
temp_faultState = 0U;
}
else
{
temp_faultState = pHandle->FaultState;
}
return (temp_faultState);
#else
return (pHandle->FaultState);
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 4,512 | C | 26.351515 | 117 | 0.636082 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/pwm_curr_fdbk_ovm.c | /**
******************************************************************************
* @file pwm_curr_fdbk_ovm.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the following features
* of the PWM & Current Feedback component of the Motor Control SDK:
*
* * current sensing
* * regular ADC conversion execution
* * space vector modulation
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pwm_curr_fdbk
*/
/* Includes ------------------------------------------------------------------*/
#include "pwm_curr_fdbk.h"
#include "mc_math.h"
#include "mc_type.h"
/* Private defines ------------------------------------------------------------*/
/* @brief The float number 1.0 equal to 32768 ; represents the vector from center to an angle of the hexagon. */
#define OVM_ONE_POINT_ZERO ((int32_t)32768)
#define OVM_GAIN_ARRAY_SIZE ((int32_t)192)
#define OVM_GAMMA_ARRAY_SIZE ((int32_t)100)
#define OVM_GAMMA_ARRAY_OFFSET ((int32_t)92)
#define OVM_VREF_MODE1_START ((int32_t)29717)
#define OVM_VREF_MODE2_START ((int32_t)31186)
#define OVM_VREF_MODE2_END ((int32_t)32768)
#define OVM_VREF_INDEX_STEP ((int32_t)16)
#define OVM_1_DIV_SQRT3 ((int32_t)18919)
#define OVM_1_DIV_PI ((int32_t)10430)
#define OVM_PI_DIV_6 ((int32_t)17157)
#define OVM_3_DIV_PI ((int32_t)31291)
#define OVM_SQRT3 ((int32_t)56754)
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk
*
* @{
*/
/* Private variables ----------------------------------------------------------*/
/**
* @brief Vector modules T1 and T2. Specified in @ref overmodulation.md
*/
typedef struct
{
int32_t T1;
int32_t T2;
} Vector_Time_t;
/**
* @brief Overmodulation modes. Specified in @ref overmodulation.md
*/
typedef enum
{
OVM_LINEAR = 0, /**< Linear mode. */
OVM_1 = 1, /**< Overmodulation mode 1. */
OVM_2 = 2, /**< Overmodulation mode 2. */
OVM_ERROR = 3 /**< Error output. */
} OVM_Mode_t;
/**
* @}
*/
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
static Vector_Time_t PWMC_RecalcT1T2_OVM(Vector_Time_t time, OVM_Mode_t mode, int16_t gamma);
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/*
* @brief Recalculates vectors T1 and T2 stored in @p time structure,
* depending on the overmodulation @p mode and @p gamma gain.
*
* @retval New values of T1 & T2.
*/
static Vector_Time_t PWMC_RecalcT1T2_OVM(Vector_Time_t time, OVM_Mode_t mode, int16_t gamma)
{
int32_t sum_t1_t2;
int32_t offset;
int32_t gain;
int32_t t1_temp;
Vector_Time_t time_prime;
time_prime.T1 = 0;
time_prime.T2 = 0;
if ((OVM_LINEAR == mode) || (OVM_1 == mode))
{
sum_t1_t2 = time.T1 + time.T2;
if (sum_t1_t2 > OVM_ONE_POINT_ZERO)
{
time_prime.T1 = ((time.T1 * OVM_ONE_POINT_ZERO) / sum_t1_t2);
time_prime.T2 = OVM_ONE_POINT_ZERO - time_prime.T1;
}
else
{
time_prime.T1 = time.T1;
time_prime.T2 = time.T2;
}
}
else if (OVM_2 == mode)
{
if (time.T1 > OVM_ONE_POINT_ZERO)
{
time_prime.T1 = OVM_ONE_POINT_ZERO;
time_prime.T2 = 0;
}
else if (time.T2 > OVM_ONE_POINT_ZERO)
{
time_prime.T1 = 0;
time_prime.T2 = OVM_ONE_POINT_ZERO;
}
else
{
offset = (OVM_3_DIV_PI * gamma) / OVM_ONE_POINT_ZERO;
gain = (OVM_PI_DIV_6 * OVM_ONE_POINT_ZERO) / (OVM_PI_DIV_6 - gamma);
sum_t1_t2 = time.T1 + time.T2;
sum_t1_t2 = ((0 == sum_t1_t2) ? 1 : sum_t1_t2);
t1_temp = (time.T1 * OVM_ONE_POINT_ZERO) / sum_t1_t2;
t1_temp = t1_temp - offset;
if (t1_temp < 0)
{
t1_temp = 0;
}
else
{
/* Nothing to do */
}
if (gain > OVM_ONE_POINT_ZERO)
{
gain = gain / OVM_ONE_POINT_ZERO;
time_prime.T1 = t1_temp * gain;
}
else
{
time_prime.T1 = (t1_temp * gain) / OVM_ONE_POINT_ZERO;
}
if (time_prime.T1 > OVM_ONE_POINT_ZERO)
{
time_prime.T1 = OVM_ONE_POINT_ZERO;
}
else
{
/* Nothing to do */
}
time_prime.T2 = OVM_ONE_POINT_ZERO - time_prime.T1;
}
}
else /* Error mode output 0 to protect */
{
time_prime.T1 = 0;
time_prime.T2 = 0;
}
return (time_prime);
}
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk
*
* @{
*/
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Converts input voltage components @f$ V_{\alpha} @f$ and @f$ V_{\beta} @f$ into duty cycles
* and feeds them to the inverter with overmodulation function.
*
* @param pHandle: Handler of the current instance of the PWM component.
* @param Valfa_beta: Voltage Components expressed in the @f$(\alpha, \beta)@f$ reference frame.
* @retval #MC_NO_ERROR if no error occurred or #MC_DURATION if the duty cycles were
* set too late for being taken into account in the next PWM cycle.
*/
uint16_t PWMC_SetPhaseVoltage_OVM(PWMC_Handle_t *pHandle, alphabeta_t Valfa_beta)
{
/* Private variables ----------------------------------------------------------*/
/* Overmodulation gain array */
static const uint16_t aOVMGain[OVM_GAIN_ARRAY_SIZE]={\
31291,31291,31293,31295,31298,31300,31302,31306,31309,31314,\
31319,31322,31328,31334,31338,31344,31350,31357,31364,31371,\
31379,31386,31394,31402,31410,31419,31427,31439,31448,31457,\
31470,31479,31492,31502,31515,31526,31539,31554,31568,31579,\
31594,31609,31624,31639,31655,31675,31691,31707,31728,31745,\
31766,31783,31805,31827,31845,31868,31891,31914,31942,31966,\
31990,32019,32044,32074,32104,32134,32165,32202,32233,32271,\
32303,32341,32386,32425,32470,32516,32562,32609,32662,32716,\
32777,32838,32907,32982,33059,33144,33236,33343,33466,33612,\
33797,34106,34463,34507,34551,34596,34640,34684,34729,34779,\
34824,34869,34920,34971,35017,35068,35120,35178,35230,35282,\
35340,35392,35451,35509,35568,35627,35686,35752,35811,35877,\
35943,36009,36075,36148,36214,36287,36360,36434,36507,36581,\
36661,36742,36822,36903,36990,37078,37159,37253,37342,37436,\
37531,37627,37729,37831,37933,38042,38152,38261,38378,38495,\
38612,38736,38860,38991,39122,39261,39399,39545,39691,39844,\
40004,40165,40332,40507,40682,40871,41061,41264,41469,41680,\
41906,42139,42387,42649,42911,43188,43488,43801,44137,44487,\
44866,45275,45713,46195,46715,47300,47958,48720,49629,50759,\
52346,56660,\
};
/* Overmodulation gamma array */
static const int16_t aOVMGamma[OVM_GAMMA_ARRAY_SIZE]={\
52,154,255,354,453,551,648,757,852,947,\
1052,1157,1249,1352,1454,1566,1666,1765,1875,1972,\
2079,2186,2291,2395,2499,2612,2713,2824,2934,3042,\
3150,3266,3372,3486,3599,3711,3821,3931,4049,4166,\
4281,4395,4517,4637,4748,4875,4992,5115,5238,5359,\
5487,5614,5739,5870,6000,6129,6263,6396,6528,6665,\
6800,6941,7080,7224,7367,7514,7659,7809,7963,8115,\
8272,8432,8590,8757,8922,9096,9268,9442,9624,9809,\
10001,10200,10395,10597,10810,11028,11255,11487,11731,11987,\
12254,12539,12835,13158,13507,13895,14335,14853,15530,17125,\
};
uint16_t retvalue;
#ifdef NULL_PTR_CHECK_PWM_CUR_FDB_OVM
if (NULL == pHandle)
{
retvalue = 0U;
}
else
{
#endif
int32_t wX;
int32_t wY;
int32_t wZ;
int32_t wUAlpha;
int32_t wUBeta;
int32_t vref;
int32_t gain;
int32_t neg_beta_cmd_div_sqrt3;
int32_t duty_a;
int32_t duty_b;
int32_t duty_c;
int32_t gama = 0;
int16_t index;
OVM_Mode_t ovm_mode_flag;
Vector_Time_t vector_time;
/* Transfer vref to vcmd */
vref = (int32_t)MCM_Modulus( Valfa_beta.alpha, Valfa_beta.beta );
if (vref < OVM_VREF_MODE1_START) /* Linear range */
{
wUAlpha = Valfa_beta.alpha;
wUBeta = Valfa_beta.beta;
ovm_mode_flag = OVM_LINEAR;
}
else if (vref < OVM_VREF_MODE2_START) /* OVM mode 1 range */
{
index = (int16_t)((vref - OVM_VREF_MODE1_START) / OVM_VREF_INDEX_STEP);
gain = (int32_t)aOVMGain[index];
wUAlpha = (Valfa_beta.alpha * gain) / OVM_ONE_POINT_ZERO;
wUBeta = (Valfa_beta.beta * gain) / OVM_ONE_POINT_ZERO;
ovm_mode_flag = OVM_1;
}
else if (vref < OVM_VREF_MODE2_END) /* OVM mode 2 range */
{
index = (int16_t)((vref - OVM_VREF_MODE1_START) / OVM_VREF_INDEX_STEP);
gain = (int32_t)aOVMGain[index];
wUAlpha = (Valfa_beta.alpha * gain) / OVM_ONE_POINT_ZERO;
wUBeta = (Valfa_beta.beta * gain) / OVM_ONE_POINT_ZERO;
if (index > OVM_GAMMA_ARRAY_OFFSET)
{
gama = aOVMGamma[index - OVM_GAMMA_ARRAY_OFFSET];
}
else
{
gama = aOVMGamma[0];
}
ovm_mode_flag = OVM_2;
}
else /* Out of OVM mode 2 range only a protection to prevent the code to a undefined branch */
{
wUAlpha = 0;
wUBeta = 0;
ovm_mode_flag = OVM_ERROR;
}
/* Vcmd to X, Y, Z */
neg_beta_cmd_div_sqrt3 = ((-wUBeta) * OVM_1_DIV_SQRT3) / OVM_ONE_POINT_ZERO;
wX = neg_beta_cmd_div_sqrt3 * 2; /* x=-(2/sqrt(3))*beta */
wY = wUAlpha + neg_beta_cmd_div_sqrt3; /* x=alpha-(1/sqrt(3))*beta */
wZ = -wUAlpha + neg_beta_cmd_div_sqrt3;; /* x=-alpha-(1/sqrt(3))*beta */
/* Sector calculation from wX, wY, wZ */
if (wY < 0)
{
if (wZ < 0)
{
pHandle->Sector = SECTOR_5;
vector_time.T1 = -wY;
vector_time.T2 = -wZ;
vector_time = PWMC_RecalcT1T2_OVM( vector_time, ovm_mode_flag, (int16_t)gama );
duty_a = 16384 + ((-vector_time.T1 + vector_time.T2) / 2);
#ifndef FULL_MISRA_C_COMPLIANCY_PW_CURR_FDB_OVM
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) >> 16;
duty_b = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) >> 16;
duty_c = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) >> 16;
#else
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) / 65536;
duty_b = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) / 65536;
duty_c = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) / 65536;
#endif
pHandle->lowDuty = (uint16_t)duty_c;
pHandle->midDuty = (uint16_t)duty_a;
pHandle->highDuty = (uint16_t)duty_b;
}
else /* wZ >= 0 */
if (wX <= 0)
{
pHandle->Sector = SECTOR_4;
vector_time.T1 = wZ;
vector_time.T2 = -wX;
vector_time = PWMC_RecalcT1T2_OVM( vector_time, ovm_mode_flag, (int16_t)gama );
duty_a = 16384 + ((- vector_time.T1 - vector_time.T2) / 2);
#ifndef FULL_MISRA_C_COMPLIANCY_PW_CURR_FDB_OVM
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) >> 16;
duty_b = 16384 + ((vector_time.T1 - vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) >> 16;
duty_c = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) >> 16;
#else
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) / 65536;
duty_b = 16384 + ((vector_time.T1 - vector_time.T2) / 2);
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) / 65536;
duty_c = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) / 65536;
#endif
pHandle->lowDuty = (uint16_t)duty_c;
pHandle->midDuty = (uint16_t)duty_b;
pHandle->highDuty = (uint16_t)duty_a;
}
else /* wX > 0 */
{
pHandle->Sector = SECTOR_3;
vector_time.T1 = wX;
vector_time.T2 = -wY;
vector_time = PWMC_RecalcT1T2_OVM( vector_time, ovm_mode_flag, (int16_t)gama );
duty_a = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
#ifndef FULL_MISRA_C_COMPLIANCY_PW_CURR_FDB_OVM
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) >> 16;
duty_b = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) >> 16;
duty_c = 16384 + ((- vector_time.T1 + vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) >> 16;
#else
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) / 65536;
duty_b = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) / 65536;
duty_c = 16384 + ((- vector_time.T1 + vector_time.T2) / 2);
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) / 65536;
#endif
pHandle->lowDuty = (uint16_t)duty_b;
pHandle->midDuty = (uint16_t)duty_c;
pHandle->highDuty = (uint16_t)duty_a;
}
}
else /* wY > 0 */
{
if (wZ >= 0)
{
pHandle->Sector = SECTOR_2;
vector_time.T1 = wY;
vector_time.T2 = wZ;
vector_time = PWMC_RecalcT1T2_OVM( vector_time, ovm_mode_flag, (int16_t)gama);
duty_a = 16384 + ((vector_time.T1 - vector_time.T2) / 2);
#ifndef FULL_MISRA_C_COMPLIANCY_PW_CURR_FDB_OVM
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) >> 16;
duty_b = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) >> 16;
duty_c = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) >> 16;
#else
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) / 65536;
duty_b = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) / 65536;
duty_c = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) / 65536;
#endif
pHandle->lowDuty = (uint16_t)duty_b;
pHandle->midDuty = (uint16_t)duty_a;
pHandle->highDuty = (uint16_t)duty_c;
}
else /* wZ < 0 */
if (wX <= 0)
{
pHandle->Sector = SECTOR_6;
vector_time.T1 = -wX;
vector_time.T2 = wY;
vector_time = PWMC_RecalcT1T2_OVM( vector_time, ovm_mode_flag, (int16_t)gama);
duty_a = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
#ifndef FULL_MISRA_C_COMPLIANCY_PW_CURR_FDB_OVM
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) >> 16;
duty_b = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) >> 16;
duty_c = 16384 + ((vector_time.T1 - vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) >> 16;
#else
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) / 65536;
duty_b = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) / 65536;
duty_c = 16384 + ((vector_time.T1 - vector_time.T2) / 2);
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) / 65536;
#endif
pHandle->lowDuty = (uint16_t)duty_a;
pHandle->midDuty = (uint16_t)duty_c;
pHandle->highDuty = (uint16_t)duty_b;
}
else /* wX > 0 */
{
pHandle->Sector = SECTOR_1;
vector_time.T1 = -wZ;
vector_time.T2 = wX;
vector_time = PWMC_RecalcT1T2_OVM( vector_time, ovm_mode_flag, (int16_t)gama);
duty_a = 16384 + ((vector_time.T1 + vector_time.T2) / 2);
#ifndef FULL_MISRA_C_COMPLIANCY_PW_CURR_FDB_OVM
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) >> 16;
duty_b = 16384 + ((-vector_time.T1 + vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) >> 16;
duty_c = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) >> 16;
#else
duty_a = (((int32_t)pHandle->PWMperiod) * duty_a) / 65536;
duty_b = 16384 + ((-vector_time.T1 + vector_time.T2) / 2);
duty_b = (((int32_t)pHandle->PWMperiod) * duty_b) / 65536;
duty_c = 16384 + ((-vector_time.T1 - vector_time.T2) / 2);
duty_c = (((int32_t)pHandle->PWMperiod) * duty_c) / 65536;
#endif
pHandle->lowDuty = (uint16_t)duty_a;
pHandle->midDuty = (uint16_t)duty_b;
pHandle->highDuty = (uint16_t)duty_c;
}
}
pHandle->CntPhA = (uint16_t)duty_a ;
pHandle->CntPhB = (uint16_t)duty_b ;
pHandle->CntPhC = (uint16_t)duty_c;
retvalue = pHandle->pFctSetADCSampPointSectX(pHandle);
#ifdef NULL_PTR_CHECK_PWM_CUR_FDB_OVM
}
#endif
return (retvalue);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 19,199 | C | 35.852207 | 112 | 0.567634 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/speed_regulator_potentiometer.c | /**
******************************************************************************
* @file speed_regulator_potentiometer.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Speed Regulator Potentiometer component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*
* @ingroup SpeedRegulatorPotentiometer
*/
/* Includes ------------------------------------------------------------------*/
#include "speed_regulator_potentiometer.h"
/** @addtogroup MCSDK
* @{
*/
/**
* @defgroup SpeedRegulatorPotentiometer Speed Potentiometer
* @brief Potentiometer for motor speed reference setting compotent of the Motor Control SDK.
*
* Reads a potentiometer and sets the mechanical speed reference of the rotor accordingly.
*
* The Speed Regulator Potentiometer component reads a potentiometer thro.
*
* @todo Complete the documentation of the Speed Regulator Potentiometer component.
*
* @{
*/
/* Functions ---------------------------------------------------- */
/**
* @brief Initializes a Speed Regulator Potentiometer component.
*
* @param pHandle The Speed Regulator Potentiometer component to initialize.
*
*/
__weak void SRP_Init(SRP_Handle_t *pHandle, SpeednTorqCtrl_Handle_t *pSTC)
{
#ifdef NULL_PTR_CHECK_SPD_REG_POT
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
/* Need to be register with RegularConvManager */
pHandle->convHandle = RCM_RegisterRegConv(&pHandle->SpeedRegConv);
pHandle->pSTC = pSTC;
SRP_Clear(pHandle);
#ifdef NULL_PTR_CHECK_SPD_REG_POT
}
#endif
}
/**
* @brief Resets the internal state of a Speed Regulator Potentiometer component.
*
* @param pHandle Handle of the Speed Regulator Potentiometer component.
*/
__weak void SRP_Clear(SRP_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_SPD_REG_POT
if (MC_NULL == pHandle)
{
/* nothing to do */
}
else
{
#endif
uint16_t aux;
uint16_t index;
aux = (pHandle->MaximumSpeedRange + pHandle->MinimumSpeedRange) / 2u;
for (index = 0u; index < pHandle->LowPassFilterBW; index++)
{
pHandle->aBuffer[index] = aux;
}
pHandle->LatestConv = aux;
pHandle->AvSpeedReg_d = aux;
pHandle->index = 0;
#ifdef NULL_PTR_CHECK_SPD_REG_POT
}
#endif
}
/**
* @brief
*
* @param pHandle
* @return uint16_t
*/
static uint16_t SRP_ConvertSpeedRegFiltered(SRP_Handle_t *pHandle, uint16_t rawValue)
{
uint16_t hAux;
uint8_t vindex;
uint16_t max = 0, min = 0;
uint32_t tot = 0u;
for (vindex = 0; vindex < pHandle->LowPassFilterBW;)
{
hAux = rawValue;
if (hAux != 0xFFFFu)
{
if (vindex == 0)
{
min = hAux;
max = hAux;
}
else
{
if (hAux < min)
{
min = hAux;
}
if (hAux > max)
{
max = hAux;
}
}
vindex++;
tot += hAux;
}
}
tot -= max;
tot -= min;
return ((uint16_t)(tot / (pHandle->LowPassFilterBW - 2u)));
}
/**
* @brief
*
* @param pHandle
* @param DigitValue
* @return uint16_t
*/
static inlineuint16_t SRP_SpeedDigitToSpeedUnit(SRP_Handle_t *pHandle, uint16_t DigitValue)
{
uint16_t hAux;
hAux = (DigitValue / pHandle->ConversionFactor) + pHandle->MinimumSpeedRange;
return (hAux);
}
/**
* @brief
*
* @param pHandle
* @param SpeedUnitValue
* @return uint16_t
*/
static uint16_t SRP_SpeedUnitToSpeedDigit(SRP_Handle_t *pHandle, int16_t SpeedUnitValue)
{
uint16_t hAux = 0;
if (SpeedUnitValue < 0)
{
SpeedUnitValue = -SpeedUnitValue;
}
else
{
/* Nothing to do */
}
if (SpeedUnitValue > pHandle->MinimumSpeedRange)
{
hAux = (SpeedUnitValue - pHandle->MinimumSpeedRange) * pHandle->ConversionFactor;
}
else
{
/* Nothing to do */
}
return (hAux);
}
/**
* @brief Reads the potentiometer of an SRP component and filters it to compute an average speed reference.
*
* It actually performes the Speed regulator ADC conversion and updates average value.
* @param pHandle related SRP_Handle_t.
* @retval bool OutOfSynch signal.
*/
__weak bool SRP_CalcAvSpeedRegFilt(SRP_Handle_t *pHandle, uint16_t rawValue)
{
uint32_t wtemp;
uint16_t hAux;
uint8_t i;
hAux = SRP_ConvertSpeedRegFiltered(pHandle, rawValue);
if (hAux != 0xFFFF)
{
pHandle->aBuffer[pHandle->index] = hAux;
wtemp = 0;
for (i = 0; i < pHandle->LowPassFilterBW; i++)
{
wtemp += pHandle->aBuffer[i];
}
wtemp /= pHandle->LowPassFilterBW;
pHandle->AvSpeedReg_d = (uint16_t)wtemp;
pHandle->LatestConv = hAux;
if (pHandle->index < (pHandle->LowPassFilterBW - 1))
{
pHandle->index++;
}
else
{
pHandle->index = 0;
}
}
else
{
/* Nothing to do */
}
pHandle->OutOfSynchro = SRP_CheckSpeedRegSync(pHandle);
return (pHandle->OutOfSynchro);
}
#ifdef NOT_IMPLEMENTED
/**
* @brief It actually performes the speed regulator ADC conversion and updates average value.
* @param pHandle related SRP_Handle_t.
* @retval bool OutOfSynch signal.
*/
__weak bool SRP_CalcAvSpeedReg(SRP_Handle_t * pHandle)
{
uint32_t wtemp;
uint16_t hAux;
uint8_t i;
hAux = RCM_ExecRegularConv(pHandle->convHandle);
if (hAux != 0xFFFF)
{
pHandle->aBuffer[pHandle->index] = hAux;
wtemp = 0;
for (i = 0; i < pHandle->LowPassFilterBW; i++)
{
wtemp += pHandle->aBuffer[i];
}
wtemp /= pHandle->LowPassFilterBW;
pHandle->AvSpeedReg_d = (uint16_t)wtemp;
pHandle->LatestConv = hAux;
if (pHandle->index < pHandle->LowPassFilterBW - 1)
{
pHandle->index++;
}
else
{
pHandle->index = 0;
}
}
pHandle->OutOfSynchro = SRP_CheckSpeedRegSync(pHandle);
return (pHandle->OutOfSynchro);
}
#endif
__weak bool SRP_CalcAvgSpeedReg(void)
{
uint32_t wtemp;
uint16_t hAux;
uint8_t i;
/* Check regular conversion state */
if (RCM_GetUserConvState() == RCM_USERCONV_IDLE)
{
/* If Idle, then program a new conversion request */
RCM_RequestUserConv(handle);
}
else if (RCM_GetUserConvState() == RCM_USERCONV_EOC)
{
/* If completed, then read the captured value */
hAux = RCM_GetUserConv();
if (hAux != 0xFFFF)
{
pHandle->aBuffer[pHandle->index] = hAux;
wtemp = 0;
for (i = 0; i < pHandle->LowPassFilterBW; i++)
{
wtemp += pHandle->aBuffer[i];
}
wtemp /= pHandle->LowPassFilterBW;
pHandle->AvSpeedReg_d = (uint16_t)wtemp;
pHandle->LatestConv = hAux;
if (pHandle->index < pHandle->LowPassFilterBW - 1)
{
pHandle->index++;
}
else
{
pHandle->index = 0;
}
}
else
{
/* Nothing to do */
}
}
pHandle->OutOfSynchro = SRP_CheckSpeedRegSync(pHandle);
return (pHandle->OutOfSynchro);
}
/**
* @brief It returns OutOfSync check between current potentiometer setting and measured speed.
* @param pHandle related SRP_Handle_t.
* @retval bool OutOfSynch signal.
*/
__weak bool SRP_CheckSpeedRegSync(SRP_Handle_t *pHandle)
{
uint16_t speedRegValue = SRP_SpeedDigitToSpeedUnit(pHandle, pHandle->AvSpeedReg_d);
uint16_t speedRegTol = SRP_SpeedDigitToSpeedUnit(pHandle, pHandle->SpeedAdjustmentRange);
SpeednPosFdbk_Handle_t *speedHandle;
bool hAux = false;
speedHandle = STC_GetSpeedSensor(pHandle->pSTC);
if ((speedHandle->hAvrMecSpeedUnit > (speedRegValue + speedRegTol)) ||
(speedHandle->hAvrMecSpeedUnit < (speedRegValue - speedRegTol)))
{
hAux = true;
}
else
{
/* Nothing to do */
}
return (hAux);
}
/**
* @brief Executes speed ramp and applies external speed regulator new setpoint if ajustment range is violated
* @param pHandle related SRP_Handle_t
* @retval bool final speed is equal to measured speed
*/
__weak bool SRP_ExecPotRamp(SRP_Handle_t *pHandle)
{
bool hAux = SRP_CheckSpeedRegSync(pHandle);
uint16_t PotentiometerReqSpeed = pHandle->LatestConv;
uint16_t PotentiometerCurrentSpeed = pHandle->AvSpeedReg_d;
SpeednPosFdbk_Handle_t *speedHandle;
speedHandle = STC_GetSpeedSensor(pHandle->pSTC);
int16_t CurrentSpeed = speedHandle->hAvrMecSpeedUnit;
/* Requested speed must be different from previous one */
if ((PotentiometerReqSpeed <= PotentiometerCurrentSpeed - pHandle->SpeedAdjustmentRange) |
(PotentiometerReqSpeed >= PotentiometerCurrentSpeed + pHandle->SpeedAdjustmentRange))
{
uint32_t hDuration;
int16_t deltaSpeed;
uint16_t RequestedSpeed = SRP_SpeedDigitToSpeedUnit(pHandle, PotentiometerReqSpeed);
deltaSpeed = (int16_t) RequestedSpeed - CurrentSpeed;
if (deltaSpeed > 0)
{
hDuration = (((uint32_t)deltaSpeed) * 1000) / pHandle->RampSlope;
}
else
{
hDuration = (((uint32_t)(- deltaSpeed)) * 1000) / pHandle->RampSlope;
}
if (CurrentSpeed < 0)
{
STC_ExecRamp(pHandle->pSTC, (int16_t)(- RequestedSpeed), hDuration);
}
else
{
STC_ExecRamp(pHandle->pSTC, (int16_t)RequestedSpeed, hDuration);
}
}
return (hAux);
}
/**
* @brief Returns the latest value read from the potentiometer of a Speed Regulator Potentiometer component
*
* @param pHandle Handle of the Speed Regulator Potentiometer component
*/
__weak uint16_t SRP_GetSpeedReg_d(SRP_Handle_t *pHandle)
{
return (pHandle->LatestConv);
}
/**
* @brief Returns the speed reference computed by a Speed Regulator Potentiometer
* component expressed in u16digits.
*
* This speed reference is an average computed over the last values read from the potentiometer.
*
* The number of values on which the average is computed is given by SRP_Handle_t::LowPassFilterBW.
*
* @param pHandle Handle of the Speed Regulator Potentiometer component
*/
__weak uint16_t SRP_GetAvSpeedReg_d(SRP_Handle_t *pHandle)
{
return (pHandle->AvSpeedReg_d);
}
/**
* @brief Returns the speed reference computed by a Speed Regulator Potentiometer component
* expressed in #SPEED_UNIT
*
* @param pHandle Handle of the Speed Regulator Potentiometer component
*/
__weak uint16_t SRP_GetAvSpeedReg_SU(SRP_Handle_t *pHandle)
{
uint16_t temp = SRP_SpeedDigitToSpeedUnit(pHandle, pHandle->AvSpeedReg_d);
return (temp);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 10,976 | C | 23.722973 | 112 | 0.630102 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/datalog.c | /**
******************************************************************************
* @file datalog.c
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* datalog.c */
#include "datalog.h"
#include <string.h> // memset
bool DATALOG_checkTrigger(DATALOG_Handle handle);
void DATALOG_clearChannelData(DATALOG_Handle handle, int channel);
void DATALOG_setSampleWindow(DATALOG_Handle handle);
DATALOG_Handle DATALOG_init(void* pMemory, const size_t numBytes)
{
DATALOG_Handle handle = (DATALOG_Handle) NULL;
if (numBytes >= sizeof(DATALOG_Obj)) /* Size was mismatched once - Are dependancies to .h files being checked correctly? */
{
handle = (DATALOG_Handle) pMemory;
memset(pMemory, 0, numBytes);
}
return (handle);
} /* end of DATALOG_init() function */
void DATALOG_setup(DATALOG_Handle handle)
{
DATALOG_Obj* obj = handle;
int channel;
for (channel = 0; channel < DATALOG_NUM_CHANNELS; channel++)
{
DATALOG_CHANNEL_s* pChannel = &handle->channel[channel];
pChannel->bEnabled = false;
pChannel->pSource = (void*) NULL;
DATALOG_clearChannelData(handle, channel);
}
obj->nextSampleIdx = 0;
obj->endSampleIdx = 0;
obj->dataStartIdx = 0;
obj->triggerIdx = 0;
obj->bClear = false;
obj->bArmTrigger = false;
obj->bClearHold = false;
obj->trigger.channel = 0;
obj->trigger.level = 16384;
obj->trigger.mode = DATALOG_TRIGGER_MODE_Normal;
obj->trigger.state = DATALOG_TRIGGER_STATE_Idle;
obj->trigger.edge = DATALOG_TRIGGER_EDGE_DIRECTION_Rising;
obj->trigger.preTrigger = 1;
obj->state = DATALOG_STATE_Idle;
obj->command = DATALOG_COMMAND_None;
obj->downsample = 3;
obj->downsamplecounter = 0;
} /* end of DATALOG_setup() function */
void DATALOG_run(DATALOG_Handle handle)
{
DATALOG_Obj* obj = handle;
/* Debug control of scope */
if (obj->bClearHold)
{
if (obj->trigger.state == DATALOG_TRIGGER_STATE_Holding)
{
obj->trigger.state = DATALOG_TRIGGER_STATE_Idle;
}
obj->bClearHold = false;
}
if (obj->bArmTrigger)
{
obj->trigger.state = DATALOG_TRIGGER_STATE_Armed;
obj->channel[obj->trigger.channel].lastSample = 0;
obj->channel[obj->trigger.channel].currentSample = 0;
obj->bArmTrigger = false;
obj->trigger.justArmed = true;
}
if (obj->bClear)
{
int channel;
for (channel = 0; channel < DATALOG_NUM_CHANNELS; channel++)
{
DATALOG_clearChannelData(handle, channel);
}
obj->bClear = false;
}
switch (obj->command)
{
case DATALOG_COMMAND_None:
break;
case DATALOG_COMMAND_Arm:
// Only when holding or idle /* Whatever the current state, reset and re-arm the trigger */
if (obj->trigger.state == DATALOG_TRIGGER_STATE_Idle || obj->trigger.state == DATALOG_TRIGGER_STATE_Holding)
{
obj->trigger.state = DATALOG_TRIGGER_STATE_Armed;
obj->channel[obj->trigger.channel].lastSample = 0;
obj->channel[obj->trigger.channel].currentSample = 0;
obj->state = DATALOG_STATE_Armed;
obj->trigger.justArmed = true;
}
break;
case DATALOG_COMMAND_Stop:
break;
}
/* Clear the command */
obj->command = DATALOG_COMMAND_None;
/* Scope functionality */
if (obj->trigger.mode == DATALOG_TRIGGER_MODE_Normal)
{
uint16_t nextSampleIdx = obj->nextSampleIdx;
DATALOG_TRIGGER_STATE_e triggerState = obj->trigger.state;
if (triggerState == DATALOG_TRIGGER_STATE_Holding)
{
// No capture during holding
return;
}
if (triggerState == DATALOG_TRIGGER_STATE_Armed)
{
/* While armed, we need to update the triggering channel values, or we won't see the trigger */
DATALOG_CHANNEL_s* pChannel = &obj->channel[obj->trigger.channel];
if (pChannel->bEnabled)
{
DATALOG_SAMPLE_TYPE sample = *((DATALOG_SAMPLE_TYPE*) pChannel->pSource);
pChannel->lastSample = pChannel->currentSample;
pChannel->currentSample = sample;
}
// Check for trigger
if (DATALOG_checkTrigger(handle))
{
#ifdef SUPPORT_PRETRIGGER_AND_WRAPPED_DATA
/* Can only be used if the client supports unwrapping the data */
// Trigger fired, determine end of log
DATALOG_setSampleWindow(handle);
obj->triggerIdx = nextSampleIdx;
obj->trigger.state = DATALOG_TRIGGER_STATE_Running;
obj->state = DATALOG_STATE_Running;
#else /* SUPPORT_PRETRIGGER_AND_WRAPPED_DATA */
/* Simple capture, from start to end, no wrapping */
obj->nextSampleIdx = 0;
obj->endSampleIdx = 0; // DATALOG_SAMPLE_COUNT;
obj->dataStartIdx = 0;
obj->triggerIdx = 0;
obj->trigger.state = DATALOG_TRIGGER_STATE_Running;
obj->state = DATALOG_STATE_Running;
#endif /* SUPPORT_PRETRIGGER_AND_WRAPPED_DATA */
}
}
if (obj->trigger.state == DATALOG_TRIGGER_STATE_Running)
{
if (obj->downsamplecounter >= obj->downsample)
{
obj->downsamplecounter = 0;
/* This is the actual sampling */
{
int channel;
for (channel = 0; channel < DATALOG_NUM_CHANNELS; channel++)
{
DATALOG_CHANNEL_s* pChannel = &obj->channel[channel];
if (pChannel->bEnabled)
{
DATALOG_SAMPLE_TYPE sample = *((DATALOG_SAMPLE_TYPE*) pChannel->pSource);
pChannel->lastSample = pChannel->currentSample;
pChannel->currentSample = sample;
pChannel->samples[nextSampleIdx] = sample;
}
}
nextSampleIdx++;
if (nextSampleIdx >= DATALOG_SAMPLE_COUNT) nextSampleIdx = 0;
obj->nextSampleIdx = nextSampleIdx;
}
/* Detect end of sampling */
if (obj->nextSampleIdx == obj->endSampleIdx)
{
obj->trigger.state = DATALOG_TRIGGER_STATE_Holding;
obj->state = DATALOG_STATE_Holding;
}
}
else
{
obj->downsamplecounter++;
}
}
}
else if (obj->trigger.mode == DATALOG_TRIGGER_MODE_Rolling)
{
/* Basic continous rolling mode, for debugging use */
uint16_t nextSampleIdx = obj->nextSampleIdx;
int channel;
for (channel = 0; channel < DATALOG_NUM_CHANNELS; channel++)
{
DATALOG_CHANNEL_s* pChannel = &obj->channel[channel];
if (pChannel->bEnabled)
{
DATALOG_SAMPLE_TYPE sample = *((DATALOG_SAMPLE_TYPE*) pChannel->pSource);
pChannel->lastSample = pChannel->currentSample;
pChannel->currentSample = sample;
pChannel->samples[nextSampleIdx] = sample;
}
}
nextSampleIdx++;
if (nextSampleIdx >= DATALOG_SAMPLE_COUNT)
{
nextSampleIdx = 0;
}
obj->nextSampleIdx = nextSampleIdx;
}
} /* end of DATALOG_run() function */
bool DATALOG_checkTrigger(DATALOG_Handle handle)
{
DATALOG_Obj* obj = handle;
bool bTriggered = false;
if (obj->trigger.justArmed)
{
/* Don't trigger directly after arming */
obj->trigger.justArmed = false;
return (false);
}
if (obj->trigger.state == DATALOG_TRIGGER_STATE_Armed)
{
DATALOG_TRIGGER_s* pTrigger = &obj->trigger;
DATALOG_SAMPLE_TYPE currentSample = obj->channel[pTrigger->channel].currentSample;
DATALOG_SAMPLE_TYPE lastSample = obj->channel[pTrigger->channel].lastSample;
DATALOG_TRIGGER_EDGE_DIRECTION_e edge = pTrigger->edge;
DATALOG_SAMPLE_TYPE level = pTrigger->level;
switch (edge)
{
case DATALOG_TRIGGER_EDGE_DIRECTION_Rising:
if (lastSample < level && currentSample >= level)
{
bTriggered = true;
}
break;
case DATALOG_TRIGGER_EDGE_DIRECTION_Falling:
if (lastSample > level && currentSample <= level)
{
bTriggered = true;
}
break;
case DATALOG_TRIGGER_EDGE_DIRECTION_Both:
if ((lastSample < level && currentSample >= level) ||
(lastSample > level && currentSample <= level))
{
bTriggered = true;
}
break;
}
}
return (bTriggered);
} /* end of DATALOG_checkTrigger() function */
void DATALOG_clearChannelData(DATALOG_Handle handle, int channel)
{
DATALOG_Obj* obj = handle;
DATALOG_CHANNEL_s* pChannel = &obj->channel[channel];
int sample;
for (sample = 0; sample < DATALOG_SAMPLE_COUNT; sample++)
{
pChannel->samples[sample] = 0;
}
} /* end of DATALOG_clearChannelData() function */
void DATALOG_setChannel(DATALOG_Handle handle, uint16_t channel, DATALOG_SAMPLE_TYPE* pSample)
{
DATALOG_Obj* obj = handle;
DATALOG_CHANNEL_s* pChannel = &obj->channel[channel];
pChannel->bEnabled = true;
pChannel->pSource = pSample;
} /* end of DATALOG_setChannel() function */
void DATALOG_setCommand(DATALOG_Handle handle, const DATALOG_COMMAND_e command)
{
DATALOG_Obj* obj = handle;
obj->command = command;
return;
} /* end of DATALOG_setCommand() function */
void DATALOG_getChannelBuffer(DATALOG_Handle handle, const int channel, DATALOG_SAMPLE_TYPE** ppBuffer, uint16_t* pSizeBytes)
{
/* Does not support wrapped buffers */
DATALOG_Obj* obj = handle;
*ppBuffer = &obj->channel[channel].samples[0];
*pSizeBytes = obj->endSampleIdx << 1; /* Samples are 16-bit, so we send twice the number of bytes */
if (obj->dataStartIdx == 0 && obj->endSampleIdx == 0)
{
// ToDo: Figure out way to support a full buffer, 60 samples in all
*pSizeBytes = DATALOG_SAMPLE_COUNT * 2;
}
return;
}
void DATALOG_setSampleWindow(DATALOG_Handle handle)
{
DATALOG_Obj* obj = handle;
uint16_t preTrigger = obj->trigger.preTrigger;
uint16_t postTrigger = DATALOG_SAMPLE_COUNT - preTrigger;
uint16_t preTriggerSamples = preTrigger;
uint16_t postTriggerSamples = postTrigger;
uint16_t dataStartIdx;
if (preTriggerSamples > obj->nextSampleIdx)
{
// wrapped
dataStartIdx = (obj->nextSampleIdx + DATALOG_SAMPLE_COUNT - preTriggerSamples);
} else {
dataStartIdx = obj->nextSampleIdx - preTriggerSamples;
}
obj->dataStartIdx = dataStartIdx;
uint16_t endSampleIdx = obj->nextSampleIdx + postTriggerSamples;
// Wrap
if (endSampleIdx >= DATALOG_SAMPLE_COUNT)
{
endSampleIdx -= DATALOG_SAMPLE_COUNT;
}
obj->endSampleIdx = endSampleIdx;
} /* end of DATALOG_setSampleWindow() function */
/* end of datalog.c */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 11,508 | C | 27.7725 | 127 | 0.601842 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/sto_pll_speed_pos_fdbk.c | /**
******************************************************************************
* @file sto_pll_speed_pos_fdbk.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the State Observer + PLL Speed & Position Feedback component of the
* Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup SpeednPosFdbk_STO_PLL
*/
/* Includes ------------------------------------------------------------------*/
#include "sto_pll_speed_pos_fdbk.h"
#include "mc_math.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup SpeednPosFdbk
* @{
*/
/**
* @defgroup SpeednPosFdbk_STO_PLL State Observer PLL Speed & Position Feedback.
* @brief State Observer with PLL Speed & Position Feedback component of MCSDK.
*
* This component uses a State Observer coupled with a software PLL to provide an estimation of
* the speed and the position of the rotor of the motor.
*
* See the [Speed & position feedback sensorless chapter of the User Manual](speed_pos_sensorless_bemf_reconstruction.md) for more details on the sensorless algorithm.
* @{
*/
/* Private defines -----------------------------------------------------------*/
#define C6_COMP_CONST1 ((int32_t)1043038)
#define C6_COMP_CONST2 ((int32_t)10430)
/* Private function prototypes -----------------------------------------------*/
static void STO_Store_Rotor_Speed(STO_PLL_Handle_t *pHandle, int16_t hRotor_Speed);
static int16_t STO_ExecutePLL(STO_PLL_Handle_t *pHandle, int16_t hBemf_alfa_est, int16_t hBemf_beta_est);
static void STO_InitSpeedBuffer(STO_PLL_Handle_t *pHandle);
/**
* @brief Initializes the @p pHandle of STate Observer (STO) PLL component.
*
*/
__weak void STO_PLL_Init(STO_PLL_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int16_t htempk;
int32_t wAux;
pHandle->ConsistencyCounter = pHandle->StartUpConsistThreshold;
pHandle->EnableDualCheck = true;
wAux = ((int32_t)1);
pHandle->F3POW2 = 0U;
htempk = (int16_t)(C6_COMP_CONST1 / pHandle->hF2);
while (htempk != 0)
{
htempk /= ((int16_t)2);
wAux *= ((int32_t)2);
pHandle->F3POW2++;
}
pHandle->hF3 = (int16_t)wAux;
wAux = ((int32_t)(pHandle->hF2)) * pHandle->hF3;
pHandle->hC6 = (int16_t)(wAux / C6_COMP_CONST2);
STO_PLL_Clear(pHandle);
PID_HandleInit(&pHandle->PIRegulator);
/* Acceleration measurement set to zero */
pHandle->_Super.hMecAccelUnitP = 0;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
return;
}
/**
* @brief Necessary empty return to implement fictitious IRQ_Handler.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param uint8_t: Fictitious interrupt flag.
*/
//cstat !MISRAC2012-Rule-8.13 !RED-func-no-effect
__weak void STO_PLL_Return(STO_PLL_Handle_t *pHandle, uint8_t flag)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if ((MC_NULL == (void *)pHandle) || ((uint8_t)0 == flag))
{
/* Nothing to do */
}
else
{
/* Nothing to do */
}
#endif
return;
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief Calculates the estimated electrical angle.
*
* Executes Luenberger state observer equations and calls
* PLL to compute a new speed estimation and
* update the estimated electrical angle.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param pInput: Pointer to the observer inputs structure.
* @retval int16_t Rotor electrical angle (s16Degrees).
*/
//cstat !MISRAC2012-Rule-8.13
__weak int16_t STO_PLL_CalcElAngle(STO_PLL_Handle_t *pHandle, Observer_Inputs_t *pInputs)
{
int16_t retValue;
if ((MC_NULL == pHandle) || (MC_NULL == pInputs))
{
retValue = 0;
}
else
{
int32_t wAux;
int32_t wDirection;
int32_t wIalfa_est_Next;
int32_t wIbeta_est_Next;
int32_t wBemf_alfa_est_Next;
int32_t wBemf_beta_est_Next;
int16_t hAux;
int16_t hAux_Alfa;
int16_t hAux_Beta;
int16_t hIalfa_err;
int16_t hIbeta_err;
int16_t hRotor_Speed;
int16_t hValfa;
int16_t hVbeta;
if (pHandle->wBemf_alfa_est > (((int32_t)pHandle->hF2) * INT16_MAX))
{
pHandle->wBemf_alfa_est = INT16_MAX * ((int32_t)pHandle->hF2);
}
else if (pHandle->wBemf_alfa_est <= (-INT16_MAX * ((int32_t)pHandle->hF2)))
{
pHandle->wBemf_alfa_est = -INT16_MAX * ((int32_t)pHandle->hF2);
}
else
{
/* Nothing to do */
}
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hAux_Alfa = (int16_t)(pHandle->wBemf_alfa_est >> pHandle->F2LOG);
#else
hAux_Alfa = (int16_t)(pHandle->wBemf_alfa_est / pHandle->hF2);
#endif
if (pHandle->wBemf_beta_est > (INT16_MAX * ((int32_t)pHandle->hF2)))
{
pHandle->wBemf_beta_est = INT16_MAX * ((int32_t)pHandle->hF2);
}
else if (pHandle->wBemf_beta_est <= (-INT16_MAX * ((int32_t)pHandle->hF2)))
{
pHandle->wBemf_beta_est = (-INT16_MAX * ((int32_t)pHandle->hF2));
}
else
{
/* Nothing to do */
}
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hAux_Beta = (int16_t)(pHandle->wBemf_beta_est >> pHandle->F2LOG);
#else
hAux_Beta = (int16_t)(pHandle->wBemf_beta_est / pHandle->hF2);
#endif
if (pHandle->Ialfa_est > (INT16_MAX * ((int32_t)pHandle->hF1)))
{
pHandle->Ialfa_est = INT16_MAX * ((int32_t)pHandle->hF1);
}
else if (pHandle->Ialfa_est <= (-INT16_MAX * ((int32_t)pHandle->hF1)))
{
pHandle->Ialfa_est = -INT16_MAX * ((int32_t)pHandle->hF1);
}
else
{
/* Nothing to do */
}
if (pHandle->Ibeta_est > (INT16_MAX * ((int32_t)pHandle->hF1)))
{
pHandle->Ibeta_est = INT16_MAX * ((int32_t)pHandle->hF1);
}
else if (pHandle->Ibeta_est <= (-INT16_MAX * ((int32_t)pHandle->hF1)))
{
pHandle->Ibeta_est = -INT16_MAX * ((int32_t)pHandle->hF1);
}
else
{
/* Nothing to do */
}
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hIalfa_err = (int16_t)(pHandle->Ialfa_est >> pHandle->F1LOG);
#else
hIalfa_err = (int16_t)(pHandle->Ialfa_est / pHandle->hF1);
#endif
hIalfa_err = hIalfa_err - pInputs->Ialfa_beta.alpha;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hIbeta_err = (int16_t)(pHandle->Ibeta_est >> pHandle->F1LOG);
#else
hIbeta_err = (int16_t)(pHandle->Ibeta_est / pHandle->hF1);
#endif
hIbeta_err = hIbeta_err - pInputs->Ialfa_beta.beta;
wAux = ((int32_t)pInputs->Vbus) * pInputs->Valfa_beta.alpha;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
hValfa = (int16_t)(wAux >> 16); //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
hValfa = (int16_t)(wAux / 65536);
#endif
wAux = ((int32_t)pInputs->Vbus) * pInputs->Valfa_beta.beta;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
hVbeta = ( int16_t ) ( wAux >> 16 ); //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
hVbeta = (int16_t)(wAux / 65536);
#endif
/* alfa axes observer */
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hAux = (int16_t)(pHandle->Ialfa_est >> pHandle->F1LOG);
#else
hAux = (int16_t)(pHandle->Ialfa_est / pHandle->hF1);
#endif
wAux = ((int32_t)pHandle->hC1) * hAux;
wIalfa_est_Next = pHandle->Ialfa_est - wAux;
wAux = ((int32_t)pHandle->hC2) * hIalfa_err;
wIalfa_est_Next += wAux;
wAux = ((int32_t)pHandle->hC5) * hValfa;
wIalfa_est_Next += wAux;
wAux = ((int32_t)pHandle->hC3) * hAux_Alfa;
wIalfa_est_Next -= wAux;
wAux = ((int32_t)pHandle->hC4) * hIalfa_err;
wBemf_alfa_est_Next = pHandle->wBemf_alfa_est + wAux;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
wAux = (int32_t)hAux_Beta >> pHandle->F3POW2; //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
wAux = ((int32_t)hAux_Beta) / pHandle->hF3;
#endif
wAux = wAux * pHandle->hC6;
wAux = pHandle->_Super.hElSpeedDpp * wAux;
wBemf_alfa_est_Next += wAux;
/* beta axes observer */
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
hAux = (int16_t)(pHandle->Ibeta_est >> pHandle->F1LOG);
#else
hAux = (int16_t)(pHandle->Ibeta_est / pHandle->hF1);
#endif
wAux = ((int32_t)pHandle->hC1) * hAux;
wIbeta_est_Next = pHandle->Ibeta_est - wAux;
wAux = ((int32_t)pHandle->hC2) * hIbeta_err;
wIbeta_est_Next += wAux;
wAux = ((int32_t)pHandle->hC5) * hVbeta;
wIbeta_est_Next += wAux;
wAux = ((int32_t)pHandle->hC3) * hAux_Beta;
wIbeta_est_Next -= wAux;
wAux = ((int32_t)pHandle->hC4) * hIbeta_err;
wBemf_beta_est_Next = pHandle->wBemf_beta_est + wAux;
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
wAux = (int32_t)hAux_Alfa >> pHandle->F3POW2; //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
wAux = ((int32_t)hAux_Alfa) / pHandle->hF3;
#endif
wAux = wAux * pHandle->hC6;
wAux = pHandle->_Super.hElSpeedDpp * wAux;
wBemf_beta_est_Next -= wAux;
/* Calls the PLL blockset */
pHandle->hBemf_alfa_est = hAux_Alfa;
pHandle->hBemf_beta_est = hAux_Beta;
if (0 == pHandle->hForcedDirection)
{
/* We are in auxiliary mode, then rely on the speed detected */
if(pHandle->_Super.hElSpeedDpp >= 0)
{
wDirection = 1;
}
else
{
wDirection = -1;
}
}
else
{
/* We are in main sensor mode, use a forced direction */
wDirection = pHandle->hForcedDirection;
}
hAux_Alfa = (int16_t)(hAux_Alfa * wDirection);
hAux_Beta = (int16_t)(hAux_Beta * wDirection);
hRotor_Speed = STO_ExecutePLL(pHandle, hAux_Alfa, -hAux_Beta);
pHandle->_Super.InstantaneousElSpeedDpp = hRotor_Speed;
STO_Store_Rotor_Speed(pHandle, hRotor_Speed);
pHandle->_Super.hElAngle += hRotor_Speed;
/* Storing previous values of currents and bemfs */
pHandle->Ialfa_est = wIalfa_est_Next;
pHandle->wBemf_alfa_est = wBemf_alfa_est_Next;
pHandle->Ibeta_est = wIbeta_est_Next;
pHandle->wBemf_beta_est = wBemf_beta_est_Next;
retValue = pHandle->_Super.hElAngle;
}
return (retValue);
}
/**
* @brief Computes and returns the average mechanical speed.
*
* This method must be called - at least - with the same periodicity
* on which speed control is executed. It computes and returns - through
* parameter hMecSpeedUnit - the rotor average mechanical speed,
* expressed in #SPEED_UNIT. Average is computed considering a FIFO depth
* equal to bSpeedBufferSizeUnit. Moreover it also computes and returns
* the reliability state of the sensor.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param pMecSpeedUnit: Pointer to int16_t, used to return the rotor average
* mechanical speed (expressed in #SPEED_UNIT).
* @retval True if the sensor information is reliable, false otherwise.
*/
__weak bool STO_PLL_CalcAvrgMecSpeedUnit(STO_PLL_Handle_t *pHandle, int16_t *pMecSpeedUnit)
{
bool bAux;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if ((MC_NULL == pHandle) || (MC_NULL == pMecSpeedUnit))
{
bAux = false;
}
else
{
#endif
int32_t wAvrSpeed_dpp = (int32_t)0;
int32_t wError;
int32_t wAux;
int32_t wAvrSquareSpeed;
int32_t wAvrQuadraticError = 0;
int32_t wObsBemf, wEstBemf;
int32_t wObsBemfSq = 0;
int32_t wEstBemfSq = 0;
int32_t wEstBemfSqLo;
bool bIs_Speed_Reliable = false;
bool bIs_Bemf_Consistent = false;
uint8_t i, bSpeedBufferSizeUnit = pHandle->SpeedBufferSizeUnit;
for (i = 0U; i < bSpeedBufferSizeUnit; i++)
{
wAvrSpeed_dpp += (int32_t)(pHandle->Speed_Buffer[i]);
}
if (0U == bSpeedBufferSizeUnit)
{
/* Nothing to do */
}
else
{
wAvrSpeed_dpp = wAvrSpeed_dpp / ((int16_t)bSpeedBufferSizeUnit);
}
for (i = 0U; i < bSpeedBufferSizeUnit; i++)
{
wError = ((int32_t)pHandle->Speed_Buffer[i]) - wAvrSpeed_dpp;
wError = (wError * wError);
wAvrQuadraticError += wError;
}
/* It computes the measurement variance */
wAvrQuadraticError = wAvrQuadraticError / ((int16_t)bSpeedBufferSizeUnit);
/* The maximum variance acceptable is here calculated as a function of average speed */
wAvrSquareSpeed = wAvrSpeed_dpp * wAvrSpeed_dpp;
int64_t lAvrSquareSpeed = (int64_t)(wAvrSquareSpeed) * (int64_t)pHandle->VariancePercentage;
wAvrSquareSpeed = (int32_t)(lAvrSquareSpeed / (int64_t)128);
if (wAvrQuadraticError < wAvrSquareSpeed)
{
bIs_Speed_Reliable = true;
}
/* Computation of Mechanical speed Unit */
wAux = wAvrSpeed_dpp * ((int32_t)pHandle->_Super.hMeasurementFrequency);
wAux = wAux * ((int32_t)pHandle->_Super.SpeedUnit);
wAux = wAux / ((int32_t)pHandle->_Super.DPPConvFactor);
wAux = wAux / ((int16_t)pHandle->_Super.bElToMecRatio);
*pMecSpeedUnit = (int16_t)wAux;
pHandle->_Super.hAvrMecSpeedUnit = (int16_t)wAux;
pHandle->IsSpeedReliable = bIs_Speed_Reliable;
/* Bemf Consistency Check algorithm */
if (true == pHandle->EnableDualCheck) /* Do algorithm if it's enabled */
{
/* wAux abs value */
//cstat !MISRAC2012-Rule-14.3_b !RED-func-no-effect !RED-cmp-never !RED-cond-never
wAux = ((wAux < 0) ? (-wAux) : (wAux));
if (wAux < (int32_t)(pHandle->MaxAppPositiveMecSpeedUnit))
{
/* Computation of Observed back-emf */
wObsBemf = (int32_t)pHandle->hBemf_alfa_est;
wObsBemfSq = wObsBemf * wObsBemf;
wObsBemf = (int32_t)pHandle->hBemf_beta_est;
wObsBemfSq += wObsBemf * wObsBemf;
/* Computation of Estimated back-emf */
wEstBemf = (wAux * 32767) / ((int16_t)pHandle->_Super.hMaxReliableMecSpeedUnit);
wEstBemfSq = (wEstBemf * ((int32_t)pHandle->BemfConsistencyGain)) / 64;
wEstBemfSq *= wEstBemf;
/* Computation of threshold */
wEstBemfSqLo = wEstBemfSq - ((wEstBemfSq / 64) * ((int32_t)pHandle->BemfConsistencyCheck));
/* Check */
if (wObsBemfSq > wEstBemfSqLo)
{
bIs_Bemf_Consistent = true;
}
else
{
/* Nothing to do */
}
}
pHandle->IsBemfConsistent = bIs_Bemf_Consistent;
pHandle->Obs_Bemf_Level = wObsBemfSq;
pHandle->Est_Bemf_Level = wEstBemfSq;
}
else
{
bIs_Bemf_Consistent = true;
}
/* Decision making */
if (false == pHandle->IsAlgorithmConverged)
{
bAux = SPD_IsMecSpeedReliable (&pHandle->_Super, pMecSpeedUnit);
}
else
{
if ((false == pHandle->IsSpeedReliable) || (false == bIs_Bemf_Consistent))
{
pHandle->ReliabilityCounter++;
if (pHandle->ReliabilityCounter >= pHandle->Reliability_hysteresys)
{
pHandle->ReliabilityCounter = 0U;
pHandle->_Super.bSpeedErrorNumber = pHandle->_Super.bMaximumSpeedErrorsNumber;
bAux = false;
}
else
{
bAux = SPD_IsMecSpeedReliable (&pHandle->_Super, pMecSpeedUnit);
}
}
else
{
pHandle->ReliabilityCounter = 0U;
bAux = SPD_IsMecSpeedReliable (&pHandle->_Super, pMecSpeedUnit);
}
}
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
return (bAux);
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__( ( section ( ".ccmram" ) ) )
#endif
#endif
/**
* @brief Computes and updates the average electrical speed.
*
* This method must be called - at least - with the same periodicity
* on which speed control is executed. It computes and update component
* variable hElSpeedDpp that is estimated average electrical speed
* expressed in dpp used for instance in observer equations.
* Average is computed considering a FIFO depth equal to
* bSpeedBufferSizedpp.
*
* @param pHandle: Handler of the current instance of the STO component.
*/
__weak void STO_PLL_CalcAvrgElSpeedDpp(STO_PLL_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wSum = pHandle->DppBufferSum;
int32_t wAvrSpeed_dpp;
int16_t hSpeedBufferSizedpp = (int16_t)pHandle->SpeedBufferSizeDpp;
int16_t hSpeedBufferSizeUnit = (int16_t)pHandle->SpeedBufferSizeUnit;
int16_t hBufferSizeDiff;
int16_t hIndexNew = (int16_t)pHandle->Speed_Buffer_Index;
int16_t hIndexOld;
int16_t hIndexOldTemp;
hBufferSizeDiff = hSpeedBufferSizeUnit - hSpeedBufferSizedpp;
if (0 == hBufferSizeDiff)
{
wSum = wSum + pHandle->Speed_Buffer[hIndexNew] - pHandle->SpeedBufferOldestEl;
}
else
{
hIndexOldTemp = hIndexNew + hBufferSizeDiff;
if (hIndexOldTemp >= hSpeedBufferSizeUnit)
{
hIndexOld = hIndexOldTemp - hSpeedBufferSizeUnit;
}
else
{
hIndexOld = hIndexOldTemp;
}
wSum = wSum + pHandle->Speed_Buffer[hIndexNew] - pHandle->Speed_Buffer[hIndexOld];
}
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
wAvrSpeed_dpp = wSum >> pHandle->SpeedBufferSizeDppLOG;
#else
if ((int16_t )0 == hSpeedBufferSizedpp)
{
/* Nothing to do */
wAvrSpeed_dpp = wSum;
}
else
{
wAvrSpeed_dpp = wSum / hSpeedBufferSizedpp;
}
#endif
pHandle->_Super.hElSpeedDpp = (int16_t)wAvrSpeed_dpp;
pHandle->DppBufferSum = wSum;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Clears state observer component by re-initializing private variables in @p pHandle.
*
*/
__weak void STO_PLL_Clear(STO_PLL_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->Ialfa_est = (int32_t)0;
pHandle->Ibeta_est = (int32_t)0;
pHandle->wBemf_alfa_est = (int32_t)0;
pHandle->wBemf_beta_est = (int32_t)0;
pHandle->_Super.hElAngle = (int16_t)0;
pHandle->_Super.hElSpeedDpp = (int16_t)0;
pHandle->ConsistencyCounter = 0u;
pHandle->ReliabilityCounter = 0u;
pHandle->IsAlgorithmConverged = false;
pHandle->IsBemfConsistent = false;
pHandle->Obs_Bemf_Level = (int32_t)0;
pHandle->Est_Bemf_Level = (int32_t)0;
pHandle->DppBufferSum = (int32_t)0;
pHandle->ForceConvergency = false;
pHandle->ForceConvergency2 = false;
STO_InitSpeedBuffer(pHandle);
PID_SetIntegralTerm(& pHandle->PIRegulator, (int32_t)0);
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Stores in @p pHandle the latest calculated value of @p hRotor_Speed.
*
*/
inline static void STO_Store_Rotor_Speed(STO_PLL_Handle_t *pHandle, int16_t hRotor_Speed)
{
uint8_t bBuffer_index = pHandle->Speed_Buffer_Index;
bBuffer_index++;
if (bBuffer_index == pHandle->SpeedBufferSizeUnit)
{
bBuffer_index = 0U;
}
else
{
/* Nothing to do */
}
pHandle->SpeedBufferOldestEl = pHandle->Speed_Buffer[bBuffer_index];
pHandle->Speed_Buffer[bBuffer_index] = hRotor_Speed;
pHandle->Speed_Buffer_Index = bBuffer_index;
}
/**
* @brief Executes PLL algorithm for rotor position extraction from B-emf alpha and beta.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param hBemf_alfa_est: Estimated Bemf alpha on the stator reference frame.
* @param hBemf_beta_est: Estimated Bemf beta on the stator reference frame.
* @retval
*/
inline static int16_t STO_ExecutePLL(STO_PLL_Handle_t *pHandle, int16_t hBemf_alfa_est, int16_t hBemf_beta_est)
{
int32_t wAlfa_Sin_tmp;
int32_t wBeta_Cos_tmp;
int16_t hAux1;
int16_t hAux2;
int16_t hOutput;
Trig_Components Local_Components;
Local_Components = MCM_Trig_Functions(pHandle->_Super.hElAngle);
/* Alfa & Beta BEMF multiplied by Cos & Sin */
wAlfa_Sin_tmp = ((int32_t )hBemf_alfa_est) * ((int32_t )Local_Components.hSin);
wBeta_Cos_tmp = ((int32_t )hBemf_beta_est) * ((int32_t )Local_Components.hCos);
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
hAux1 = (int16_t)(wBeta_Cos_tmp >> 15); //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
hAux1 = (int16_t)(wBeta_Cos_tmp / 32768);
#endif
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
hAux2 = (int16_t)(wAlfa_Sin_tmp >> 15); //cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
#else
hAux2 = (int16_t)(wAlfa_Sin_tmp / 32768);
#endif
/* Speed PI regulator */
hOutput = PI_Controller(& pHandle->PIRegulator, (int32_t)(hAux1 ) - hAux2);
return (hOutput);
}
/**
* @brief Clears the estimated speed buffer in @p pHandle.
*
*/
static void STO_InitSpeedBuffer(STO_PLL_Handle_t * pHandle)
{
uint8_t b_i;
uint8_t bSpeedBufferSize = pHandle->SpeedBufferSizeUnit;
/* Init speed buffer */
for (b_i = 0U; b_i < bSpeedBufferSize; b_i++)
{
pHandle->Speed_Buffer[b_i] = (int16_t)0;
}
pHandle->Speed_Buffer_Index = 0U;
pHandle->SpeedBufferOldestEl = (int16_t)0;
}
/**
* @brief Checks if the state observer algorithm converged.
*
* Internally performs a set of checks necessary to state whether
* the state observer algorithm converged. To be periodically called
* during motor open-loop ramp-up (e.g. at the same frequency of
* SPD_CalcElAngle), it returns true if the estimated angle and speed
* can be considered reliable, false otherwise.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param hForcedMecSpeedUnit: Mechanical speed in 0.1Hz unit as forced by VSS.
* @retval bool True if the estimated angle and speed are reliables, false otherwise.
*/
__weak bool STO_PLL_IsObserverConverged(STO_PLL_Handle_t *pHandle, int16_t *phForcedMecSpeedUnit)
{
bool bAux = false;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if ((MC_NULL == pHandle) || (MC_NULL == phForcedMecSpeedUnit))
{
/* Nothing to do */
}
else
{
#endif
int32_t wAux;
int32_t wtemp;
int16_t hEstimatedSpeedUnit;
int16_t hUpperThreshold;
int16_t hLowerThreshold;
if (true == pHandle->ForceConvergency2)
{
*phForcedMecSpeedUnit = pHandle->_Super.hAvrMecSpeedUnit;
}
else
{
/* Nothing to do */
}
if (true == pHandle->ForceConvergency)
{
bAux = true;
pHandle->IsAlgorithmConverged = true;
pHandle->_Super.bSpeedErrorNumber = 0U;
}
else
{
hEstimatedSpeedUnit = pHandle->_Super.hAvrMecSpeedUnit;
wtemp = ((int32_t)hEstimatedSpeedUnit) * ((int32_t)*phForcedMecSpeedUnit);
if (wtemp > 0)
{
if (hEstimatedSpeedUnit < 0)
{
hEstimatedSpeedUnit = -hEstimatedSpeedUnit;
}
if (*phForcedMecSpeedUnit < 0)
{
*phForcedMecSpeedUnit = -*phForcedMecSpeedUnit;
}
wAux = ((int32_t)*phForcedMecSpeedUnit) * ((int16_t)pHandle->SpeedValidationBand_H);
hUpperThreshold = (int16_t)(wAux / ((int32_t)16));
wAux = ((int32_t)*phForcedMecSpeedUnit) * ((int16_t)pHandle->SpeedValidationBand_L);
hLowerThreshold = (int16_t)(wAux / ((int32_t)16));
/* If the variance of the estimated speed is low enough... */
if (true == pHandle->IsSpeedReliable)
{
if ((uint16_t)hEstimatedSpeedUnit > pHandle->MinStartUpValidSpeed)
{
/* ...and the estimated value is quite close to the expected value... */
if (hEstimatedSpeedUnit >= hLowerThreshold)
{
if (hEstimatedSpeedUnit <= hUpperThreshold)
{
pHandle->ConsistencyCounter++;
/* ...for hConsistencyThreshold consecutive times... */
if (pHandle->ConsistencyCounter >= pHandle->StartUpConsistThreshold)
{
/* The algorithm converged */
bAux = true;
pHandle->IsAlgorithmConverged = true;
pHandle->_Super.bSpeedErrorNumber = 0U;
}
}
else
{
pHandle->ConsistencyCounter = 0U;
}
}
else
{
pHandle->ConsistencyCounter = 0U;
}
}
else
{
pHandle->ConsistencyCounter = 0U;
}
}
else
{
pHandle->ConsistencyCounter = 0U;
}
}
else
{
/* Nothing to do */
}
}
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
return (bAux);
}
/**
* @brief Exports estimated Bemf alpha-beta from @p pHandle.
*
* @retval alphabeta_t Bemf alpha-beta.
*/
//cstat !MISRAC2012-Rule-8.13
__weak alphabeta_t STO_PLL_GetEstimatedBemf(STO_PLL_Handle_t *pHandle)
{
alphabeta_t vaux;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
vaux.alpha = 0;
vaux.beta = 0;
}
else
{
#endif
vaux.alpha = pHandle->hBemf_alfa_est;
vaux.beta = pHandle->hBemf_beta_est;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
return (vaux);
}
/**
* @brief Exports from @p pHandle the stator current alpha-beta as estimated by state observer.
*
* @retval alphabeta_t State observer estimated stator current Ialpha-beta.
*/
//cstat !MISRAC2012-Rule-8.13
__weak alphabeta_t STO_PLL_GetEstimatedCurrent(STO_PLL_Handle_t *pHandle)
{
alphabeta_t iaux;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
iaux.alpha = 0;
iaux.beta = 0;
}
else
{
#endif
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
iaux.alpha = (int16_t)(pHandle->Ialfa_est >> pHandle->F1LOG);
#else
iaux.alpha = (int16_t)(pHandle->Ialfa_est / pHandle->hF1);
#endif
#ifndef FULL_MISRA_C_COMPLIANCY_STO_PLL
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
iaux.beta = (int16_t)(pHandle->Ibeta_est >> pHandle->F1LOG);
#else
iaux.beta = (int16_t)(pHandle->Ibeta_est / pHandle->hF1);
#endif
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
return (iaux);
}
/**
* @brief Exports current observer gains from @p pHandle and to parameters @p phC2 and @p phC4.
*
*/
//cstat !MISRAC2012-Rule-8.13
__weak void STO_PLL_GetObserverGains(STO_PLL_Handle_t *pHandle, int16_t *phC2, int16_t *phC4)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if ((MC_NULL == pHandle) || (MC_NULL == phC2) || (MC_NULL == phC4))
{
/* Nothing to do */
}
else
{
#endif
*phC2 = pHandle->hC2;
*phC4 = pHandle->hC4;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Stores in @p pHandle the new values @p hhC1 and @p hhC2 for observer gains.
*
*/
//cstat !MISRAC2012-Rule-8.13
__weak void STO_PLL_SetObserverGains(STO_PLL_Handle_t *pHandle, int16_t hhC1, int16_t hhC2)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hC2 = hhC1;
pHandle->hC4 = hhC2;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Exports current PLL gains from @p pHandle to @p pPgain and @p pIgain.
*
*/
//cstat !MISRAC2012-Rule-8.13
__weak void STO_GetPLLGains(STO_PLL_Handle_t *pHandle, int16_t *pPgain, int16_t *pIgain)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if ((MC_NULL == pHandle) || (MC_NULL == pPgain) || (MC_NULL == pIgain))
{
/* Nothing to do */
}
else
{
#endif
*pPgain = PID_GetKP(& pHandle->PIRegulator);
*pIgain = PID_GetKI(& pHandle->PIRegulator);
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Stores in @p pHandle the new values @p hPgain and @p hIgain for PLL gains.
*
*/
__weak void STO_SetPLLGains(STO_PLL_Handle_t *pHandle, int16_t hPgain, int16_t hIgain)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
PID_SetKP(&pHandle->PIRegulator, hPgain);
PID_SetKI(&pHandle->PIRegulator, hIgain);
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Empty function. Could be declared to set instantaneous information on rotor mechanical angle.
*
* Note: Mechanical angle management is not implemented in this
* version of State observer sensor class.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param hMecAngle: Instantaneous measure of rotor mechanical angle.
*/
//cstat !MISRAC2012-Rule-8.13 !RED-func-no-effect
__weak void STO_PLL_SetMecAngle(STO_PLL_Handle_t *pHandle, int16_t hMecAngle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if ((MC_NULL == (void *)pHandle) || ((int16_t)0 == hMecAngle))
{
/* Nothing to do */
}
else
{
/* nothing to do */
}
#endif
}
/**
* @brief Resets the PLL integral term during on-the-fly startup.
*
* @param pHandle: Handler of the current instance of the STO component.
*/
__weak void STO_OTF_ResetPLL(STO_Handle_t * pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
STO_PLL_Handle_t *pHdl = (STO_PLL_Handle_t *)pHandle->_Super; //cstat !MISRAC2012-Rule-11.3
PID_SetIntegralTerm(&pHdl->PIRegulator, (int32_t)0);
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__( ( section ( ".ccmram" ) ) )
#endif
#endif
/**
* @brief Resets the PLL integral term.
*
* @param pHandle: Handler of the current instance of the STO component.
*/
__weak void STO_ResetPLL(STO_PLL_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
PID_SetIntegralTerm(&pHandle->PIRegulator, (int32_t)0);
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Sends locking info for PLL.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param hElSpeedDpp: Estimated average electrical speed expressed in dpp.
* @param hElAngle: Estimated electrical angle expressed in s16Degrees.
*/
__weak void STO_SetPLL(STO_PLL_Handle_t *pHandle, int16_t hElSpeedDpp, int16_t hElAngle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
PID_SetIntegralTerm(&pHandle->PIRegulator, ((int32_t)hElSpeedDpp)
* (int32_t)(PID_GetKIDivisor(&pHandle->PIRegulator)));
pHandle->_Super.hElAngle = hElAngle;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Exports estimated Bemf squared level stored in @p pHandle.
*
* @retval int32_t Magnitude of estimated Bemf Level squared based on speed measurement.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int32_t STO_PLL_GetEstimatedBemfLevel(STO_PLL_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
return ((MC_NULL == pHandle) ? 0 : pHandle->Est_Bemf_Level);
#else
return (pHandle->Est_Bemf_Level);
#endif
}
/**
* @brief Exports observed Bemf squared level stored in @p pHandle.
*
* @retval int32_t Magnitude of observed Bemf level squared.
*/
//cstat !MISRAC2012-Rule-8.13
__weak int32_t STO_PLL_GetObservedBemfLevel(STO_PLL_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
return ((MC_NULL == pHandle) ? 0 : pHandle->Obs_Bemf_Level);
#else
return (pHandle->Obs_Bemf_Level);
#endif
}
/**
* @brief Enables/Disables additional reliability check based on observed Bemf.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param bSel Enable/Disable check.
*/
__weak void STO_PLL_BemfConsistencyCheckSwitch(STO_PLL_Handle_t *pHandle, bool bSel)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->EnableDualCheck = bSel;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Checks if the Bemf is consistent.
*
* @param pHandle: Handler of the current instance of the STO component.
* @retval bool True when observed Bemfs are consistent with expectation, false otherwise.
*/
//cstat !MISRAC2012-Rule-8.13
__weak bool STO_PLL_IsBemfConsistent(STO_PLL_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
return ((MC_NULL == pHandle) ? false : pHandle->IsBemfConsistent);
#else
return (pHandle->IsBemfConsistent);
#endif
}
/**
* @brief Checks the value of the variance.
*
* @param pHandle: Handler of the current instance of the STO component.
* @retval bool True if the speed measurement variance is lower than threshold VariancePercentage, false otherwise.
*/
__weak bool STO_PLL_IsVarianceTight(const STO_Handle_t *pHandle)
{
bool tempStatus;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
tempStatus = false;
}
else
{
#endif
const STO_PLL_Handle_t *pHdl = (STO_PLL_Handle_t *)pHandle->_Super; //cstat !MISRAC2012-Rule-11.3
tempStatus = pHdl->IsSpeedReliable;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
return (tempStatus);
}
/**
* @brief Forces the state-observer to declare convergency.
*
* @param pHandle: Handler of the current instance of the STO component.
*/
__weak void STO_PLL_ForceConvergency1(STO_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
STO_PLL_Handle_t *pHdl = (STO_PLL_Handle_t *)pHandle->_Super; //cstat !MISRAC2012-Rule-11.3
pHdl->ForceConvergency = true;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Forces the state-observer to declare convergency.
*
* @param pHandle: Handler of the current instance of the STO component.
*/
__weak void STO_PLL_ForceConvergency2(STO_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
STO_PLL_Handle_t *pHdl = (STO_PLL_Handle_t *)pHandle->_Super; //cstat !MISRAC2012-Rule-11.3
pHdl->ForceConvergency2 = true;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Sets the Absolute value of minimum mechanical speed (expressed in
* the unit defined by #SPEED_UNIT) required to validate the start-up.
*
* @param pHandle: Handler of the current instance of the STO component.
* @param hMinStartUpValidSpeed: Absolute value of minimum mechanical speed.
*/
__weak void STO_SetMinStartUpValidSpeedUnit(STO_PLL_Handle_t *pHandle, uint16_t hMinStartUpValidSpeed)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->MinStartUpValidSpeed = hMinStartUpValidSpeed;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @brief Sets the rotation @p direction in @p pHandle.
*/
__weak void STO_SetDirection(STO_PLL_Handle_t *pHandle, int8_t direction)
{
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hForcedDirection = direction;
#ifdef NULL_PTR_CHECK_STO_PLL_SPD_POS_FDB
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/** @} */
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 36,481 | C | 27.019969 | 168 | 0.635481 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/ntc_temperature_sensor.c | /**
******************************************************************************
* @file ntc_temperature_sensor.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Temperature Sensor component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup TemperatureSensor
*/
/* Includes ------------------------------------------------------------------*/
#include "ntc_temperature_sensor.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup TemperatureSensor NTC Temperature Sensor
* @brief Allows to read the temperature of the heat sink
*
* This component implements both a virtual and a real temperature sensor,
* depending on the sensor availability.
*
* Access to the MCU peripherals needed to acquire the temperature (GPIO and ADC
* used for regular conversion) is managed by the PWM component used in the Motor
* Control subsystem. As a consequence, this NTC temperature sensor implementation
* is hardware-independent.
*
* If a real temperature sensor is available (Sensor Type = #REAL_SENSOR),
* this component can handle NTC sensors or, more generally, analog temperature sensors
* which output is related to the temperature by the following formula:
*
* @f[
* V_{out} = V_0 + \frac{dV}{dT} \cdot ( T - T_0)
* @f]
*
* In case of Pull up configuration @f$\frac{dV}{dT}@f$ is positive and @f$V_0@f$ is low.
* In case of Pull down configuration @f$\frac{dV}{dT}@f$ is negative and @f$V_0@f$ is high.
*
* In case a real temperature sensor is not available (Sensor Type = #VIRTUAL_SENSOR),
* This component will always returns a constant, programmable, temperature.
*
* @{
*/
/* Private function prototypes -----------------------------------------------*/
uint16_t NTC_SetFaultState(NTC_Handle_t *pHandle);
/* Private functions ---------------------------------------------------------*/
/**
* @brief Returns fault when temperature exceeds the related temperature voltage protection threshold
*
* @param pHandle : Pointer on Handle structure of TemperatureSensor component
*
* @retval Fault status : Updated internal fault status
*/
__weak uint16_t NTC_SetFaultState(NTC_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
uint16_t hFault;
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
if (MC_NULL == pHandle)
{
hFault = MC_SW_ERROR;
}
else
{
#endif
if (pHandle->hAvTemp_d > pHandle->hOverTempThreshold)
{
hFault = MC_OVER_TEMP;
}
else if (pHandle->hAvTemp_d < pHandle->hOverTempDeactThreshold)
{
hFault = MC_NO_ERROR;
}
else
{
hFault = pHandle->hFaultState;
}
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
}
#endif
return (hFault);
}
/* Functions ---------------------------------------------------- */
/**
* @brief Initializes temperature sensing conversions
*
* @param pHandle : Pointer on Handle structure of TemperatureSensor component
*
*/
__weak void NTC_Init(NTC_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (REAL_SENSOR == pHandle->bSensorType)
{
NTC_Clear(pHandle);
}
else /* case VIRTUAL_SENSOR */
{
pHandle->hFaultState = MC_NO_ERROR;
pHandle->hAvTemp_d = pHandle->hExpectedTemp_d;
}
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
}
#endif
}
/**
* @brief Initializes internal average temperature computed value
*
* @param pHandle : Pointer on Handle structure of TemperatureSensor component
*/
__weak void NTC_Clear(NTC_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
if (MC_NULL == pHandle)
{
/* nothing to do */
}
else
{
#endif
pHandle->hAvTemp_d = 0U;
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
}
#endif
}
/**
* @brief Performs the temperature sensing average computation after an ADC conversion
*
* @param pHandle : Pointer on Handle structure of TemperatureSensor component
*
* @retval Fault status : Error reported in case of an over temperature detection
*/
__weak uint16_t NTC_CalcAvTemp(NTC_Handle_t *pHandle, uint16_t rawValue)
{
uint16_t returnValue;
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
if (MC_NULL == pHandle)
{
returnValue = 0U;
}
else
{
#endif
if (REAL_SENSOR == pHandle->bSensorType)
{
uint16_t hAux;
hAux = rawValue;
if (0xFFFFU == hAux)
{
/* Nothing to do */
}
else
{
uint32_t wtemp;
wtemp = (uint32_t)(pHandle->hLowPassFilterBW) - 1U;
wtemp *= ((uint32_t)pHandle->hAvTemp_d);
wtemp += hAux;
wtemp /= ((uint32_t)pHandle->hLowPassFilterBW);
pHandle->hAvTemp_d = (uint16_t)wtemp;
}
pHandle->hFaultState = NTC_SetFaultState(pHandle);
}
else /* case VIRTUAL_SENSOR */
{
pHandle->hFaultState = MC_NO_ERROR;
}
returnValue = pHandle->hFaultState;
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
}
#endif
return (returnValue);
}
/**
* @brief Returns latest averaged temperature measured expressed in u16Celsius
*
* @param pHandle : Pointer on Handle structure of TemperatureSensor component
*
* @retval AverageTemperature : Current averaged temperature measured (in u16Celsius)
*/
__weak uint16_t NTC_GetAvTemp_d(const NTC_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
return ((MC_NULL == pHandle) ? 0U : pHandle->hAvTemp_d);
#else
return (pHandle->hAvTemp_d);
#endif
}
/**
* @brief Returns latest averaged temperature expressed in Celsius degrees
*
* @param pHandle : Pointer on Handle structure of TemperatureSensor component
*
* @retval AverageTemperature : Latest averaged temperature measured (in Celsius degrees)
*/
__weak int16_t NTC_GetAvTemp_C(NTC_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
int16_t returnValue;
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
if (MC_NULL == pHandle)
{
returnValue = 0;
}
else
{
#endif
int32_t wTemp;
if (REAL_SENSOR == pHandle->bSensorType)
{
wTemp = (int32_t)pHandle->hAvTemp_d;
wTemp -= ((int32_t)pHandle->wV0);
wTemp *= pHandle->hSensitivity;
#ifndef FULL_MISRA_C_COMPLIANCY_NTC_TEMP
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
wTemp = (wTemp >> 16) + (int32_t)pHandle->hT0;
#else
wTemp = (wTemp / 65536) + (int32_t)pHandle->hT0;
#endif
}
else
{
wTemp = (int32_t)pHandle->hExpectedTemp_C;
}
returnValue = (int16_t)wTemp;
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
}
#endif
return (returnValue);
}
/**
* @brief Returns Temperature measurement fault status
*
* Fault status can be either #MC_OVER_TEMP when measure exceeds the protection threshold values or
* #MC_NO_ERROR if it is inside authorized range.
*
* @param pHandle: Pointer on Handle structure of TemperatureSensor component.
*
* @retval Fault status : read internal fault state
*/
__weak uint16_t NTC_CheckTemp(const NTC_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_NTC_TEMP_SENS
return ((MC_NULL == pHandle) ? 0U : pHandle->hFaultState);
#else
return (pHandle->hFaultState);
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 7,870 | C | 26.141379 | 102 | 0.62033 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/fixpmath.c | /**
******************************************************************************
* @file fixpmath.c
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* fixpmath.c */
#include "fixpmath.h"
#include <math.h> /* fabsf() */
#include "mathlib.h"
#include "mc_stm_types.h" /* Required for CORDIC */
#if defined(CORDIC)
#define FIXPMATH_USE_CORDIC
#endif
#ifdef FIXPMATH_USE_CORDIC
// Number of cycles can be tuned as a compromise between calculation time and precision
#define CORDIC_CONFIG_BASE_COSSIN (LL_CORDIC_PRECISION_6CYCLES | LL_CORDIC_SCALE_0 | LL_CORDIC_NBWRITE_2 |\
LL_CORDIC_INSIZE_32BITS | LL_CORDIC_OUTSIZE_32BITS)
/* CORDIC FUNCTION: COSINE only q1.31 */
#define CORDIC_CONFIG_COSINE (CORDIC_CONFIG_BASE_COSSIN | LL_CORDIC_FUNCTION_COSINE)
/* CORDIC FUNCTION: SINE only q1.31 */
#define CORDIC_CONFIG_SINE (CORDIC_CONFIG_BASE_COSSIN | LL_CORDIC_FUNCTION_SINE)
/* CORDIC FUNCTION: COSINE and SINE q1.31 */
#define CORDIC_CONFIG_COSINE_AND_SINE (CORDIC_CONFIG_BASE_COSSIN | LL_CORDIC_FUNCTION_COSINE | LL_CORDIC_NBREAD_2)
/* CORDIC FUNCTION: PHASE q1.31 (Angle and magnitude computation) */
#define CORDIC_CONFIG_PHASE (LL_CORDIC_FUNCTION_PHASE | LL_CORDIC_PRECISION_15CYCLES | LL_CORDIC_SCALE_0 |\
LL_CORDIC_NBWRITE_2 | LL_CORDIC_NBREAD_2 |\
LL_CORDIC_INSIZE_32BITS | LL_CORDIC_OUTSIZE_32BITS)
/* CORDIC FUNCTION: SQUAREROOT q1.31 */
#define CORDIC_CONFIG_SQRT (LL_CORDIC_FUNCTION_SQUAREROOT | LL_CORDIC_PRECISION_3CYCLES | LL_CORDIC_SCALE_1 |\
LL_CORDIC_NBWRITE_1 | LL_CORDIC_NBREAD_1 |\
LL_CORDIC_INSIZE_32BITS | LL_CORDIC_OUTSIZE_32BITS)
// ToDo: Use LL_CORDIC_FUNCTION_HCOSINE to calculate EXP
#define ANGLE_CORDIC_TO_PU(angle_cordic) (angle_cordic >> 2) & (FIXP30(1.0f)-1) /* scale and wrap cordic angle to per unit */
#define ANGLE_PU_TO_CORDIC(angle_pu) (angle_pu << 2)
#define ANGLE_FP24_PU_TO_CORDIC(angle_pu) (angle_pu << 8)
#endif /* FIXPMATH_USE_CORDIC */
/* fixptable is a table of pre-calculated powers of 2 as float value */
const float FIXPSCALED_fixptable[] =
{
(float) (1UL << 0), /* 1.0f, which is the maximum value which will fit in an fixp30_t */
(float) (1UL << 1),
(float) (1UL << 2),
(float) (1UL << 3),
(float) (1UL << 4),
(float) (1UL << 5),
(float) (1UL << 6),
(float) (1UL << 7), /* i = 7, fixptable[i] == 128.0f, fixpFmt = 31 - 7 = 24 */
(float) (1UL << 8),
(float) (1UL << 9),
(float) (1UL << 10),
(float) (1UL << 11),
(float) (1UL << 12),
(float) (1UL << 13),
(float) (1UL << 14),
(float) (1UL << 15),
(float) (1UL << 16),
(float) (1UL << 17),
(float) (1UL << 18),
(float) (1UL << 19),
(float) (1UL << 20),
(float) (1UL << 21),
(float) (1UL << 22),
(float) (1UL << 23),
(float) (1UL << 24),
(float) (1UL << 25),
(float) (1UL << 26),
(float) (1UL << 27),
(float) (1UL << 28),
(float) (1UL << 29),
(float) (1UL << 30), /* 1073741824.0f, which is the maximum value which will fit in an fixp1_t */
(float) (1UL << 31), /* 2147483648.0f, which is the maximum value which will fit in an fixp0_t */
(float) (1ULL << 32),
(float) (1ULL << 33),
(float) (1ULL << 34),
(float) (1ULL << 35),
(float) (1ULL << 36),
(float) (1ULL << 37),
(float) (1ULL << 38),
(float) (1ULL << 39),
(float) (1ULL << 40),
(float) (1ULL << 41),
(float) (1ULL << 42),
(float) (1ULL << 43),
};
void FIXPMATH_init(void)
{
MATHLIB_init();
}
void FIXPSCALED_floatToFIXPscaled(const float value, FIXP_scaled_t *pFps)
{
int i;
fixpFmt_t fixpFmt = 0; /* use fixp0_t if number will not fit at all */
/* the absolute value is used for comparisons, but the actual value for the final calculation */
float absvalue = fabsf(value);
/* Figure out which scale will fit the float provided */
for (i = 0; i <= 31; i++)
{
if (FIXPSCALED_fixptable[i] > absvalue) /* check if it will fit */
{
/* the qFmt for the result */
fixpFmt = 31 - i;
break;
}
/* We either find a fit, or use _iq0 by default */
}
pFps->fixpFmt = fixpFmt;
pFps->value = (long) (value * FIXPSCALED_fixptable[fixpFmt]); /* may be negative */
} /* end of FIXPSCALED_floatToFIXPscaled() function */
void FIXPSCALED_floatToFIXPscaled_exp(const float value, FIXP_scaled_t *pFps, fixpFmt_t exponent)
{
pFps->fixpFmt = exponent;
pFps->value = (long) (value * FIXPSCALED_fixptable[exponent]); /* may be negative */
} /* end of FIXPSCALED_floatToFIXPscaled_exp() function */
float_t FIXPSCALED_FIXPscaledToFloat(const FIXP_scaled_t *pFps)
{
return (float) ((float) pFps->value / FIXPSCALED_fixptable[pFps->fixpFmt]);
} /* end of FIXPSCALED_FIXPscaledToFloat() function */
void FIXPSCALED_doubleToFIXPscaled(const double value, FIXP_scaled_t *pFps)
{
int i;
fixpFmt_t fixpFmt = 0; /* use fixp0_t if number will not fit at all */
/* the absolute value is used for comparisons, but the actual value for the final calculation */
double absvalue = fabs(value);
/* Figure out which scale will fit the float provided */
for (i = 0; i <= 31; i++)
{
if ((double)FIXPSCALED_fixptable[i] > absvalue) /* check if it will fit */
{
/* the qFmt for the result */
fixpFmt = 31 - i;
break;
}
/* We either find a fit, or use fixp0_t by default */
}
pFps->fixpFmt = fixpFmt;
pFps->value = (long) (value * (double)FIXPSCALED_fixptable[fixpFmt]); /* may be negative */
} /* end of FIXPSCALED_floatToFIXPscaled() function */
void FIXPSCALED_calculateScaleFactor(
const fixpFmt_t source_fixpFmt,
const fixpFmt_t target_fixpFmt,
const float source_fullscale,
const float target_fullscale,
const float datascale_factor,
FIXP_scaled_t* pFps)
{
/* fixed point scaling factor */
/* Calculated using bitshifts, to avoid using the pow function */
float fixpFmt_factor;
int_least8_t lshift = target_fixpFmt - source_fixpFmt;
if (lshift >= 0)
{
/* Positive shift, giving 2^n */
fixpFmt_factor = (float) (1ul << lshift);
}
else
{
/* Negative shift, where we need to divide to calculate the corresponding factor 1/2^abs(n) */
fixpFmt_factor = (float) (1.0f / (1ul << (-lshift)));
}
/* full scale scaling factor */
float fullscale_factor = source_fullscale / target_fullscale;
/* data scaling factor */
/* as given */
/* total scaling factor is the product of these three factors */
float ds = fixpFmt_factor * fullscale_factor * datascale_factor;
/* Convert float to fixed point in optimal scale */
FIXPSCALED_floatToFIXPscaled(ds, pFps);
} /* end of FIXPSCALED_calculateScaleFactor() function */
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
void FIXP30_CosSinPU(fixp30_t angle_pu, FIXP_CosSin_t *pCosSin)
{
#if defined(FIXPMATH_USE_CORDIC)
__disable_irq();
WRITE_REG(CORDIC->CSR, CORDIC_CONFIG_COSINE_AND_SINE);
LL_CORDIC_WriteData(CORDIC, ANGLE_PU_TO_CORDIC(angle_pu));
LL_CORDIC_WriteData(CORDIC, FIXP30(1.0f));
while (HAL_IS_BIT_CLR(CORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
pCosSin->cos = LL_CORDIC_ReadData(CORDIC);
pCosSin->sin = LL_CORDIC_ReadData(CORDIC);
__enable_irq();
#else /* FIXPMATH_USE_CORDIC */
angle_pu = (angle_pu & 0x3FFFFFFFul) >> (30-15) ; /* Wrap the angle by ANDing */
Vector_cossin_s cossin = MATHLIB_cossin(angle_pu);
pCosSin->cos = cossin.cos << (30-15);
pCosSin->sin = cossin.sin << (30-15);
#endif /* FIXPMATH_USE_CORDIC */
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
void FIXP30_polar(const fixp30_t x, const fixp30_t y, fixp30_t *pAngle_pu, fixp30_t *pMagnitude)
{
#ifdef FIXPMATH_USE_CORDIC
__disable_irq();
WRITE_REG(CORDIC->CSR, CORDIC_CONFIG_PHASE);
LL_CORDIC_WriteData(CORDIC, x);
LL_CORDIC_WriteData(CORDIC, y);
while (HAL_IS_BIT_CLR(CORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
*pAngle_pu = ANGLE_CORDIC_TO_PU(LL_CORDIC_ReadData(CORDIC));
*pMagnitude = LL_CORDIC_ReadData(CORDIC);
__enable_irq();
#else
MATHLIB_polar(x, y, pAngle_pu, pMagnitude);
#endif
}
fixp_t FIXP_mag(const fixp_t a, const fixp_t b)
{
fixp_t dummy;
fixp_t magnitude;
FIXP30_polar(a, b, &dummy, &magnitude);
return magnitude;
}
fixp30_t FIXP30_mag(const fixp30_t a, const fixp30_t b)
{
fixp_t dummy;
fixp_t magnitude;
FIXP30_polar(a, b, &dummy, &magnitude);
return magnitude;
}
fixp30_t FIXP30_atan2_PU(fixp30_t beta, fixp30_t alpha)
{
fixp30_t angle_pu;
fixp30_t dummy;
FIXP30_polar(alpha, beta, &angle_pu, &dummy);
return angle_pu;
}
fixp24_t FIXP24_atan2_PU(fixp24_t beta, fixp24_t alpha)
{
fixp24_t angle_pu;
fixp24_t dummy;
FIXP30_polar(alpha, beta, &angle_pu, &dummy);
return (angle_pu >> (30 - FIXP_FMT));
}
fixp29_t FIXP29_atan2_PU(fixp30_t beta, fixp30_t alpha)
{
fixp29_t angle_pu;
fixp29_t dummy;
FIXP30_polar(alpha, beta, &angle_pu, &dummy);
return (angle_pu >> (30 - 29));
}
fixp_t FIXP_cos(fixp_t angle_rad)
{
#ifdef FIXPMATH_USE_CORDIC
fixp30_t angle_pu = FIXP24_mpy(angle_rad, FIXP30(1.0f/M_TWOPI));
__disable_irq();
WRITE_REG(CORDIC->CSR, CORDIC_CONFIG_COSINE);
LL_CORDIC_WriteData(CORDIC, ANGLE_PU_TO_CORDIC(angle_pu));
LL_CORDIC_WriteData(CORDIC, FIXP24(1.0f));
while (HAL_IS_BIT_CLR(CORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
fixp_t data = LL_CORDIC_ReadData(CORDIC);
__enable_irq();
return data;
#else
fixp_t angle_pu = FIXP30_mpy(angle_rad, FIXP30(1.0f/M_TWOPI));
fixp15_t angle_pu_q15 = (angle_pu & (FIXP(1.0f)-1)) >> (FIXP_FMT-15) ; /* Wrap the angle by ANDing, shift to q15 format */
Vector_cossin_s cossin = MATHLIB_cossin(angle_pu_q15);
return (cossin.cos << (FIXP_FMT-15));
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
fixp_t FIXP_cos_PU(fixp_t angle_pu)
{
#ifdef FIXPMATH_USE_CORDIC
__disable_irq();
WRITE_REG(CORDIC->CSR, CORDIC_CONFIG_COSINE);
LL_CORDIC_WriteData(CORDIC, ANGLE_FP24_PU_TO_CORDIC(angle_pu));
LL_CORDIC_WriteData(CORDIC, FIXP24(1.0f));
while (HAL_IS_BIT_CLR(CORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
fixp_t data = LL_CORDIC_ReadData(CORDIC);
__enable_irq();
return data;
#else
fixp15_t angle_pu_q15 = (angle_pu & (FIXP(1.0f)-1)) >> (FIXP_FMT-15) ; /* Wrap the angle by ANDing, shift to q15 format */
Vector_cossin_s cossin = MATHLIB_cossin(angle_pu_q15);
return (cossin.cos << (FIXP_FMT-15));
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
fixp30_t FIXP30_cos_PU(fixp30_t angle_pu)
{
#ifdef FIXPMATH_USE_CORDIC
__disable_irq();
WRITE_REG(CORDIC->CSR, CORDIC_CONFIG_COSINE);
LL_CORDIC_WriteData(CORDIC, ANGLE_PU_TO_CORDIC(angle_pu));
LL_CORDIC_WriteData(CORDIC, FIXP30(1.0f));
while (HAL_IS_BIT_CLR(CORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
fixp30_t data = LL_CORDIC_ReadData(CORDIC);
__enable_irq();
return data;
#else
fixp_t angle_pu_q15 = (angle_pu & (FIXP30(1.0f)-1)) >> (30-15) ; /* Wrap the angle by ANDing, shift to q15 format */
Vector_cossin_s cossin = MATHLIB_cossin(angle_pu_q15);
return (cossin.cos << (30-15));
#endif
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
fixp30_t FIXP30_sin_PU(fixp30_t angle_pu)
{
#ifdef FIXPMATH_USE_CORDIC
__disable_irq();
WRITE_REG(CORDIC->CSR, CORDIC_CONFIG_SINE);
LL_CORDIC_WriteData(CORDIC, ANGLE_PU_TO_CORDIC(angle_pu));
LL_CORDIC_WriteData(CORDIC, FIXP30(1.0f));
while (HAL_IS_BIT_CLR(CORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
fixp30_t data = LL_CORDIC_ReadData(CORDIC);
__enable_irq();
return data;
#else
fixp_t angle_pu_q15 = (angle_pu & (FIXP30(1.0f)-1)) >> (30-15) ; /* Wrap the angle by ANDing, shift to q15 format */
Vector_cossin_s cossin = MATHLIB_cossin(angle_pu_q15);
return (cossin.sin << (30-15));
#endif
}
fixp_t FIXP_exp(fixp_t power)
{
// ToDo: Use CORDIC when supported (The exponential function, exp x, can be obtained as the sum of sinh x and cosh x.)
float_t power_flt = FIXP_toF(power);
return FIXP((float_t)expf(power_flt));
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section (".ccmram")))
#endif
#endif
fixp30_t FIXP30_sqrt(const fixp30_t value)
{
/* Return zero for negative/zero inputs */
if (value <= 0) return 0;
#ifdef FIXPMATH_USE_CORDIC_disabled /* Not reliable over the required range yet */
__disable_irq();
WRITE_REG(CORDIC->CSR, CORDIC_CONFIG_SQRT);
LL_CORDIC_WriteData(CORDIC, value);
while (HAL_IS_BIT_CLR(CORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
fixp30_t data = LL_CORDIC_ReadData(CORDIC);
__enable_irq();
return data;
#else
/* Floating point placeholder calculation */
return FIXP30(sqrtf(FIXP30_toF(value)));
#endif
}
fixp24_t FIXP24_sqrt(const fixp24_t value)
{
// ToDo: Use CORDIC when supported
/* Floating point placeholder calculation */
return FIXP24(sqrtf(FIXP24_toF(value)));
}
/* end of fixpmath.c */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 14,285 | C | 31.841379 | 126 | 0.636752 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/feed_forward_ctrl.c | /**
******************************************************************************
* @file feed_forward_ctrl.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the Feed-forward
* Control component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
* @ingroup FeedForwardCtrl
*/
/* Includes ------------------------------------------------------------------*/
#include "feed_forward_ctrl.h"
#include <stddef.h>
#include "mc_type.h"
#include "bus_voltage_sensor.h"
#include "speed_pos_fdbk.h"
#include "speed_torq_ctrl.h"
#include "r_divider_bus_voltage_sensor.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup FeedForwardCtrl Feed-forward Control
* @brief Feed-forward Control component of the Motor Control SDK
*
* See the [Feed-forward chapter of the User Manual](feed_forward_current_regulation.md) for more details on the theoretical
* background of this regulator.
* @{
*/
/* Private macros ------------------------------------------------------------*/
#define SEGMNUM (uint8_t)7 /* coeff no. -1 */
#define SATURATION_TO_S16(a) if ((a) > 32767) \
{ \
(a) = 32767; \
} \
else if ((a) < -32767) \
{ \
(a) = -32767; \
} \
else \
{} \
/**
* @brief Initializes all the component variables
* @param pHandle Feed-forward init structure.
* @param pBusSensor VBus Sensor.
* @param pPIDId Id PID structure.
* @param pPIDIq Iq PID structure.
*/
__weak void FF_Init(FF_Handle_t *pHandle, BusVoltageSensor_Handle_t *pBusSensor, PID_Handle_t *pPIDId,
PID_Handle_t *pPIDIq)
{
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->wConstant_1D = pHandle->wDefConstant_1D;
pHandle->wConstant_1Q = pHandle->wDefConstant_1Q;
pHandle->wConstant_2 = pHandle->wDefConstant_2;
pHandle->pBus_Sensor = pBusSensor;
pHandle->pPID_d = pPIDId;
pHandle->pPID_q = pPIDIq;
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
}
#endif
}
/**
* @brief It should be called before each motor start and clears the Feed-forward
* internal variables.
* @param pHandle Feed-forward structure.
*/
__weak void FF_Clear(FF_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->Vqdff.q = (int16_t)0;
pHandle->Vqdff.d = (int16_t)0;
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
}
#endif
}
/**
* @brief It implements Feed-forward controller by computing new Vqdff value.
* This will be then summed up to PI output in FF_VqdConditioning
* method.
* @param pHandle Feed-forward structure.
* @param Iqdref Iqd reference components used to calculate the Feed-forward
* action.
* @param pSTC Pointer on speed and torque controller structure.
*/
__weak void FF_VqdffComputation(FF_Handle_t *pHandle, qd_t Iqdref, SpeednTorqCtrl_Handle_t *pSTC)
{
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wtemp1, wtemp2;
int16_t hSpeed_dpp;
uint16_t hAvBusVoltage_d;
SpeednPosFdbk_Handle_t *SpeedSensor;
SpeedSensor = STC_GetSpeedSensor(pSTC);
hSpeed_dpp = SPD_GetElSpeedDpp(SpeedSensor);
hAvBusVoltage_d = VBS_GetAvBusVoltage_d(pHandle->pBus_Sensor) / 2U;
if (hAvBusVoltage_d != (uint16_t)0)
{
/*q-axes ff voltage calculation */
wtemp1 = (((int32_t)(hSpeed_dpp) * Iqdref.d) / (int32_t)32768);
wtemp2 = (wtemp1 * pHandle->wConstant_1D) / (int32_t)(hAvBusVoltage_d);
wtemp2 *= (int32_t)2;
wtemp1 = ((pHandle->wConstant_2 * hSpeed_dpp) / (int32_t)hAvBusVoltage_d) * (int32_t)16;
wtemp2 = wtemp1 + wtemp2;
SATURATION_TO_S16(wtemp2)
pHandle->Vqdff.q = (int16_t)(wtemp2);
/* d-axes ff voltage calculation */
wtemp1 = (((int32_t)(hSpeed_dpp) * Iqdref.q) / (int32_t)32768);
wtemp2 = (wtemp1 * pHandle->wConstant_1Q) / (int32_t)(hAvBusVoltage_d);
wtemp2 *= (int32_t)(-2);
SATURATION_TO_S16(wtemp2)
pHandle->Vqdff.d = (int16_t)(wtemp2);
}
else
{
pHandle->Vqdff.q = (int16_t)0;
pHandle->Vqdff.d = (int16_t)0;
}
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
}
#endif
}
//cstat #MISRAC2012-Rule-2.2_b
/* False positive */
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief It returns the Vqd components computed by input plus the Feed-forward
* action and store the last Vqd values in the internal variable.
* @param pHandle Feed-forward structure.
* @param Vqd Initial value of Vqd to be manipulated by Feed-forward action .
* @retval qd_t Vqd conditioned values.
*/
__weak qd_t FF_VqdConditioning(FF_Handle_t *pHandle, qd_t Vqd)
{
qd_t lVqd;
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
if (NULL == pHandle)
{
lVqd.q = 0;
lVqd.d = 0;
}
else
{
#endif
int32_t wtemp;
pHandle->VqdPIout = Vqd;
wtemp = (int32_t)(Vqd.q) + pHandle->Vqdff.q;
SATURATION_TO_S16(wtemp)
lVqd.q = (int16_t)wtemp;
wtemp = (int32_t)(Vqd.d) + pHandle->Vqdff.d;
SATURATION_TO_S16(wtemp)
lVqd.d = (int16_t)wtemp;
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
}
#endif
return (lVqd);
}
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
/**
* @brief It low-pass filters the Vqd voltage coming from the speed PI. Filter
* bandwidth depends on hVqdLowPassFilterBW parameter.
* @param pHandle Feed-forward structure.
*/
__weak void FF_DataProcess(FF_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
int32_t wAux;
int32_t lowPassFilterBW = (int32_t) pHandle->hVqdLowPassFilterBW - (int32_t)1;
#ifndef FULL_MISRA_C_COMPLIANCY_FWD_FDB
/* Computation of average Vqd as output by PI(D) current controllers, used by
Feed-forward controller algorithm */
wAux = (int32_t)(pHandle->VqdAvPIout.q) * lowPassFilterBW;
wAux += pHandle->VqdPIout.q;
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
pHandle->VqdAvPIout.q = (int16_t)(wAux >> pHandle->hVqdLowPassFilterBWLOG);
wAux = (int32_t)(pHandle->VqdAvPIout.d) * lowPassFilterBW;
wAux += pHandle->VqdPIout.d;
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
pHandle->VqdAvPIout.d = (int16_t)(wAux >> pHandle->hVqdLowPassFilterBWLOG);
#else
/* Computation of average Vqd as output by PI(D) current controllers, used by
Feed-forward controller algorithm */
wAux = (int32_t)(pHandle->VqdAvPIout.q) * lowPassFilterBW;
wAux += pHandle->VqdPIout.q;
pHandle->VqdAvPIout.q = (int16_t)(wAux / (int32_t)(pHandle->hVqdLowPassFilterBW));
wAux = (int32_t)(pHandle->VqdAvPIout.d) * lowPassFilterBW;
wAux += pHandle->VqdPIout.d;
pHandle->VqdAvPIout.d = (int16_t)(wAux / (int32_t)(pHandle->hVqdLowPassFilterBW));
#endif
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
}
#endif
}
/**
* @brief Use this method to initialize FF variables in START_TO_RUN state.
* @param pHandle Feed-forward structure.
*/
__weak void FF_InitFOCAdditionalMethods(FF_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->VqdAvPIout.q = 0;
pHandle->VqdAvPIout.d = 0;
PID_SetIntegralTerm(pHandle->pPID_q, 0);
PID_SetIntegralTerm(pHandle->pPID_d, 0);
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
}
#endif
}
/**
* @brief Use this method to set new constants values used by
* Feed-forward algorithm.
* @param pHandle Feed-forward structure.
* @param sNewConstants The FF_TuningStruct_t containing constants used by
* Feed-forward algorithm.
*/
__weak void FF_SetFFConstants(FF_Handle_t *pHandle, FF_TuningStruct_t sNewConstants)
{
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
if (NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->wConstant_1D = sNewConstants.wConst_1D;
pHandle->wConstant_1Q = sNewConstants.wConst_1Q;
pHandle->wConstant_2 = sNewConstants.wConst_2;
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
}
#endif
}
//cstat #MISRAC2012-Rule-2.2_b
/* False positive */
/**
* @brief Use this method to get current constants values used by
* Feed-forward algorithm.
* @param pHandle Feed-forward structure.
* @retval FF_TuningStruct_t Values of the constants used by
* Feed-forward algorithm.
*/
//cstat !MISRAC2012-Rule-8.13
__weak FF_TuningStruct_t FF_GetFFConstants(FF_Handle_t *pHandle)
{
FF_TuningStruct_t LocalConstants;
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
if (NULL == pHandle)
{
LocalConstants.wConst_1D = 0;
LocalConstants.wConst_1Q = 0;
LocalConstants.wConst_2 = 0;
}
else
{
#endif
LocalConstants.wConst_1D = pHandle->wConstant_1D;
LocalConstants.wConst_1Q = pHandle->wConstant_1Q;
LocalConstants.wConst_2 = pHandle->wConstant_2;
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
}
#endif
return (LocalConstants);
}
/**
* @brief Use this method to get present values for the Vqd Feed-forward
* components.
* @param pHandle Feed-forward structure.
* @retval qd_t Vqd Feed-forward components.
*/
__weak qd_t FF_GetVqdff(const FF_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
qd_t retqt;
if (NULL == pHandle)
{
retqt.q = 0;
retqt.d = 0;
}
else
{
retqt = pHandle->Vqdff;
}
return (retqt);
#else
return (pHandle->Vqdff);
#endif
}
/**
* @brief Use this method to get the averaged output values of qd axes
* currents PI regulators.
* @param pHandle Feed-forward structure.
* @retval qd_t Averaged output of qd axes currents PI regulators.
*/
__weak qd_t FF_GetVqdAvPIout(const FF_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_FEED_FWD_CTRL
qd_t retqt;
if (NULL == pHandle)
{
retqt.q = 0;
retqt.d = 0;
}
else
{
retqt = pHandle->VqdAvPIout;
}
return (retqt);
#else
return (pHandle->VqdAvPIout);
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 12,998 | C | 27.951002 | 125 | 0.637329 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/demag_mgt.c | /**
******************************************************************************
* @file f0xx_bemf_ADC_fdbk.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement Bemf sensing
* class to be stantiated when the six-step sensorless driving mode
* topology is used. It is specifically designed for STM32F0XX
* microcontrollers and implements the sensing using one ADC with
* DMA support.
* + MCU peripheral and handle initialization fucntion
* + ADC sampling function
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "demag_mgt.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/**
* @defgroup Demag_management Six-Step Demagnetization time management
*
* @brief Demagnetization time management
*
* This component is used in applications based on Six-Step algorithm
* using either sensorless or sensored position feedback.
*
* @todo: TODO: complete documentation.
* @{
*/
/**
* @brief It initializes ADC1, DMA and NVIC for three bemf voltages reading
* @param pHandle: handler of the current instance of the Bemf_ADC component
* @retval none
*/
__weak void DMG_Init( Demag_Handle_t *pHandle )
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->PWMCycles = 0;
pHandle->DemagCounterThreshold = pHandle->DemagMinimumThreshold;
}
}
/**
* @brief Reset the ADC status
* @param pHandle: handler of the current instance of the Bemf_ADC component
* @retval none
*/
__weak void DMG_Clear( Demag_Handle_t *pHandle )
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->PWMCycles = 0;
}
}
/**
* @brief Reset the ADC status
* @param pHandle: handler of the current instance of the Bemf_ADC component
* @retval none
*/
__weak void DMG_IncreaseDemagCounter(Demag_Handle_t *pHandle)
{
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
pHandle->PWMCycles = pHandle->PWMCycles + pHandle->PWMScaling ;
}
}
/**
* @brief Reset the ADC status
* @param pHandle: handler of the current instance of the Bemf_ADC component
* @retval none
*/
__weak uint16_t DMG_GetDemagCounter(Demag_Handle_t *pHandle)
{
return (pHandle->PWMCycles);
}
/**
* @brief Reset the ADC status
* @param pHandle: handler of the current instance of the Bemf_ADC component
* @retval none
*/
__weak bool DMG_IsDemagTElapsed(Demag_Handle_t *pHandle )
{
bool DemagElapsed = false;
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
if (pHandle->PWMCycles >= pHandle->DemagCounterThreshold)
{
DemagElapsed = true;
}
else
{
}
}
return DemagElapsed;
}
/**
* @brief It calculates and stores in the corresponding variable the demagnetization
* time in open loop operation
* @param pHandle: handler of the current instance of the Bemf_ADC component
* @param pHandleSTC: handler of the current instance of the Speed Control component
* @retval none
*/
__weak void DMG_CalcRevUpDemagT(Demag_Handle_t *pHandle, SpeednTorqCtrl_Handle_t *pHandleSTC )
{
int16_t hSpeed;
SpeednPosFdbk_Handle_t *speedHandle;
speedHandle = STC_GetSpeedSensor(pHandleSTC);
hSpeed = SPD_GetAvrgMecSpeedUnit(speedHandle);
if (hSpeed == 0)
{
pHandle->DemagCounterThreshold = pHandle->DemagMinimumThreshold;;
}
else
{
if (hSpeed < 0)
{
hSpeed = - hSpeed;
}
pHandle->DemagCounterThreshold = (uint16_t) (pHandle->RevUpDemagSpeedConv / hSpeed);
}
if (pHandle->DemagCounterThreshold < pHandle->DemagMinimumThreshold)
{
pHandle->DemagCounterThreshold = pHandle->DemagMinimumThreshold;
}
}
/**
* @brief It calculates and stores in the corresponding variable the demagnetization
* time in closed loop operation
* @param pHandle: handler of the current instance of the Bemf_ADC component
* @param pHandleSTC: handler of the current instance of the Speed Control component
* @retval none
*/
__weak void DMG_CalcRunDemagT(Demag_Handle_t *pHandle, SpeednTorqCtrl_Handle_t *pHandleSTC )
{
int16_t hSpeed;
SpeednPosFdbk_Handle_t *speedHandle;
speedHandle = STC_GetSpeedSensor(pHandleSTC);
hSpeed = SPD_GetAvrgMecSpeedUnit(speedHandle);
if (hSpeed < 0) hSpeed = - hSpeed;
if (hSpeed < pHandle->DemagMinimumSpeedUnit)
{
pHandle->DemagCounterThreshold = (uint16_t) (pHandle->RunDemagSpeedConv / hSpeed);
if (pHandle->DemagCounterThreshold < pHandle->DemagMinimumThreshold)
{
pHandle->DemagCounterThreshold = pHandle->DemagMinimumThreshold;
}
}
else
{
pHandle->DemagCounterThreshold = pHandle->DemagMinimumThreshold;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,514 | C | 25.38756 | 94 | 0.624955 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/open_loop.c | /**
******************************************************************************
* @file open_loop.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Open Loop component.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup OpenLoop
*/
/* Includes ------------------------------------------------------------------*/
#include "open_loop.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup OpenLoop Open Loop Control
* @brief Open Loop component of the Motor Control SDK
*
* Open Loop component allows to run the motor in open loop voltage mode. In that mode, the phase voltages are
* forced independently from the measured currents. To do so, the routine OL_VqdConditioning() overwrites the
* voltage command Vdq in the FOC current controller task. The voltage level to apply can be set directly by the
* user, with OL_UpdateVoltage(), or computed by OL_Calc() if the V/F mode is selected. In that mode, the voltage
* level depends on the speed, the slope and the offset selected by the user.
*
* @{
*/
/* Private defines -----------------------------------------------------------*/
/**
* @brief Initializes OpenLoop variables.it should be called
* once during Motor Control initialization.
* @param pHandle: Pointer on Handle structure of OpenLoop feature.
* @param pVSS: Pointer on virtual speed sensor structure.
*/
__weak void OL_Init(OpenLoop_Handle_t *pHandle, VirtualSpeedSensor_Handle_t *pVSS)
{
#ifdef NULL_PTR_CHECK_OPEN_LOOP
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hVoltage = pHandle->hDefaultVoltage;
pHandle->pVSS = pVSS;
#ifdef NULL_PTR_CHECK_OPEN_LOOP
}
#endif
}
/**
* @brief Sets Vqd according to open loop phase voltage. It should be
* called during current controller task.
* @param pHandle: Pointer on Handle structure of OpenLoop feature.
* @retval qd_t Vqd conditioned values.
*/
__weak qd_t OL_VqdConditioning(const OpenLoop_Handle_t *pHandle)
{
qd_t Vqd;
Vqd.d = 0;
#ifdef NULL_PTR_CHECK_OPEN_LOOP
Vqd.q = ((MC_NULL == pHandle) ? 0 : pHandle->hVoltage);
#else
Vqd.q = (pHandle->hVoltage);
#endif
return (Vqd);
}
/**
* @brief Sets new open loop phase voltage.
* @param pHandle: Pointer on Handle structure of OpenLoop feature.
* @param hNewVoltage: New voltage value to apply.
*/
__weak void OL_UpdateVoltage(OpenLoop_Handle_t *pHandle, int16_t hNewVoltage)
{
#ifdef NULL_PTR_CHECK_OPEN_LOOP
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->hVoltage = hNewVoltage;
#ifdef NULL_PTR_CHECK_OPEN_LOOP
}
#endif
}
/**
* @brief Gets open loop phase voltage.
* @param pHandle: Pointer on Handle structure of OpenLoop feature.
*/
__weak int16_t OL_GetVoltage(OpenLoop_Handle_t *pHandle) //cstat !MISRAC2012-Rule-8.13
{
int16_t hVoltage;
#ifdef NULL_PTR_CHECK_OPEN_LOOP
hVoltage = ((MC_NULL == pHandle) ? 0 : pHandle->hVoltage);
#else
hVoltage = pHandle->hVoltage;
#endif
return (hVoltage);
}
/**
* @brief Computes phase voltage to apply according to average mechanical speed (V/F Mode).
* It should be called during background task.
* @param pHandle: Pointer on Handle structure of OpenLoop feature.
*/
__weak void OL_Calc(OpenLoop_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_OPEN_LOOP
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
if (true == pHandle->VFMode)
{
/* V/F mode true means enabled */
if (pHandle->pVSS->_Super.hAvrMecSpeedUnit >= 0)
{
pHandle->hVoltage = pHandle->hVFOffset + (pHandle->hVFSlope * pHandle->pVSS->_Super.hAvrMecSpeedUnit);
}
else
{
pHandle->hVoltage = pHandle->hVFOffset - (pHandle->hVFSlope * pHandle->pVSS->_Super.hAvrMecSpeedUnit);
}
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_OPEN_LOOP
}
#endif
}
/**
* @brief Activates of the Voltage versus Frequency mode (V/F mode).
* @param pHandle: Pointer on Handle structure of OpenLoop feature.
* @param VFEnabling: Flag to enable the V/F mode.
*/
__weak void OL_VF(OpenLoop_Handle_t *pHandle, bool VFEnabling)
{
#ifdef NULL_PTR_CHECK_OPEN_LOOP
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
pHandle->VFMode = VFEnabling;
#ifdef NULL_PTR_CHECK_OPEN_LOOP
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,116 | C | 26.363636 | 115 | 0.606919 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/max_torque_per_ampere.c | /**
******************************************************************************
* @file max_torque_per_ampere.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the features
* of the Maximum Torque Per Ampere (MTPA) Control component of the Motor Control SDK:
*
* * Initialize the parameter for MTPA
* * Calculate and output id and iq reference based on torque input
* * Calculate and output id based on iq input
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
* @ingroup MTPA
*/
/* Includes ------------------------------------------------------------------*/
#include "max_torque_per_ampere.h"
#include <stdint.h>
/** @addtogroup MCSDK
* @{
*/
/** @defgroup MTPA Maximum Torque Per Ampere Control
* @brief Maximum Torque Per Ampere (MTPA) Control component of the Motor Control SDK
*
* The torque of the PMSM can be expressed with the equation shown below:
*
* @f[
* T_e = \frac{3}{2}\times p \times \phi \times i_q + \frac{3}{2}\times p\times(L_d-L_q)\times i_q\times i_d
* @f]
*
* When the motor is a surface mount permanent magnet synchronous motor (SM-PMSM), the @f$ L_d @f$ and @f$ L_q @f$
* are almost the same, so only the @f$ i_q @f$ can influence the torque. For internal permanent
* magnet synchronous motor (I-PMSM), the @f$ L_d @f$ is not equal to @f$ L_q @f$. Both @f$ i_d @f$ and @f$ i_q @f$ will influence
* the torque.
* The aim of the MTPA (maximum-torque-per-ampere) control is to calculate the
* reference currents which maximize the ratio between produced
* electromagnetic torque and copper losses.
* The input of this component
* is the @f$ i_q @f$ reference. The output of this component is @f$ i_d @f$ reference.
*
* @{
*/
/**
* @brief Calculates the Id current reference based on input Iq current reference
* @param pHandle Handle on the MTPA component
* @param Iqdref current reference in the Direct-Quadratic reference frame. Expressed
* in the qd_t format.
*
*/
__weak void MTPA_CalcCurrRefFromIq(const MTPA_Handle_t *pHandle, qd_t *Iqdref)
{
#ifdef NULL_PTR_CHECK_MAX_TRQ_PER_AMP
if ((NULL == pHandle) || (NULL == Iqdref))
{
/* Nothing to do */
}
else
{
#endif
int32_t id;
int16_t aux;
int16_t iq;
uint8_t segment;
iq = ((Iqdref->q < 0) ? (-Iqdref->q) : (Iqdref->q)); /* Teref absolute value */
aux = iq / pHandle->SegDiv;
segment = (uint8_t)aux;
if (segment > SEGMENT_NUM)
{
segment = SEGMENT_NUM;
}
else
{
/* Nothing to do */
}
#ifndef FULL_MISRA_C_COMPLIANCY_MAX_TOR
//cstat !MISRAC2012-Rule-1.3_n !ATH-shift-neg !MISRAC2012-Rule-10.1_R6
id = ((pHandle->AngCoeff[segment] * iq) >> 15) + pHandle->Offset[segment];
#else
id = ((pHandle->AngCoeff[segment] * iq) / 32768) + pHandle->Offset[segment];
#endif
Iqdref->d = (int16_t)id;
#ifdef NULL_PTR_CHECK_MAX_TRQ_PER_AMP
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,485 | C | 38.467626 | 132 | 0.64175 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/cmd_parser.c | /**
******************************************************************************
* @file register_interface.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the register access for the MCP protocol
*
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
#include "stdint.h"
#include "string.h"
#include "register_interface.h"
#include "mc_config.h"
#include "mc_parameters.h"
#include "mcp.h"
#include "mcp_config.h"
#include "mcpa.h"
#include "mc_configuration_registers.h"
//#include "dac_ui.h"
__weak uint8_t RI_SetRegCommandParser (MCP_Handle_t * pHandle, uint16_t txSyncFreeSpace)
{
uint16_t * dataElementID;
uint8_t * rxData = pHandle->rxBuffer;
uint8_t * txData = pHandle->txBuffer;
int16_t rxLength = pHandle->rxLength;
uint16_t size;
uint8_t retVal=MCP_CMD_OK;
uint8_t accessResult;
uint8_t number_of_item =0;
pHandle->txLength = 0;
while (rxLength > 0)
{
number_of_item ++;
dataElementID = (uint16_t *) rxData;
rxLength = rxLength-MCP_ID_SIZE; // We consume 2 byte in the DataID
rxData = rxData+MCP_ID_SIZE; // Shift buffer to the next data
accessResult = RI_SetReg (*dataElementID,rxData,&size,rxLength);
/* Prepare next data*/
rxLength = (int16_t) (rxLength - size);
rxData = rxData+size;
/* If there is only one CMD in the buffer, we do not store the result */
if (number_of_item == 1 && rxLength == 0)
{
retVal = accessResult;
}
else
{/* Store the result for each access to be able to report failling access */
if (txSyncFreeSpace !=0 )
{
*txData = accessResult;
txData = txData+1;
pHandle->txLength++;
txSyncFreeSpace--; /* decrement one by one no wraparound possible */
retVal = (accessResult != MCP_CMD_OK) ? MCP_CMD_NOK : retVal;
if ((accessResult == MCP_ERROR_BAD_DATA_TYPE) || (accessResult == MCP_ERROR_BAD_RAW_FORMAT))
{ /* From this point we are not able to continue to decode CMD buffer*/
/* We stop the parsing */
rxLength = 0;
}
}
else
{
/* Stop parsing the cmd buffer as no space to answer */
/* If we reach this state, chances are high the command was badly formated or received */
rxLength = 0;
retVal = MCP_ERROR_NO_TXSYNC_SPACE;
}
}
}
/* If all accesses are fine, just one global MCP_CMD_OK is required*/
if (retVal == MCP_CMD_OK)
{
pHandle->txLength = 0;
}
return retVal;
}
__weak uint8_t RI_GetRegCommandParser (MCP_Handle_t * pHandle, uint16_t txSyncFreeSpace)
{
uint16_t * dataElementID;
uint8_t * rxData = pHandle->rxBuffer;
uint8_t * txData = pHandle->txBuffer;
uint16_t size = 0;
uint16_t rxLength = pHandle->rxLength;
int16_t freeSpaceS16 = (int16_t) txSyncFreeSpace;
uint8_t retVal = MCP_CMD_NOK;
pHandle->txLength = 0;
while (rxLength > 0)
{
dataElementID = (uint16_t *) rxData;
rxLength = rxLength-MCP_ID_SIZE;
rxData = rxData+MCP_ID_SIZE; // Shift buffer to the next MCP_ID
retVal = RI_GetReg (*dataElementID,txData, &size, freeSpaceS16);
if (retVal == MCP_CMD_OK )
{
txData = txData+size;
pHandle->txLength += size;
freeSpaceS16 = freeSpaceS16-size;
}
else
{
rxLength = 0;
}
}
return retVal;
}
| 3,935 | C | 31.262295 | 106 | 0.587802 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/circle_limitation.c | /**
******************************************************************************
* @file circle_limitation.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides the functions that implement the circle
* limitation feature of the STM32 Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup CircleLimitation
*/
/* Includes ------------------------------------------------------------------*/
#include "circle_limitation.h"
#include "mc_math.h"
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @defgroup CircleLimitation Circle Limitation
* @brief Circle Limitation component of the Motor Control SDK
*
* @{
*/
#if defined (CCMRAM)
#if defined (__ICCARM__)
#pragma location = ".ccmram"
#elif defined (__CC_ARM) || defined(__GNUC__)
__attribute__((section(".ccmram")))
#endif
#endif
#if defined CIRCLE_LIMITATION_SQRT_M0
const uint16_t SqrtTable[1025] = SQRT_CIRCLE_LIMITATION;
#endif
/**
* @brief Returns the saturated @f$v_q, v_d@f$ component values
* @param pHandle Handler of the CircleLimitation component
* @param Vqd @f$v_q, v_d@f$ values
* @retval Saturated @f$v_q, v_d@f$ values
*
* This function implements the CircleLimitation feature described CircleLimitation component.
*
* @f$v_d = \min(v_d^*, v_d MAX) @f$
*
* @f$v_q = \sqrt(MaxModule^2-v_d^2\ ) @f$
*
*/
__weak qd_t Circle_Limitation(const CircleLimitation_Handle_t *pHandle, qd_t Vqd)
{
qd_t local_vqd = Vqd;
#ifdef NULL_PTR_CHECK_CRC_LIM
if (MC_NULL == pHandle)
{
local_vqd.q = 0;
local_vqd.d = 0;
}
else
{
#endif
int32_t maxModule;
int32_t square_q;
int32_t square_temp;
int32_t square_d;
int32_t square_sum;
int32_t square_limit;
int32_t vd_square_limit;
int32_t new_q;
int32_t new_d;
maxModule = (int32_t)pHandle->MaxModule;
square_q = ((int32_t)(Vqd.q)) * Vqd.q;
square_d = ((int32_t)(Vqd.d)) * Vqd.d;
square_limit = maxModule * maxModule;
vd_square_limit = ((int32_t)pHandle->MaxVd) * ((int32_t)pHandle->MaxVd);
square_sum = square_q + square_d;
if (square_sum > square_limit)
{
if (square_d <= vd_square_limit)
{
#if defined CIRCLE_LIMITATION_SQRT_M0
square_temp = (square_limit - square_d) / 1048576;
new_q = SqrtTable[square_temp];
#else
square_temp = square_limit - square_d;
new_q = MCM_Sqrt(square_temp);
#endif
if (Vqd.q < 0)
{
new_q = -new_q;
}
else
{
/* Nothing to do */
}
new_d = Vqd.d;
}
else
{
new_d = (int32_t)pHandle->MaxVd;
if (Vqd.d < 0)
{
new_d = -new_d;
}
else
{
/* Nothing to do */
}
#if defined CIRCLE_LIMITATION_SQRT_M0
square_temp = (square_limit - vd_square_limit) / 1048576;
new_q = SqrtTable[square_temp];
#else
square_temp = square_limit - vd_square_limit;
new_q = MCM_Sqrt(square_temp);
#endif
if (Vqd.q < 0)
{
new_q = - new_q;
}
else
{
/* Nothing to do */
}
}
local_vqd.q = (int16_t)new_q;
local_vqd.d = (int16_t)new_d;
}
#ifdef NULL_PTR_CHECK_CRC_LIM
}
#endif
return (local_vqd);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 3,984 | C | 23.90625 | 95 | 0.525602 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Src/mcpa.c | /******************************************************************************
* @file mcpa.c
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the datalog feature
* of the MCP protocol
*
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
#include "mc_type.h"
#include "string.h"
#include "mcp.h"
#include "register_interface.h"
#include "mcpa.h"
uint32_t GLOBAL_TIMESTAMP = 0U;
static void MCPA_stopDataLog(MCPA_Handle_t *pHandle);
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup MCP
* @{
*/
/**
* @brief Allocates and fills buffer with asynchronous data to be sent to controller
*
* @param *pHandle Pointer to the MCPA Handle
*/
void MCPA_dataLog(MCPA_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_MCPA
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
uint32_t *logValue;
uint16_t *logValue16;
uint8_t i;
if (pHandle->HFIndex == pHandle->HFRateBuff) /* */
{
pHandle->HFIndex = 0U;
if (0U == pHandle->bufferIndex)
{
/* New buffer allocation */
if (0U == pHandle->pTransportLayer->fGetBuffer (pHandle->pTransportLayer,
(void **) &pHandle->currentBuffer, //cstat !MISRAC2012-Rule-11.3
MCTL_ASYNC))
{
/* Nothing to do, try next HF Task to get an Async buffer */
#ifdef MCP_DEBUG_METRICS
pHandle->bufferMissed++;
#endif
}
else
{
logValue = (uint32_t *)pHandle->currentBuffer; //cstat !MISRAC2012-Rule-11.3
*logValue = GLOBAL_TIMESTAMP; /* 32 first bits is used to store Timestamp */
pHandle->bufferIndex = 4U;
pHandle->MFIndex = 0U; /* Restart the motif from scratch at each buffer */
/* Check if configuration has changed for this new buffer */
if (pHandle->Mark == pHandle->MarkBuff)
{
/* Nothing to do */
}
else
{
pHandle->MarkBuff = pHandle->Mark;
pHandle->HFNumBuff = pHandle->HFNum;
pHandle->MFNumBuff = pHandle->MFNum;
pHandle->HFRateBuff = pHandle->HFRate;
pHandle->MFRateBuff = pHandle->MFRate;
pHandle->bufferTxTriggerBuff = pHandle->bufferTxTrigger;
/* We store pointer here, so 4 bytes */
(void)memcpy(pHandle->dataPtrTableBuff, pHandle->dataPtrTable,
((uint32_t)pHandle->HFNum + (uint32_t)pHandle->MFNum) * 4U); /* We store pointer here,
so 4 bytes */
(void)memcpy(pHandle->dataSizeTableBuff, pHandle->dataSizeTable,
(uint32_t)pHandle->HFNum + (uint32_t)pHandle->MFNum); /* 1 size byte per ID */
}
}
}
else
{
/* Nothing to do */
}
/* */
if ((pHandle->bufferIndex > 0U) && (pHandle->bufferIndex <= pHandle->bufferTxTriggerBuff))
{
logValue16 = (uint16_t *)&pHandle->currentBuffer[pHandle->bufferIndex]; //cstat !MISRAC2012-Rule-11.3
for (i = 0U; i < pHandle->HFNumBuff; i++)
{
*logValue16 = *((uint16_t *) pHandle->dataPtrTableBuff[i]) ; //cstat !MISRAC2012-Rule-11.5
logValue16++;
pHandle->bufferIndex = pHandle->bufferIndex + 2U;
}
/* MFRateBuff=254 means we dump MF data once per buffer */
/* MFRateBuff=255 means we do not dump MF data */
if (pHandle->MFRateBuff < 254U)
{
if (pHandle->MFIndex == pHandle->MFRateBuff)
{
pHandle->MFIndex = 0U;
for (i = pHandle->HFNumBuff; i < (pHandle->MFNumBuff + pHandle->HFNumBuff); i++)
{
/* Dump MF data */
logValue = (uint32_t *)&pHandle->currentBuffer[pHandle->bufferIndex]; //cstat !MISRAC2012-Rule-11.3
*logValue = *((uint32_t *)pHandle->dataPtrTableBuff[i]); //cstat !MISRAC2012-Rule-11.5
#ifdef NOT_IMPLEMENTED /* Code not implemented. */
switch (pHandle->dataSizeTableBuff[i])
{
case 1:
{
logValue8 = (uint8_t *)&pHandle->currentBuffer[pHandle->bufferIndex];
*logValue8 = *((uint8_t *)pHandle->dataPtrTableBuff[i]);
break;
}
case 2:
{
logValue16 = (uint16_t *)&pHandle->currentBuffer[pHandle->bufferIndex];
*logValue16 = *((uint16_t *)pHandle->dataPtrTableBuff[i]);
break;
}
case 4:
{
logValue32 = (uint32_t *)&pHandle->currentBuffer[pHandle->bufferIndex];
*logValue32 = *((uint32_t *)pHandle->dataPtrTableBuff[i]);
break;
}
default:
break;
}
#endif
pHandle->bufferIndex = pHandle->bufferIndex+pHandle->dataSizeTableBuff[i];
}
}
else
{
pHandle->MFIndex ++;
}
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
if (pHandle->bufferIndex > pHandle->bufferTxTriggerBuff)
{
if (pHandle->MFRateBuff == 254U) /* MFRateBuff = 254 means we dump MF data once per buffer */
{
for (i = pHandle->HFNumBuff; i < (pHandle->MFNumBuff + pHandle->HFNumBuff); i++)
{
logValue = (uint32_t *)&pHandle->currentBuffer[pHandle->bufferIndex]; //cstat !MISRAC2012-Rule-11.3
*logValue = *((uint32_t *)pHandle->dataPtrTableBuff[i]); //cstat !MISRAC2012-Rule-11.5
pHandle->bufferIndex = pHandle->bufferIndex + pHandle->dataSizeTableBuff[i];
}
}
else
{
/* Nothing to do */
}
/* Buffer is ready to be send */
logValue16 = (uint16_t *)&pHandle->currentBuffer[pHandle->bufferIndex]; //cstat !MISRAC2012-Rule-11.3
*logValue16 = pHandle->MarkBuff; /* MarkBuff is actually 8 bits, but we add also 8 bits of the ASYNCID=0 after
the MARK. */
pHandle->pTransportLayer->fSendPacket(pHandle->pTransportLayer, pHandle->currentBuffer,
pHandle->bufferIndex + 2U, MCTL_ASYNC);
pHandle->bufferIndex = 0U;
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to log just waiting next call to MCPA_datalog */
pHandle->HFIndex++;
}
#ifdef NULL_PTR_CHECK_MCPA
}
#endif
}
/**
* @brief Sends asynchronous data to controller when the buffer is full
*
* @param *pHandle Pointer to the MCPA Handle
*/
void MCPA_flushDataLog (MCPA_Handle_t *pHandle)
{
#ifdef NULL_PTR_CHECK_MCPA
if (MC_NULL == pHandle)
{
/* Nothing to do */
}
else
{
#endif
uint32_t *logValue;
uint16_t *logValue16;
uint8_t i;
if (pHandle->bufferIndex > 0U)
{ /* If buffer is allocated, we must send it */
if (pHandle->MFRateBuff == 254U) /* In case of flush, we must respect the packet format to allow
proper decoding */
{
for (i = pHandle->HFNumBuff; i < (pHandle->MFNumBuff + pHandle->HFNumBuff); i++)
{
logValue = (uint32_t *)&pHandle->currentBuffer[pHandle->bufferIndex]; //cstat !MISRAC2012-Rule-11.3
*logValue = *((uint32_t *)pHandle->dataPtrTableBuff[i]); //cstat !MISRAC2012-Rule-11.5
pHandle->bufferIndex = pHandle->bufferIndex+pHandle->dataSizeTableBuff[i];
}
}
else
{
/* Nothing to do */
}
logValue16 = (uint16_t *)&pHandle->currentBuffer[pHandle->bufferIndex]; //cstat !MISRAC2012-Rule-11.3
*logValue16 = pHandle->MarkBuff; /* MarkBuff is actually 8 bits, but we add also 8 bits of the ASYNCID=0 after
the MARK */
pHandle->pTransportLayer->fSendPacket (pHandle->pTransportLayer, pHandle->currentBuffer,
pHandle->bufferIndex + 2U, MCTL_ASYNC);
pHandle->bufferIndex = 0U;
}
else
{
/* Nothing to do */
}
#ifdef NULL_PTR_CHECK_MCPA
}
#endif
}
/**
* @brief Stops the asynchronous communication
*
* @param *pHandle Pointer to the MCPA Handle
*/
void MCPA_stopDataLog(MCPA_Handle_t *pHandle)
{
uint16_t *logValue16;
pHandle->Mark = 0U;
if (pHandle->bufferIndex > 0U)
{ /* If buffer is allocated, we must send it */
logValue16 = (uint16_t *)&pHandle->currentBuffer[pHandle->bufferIndex]; //cstat !MISRAC2012-Rule-11.3
*logValue16 = pHandle->MarkBuff; /* MarkBuff is actually 8 bits, but we add also 8 bits of the ASYNCID=0 after
the MARK */
pHandle->pTransportLayer->fSendPacket (pHandle->pTransportLayer, pHandle->currentBuffer,
pHandle->bufferIndex + 2U, MCTL_ASYNC);
}
else
{
/* Nothing to do */
}
pHandle->bufferIndex = 0U;
pHandle->MarkBuff = 0U;
pHandle->HFIndex = 0U;
pHandle->HFRateBuff = 0U; /* We do not want to miss any sample at the restart */
}
/**
* @brief Stores the asynchronous configuration stating all the register to be continuously sent to controller
*
* @param *pHandle Pointer to the MCPA Handle
* @param *cfgdata Configuration of the Async communication
*/
uint8_t MCPA_cfgLog(MCPA_Handle_t *pHandle, uint8_t *cfgdata)
{
uint8_t result = MCP_CMD_OK;
#ifdef NULL_PTR_CHECK_MCPA
if (MC_NULL == pHandle)
{
result = MCP_CMD_NOK;
}
else
{
#endif
uint8_t i;
uint16_t logSize = 0U; /* Max size of a log per iteration (HF+MF) */
uint16_t newID, buffSize;
uint8_t *pCfgData = cfgdata;
buffSize = *((uint16_t *)pCfgData); //cstat !MISRAC2012-Rule-11.3
if (buffSize == 0U)
{
/* Switch Off condition */
MCPA_stopDataLog(pHandle);
}
else if (buffSize > pHandle->pTransportLayer->txAsyncMaxPayload)
{
result = MCP_ERROR_NO_TXASYNC_SPACE;
}
else
{
pHandle->HFRate = *((uint8_t *)&pCfgData[2]);
pHandle->HFNum = *((uint8_t *)&pCfgData[3]);
pHandle->MFRate = *((uint8_t *)&pCfgData[4]);
pHandle->MFNum = *((uint8_t *)&pCfgData[5]);
pCfgData = &pCfgData[6]; /* Start of the HF IDs */
if ((pHandle->HFNum + pHandle->MFNum) <= pHandle->nbrOfDataLog)
{
for (i = 0; i < (pHandle->HFNum + pHandle->MFNum); i++)
{
newID = *((uint16_t *)pCfgData); //cstat !MISRAC2012-Rule-11.3
(void)RI_GetPtrReg(newID, &pHandle->dataPtrTable[i]);
/* HF Data are fixed to 2 bytes */
pHandle->dataSizeTable[i] = (i < pHandle->HFNum ) ? 2U : RI_GetIDSize(newID);
pCfgData++; /* Point to the next UID */
pCfgData++;
logSize = logSize+pHandle->dataSizeTable[i];
}
/* Smallest packet must be able to contain logSize Markbyte AsyncID and TimeStamp */
if (buffSize < (logSize + 2U + 4U))
{
result = MCP_ERROR_NO_TXASYNC_SPACE;
}
else
{
pHandle->bufferTxTrigger = buffSize-logSize - 2U; /* 2 is required to add the last Mark byte and NUL
ASYNCID */
pHandle->Mark = *((uint8_t *)pCfgData);
if (0U == pHandle->Mark)
{ /* Switch Off condition */
MCPA_stopDataLog(pHandle);
}
else
{
/* Nothing to do */
}
}
}
else
{
result = MCP_ERROR_BAD_RAW_FORMAT;
}
}
#ifdef NULL_PTR_CHECK_MCPA
}
#endif
return (result);
}
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 12,669 | C | 31.909091 | 119 | 0.530271 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/pwm_common_sixstep.h | /**
******************************************************************************
* @file pwm_common_sixstep.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* six-step PWM component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pwm_curr_fdbk_6s
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef PWMNCOMMON_SIXSTEP_H
#define PWMNCOMMON_SIXSTEP_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
#define NB_CONVERSIONS 16u
#define S16_120_PHASE_SHIFT (int16_t)(65536/3)
#define S16_60_PHASE_SHIFT (int16_t)(65536/6)
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk
* @{
*/
/** @addtogroup pwm_curr_fdbk_6s
* @{
*/
/* Exported defines ------------------------------------------------------------*/
#define STEP_1 0U
#define STEP_2 1U
#define STEP_3 2U
#define STEP_4 3U
#define STEP_5 4U
#define STEP_6 5U
/* Exported defines ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @brief PWMC component handle type */
typedef struct PWMC_Handle PWMC_Handle_t; //cstat !MISRAC2012-Rule-2.4
/**
* @brief Pointer on callback functions used by PWMC components
*
* This type is needed because the actual functions to use can change at run-time.
*
* See the following items:
* - PWMC_Handle::pFctSwitchOffPwm
* - PWMC_Handle::pFctSwitchOnPwm
*
*
*/
typedef void (*PWMC_Generic_Cb_t)(PWMC_Handle_t *pHandle);
/**
* @brief Pointer on the function provided by the PMWC component instance to set low sides ON.
*
* This type is needed because the actual function to use can change at run-time
* (See PWMC_Handle::pFctTurnOnLowSides).
*
*/
typedef void (*PWMC_TurnOnLowSides_Cb_t)(PWMC_Handle_t *pHandle, const uint32_t ticks);
/**
* @brief Pointer on the function provided by the PMWC component instance to set the trigger point
* of the ADC.
*
* This type is needed because the actual function to use can change at run-time
* (See PWMC_Handle::pFctOCPSetReferenceVoltage).
*
*/
typedef void (*PWMC_SetADCTriggerChannel_Cb_t)(PWMC_Handle_t *pHandle, uint16_t hDACVref);
/**
* @brief Pointer on the function provided by the PMWC component instance to check if an over current
* condition has occured.
*
* This type is needed because the actual function to use can change at run-time
* (See PWMC_Handle::pFctIsOverCurrentOccurred).
*
*/
typedef uint16_t (*PWMC_OverCurr_Cb_t)(PWMC_Handle_t *pHandle);
/**
* @brief Pointer on the function provided by the PMWC component instance to check optional
* modulation features flag (fast demagnetization and quasi-synchronous rectification)
*
*/
typedef uint8_t (*PWMC_ModFlag_Cb_t)(PWMC_Handle_t *pHandle);
/**
* @brief This structure is used to handle the status change of optional modulation features
*
*/
typedef enum
{
NO_REQUEST,
ENABLE_FAST_DEMAG,
DISABLE_FAST_DEMAG,
ENABLE_QUASI_SYNCH,
DISABLE_QUASI_SYNCH
} PWMTableUpdate_t;
/**
* @brief This structure is used to handle the data of an instance of the PWM component
*
*/
struct PWMC_Handle
{
/** @{ */
PWMC_Generic_Cb_t
pFctSwitchOffPwm; /**< pointer on the function the component instance used to switch PWM off */
PWMC_Generic_Cb_t
pFctSwitchOnPwm; /**< pointer on the function the component instance used to switch PWM on */
PWMC_SetADCTriggerChannel_Cb_t /**< pointer on the function the component instance used to set the trigger point of the ADC */
pFctSetADCTriggerChannel;
PWMC_TurnOnLowSides_Cb_t
pFctTurnOnLowSides; /**< pointer on the function the component instance used to turn low sides on */
PWMC_OverCurr_Cb_t
pFctIsOverCurrentOccurred; /**< pointer on the fct the component instance used to return the over current status */
PWMC_ModFlag_Cb_t
pGetFastDemagFlag; /**< pointer on the fct the component instance used to return the fast demag status */
PWMC_ModFlag_Cb_t
pGetQuasiSynchFlag; /**< pointer on the fct the component instance used to return the quasi-Synch rectification status */
/** @} */
uint16_t CntPh; /**< PWM Duty cycle phase*/
uint16_t StartCntPh; /**< Start-up PWM Duty cycle phase*/
uint16_t ADCTriggerCnt; /**< Timer output trigger point used for ADC triggering */
uint16_t SWerror; /**< Contains status about SW error */
uint16_t PWMperiod; /**< PWM period expressed in timer clock cycles unit:
* @f$hPWMPeriod = TimerFreq_{CLK} / F_{PWM}@f$ */
uint16_t DTCompCnt; /**< Half of Dead time expressed
* in timer clock cycles unit:
* @f$hDTCompCnt = (DT_s \cdot TimerFreq_{CLK})/2@f$ */
uint8_t Motor; /**< Motor reference number */
int16_t AlignFlag; /*!< phase current 0 is reliable, 1 is bad */
uint8_t NextStep; /**< Step number to be applied the step number */
uint8_t Step; /**< Step number */
uint16_t DemagCounterThreshold;
int16_t hElAngle;
bool OverCurrentFlag; /*!< This flag is set when an overcurrent occurs.*/
bool OverVoltageFlag; /*!< This flag is set when an overvoltage occurs.*/
bool BrakeActionLock; /*!< This flag is set to avoid that brake action is
* interrupted.*/
bool driverProtectionFlag;
bool TurnOnLowSidesAction; /**< true if TurnOnLowSides action is active,
false otherwise. */
PWMTableUpdate_t ModUpdateReq; /**< Request flag of optional modulation features status */
};
/* Exported functions --------------------------------------------------------*/
/* Switches the PWM generation off, setting the outputs to inactive */
void PWMC_SwitchOffPWM(PWMC_Handle_t *pHandle);
/* Switches the PWM generation on */
void PWMC_SwitchOnPWM(PWMC_Handle_t *pHandle);
/* Set the trigger instant of the ADC for Bemf acquisition*/
void PWMC_SetADCTriggerChannel( PWMC_Handle_t * pHdl, uint16_t SamplingPoint );
/* Turns low sides on. This function is intended to be used for
* charging boot capacitors of driving section. It has to be called on each
* motor start-up when using high voltage drivers. */
void PWMC_TurnOnLowSides(PWMC_Handle_t * pHandle, uint32_t ticks);
/* Retrieves the status of the "TurnOnLowSides" action. */
bool PWMC_GetTurnOnLowSidesAction( PWMC_Handle_t * pHandle );
/* It is used to set the align motor flag.*/
void PWMC_SetAlignFlag(PWMC_Handle_t *pHandle, int16_t flag);
/* Sets the Callback that the PWMC component shall invoke to switch off PWM
* generation. */
void PWMC_RegisterSwitchOffPwmCallBack(PWMC_Generic_Cb_t pCallBack, PWMC_Handle_t *pHandle);
/* Sets the Callback that the PWMC component shall invoke to switch on PWM
* generation. */
void PWMC_RegisterSwitchonPwmCallBack(PWMC_Generic_Cb_t pCallBack, PWMC_Handle_t *pHandle);
/* Sets the Callback that the PWMC component shall invoke to turn on low sides. */
void PWMC_RegisterTurnOnLowSidesCallBack(PWMC_TurnOnLowSides_Cb_t pCallBack, PWMC_Handle_t *pHandle);
/* Sets the Callback that the PWMC component shall invoke to the over current status. */
void PWMC_RegisterIsOverCurrentOccurredCallBack(PWMC_OverCurr_Cb_t pCallBack, PWMC_Handle_t *pHandle);
/* It is used to clear the variable in CPWMC. */
void PWMC_Clear(PWMC_Handle_t *pHandle);
/* It forces the Fast Demag interval to the passed value */
void PWMC_ForceFastDemagTime(PWMC_Handle_t * pHdl, uint16_t constFastDemagTime );
/* It enables/disables the Fast Demag feature */
void PWMC_SetFastDemagState(PWMC_Handle_t * pHandle, uint8_t State );
/* It enables/disables the Qusi Synch feature */
void PWMC_SetQuasiSynchState(PWMC_Handle_t * pHandle, uint8_t State );
/* It returns the Fast Demag feature status */
uint8_t PWMC_GetFastDemagState(PWMC_Handle_t * pHandle );
/* It returns the Quasi Synch feature status */
uint8_t PWMC_GetQuasiSynchState(PWMC_Handle_t * pHandle );
/* It converts the motor electrical angle to the corresponding step in the six-step sequence */
uint8_t PWMC_ElAngleToStep( PWMC_Handle_t * pHandle );
/* Checks if an overcurrent occurred since last call. */
uint16_t PWMC_IsFaultOccurred(PWMC_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* PWMNCOMMON_SIXSTEP_H*/
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 9,824 | C | 37.378906 | 144 | 0.61024 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/pwmc_6pwm.h | /**
******************************************************************************
* @file pwmc_6pwm.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* pwmc_6pwm component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pwmc_6pwm
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PWMC_6PWM_H
#define __PWMC_6PWM_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "pwm_common_sixstep.h"
/**
* @addtogroup MCSDK
* @{
*/
/**
* @addtogroup pwm_curr_fdbk_6s
* @{
*/
/**
* @addtogroup pwmc_6pwm
* @{
*/
/* Exported constants --------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief R3_F0XX parameters definition
*/
typedef struct
{
TIM_TypeDef * TIMx; /*!< It contains the pointer to the timer
used for PWM generation. */
uint8_t RepetitionCounter; /*!< It expresses the number of PWM
periods to be elapsed before compare
registers are updated again. In
particular:
RepetitionCounter= (2* #PWM periods)-1*/
uint32_t OCPolarity; /*!< Current channel output polarity.*/
uint32_t OCNPolarity; /*!< Current complementary channel output polarity. */
} SixPwm_Params_t;
/**
* @brief Handle structure of the r1_f0xx_pwm_curr_fdbk Component
*/
typedef struct
{
PWMC_Handle_t _Super; /*!< Offset of current sensing network */
bool QuasiSynchDecay; /*!< This flag is set when the quasi-synchronous decay is activated.*/
bool FastDemag; /*!< This flag is set when the fast-demagmatization is activated.*/
bool Oversampling; /*!< This flag is set when the bemf oversampling feature is enabled.*/
bool FastDemagUpdated; /*!< This flag is set when fast-demagmatization is configuration is switched off.*/
uint32_t NegOCPolarity; /*!< Channel output opposite polarity.*/
uint32_t NegOCNPolarity; /*!< Complementary channel output opposite polarity. */
uint16_t DemagCounter;
SixPwm_Params_t const * pParams_str;
} PWMC_SixPwm_Handle_t;
/* Exported functions ------------------------------------------------------- */
/**
* It initializes TIMx and NVIC
*/
void SixPwm_Init( PWMC_SixPwm_Handle_t * pHandle );
/**
* It updates the stored duty cycle variable.
*/
void PWMC_SetPhaseVoltage( PWMC_Handle_t * pHandle, uint16_t DutyCycle );
/**
* It writes the duty cycle into shadow timer registers.
*/
void SixPwm_LoadNextStep( PWMC_SixPwm_Handle_t * pHandle, int16_t Direction );
/**
* It uploads the duty cycle into timer registers.
*/
bool SixPwm_ApplyNextStep( PWMC_SixPwm_Handle_t * pHandle );
/**
* It uploads the duty cycle into timer registers.
*/
bool SixPwm_IsFastDemagUpdated( PWMC_SixPwm_Handle_t * pHandle );
/**
* It resets the polarity of the timer PWM channel outputs to default
*/
void SixPwm_ResetOCPolarity( PWMC_SixPwm_Handle_t * pHandle );
/**
* It turns on low sides switches. This function is intended to be
* used for charging boot capacitors of driving section. It has to be
* called each motor start-up when using high voltage drivers
*/
void SixPwm_TurnOnLowSides( PWMC_Handle_t * pHdl, uint32_t ticks);
/**
* This function enables the PWM outputs
*/
void SixPwm_SwitchOnPWM( PWMC_Handle_t * pHdl );
/**
* It disables PWM generation on the proper Timer peripheral acting on
* MOE bit and reset the TIM status
*/
void SixPwm_SwitchOffPWM( PWMC_Handle_t * pHdl );
/**
* It sets the capcture compare of the timer channel used for ADC triggering
*/
void SixPwm_SetADCTriggerChannel( PWMC_Handle_t * pHdl, uint16_t SamplingPoint );
/**
* It is used to check if an overcurrent occurred since last call.
*/
uint16_t SixPwm_IsOverCurrentOccurred( PWMC_Handle_t * pHdl );
/**
* It contains the Break event interrupt
*/
void * SixPwm_BRK_IRQHandler( PWMC_SixPwm_Handle_t * pHandle );
/**
* It is used to return the fast demag flag.
*/
uint8_t SixPwm_FastDemagFlag( PWMC_Handle_t * pHdl );
/**
* It is used to return the quasi-synchronous rectification flag.
*/
uint8_t SixPwm_QuasiSynchFlag( PWMC_Handle_t * pHdl );
/**
* It increases the demagnetization counter in the update event.
*/
void SixPwm_UpdatePwmDemagCounter( PWMC_SixPwm_Handle_t * pHandle );
/**
* It disables the update event and the updated of the demagnetization counter.
*/
void SixPwm_DisablePwmDemagCounter( PWMC_SixPwm_Handle_t * pHandle );
/**
* @}
*/
/**
* @}
*/
/** @} */
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /*__PWMC_6PWM_H*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,635 | C | 29.301075 | 115 | 0.587578 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/mcpa.h | /**
******************************************************************************
* @file mcpa.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the Datalog
* of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef MCPA_H
#define MCPA_H
#include "mcptl.h"
extern uint32_t GLOBAL_TIMESTAMP;
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup MCP
* @{
*/
/**
* @brief MCP asynchronous parameters handle.
*
* Defined differently depending on the UART used.
*
*/
typedef struct
{
MCTL_Handle_t *pTransportLayer; /** Pointer to the transport layer structure, containing Performer capabilities. */
void ** dataPtrTable; /** Table of pointers to the value to be returned. */
void ** dataPtrTableBuff; /** Buffered version of dataPtrTable. */
uint8_t *dataSizeTable; /** Table containing the sizes of the values to be returned.*/
uint8_t *dataSizeTableBuff; /** Buffered version of dataSizeTable. */
uint8_t *currentBuffer; /** Current buffer allocated. */
uint16_t bufferIndex; /** Index of the position inside the bufer, a new buffer is allocated when bufferIndex = 0. */
uint16_t bufferTxTrigger; /** Threshold upon which data is dumped. */
uint16_t bufferTxTriggerBuff; /** Buffered version of bufferTxTrigger. */
#ifdef MCP_DEBUG_METRICS
uint16_t bufferMissed; /** Incremented each time a buffer is missed. Debug only. */
#endif
uint8_t nbrOfDataLog; /** Total number of values the performer is able to send at once. */
uint8_t HFIndex; /** Incremental value going from 0 to HFRateBuff, data is dump when HFRateBuff is reached. Incremented every HFT. */
uint8_t MFIndex; /** Incremental value going from 0 to MFRateBuff, data is dump when MFRateBuff is reached with an exception made for MFRateBuff == 254. Incremented every MFT.*/
uint8_t HFRate; /** Rate at which HF data is dumped. 0 means every HFT, 1 means 1 in 2. */
uint8_t HFRateBuff; /** Buffered version of HFRate. */
uint8_t HFNum; /** Number of HF values to be returned. */
uint8_t HFNumBuff; /** Buffered version of HFNum. */
uint8_t MFRate; /** Rate at which MF data is dumped. 254 means once per buffer, 255 means MF data is not dumped. */
uint8_t MFRateBuff; /** Buffered version of MFRate. */
uint8_t MFNum; /** Number of MF values to be returned. */
uint8_t MFNumBuff; /** Buffered version of MFNum. */
uint8_t Mark; /** Configuration of the ASYNC communication. */
uint8_t MarkBuff; /** Buffered version of Mark. */
} MCPA_Handle_t; /* MCP Async handle type */
void MCPA_dataLog(MCPA_Handle_t *pHandle);
uint8_t MCPA_cfgLog(MCPA_Handle_t *pHandle, uint8_t *cfgdata);
void MCPA_flushDataLog (MCPA_Handle_t *pHandle);
#endif /* MCPA_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 3,856 | C | 42.337078 | 198 | 0.57028 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/mcp.h | /**
******************************************************************************
* @file mcp.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides firmware functions that implement the Motor control protocol
* of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef MOTOR_CONTROL_PROTOCOL_H
#define MOTOR_CONTROL_PROTOCOL_H
#include "mcptl.h"
#define MCP_VERSION 0x1U
/* Action suppoted by the Motor control protocol*/
#define CMD_MASK 0xFFF8U
#define MCP_USER_CMD_MASK 0xFF00U
#define GET_MCP_VERSION 0x0
#define SET_DATA_ELEMENT 0x8
#define GET_DATA_ELEMENT 0x10
#define START_MOTOR 0x18
#define STOP_MOTOR 0x20
#define STOP_RAMP 0x28
#define START_STOP 0x30
#define FAULT_ACK 0x38
#define CPULOAD_CLEAR 0x40
#define IQDREF_CLEAR 0x48
#define PFC_ENABLE 0x50
#define PFC_DISABLE 0x58
#define PFC_FAULT_ACK 0x60
#define PROFILER_CMD 0x68
#define SW_RESET 0x78
#define MCP_USER_CMD 0x100U
/* MCP ERROR CODE */
#define MCP_CMD_OK 0x00U
#define MCP_CMD_NOK 0x01U
#define MCP_CMD_UNKNOWN 0x02U
#define MCP_DATAID_UNKNOWN 0x03U
#define MCP_ERROR_RO_REG 0x04U
#define MCP_ERROR_UNKNOWN_REG 0x05U
#define MCP_ERROR_STRING_FORMAT 0x06U
#define MCP_ERROR_BAD_DATA_TYPE 0x07U
#define MCP_ERROR_NO_TXSYNC_SPACE 0x08U
#define MCP_ERROR_NO_TXASYNC_SPACE 0x09U
#define MCP_ERROR_BAD_RAW_FORMAT 0x0AU
#define MCP_ERROR_WO_REG 0x0BU
#define MCP_ERROR_REGISTER_ACCESS 0x0CU
#define MCP_ERROR_CALLBACK_NOT_REGISTRED 0x0DU
#define MCP_HEADER_SIZE 2U
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup MCP
* @{
*/
/**
* @brief MCP User call back function pointer structure
*
* @param rxLength : Length of the transmitted buffer
* @param *rxBuffer : Buffer of data transmitted by the MCP controller device
* @param txSyncFreeSpace : space available in txBuffer to send data back to the MCP controller
* @param *txLength : Actual size of data that will be transmitted to the MCP controller must be < txSyncFreeSpace
* @param *txBuffer : Data that will be transmitted to the MCP controller in response to the user command
*
* @retval MCP status
*/
typedef uint8_t (*MCP_user_cb_t)(uint16_t rxLength, uint8_t *rxBuffer, int16_t txSyncFreeSpace, uint16_t *txLength,
uint8_t *txBuffer);
/**
* @brief Handle structure for MCP related components
*/
typedef struct
{
MCTL_Handle_t *pTransportLayer; /** Pointer to the MCTL structure */
uint8_t *rxBuffer; /** Buffer of data transmitted by the MCP controller device */
uint8_t *txBuffer; /** Data that will be transmitted to the MCP controller in response to the user command */
uint16_t rxLength; /** Length of the transmitted buffer */
uint16_t txLength; /** Actual size of data that will be transmitted to the MCP controller ; must be < txSyncFreeSpace*/
} MCP_Handle_t;
/* Parses the received packet and call the required function depending on the command sent by the controller device. */
void MCP_ReceivedPacket(MCP_Handle_t *pHandle);
/* Stores user's MCP functions to be acknowledged as MCP functions. */
uint8_t MCP_RegisterCallBack (uint8_t callBackID, MCP_user_cb_t fctCB);
#endif /* MOTOR_CONTROL_PROTOCOL_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 4,558 | C | 36.368852 | 138 | 0.570864 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/esc.h | /**
******************************************************************************
* @file esc.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* esc component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup esc
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef ESC_H
#define ESC_H
#define ESC_FILTER_DEEP 4
#define ESC_BEEP_FEATURE
typedef enum
{
ESC_ARMING = 0x00,
ESC_ARMED = 0x01,
ESC_POSITIVE_RUN = 0x02,
ESC_STOP = 0x03,
} ESC_sm_t;
typedef enum
{
ESC_NOERROR = 0,
ESC_NOSIGNAL = 1,
ESC_PWM_BELOW_MIN = 2
} ESC_State_t;
typedef enum
{
SM_BEEP_1 = 0x01,
SM_BEEP_2 = 0x02,
SM_BEEP_3 = 0x03,
SM_BEEP_4 = 0x04,
} ESC_Beep_State;
typedef struct
{
TIM_TypeDef * Command_TIM;
TIM_TypeDef * Motor_TIM;
uint32_t ARMING_TIME;
uint32_t PWM_TURNOFF_MAX;
uint32_t TURNOFF_TIME_MAX;
uint32_t Ton_max;
uint32_t Ton_min;
uint32_t Ton_arming;
uint32_t delta_Ton_max;
uint16_t speed_max_valueRPM;
uint16_t speed_min_valueRPM;
uint8_t motor;
} ESC_Params_t;
typedef struct
{
ESC_Params_t const * pESC_params;
uint32_t pwm_buffer[ESC_FILTER_DEEP]; /*!< PWM filter variable */
uint32_t index_filter;
uint32_t pwm_accumulator;
uint32_t arming_counter;
uint32_t pwm_timeout;
int32_t turnoff_delay;
volatile uint32_t Ton_value;
int16_t restart_delay;
#ifdef ESC_BEEP_FEATURE
uint16_t beep_stop_time;
uint16_t beep_counter;
ESC_Beep_State beep_state;
uint8_t beep_num;
bool phase_check_status;
bool start_check_flag;
#endif
ESC_sm_t sm_state;
uint8_t watchdog_counter;
uint8_t watchdog_counter_prev;
bool buffer_completed;
} ESC_Handle_t;
void esc_boot(ESC_Handle_t * pHandle);
void esc_pwm_stop(ESC_Handle_t * pHandle);
ESC_State_t esc_pwm_run(ESC_Handle_t * pHandle);
void esc_pwm_control(ESC_Handle_t * pHandle);
#endif /*ESC_H*/
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,660 | C | 25.088235 | 84 | 0.584211 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/speed_pos_fdbk.h | /**
******************************************************************************
* @file speed_pos_fdbk.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides all definitions and functions prototypes
* of the Speed & Position Feedback component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup SpeednPosFdbk
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef SPEEDNPOSFDBK_H
#define SPEEDNPOSFDBK_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
/* Already into mc_type.h */
/* #include "stdint.h" */
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup SpeednPosFdbk
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief SpeednPosFdbk handles definitions of mechanical and electrical speed, mechanical acceleration, mechanical
* and electrical angle and all constants and scale values for a reliable measure and
* computation in appropriated unit.
*/
typedef struct
{
uint8_t bSpeedErrorNumber; /*!< Number of time the average mechanical speed is not valid. */
uint8_t bElToMecRatio; /*!< Coefficient used to transform electrical to mechanical quantities and
viceversa. It usually coincides with motor pole pairs number. */
uint8_t SpeedUnit; /*!< The speed unit value is defined into mc_stm_types.h by
[SPEED_UNIT](measurement_units.md) in tenth of Hertz.*/
uint8_t bMaximumSpeedErrorsNumber; /*!< Maximum value of not valid speed measurements before an error is reported.*/
int16_t hElAngle; /*!< Estimated electrical angle reported by the implemented speed and position
method. */
int16_t hMecAngle; /*!< Instantaneous measure of rotor mechanical angle. */
int32_t wMecAngle; /*!< Mechanical angle frame based on coefficient #bElToMecRatio. */
int16_t hAvrMecSpeedUnit; /*!< Average mechanical speed expressed in the unit defined by
[SPEED_UNIT](measurement_units.md). */
int16_t hElSpeedDpp; /*!< Instantaneous electrical speed expressed in Digit Per control Period
([dpp](measurement_units.md)),
expresses the angular speed as the variation of the electrical angle. */
int16_t InstantaneousElSpeedDpp; /*!< Instantaneous computed electrical speed, expressed in
[dpp](measurement_units.md). */
int16_t hMecAccelUnitP; /*!< Average mechanical acceleration expressed in the unit defined by #SpeedUnit,
only reported with encoder implementation */
uint16_t hMaxReliableMecSpeedUnit; /*!< Maximum value of measured mechanical speed that is considered to be valid.
Expressed in the unit defined by [SPEED_UNIT](measurement_units.md). */
uint16_t hMinReliableMecSpeedUnit; /*!< Minimum value of measured mechanical speed that is considered to be valid.
Expressed in the unit defined by [SPEED_UNIT](measurement_units.md).*/
uint16_t hMaxReliableMecAccelUnitP; /*!< Maximum value of measured acceleration that is considered to be valid.
Constant value equal to 65535, expressed in the unit defined by
[SPEED_UNIT](measurement_units.md). */
uint16_t hMeasurementFrequency; /*!< Frequency at which the user will request a measurement of the rotor
electrical angle. Expressed in PWM_FREQ_SCALING * Hz. */
uint32_t DPPConvFactor; /*!< Conversion factor (65536/#PWM_FREQ_SCALING) used to convert measured speed
from the unit defined by [SPEED_UNIT](measurement_units.md) to
[dpp](measurement_units.md). */
} SpeednPosFdbk_Handle_t;
/**
* @brief input structure type definition for SPD_CalcAngle
*/
typedef struct
{
alphabeta_t Valfa_beta; /*!< Voltage Components in alfa beta reference frame */
alphabeta_t Ialfa_beta; /*!< Current Components in alfa beta reference frame */
uint16_t Vbus; /*!< Virtual Bus Voltage information */
} Observer_Inputs_t;
int16_t SPD_GetElAngle(const SpeednPosFdbk_Handle_t *pHandle);
int32_t SPD_GetMecAngle(const SpeednPosFdbk_Handle_t *pHandle);
int16_t SPD_GetAvrgMecSpeedUnit(const SpeednPosFdbk_Handle_t *pHandle);
int16_t SPD_GetElSpeedDpp(const SpeednPosFdbk_Handle_t *pHandle);
int16_t SPD_GetInstElSpeedDpp(const SpeednPosFdbk_Handle_t *pHandle);
bool SPD_Check(const SpeednPosFdbk_Handle_t *pHandle);
bool SPD_IsMecSpeedReliable(SpeednPosFdbk_Handle_t *pHandle, const int16_t *pMecSpeedUnit);
int16_t SPD_GetS16Speed(const SpeednPosFdbk_Handle_t *pHandle);
uint8_t SPD_GetElToMecRatio(const SpeednPosFdbk_Handle_t *pHandle);
void SPD_SetElToMecRatio(SpeednPosFdbk_Handle_t *pHandle, uint8_t bPP);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* SPEEDNPOSFDBK_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 6,196 | C | 45.246268 | 119 | 0.57876 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/profiler_fluxestim.h | /**
******************************************************************************
* @file profiler_fluxestim.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* profiler flux estimator component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*
*/
#ifndef _PROFILER_FLUXESTIM_H_
#define _PROFILER_FLUXESTIM_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "profiler_types.h"
/**
* @brief todo
*/
typedef enum _PROFILER_FLUXESTIM_State_e_
{
PROFILER_FLUXESTIM_STATE_Idle, /*!< @brief todo */
PROFILER_FLUXESTIM_STATE_RampUpCur, /*!< @brief todo */
PROFILER_FLUXESTIM_STATE_RampUpFreq, /*!< @brief todo */
PROFILER_FLUXESTIM_STATE_FluxRefAuto, /*!< @brief todo */
PROFILER_FLUXESTIM_STATE_RampDownFreq, /*!< @brief todo */
PROFILER_FLUXESTIM_STATE_RampDownCur, /*!< @brief todo */
PROFILER_FLUXESTIM_STATE_Complete, /*!< @brief todo */
PROFILER_FLUXESTIM_STATE_Error, /*!< @brief todo */
} PROFILER_FLUXESTIM_State_e;
/**
* @brief todo
*/
typedef enum _PROFILER_FLUXESTIM_Error_e_
{
PROFILER_FLUXESTIM_ERROR_None, /*!< @brief todo */
PROFILER_FLUXESTIM_ERROR_FluxNotValid, /*!< @brief todo */
} PROFILER_FLUXESTIM_Error_e;
/**
* @brief todo
*/
typedef struct _PROFILER_FLUXESTIM_Obj_
{
PROFILER_FLUXESTIM_State_e state; /*!< @brief todo */
PROFILER_FLUXESTIM_Error_e error; /*!< @brief todo */
/* inputs */
/* outputs */
fixp30_t flux_Wb; /*!< @brief todo */
/* configuration */
bool glue_dcac_fluxestim_on; /*!< @brief todo */
uint32_t measurement_counts; /*!< @brief todo */
float_t measurement_time_s; /*!< @brief todo */
fixp30_t CurToRamp_sf_pu; /*!< @brief todo */
fixp30_t FreqToRamp_sf_pu; /*!< @brief todo */
fixp30_t Id_ref_pu; /*!< @brief todo */
fixp30_t FluxEstFreq_pu; /*!< @brief todo */
fixp30_t freqEst_pu; /*!< @brief todo */
fixp30_t freqHSO_pu; /*!< @brief todo */
fixp30_t ramp_rate_A_pu_per_cycle; /*!< @brief todo */
fixp30_t ramp_rate_freq_pu_per_cycle; /*!< @brief todo */
fixp30_t fluxEstimPoleTs; /*!< @brief todo */
float_t background_rate_hz; /*!< @brief todo */
float_t fullScaleCurrent_A; /*!< @brief todo */
float_t fullScaleVoltage_V; /*!< @brief todo */
float_t fullScaleFreq_Hz; /*!< @brief todo */
float_t voltagefilterpole_rps; /*!< @brief todo */
/* FluxEstim state data */
uint32_t counter; /*!< @brief todo */
} PROFILER_FLUXESTIM_Obj;
/**
* @brief todo
*/
typedef PROFILER_FLUXESTIM_Obj* PROFILER_FLUXESTIM_Handle;
void PROFILER_FLUXESTIM_init(PROFILER_FLUXESTIM_Handle handle);
void PROFILER_FLUXESTIM_setParams(PROFILER_FLUXESTIM_Handle handle, PROFILER_Params* pParams);
void PROFILER_FLUXESTIM_run(PROFILER_FLUXESTIM_Handle handle, MOTOR_Handle motor);
void PROFILER_FLUXESTIM_runBackground(PROFILER_FLUXESTIM_Handle handle, MOTOR_Handle motor);
void PROFILER_FLUXESTIM_reset(PROFILER_FLUXESTIM_Handle handle, MOTOR_Handle motor);
/* Accessors */
float_t PROFILER_FLUXESTIM_getFluxEstFreq_Hz(const PROFILER_FLUXESTIM_Handle handle);
float_t PROFILER_FLUXESTIM_getMeasurementTime(PROFILER_FLUXESTIM_Handle handle);
void PROFILER_FLUXESTIM_setFluxEstFreq_Hz(PROFILER_FLUXESTIM_Handle handle, const float_t fluxEstFreq_Hz);
void PROFILER_FLUXESTIM_setMeasurementTime(PROFILER_FLUXESTIM_Handle handle, const float_t time_seconds);
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* _PROFILER_FLUXESTIM_H_ */
/* end of profiler_fluxestim.h */
| 4,544 | C | 35.071428 | 106 | 0.580106 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/digital_output.h | /**
******************************************************************************
* @file digital_output.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* digital output component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup DigitalOutput
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef DIGITALOUTPUT_H
#define DIGITALOUTPUT_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup DigitalOutput
* @{
*/
/* Exported constants --------------------------------------------------------*/
#define DOutputActiveHigh 1U /*!< Digital output active high flag */
#define DOutputActiveLow 0U /*!< Digital output active low flag */
/* Exported types ------------------------------------------------------------*/
/**
* @brief Digital output handler definition
*/
typedef struct
{
DOutputState_t OutputState; /*!< Indicates the state of the digital output. */
GPIO_TypeDef *hDOutputPort; /*!< GPIO output port. It must be equal to GPIOx x= A, B, ...*/
uint16_t hDOutputPin; /*!< GPIO output pin. It must be equal to GPIO_Pin_x x= 0, 1, ...*/
uint8_t bDOutputPolarity; /*!< GPIO output polarity. It must be equal to DOutputActiveHigh or
DOutputActiveLow */
} DOUT_handle_t;
/* Accordingly with selected polarity, it sets to active or inactive the
* digital output
*/
void DOUT_SetOutputState(DOUT_handle_t *pHandle, DOutputState_t State);
/* It returns the state of the digital output */
__weak DOutputState_t DOUT_GetOutputState(DOUT_handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* DIGITALOUTPUT_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,617 | C | 29.8 | 103 | 0.5235 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/pqd_motor_power_measurement.h | /**
******************************************************************************
* @file pqd_motor_power_measurement.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* PQD Motor Power Measurement component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pqd_motorpowermeasurement
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef PQD_MOTORPOWERMEASUREMENT_H
#define PQD_MOTORPOWERMEASUREMENT_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "bus_voltage_sensor.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pqd_motorpowermeasurement
* @{
*/
/**
* @brief Handle of a PQD Motor Power Measurement component
*
* PQD Motor Power Measurement components compute a value of the average electrical power
* flowing into a motor from the QD-frame @f$I_{qd}@f$ and @f$V_{qd}@f$ values.
*
*/
typedef struct
{
int16_t hAvrgElMotorPower; /**< @brief Average measured motor power expressed in s16 digit (s16A x s16V). */
float_t ConvFact; /**< @brief Factor used to convert s16 digit average motor power values into Watts.
Set to @f[\sqrt{3} \frac{V_{dd}}{R_{shunt} \times A_{op} \times 65536}@f]. */
pFOCVars_t pFOCVars; /**< @brief Pointer to FOC vars. */
BusVoltageSensor_Handle_t *pVBS; /**< @brief Bus voltage sensor component handle. */
} PQD_MotorPowMeas_Handle_t;
/* Updates the average electrical motor power measure with the latest values of the DQ currents and voltages */
void PQD_CalcElMotorPower(PQD_MotorPowMeas_Handle_t *pHandle);
/* Clears the the int16_t digit average motor power value stored in the handle */
void PQD_Clear(PQD_MotorPowMeas_Handle_t *pHandle);
/* Returns an average value of the measured motor power expressed in Watts */
float_t PQD_GetAvrgElMotorPowerW(const PQD_MotorPowMeas_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* PQD_MOTORPOWERMEASUREMENT_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,844 | C | 32.470588 | 118 | 0.583333 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/gap_gate_driver_ctrl.h | /**
******************************************************************************
* @file gap_gate_driver_ctrl.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* GAP component of the Motor Control SDK that provides support
* the STGAPxx galvanically isolated gate drivers family.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup GAP_GATE_DRIVER_CTRL
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GAP_GATE_DRIVER_CTR_H
#define __GAP_GATE_DRIVER_CTR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup GAP_GATE_DRIVER_CTRL
* @{
*/
#define GPIO_NoRemap_SPI ((uint32_t)(0))
#define MAX_DEVICES_NUMBER 7 /**< @brief Number of GAP used in the project. */
#define CFG1_REG_MASK (uint8_t)(0xFF) /**< @brief Data mask for CFG1 register. */
#define CFG2_REG_MASK (uint8_t)(0xFF) /**< @brief Data mask for CFG2 register. */
#define CFG3_REG_MASK (uint8_t)(0xFF) /**< @brief Data mask for CFG3 register. */
#define CFG4_REG_MASK (uint8_t)(0x3F) /**< @brief Data mask for CFG4 register. */
#define CFG5_REG_MASK (uint8_t)(0x0F) /**< @brief Data mask for CFG5 register. */
#define STATUS1_REG_MASK (uint8_t)(0xFF) /**< @brief Data mask for STATUS1 register. */
#define STATUS2_REG_MASK (uint8_t)(0x06) /**< @brief Data mask for STATUS2 register. */
#define STATUS3_REG_MASK (uint8_t)(0x1F) /**< @brief Data mask for STATUS3 register. */
#define TEST1_REG_MASK (uint8_t)(0x1F) /**< @brief Data mask for TEST1 register. */
#define DIAG1_REG_MASK (uint8_t)(0xFF) /**< @brief Data mask for DIAG1 register. */
#define DIAG2_REG_MASK (uint8_t)(0xFF) /**< @brief Data mask for DIAG2 register. */
#define GAP_ERROR_CLEAR (uint32_t)(0x00000000) /**< @brief No ERROR occured. */
#define GAP_ERROR_CODE_UVLOD (uint32_t)(0x00000001) /**< @brief Under Voltage Lockout ERROR occured. */
#define GAP_ERROR_CODE_OVLOD (uint32_t)(0x00000002) /**< @brief Over Voltage Lockout ERROR occured. */
#define GAP_ERROR_CODE_REGERRL (uint32_t)(0x00000004) /**< @brief Configuration procedure occured. */
#define GAP_ERROR_CODE_SPI_ERR (uint32_t)(0x00000008) /**< @brief SPI communication ERROR occured. */
#define GAP_ERROR_CODE_DT_ERR (uint32_t)(0x00000010) /**< @brief Deadtime ERROR occured. */
#define GAP_ERROR_CODE_CFG (uint32_t)(0x00000020) /**< @brief Configuration ERROR occured. */
#define GAP_ERROR_CODE_GATE (uint32_t)(0x00000100) /**< @brief GATE path ERROR occured. */
#define GAP_ERROR_CODE_ASC (uint32_t)(0x00000200) /**< @brief Asynchronous stop command ERROR occured. */
#define GAP_ERROR_CODE_REGERRR (uint32_t)(0x00000400) /**< @brief Configuration procedure occured. */
#define GAP_ERROR_CODE_TWN (uint32_t)(0x00010000) /**< @brief Temperature warning threshold ERROR occured. */
#define GAP_ERROR_CODE_TSD (uint32_t)(0x00020000) /**< @brief Temperature threshold ERROR occured. */
#define GAP_ERROR_CODE_UVLOL (uint32_t)(0x00040000) /**< @brief Under Voltage Lockout on VL ERROR occured. */
#define GAP_ERROR_CODE_UVLOH (uint32_t)(0x00080000) /**< @brief Under Voltage Lockout on VH ERROR occured. */
#define GAP_ERROR_CODE_SENSE (uint32_t)(0x00100000) /**< @brief sensor SENS voltage ERROR occured. */
#define GAP_ERROR_CODE_DESAT (uint32_t)(0x00200000) /**< @brief sensor Desaturation protection ERROR occured. */
#define GAP_ERROR_CODE_OVLOL (uint32_t)(0x00400000) /**< @brief Over Voltage Lockout on VL ERROR occured. */
#define GAP_ERROR_CODE_OVLOH (uint32_t)(0x00800000) /**< @brief Over Voltage Lockout on VH ERROR occured. */
#define GAP_ERROR_CODE_SPI_CRC (uint32_t)(0x40000000) /**< @brief CRC SPI ERROR occured. */
#define GAP_ERROR_CODE_DEVICES_NOT_PROGRAMMABLE (uint32_t)(0x80000000) /**< @brief Device access ERROR occured. */
#define GAP_CFG1_CRC_SPI (uint8_t)(0x80) /**< @brief CFG1 register: SPI communication protocol CRC enable. */
#define GAP_CFG1_UVLOD (uint8_t)(0x40) /**< @brief CFG1 register: UVLO protection on VDD supply voltage enable. */
#define GAP_CFG1_SD_FLAG (uint8_t)(0x20) /**< @brief CFG1 register: SD pin functionality. */
#define GAP_CFG1_DIAG_EN (uint8_t)(0x10) /**< @brief CFG1 register: IN-/DIAG2 pin functionality. */
#define GAP_CFG1_DT_DISABLE (uint8_t)(0x00) /**< @brief CFG1 register: No deadtime value. */
#define GAP_CFG1_DT_250NS (uint8_t)(0x04) /**< @brief CFG1 register: 250ns deadtime value. */
#define GAP_CFG1_DT_800NS (uint8_t)(0x08) /**< @brief CFG1 register: 800ns deadtime value. */
#define GAP_CFG1_DT_1200NS (uint8_t)(0x0C) /**< @brief CFG1 register: 1200ns deadtime value. */
#define GAP_CFG1_INFILTER_DISABLE (uint8_t)(0x00) /**< @brief CFG1 register: No Input deglitch time value. */
#define GAP_CFG1_INFILTER_210NS (uint8_t)(0x01) /**< @brief CFG1 register: 210ns Input deglitch time value. */
#define GAP_CFG1_INFILTER_560NS (uint8_t)(0x02) /**< @brief CFG1 register: 560ns Input deglitch time value. */
#define GAP_CFG1_INFILTER_70NS (uint8_t)(0x03) /**< @brief CFG1 register: 70ns Input deglitch time value. */
#define GAP_CFG2_SENSETH_100MV (uint8_t)(0x00) /**< @brief CFG2 register: 100mV SENSE comparator threshold value. */
#define GAP_CFG2_SENSETH_125MV (uint8_t)(0x20) /**< @brief CFG2 register: 125mV SENSE comparator threshold value. */
#define GAP_CFG2_SENSETH_150MV (uint8_t)(0x40) /**< @brief CFG2 register: 150mV SENSE comparator threshold value. */
#define GAP_CFG2_SENSETH_175MV (uint8_t)(0x60) /**< @brief CFG2 register: 175mV SENSE comparator threshold value. */
#define GAP_CFG2_SENSETH_200MV (uint8_t)(0x80) /**< @brief CFG2 register: 200mV SENSE comparator threshold value. */
#define GAP_CFG2_SENSETH_250MV (uint8_t)(0xA0) /**< @brief CFG2 register: 250mV SENSE comparator threshold value. */
#define GAP_CFG2_SENSETH_300MV (uint8_t)(0xC0) /**< @brief CFG2 register: 300mV SENSE comparator threshold value. */
#define GAP_CFG2_SENSETH_400MV (uint8_t)(0xE0) /**< @brief CFG2 register: 400mV SENSE comparator threshold value. */
#define GAP_CFG2_DESATCURR_250UA (uint8_t)(0x00) /**< @brief CFG2 register: 250uA current value sourced by the DESAT. */
#define GAP_CFG2_DESATCURR_500UA (uint8_t)(0x08) /**< @brief CFG2 register: 500uA current value sourced by the DESAT. */
#define GAP_CFG2_DESATCURR_750UA (uint8_t)(0x10) /**< @brief CFG2 register: 750uA current value sourced by the DESAT. */
#define GAP_CFG2_DESATCURR_1000UA (uint8_t)(0x18) /**< @brief CFG2 register: 1000uA current value sourced by the DESAT. */
#define GAP_CFG2_DESATTH_3V (uint8_t)(0x00) /**< @brief CFG2 register: 3V DESAT comparator threshold value. */
#define GAP_CFG2_DESATTH_4V (uint8_t)(0x01) /**< @brief CFG2 register: 4V DESAT comparator threshold value. */
#define GAP_CFG2_DESATTH_5V (uint8_t)(0x02) /**< @brief CFG2 register: 5V DESAT comparator threshold value. */
#define GAP_CFG2_DESATTH_6V (uint8_t)(0x03) /**< @brief CFG2 register: 6V DESAT comparator threshold value. */
#define GAP_CFG2_DESATTH_7V (uint8_t)(0x04) /**< @brief CFG2 register: 7V DESAT comparator threshold value. */
#define GAP_CFG2_DESATTH_8V (uint8_t)(0x05) /**< @brief CFG2 register: 8V DESAT comparator threshold value. */
#define GAP_CFG2_DESATTH_9V (uint8_t)(0x06) /**< @brief CFG2 register: 9V DESAT comparator threshold value. */
#define GAP_CFG2_DESATTH_10V (uint8_t)(0x07) /**< @brief CFG2 register: 10V DESAT comparator threshold value. */
#define GAP_CFG3_2LTOTH_7_0V (uint8_t)(0x00) /**< @brief CFG3 register: 7V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_7_5V (uint8_t)(0x10) /**< @brief CFG3 register: 7.5V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_8_0V (uint8_t)(0x20) /**< @brief CFG3 register: 8V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_8_5V (uint8_t)(0x30) /**< @brief CFG3 register: 8.5V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_9_0V (uint8_t)(0x40) /**< @brief CFG3 register: 9V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_9_5V (uint8_t)(0x50) /**< @brief CFG3 register: 9.5V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_10_0V (uint8_t)(0x60) /**< @brief CFG3 register: 10V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_10_5V (uint8_t)(0x70) /**< @brief CFG3 register: 10.5V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_11_0V (uint8_t)(0x80) /**< @brief CFG3 register: 11V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_11_5V (uint8_t)(0x90) /**< @brief CFG3 register: 11.5V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_12_0V (uint8_t)(0xA0) /**< @brief CFG3 register: 12V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_12_5V (uint8_t)(0xB0) /**< @brief CFG3 register: 12.5V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_13_0V (uint8_t)(0xC0) /**< @brief CFG3 register: 13V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_13_5V (uint8_t)(0xD0) /**< @brief CFG3 register: 13.5V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_14_0V (uint8_t)(0xE0) /**< @brief CFG3 register: 14V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTH_14_5V (uint8_t)(0xF0) /**< @brief CFG3 register: 14.5V threshold voltage value which is actively forced during the 2-level turnoff sequence. */
#define GAP_CFG3_2LTOTIME_DISABLE (uint8_t)(0x00) /**< @brief CFG3 register: No duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_0_75_US (uint8_t)(0x01) /**< @brief CFG3 register: 0.75us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_1_00_US (uint8_t)(0x02) /**< @brief CFG3 register: 1us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_1_50_US (uint8_t)(0x03) /**< @brief CFG3 register: 1.5us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_2_00_US (uint8_t)(0x04) /**< @brief CFG3 register: 2us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_2_50_US (uint8_t)(0x05) /**< @brief CFG3 register: 2.5us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_3_00_US (uint8_t)(0x06) /**< @brief CFG3 register: 3us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_3_50_US (uint8_t)(0x07) /**< @brief CFG3 register: 3.5us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_3_75_US (uint8_t)(0x08) /**< @brief CFG3 register: 3.75us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_4_00_US (uint8_t)(0x09) /**< @brief CFG3 register: 4us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_4_25_US (uint8_t)(0x0A) /**< @brief CFG3 register: 4.25us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_4_50_US (uint8_t)(0x0B) /**< @brief CFG3 register: 4.5us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_4_75_US (uint8_t)(0x0C) /**< @brief CFG3 register: 4.75us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_5_00_US (uint8_t)(0x0D) /**< @brief CFG3 register: 5us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_5_25_US (uint8_t)(0x0E) /**< @brief CFG3 register: 5.25us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG3_2LTOTIME_5_50_US (uint8_t)(0x0F) /**< @brief CFG3 register: 5.5us duration time value of the 2-level turn-off sequence. */
#define GAP_CFG4_OVLO (uint8_t)(0x20) /**< @brief CFG4 register: enables the OVLO protection on the VH and VL power supply. */
#define GAP_CFG4_UVLOLATCH (uint8_t)(0x10) /**< @brief CFG4 register: sets if the UVLO is latched or not. */
#define GAP_CFG4_UVLOTH_VH_DISABLE (uint8_t)(0x00) /**< @brief CFG4 register: disables the UVLO threshold on the positive power supply. */
#define GAP_CFG4_UVLOTH_VH_10V (uint8_t)(0x01) /**< @brief CFG4 register: sets the VH positive supply voltage UVLO threshold to 10v on the positive power supply. */
#define GAP_CFG4_UVLOTH_VH_12V (uint8_t)(0x02) /**< @brief CFG4 register: sets the VH positive supply voltage UVLO threshold to 12v on the positive power supply. */
#define GAP_CFG4_UVLOTH_VH_14V (uint8_t)(0x03) /**< @brief CFG4 register: sets the VH positive supply voltage UVLO threshold to 140v on the positive power supply. */
#define GAP_CFG4_UVLOTH_VL_DISABLE (uint8_t)(0x00) /**< @brief CFG4 register: disables the UVLO threshold on the negative power supply. */
#define GAP_CFG4_UVLOTH_VL_N3V (uint8_t)(0x04) /**< @brief CFG4 register: sets the VL negative supply voltage UVLO threshold to -3v on the negative power supply. */
#define GAP_CFG4_UVLOTH_VL_N5V (uint8_t)(0x08) /**< @brief CFG4 register: sets the VL negative supply voltage UVLO threshold to -5v on the negative power supply. */
#define GAP_CFG4_UVLOTH_VL_N7V (uint8_t)(0x0C) /**< @brief CFG4 register: sets the VL negative supply voltage UVLO threshold to -7v on the negative power supply. */
#define GAP_CFG5_2LTO_ON_FAULT (uint8_t)(0x08) /**< @brief CFG5 register: 2LTO active only after a fault event. */
#define GAP_CFG5_CLAMP_EN (uint8_t)(0x04) /**< @brief CFG5 register: enables enable the Miller clamp feature. */
#define GAP_CFG5_DESAT_EN (uint8_t)(0x02) /**< @brief CFG5 register: enables the DESAT desaturation protection function comparator. */
#define GAP_CFG5_SENSE_EN (uint8_t)(0x01) /**< @brief CFG5 register: enables the sense overcurrent function comparator. */
#define GAP_STATUS1_OVLOH (uint8_t)(0x80) /**< @brief STATUS1 register: VH overvoltage flag is forced high when VH is over OVVHoff threshold. */
#define GAP_STATUS1_OVLOL (uint8_t)(0x40) /**< @brief STATUS1 register: VL overvoltage flag is forced high when VL is over OVVLoff threshold. */
#define GAP_STATUS1_DESAT (uint8_t)(0x20) /**< @brief STATUS1 register: Desaturation flag is forced high when DESAT pin voltage reach VDESATth threshold. */
#define GAP_STATUS1_SENSE (uint8_t)(0x10) /**< @brief STATUS1 register: Sense flag is forced high when SENSE pin voltage reach VSENSEth threshold. */
#define GAP_STATUS1_UVLOH (uint8_t)(0x08) /**< @brief STATUS1 register: VH undervoltage flag is forced high when VH is below VHoff threshold. */
#define GAP_STATUS1_UVLOL (uint8_t)(0x04) /**< @brief STATUS1 register: VL undervoltage flag is forced high when VL is over VLoff threshold. */
#define GAP_STATUS1_TSD (uint8_t)(0x02) /**< @brief STATUS1 register: Thermal shutdown protection flag is forced high when overtemperature shutdown threshold is reached.*/
#define GAP_STATUS1_TWN (uint8_t)(0x01) /**< @brief STATUS1 register: Thermal warning flag is forced high when overtemperature shutdown threshold is reached. */
#define GAP_STATUS2_REGERRR (uint8_t)(0x02) /**< @brief STATUS2 register: Register or communication error on isolated side is forced high when:
1 Programming procedure is not correctly performed.
2 Isolated interface communication fails.
3 An unexpected register value change occurs in one of the remote registers.
It is also latched at power-up/reset and from Sleep state. */
#define GAP_STATUS2_ASC (uint8_t)(0x01) /**< @brief STATUS2 register: ASC pin status. When ASC pin is high the flag reports '1', otherwise is '0'.. */
#define GAP_STATUS3_CFG (uint8_t)(0x20) /**< @brief STATUS3 register: CFG error flag. */
#define GAP_STATUS3_DT_ERR (uint8_t)(0x10) /**< @brief STATUS3 register: Deadtime error flag is forced high when a violation of internal DT is detected. */
#define GAP_STATUS3_SPI_ERR (uint8_t)(0x08) /**< @brief STATUS3 register: SPI communication error flag is forced high when the SPI communication fails cause:
1 Wrong CRC check.
2 Wrong number of CK rising edges.
3 Attempt to execute a not-allowed command.
4 Attempt to read, write or reset at a not available address. */
#define GAP_STATUS3_REGERRL (uint8_t)(0x04) /**< @brief STATUS3 register: Register or communication error on low voltage side is forced high when: -
1 Programming procedure is not correctly performed.
2 Isolated interface communication fails.
3 An unexpected register value change occurs in one of the remote registers.
* It is latched at power-up/reset also. */
#define GAP_STATUS3_OVLOD (uint8_t)(0x02) /**< @brief STATUS3 register: VDD overvoltage flag is forced high when VDD is over OVVDDoff threshold. */
#define GAP_STATUS3_UVLOD (uint8_t)(0x01) /**< @brief STATUS3 register: VDD undervoltage flag is forced high when VDD is below VDDon threshold.
It is latched at power-up/reset also. */
#define GAP_TEST1_GOFFCHK (uint8_t)(0x10) /**< @brief TEST1 register: enables the GOFF to gate path check mode */
#define GAP_TEST1_GONCHK (uint8_t)(0x08) /**< @brief TEST1 register: enables the GON to gate path check mode */
#define GAP_TEST1_DESCHK (uint8_t)(0x04) /**< @brief TEST1 register: enables the DESAT comparator check mode */
#define GAP_TEST1_SNSCHK (uint8_t)(0x02) /**< @brief TEST1 register: enables the SENSE comparator check mode */
#define GAP_TEST1_RCHK (uint8_t)(0x01) /**< @brief TEST1 register: enables the SENSE resistor check mode */
#define GAP_DIAG_SPI_REGERR (uint8_t)(0x80) /**< @brief DIAG register: enables the DIAGxCFG event SPI communication error or register failure */
#define GAP_DIAG_UVLOD_OVLOD (uint8_t)(0x40) /**< @brief DIAG register: enables the DIAGxCFG event VDD power supply failure */
#define GAP_DIAG_UVLOH_UVLOL (uint8_t)(0x20) /**< @brief DIAG register: enables the DIAGxCFG event Undervoltage failure */
#define GAP_DIAG_OVLOH_OVLOL (uint8_t)(0x10) /**< @brief DIAG register: enables the DIAGxCFG event Overvoltage failure */
#define GAP_DIAG_DESAT_SENSE (uint8_t)(0x08) /**< @brief DIAG register: enables the DIAGxCFG event SDesaturation and sense detection */
#define GAP_DIAG_ASC_DT_ERR (uint8_t)(0x04) /**< @brief DIAG register: enables the DIAGxCFG event ASC feedback */
#define GAP_DIAG_TSD (uint8_t)(0x02) /**< @brief DIAG register: enables the DIAGxCFG event Thermal shutdown */
#define GAP_DIAG_TWN (uint8_t)(0x01) /**< @brief DIAG register: enables the DIAGxCFG event Thermal warning */
#define GAP_DIAG_NONE (uint8_t)(0x00) /**< @brief DIAG register: No DIAGxCFG event. */
/** Define the GAP register enum.
*
*/
typedef enum
{
CFG1 = 0x0C, /*!< Address of CFG1 register (low voltage side). */
CFG2 = 0x1D, /*!< Address of CFG2 register (isolated side). */
CFG3 = 0x1E, /*!< Address of CFG3 register (isolated side). */
CFG4 = 0x1F, /*!< Address of CFG4 register (isolated side). */
CFG5 = 0x19, /*!< Address of CFG5 register (isolated side). */
STATUS1 = 0x02, /*!< Address of STATUS1 register (low voltage side).
The STATUS1 is a read only register that reports some device failure flags. */
STATUS2 = 0x01, /*!< Address of STATUS2 register (low voltage side). */
STATUS3 = 0x0A, /*!< Address of STATUS3 register (low voltage side). */
TEST1 = 0x11, /*!< Address of TEST1 register (isolated side). */
DIAG1 = 0x05, /*!< Address of DIAG1CFG registers (low voltage side). */
DIAG2 = 0x06 /*!< Address of DIAG2CFG registers (low voltage side). */
} GAP_Registers_Handle_t;
/** Define test modes
*
*/
typedef enum
{
SENSE_RESISTOR_CHK, /*!< Security check to verify the connection between the device and the sense shunt
resistor and to verify the optional sense resistor filter network is not open. */
SENSE_COMPARATOR_CHK, /*!< Security check to verify the functionality of the sense comparator. */
GON_CHK, /*!< Security check to verify the path integrity including the driver's GON output,
the GON (turn-on) gate resistor, the power switch gate and the CLAMP pin. */
GOFF_CHK, /*!< Security check to verify the path integrity including the driver's GOFF output,
the GOFF (turn-off) gate resistor, the power switch gate and the CLAMP pin. */
DESAT_CHK /*!< Security check to verify the functionality of the de-saturation. */
} GAP_TestMode_t;
/**
* @brief GAP class register bank definition
*
* This structure contains configuration value for register bank of the GAP driver.
*
*/
typedef struct
{
uint8_t CFG1; /*!< Configuration value for CFG1 register. */
uint8_t CFG2; /*!< Configuration value for CFG2 register. */
uint8_t CFG3; /*!< Configuration value for CFG3 register. */
uint8_t CFG4; /*!< Configuration value for CFG4 register. */
uint8_t CFG5; /*!< Configuration value for CFG5 register. */
uint8_t DIAG1; /*!< Configuration value for DIAG1 register. */
uint8_t DIAG2; /*!< Configuration value for DIAG2 register. */
} GAP_DeviceParams_Handle_t;
/**
* @brief Handle of the GAP component
*
* This structure holds all the parameters needed to access and manage GAP drivers.
*/
typedef struct
{
uint8_t DeviceNum; /*!< Number of GAP used in the daisy chain. */
GAP_DeviceParams_Handle_t DeviceParams[MAX_DEVICES_NUMBER]; /*!< Device parameters pointers */
/* SPI related parameters. */
SPI_TypeDef *SPIx;
GPIO_TypeDef *NCSPort; /*!< GPIO port used by NCS. It must be equal to GPIOx x= A, B, ...*/
uint16_t NCSPin; /*!< GPIO pin used by NCS. It must be equal to GPIO_Pin_x x= 0, 1, ...*/
GPIO_TypeDef *NSDPort; /*!< GPIO port used by NSD. It must be equal to GPIOx x= A, B, ...*/
uint16_t NSDPin; /*!< GPIO pin used by NSD. It must be equal to GPIO_Pin_x x= 0, 1, ...*/
uint32_t GAP_ErrorsNow[MAX_DEVICES_NUMBER]; /*!< Bitfield with extra error codes that is currently active.
The error code available are listed here (TBF).*/
uint32_t GAP_ErrorsOccurred[MAX_DEVICES_NUMBER]; /*!< Bitfield with extra error codes that occurs and is over.
The error code available are listed here (TBF).*/
} GAP_Handle_t;
/* Exported functions ------------------------------------------------------- */
bool GAP_CheckErrors(GAP_Handle_t *pHandle, uint32_t *error_now, uint32_t *error_occurred);
void GAP_FaultAck(GAP_Handle_t *pHandle);
bool GAP_Configuration(GAP_Handle_t *pHandle);
bool GAP_IsDevicesProgrammed(GAP_Handle_t *pHandle);
bool GAP_DevicesConfiguration(GAP_Handle_t *pHandle);
uint16_t GAP_CRCCalculate(uint8_t data, uint8_t crc_initial_value);
bool GAP_CRCCheck(uint8_t *out, uint16_t data_in);
void wait(uint16_t count);
uint8_t GAP_RegMask(GAP_Registers_Handle_t reg);
bool GAP_ReadRegs(GAP_Handle_t *pHandle, uint8_t *pDataRead, GAP_Registers_Handle_t reg);
void GAP_StartConfig(GAP_Handle_t *pHandle);
void GAP_StopConfig(GAP_Handle_t *pHandle);
bool GAP_WriteRegs(GAP_Handle_t *pHandle, uint8_t *pDataWrite, GAP_Registers_Handle_t reg);
void GAP_GlobalReset(GAP_Handle_t *pHandle);
bool GAP_ResetStatus(GAP_Handle_t *pHandle, GAP_Registers_Handle_t reg);
bool GAP_Test(GAP_Handle_t *pHandle, GAP_TestMode_t testMode);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* __GAP_GATE_DRIVER_CTR_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 29,376 | C | 91.380503 | 199 | 0.585103 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/r_divider_bus_voltage_sensor.h | /**
******************************************************************************
* @file r_divider_bus_voltage_sensor.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* Resistor Divider Bus Voltage Sensor component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup RDividerBusVoltageSensor
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef RDIVIDER_BUSVOLTAGESENSOR_H
#define RDIVIDER_BUSVOLTAGESENSOR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "regular_conversion_manager.h"
#include "bus_voltage_sensor.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup BusVoltageSensor
* @{
*/
/** @addtogroup RDividerBusVoltageSensor
* @{
*/
/**
* @brief Rdivider class parameters definition
*/
typedef struct
{
BusVoltageSensor_Handle_t _Super; /*!< Bus voltage sensor component handle. */
uint16_t LowPassFilterBW; /*!< Use this number to configure the Vbus
first order software filter bandwidth.
hLowPassFilterBW = VBS_CalcBusReading
call rate [Hz]/ FilterBandwidth[Hz] */
uint16_t OverVoltageThreshold; /*!< It represents the over voltage protection
intervention threshold. To be expressed
in digital value through formula:
hOverVoltageThreshold (digital value) =
Over Voltage Threshold (V) * 65536
/ hConversionFactor */
uint16_t OverVoltageThresholdLow; /*!< It represents the over voltage protection
intervention threshold low level for hysteresis
feature when "switch on brake resistor" is used.
To be expressed in digital value through formula:
hOverVoltageThresholdLow (digital value) =
Over Voltage Threshold Low(V) * 65536
/ hConversionFactor */
bool OverVoltageHysteresisUpDir; /*!< "Switch on brake resistor" hysteresis direction. */
uint16_t UnderVoltageThreshold; /*!< It represents the under voltage protection
intervention threshold. To be expressed
in digital value through formula:
hUnderVoltageThreshold (digital value)=
Under Voltage Threshold (V) * 65536
/ hConversionFactor */
uint16_t *aBuffer; /*!< Buffer used to compute average value.*/
uint8_t elem; /*!< Number of stored elements in the average buffer.*/
uint8_t index; /*!< Index of last stored element in the average buffer.*/
uint8_t convHandle; /*!< handle to the regular conversion */
} RDivider_Handle_t;
/* Exported functions ------------------------------------------------------- */
void RVBS_Init(RDivider_Handle_t *pHandle);
void RVBS_Clear(RDivider_Handle_t *pHandle);
uint16_t RVBS_CalcAvVbusFilt(RDivider_Handle_t *pHandle);
uint16_t RVBS_CalcAvVbus(RDivider_Handle_t *pHandle, uint16_t rawValue);
uint16_t RVBS_CheckFaultState(RDivider_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
/** @} */
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* RDIVIDER_BUSVOLTAGESENSOR_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 4,733 | C | 42.431192 | 103 | 0.484893 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/profiler_handle.h | /**
******************************************************************************
* @file profiler_handle.h
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* profiler_handle.h */
#ifndef _PROFILER_HANDLE_H_
#define _PROFILER_HANDLE_H_
typedef struct _PROFILER_Obj_* PROFILER_Handle;
#endif /* _PROFILER_HANDLE_H_ */
/* end of profiler_handle.h */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 1,075 | C | 33.709676 | 94 | 0.488372 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/mp_hall_tuning.h | /**
******************************************************************************
* @file mp_hall_tuning.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for
* for the Hall effect position sensors Tuning component
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MP_HALL_TUNING_H
#define __MP_HALL_TUNING_H
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
#include "pwm_curr_fdbk.h"
#include "ramp_ext_mngr.h"
#include "bus_voltage_sensor.h"
#include "speed_pos_fdbk.h"
#include "virtual_speed_sensor.h"
#include "open_loop.h"
#include "circle_limitation.h"
#include "pid_regulator.h"
#include "revup_ctrl.h"
#include "speed_torq_ctrl.h"
#include "r_divider_bus_voltage_sensor.h"
#include "sto_pll_speed_pos_fdbk.h"
#include "mp_one_touch_tuning.h"
#include "hall_speed_pos_fdbk.h"
#include "pmsm_motor_parameters.h"
#include "ramp_ext_mngr.h"
#include "mc_math.h"
#include "mc_interface.h"
/* Hall Sensors Pins Def------------------------------------------------------*/
#define NO_COMPLEMENT 0x0
#define H1 0x1
#define H2 0x2
#define H3 0x4
#define HALL_FLAG_TIMEOUT 1000
#define WAIT_RAMP_TIMEOUT 10000
/** @addtogroup STM32_PMSM_MC_Library
* @{
*/
/** @addtogroup SelfComCtrl
* @{
*/
/** @defgroup SelfComCtrl_class_private_types SelfComCtrl class private types
* @{
*/
/**
* @brief HT_State_t enum type definition, it lists all the possible HT
machine states.
*/
typedef enum
{
HT_IDLE, /* 0 */
HT_PRIOR_CHECK, /* 1 */
HT_START_RAMP, /* 2 */
HT_WAIT_RAMP, /* 3 */
HT_WAIT_HALL_FLAG, /* 4 */
HT_CHECK_HALL_RELIABILITY, /* 5 */
HT_WAIT_USER_DIRECTION_CHOICE, /* 6 */
HT_ERROR_RELIABILITY, /* 7 */
HT_ERROR_PINS_READING, /* 8 */
HT_WARNING_PHASES_NEED_SWAP, /* 9 */
HT_DETECTING_CONF, /* 10 */
HT_DETERMINE_PTC, /* 11 */
HT_DETECTING_SWAP, /* 12 */
HT_WAIT_STABILIZATION, /* 13 */
HT_DETECTING_EDGE,
HT_GET_ANGLE_EDGE,
HT_CALC_EDGE_ANGLE,
HT_EDGE_COMPUTATION,
HT_RST, /* 16 */
HT_RESULT /* 17 */
} HT_State_t;
/**
* @brief HT_State_t enum type definition, it lists all the possible HT_SHIF_EDGE
machine states.
*/
typedef enum
{
SHIFT_EDGE_IDLE, /* 0 */
SHIFT_EDGE_1, /* 1 */
SHIFT_EDGE_2, /* 2 */
SHIFT_EDGE_3, /* 3 */
SHIFT_EDGE_4, /* 4 */
SHIFT_EDGE_5, /* 5 */
SHIFT_EDGE_6, /* 6 */
SHIFT_EDGE_END /* 7 */
} ShiftEdge_State_t;
/**
* * @brief Handle structure of the HallTuning.
*/
typedef struct
{
MCI_Handle_t *pMCI; /*!< State machine of related MC.*/
OTT_Handle_t *pOTT;
HALL_Handle_t *pHALL_M1;
STO_PLL_Handle_t *pSTO_PLL_M1;
HT_State_t sm_state; /*!< HT state machine state.*/
bool HT_Start;
bool directionAlreadyChosen;
bool userWantsToRestart;
bool userWantsToAbort;
bool flagState0; /*!< true if current HALL state configuration is H1=H2=H3=0. Used to detect 60 degrees Hall configuration */
bool flagState1; /*!< true if current HALL state configuration H1=H2=H3=1. Used to detect 60 degrees Hall configuration */
bool H1Connected;
bool H2Connected;
bool H3Connected;
bool PTCWellPositioned;
bool waitHallFlagCompleted;
bool reliable;
bool edgeAngleDirPos;
uint8_t bPlacement;
uint8_t bMechanicalWantedDirection;
uint8_t bNewH1;
uint8_t bNewH2;
uint8_t bNewH3;
uint8_t bProgressPercentage;
int8_t bPinToComplement;
uint16_t hHallFlagCnt;
uint16_t hWaitRampCnt;
uint16_t hShiftAngleDepth;
int16_t hPhaseShiftInstantaneous;
int16_t hPhaseShiftCircularMean;
int16_t hPhaseShiftCircularMeanDeg;
int16_t hPhaseShiftCircularMeanNeg;
int16_t hPhaseShiftCircularMeanNegDeg;
uint32_t previousH1;
uint32_t previousH2;
uint32_t previousH3;
int32_t wSinMean;
int32_t wCosMean;
ShiftEdge_State_t shiftEdge_state;
int32_t wSinSum1;
int32_t wCosSum1;
int32_t wSinSum2;
int32_t wCosSum2;
int32_t wSinSum3;
int32_t wCosSum3;
int32_t wSinSum4;
int32_t wCosSum4;
int32_t wSinSum5;
int32_t wCosSum5;
int32_t wSinSum6;
int32_t wCosSum6;
int16_t hPhaseShiftCircularMean5_1;
int16_t hPhaseShiftCircularMeanDeg5_1;
int16_t hPhaseShiftCircularMean1_3;
int16_t hPhaseShiftCircularMeanDeg1_3;
int16_t hPhaseShiftCircularMean3_2;
int16_t hPhaseShiftCircularMeanDeg3_2;
int16_t hPhaseShiftCircularMean2_6;
int16_t hPhaseShiftCircularMeanDeg2_6;
int16_t hPhaseShiftCircularMean6_4;
int16_t hPhaseShiftCircularMeanDeg6_4;
int16_t hPhaseShiftCircularMean4_5;
int16_t hPhaseShiftCircularMeanDeg4_5;
int16_t hPhaseShiftCircularMean5_4;
int16_t hPhaseShiftCircularMeanDeg5_4;
int16_t hPhaseShiftCircularMean4_6;
int16_t hPhaseShiftCircularMeanDeg4_6;
int16_t hPhaseShiftCircularMean6_2;
int16_t hPhaseShiftCircularMeanDeg6_2;
int16_t hPhaseShiftCircularMean2_3;
int16_t hPhaseShiftCircularMeanDeg2_3;
int16_t hPhaseShiftCircularMean3_1;
int16_t hPhaseShiftCircularMeanDeg3_1;
int16_t hPhaseShiftCircularMean1_5;
int16_t hPhaseShiftCircularMeanDeg1_5;
} HT_Handle_t;
void HT_Init( HT_Handle_t * pHandleHT, bool pRST );
void HT_MF( HT_Handle_t * pHandleHT );
void HT_GetPhaseShift( HT_Handle_t * pHandleHT );
void HT_Stop( HT_Handle_t * pHandleHT );
void HT_SetMechanicalWantedDirection( HT_Handle_t * pHandleHT, uint8_t bMWD );
void HT_SetStart ( HT_Handle_t * pHandleHT, bool value );
void HT_SetRestart ( HT_Handle_t * pHandleHT );
void HT_SetAbort( HT_Handle_t * pHandleHT );
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /*__MP_HALL_TUNING_H*/
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 6,491 | C | 26.74359 | 127 | 0.62733 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/fixpmpyxufloat.h | /**
******************************************************************************
* @file fixpmpyxufloat.h
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* fixpmpyxufloat.h */
#ifndef _FIXPMPYXUFLOAT_H_
#define _FIXPMPYXUFLOAT_H_
/* Multiply a variable of _any_ FIXP format with a floating point number
* This is used for compile-time constant float values only
*/
#define FIXPmpy_xuFloat(var,fixed_float) \
(((fixed_float) < 1.0) ? (FIXP30_rsmpy((var),FIXP30(fixed_float)))\
:(((fixed_float) < 2.0) ? (FIXP29_rsmpy((var),FIXP29(fixed_float)))\
:(((fixed_float) < 4.0) ? (FIXP28_rsmpy((var),FIXP28(fixed_float)))\
:(((fixed_float) < 8.0) ? (FIXP27_rsmpy((var),FIXP27(fixed_float)))\
:(((fixed_float) < 16.0) ? (FIXP26_rsmpy((var),FIXP26(fixed_float)))\
:(((fixed_float) < 32.0) ? (FIXP25_rsmpy((var),FIXP25(fixed_float)))\
:(((fixed_float) < 64.0) ? (FIXP24_rsmpy((var),FIXP24(fixed_float)))\
:(((fixed_float) < 128.0) ? (FIXP23_rsmpy((var),FIXP23(fixed_float)))\
:(((fixed_float) < 256.0) ? (FIXP22_rsmpy((var),FIXP22(fixed_float)))\
:(((fixed_float) < 512.0) ? (FIXP21_rsmpy((var),FIXP21(fixed_float)))\
:(((fixed_float) < 1024.0) ? (FIXP20_rsmpy((var),FIXP20(fixed_float)))\
:(((fixed_float) < 2048.0) ? (FIXP19_rsmpy((var),FIXP19(fixed_float)))\
:(((fixed_float) < 4096.0) ? (FIXP18_rsmpy((var),FIXP18(fixed_float)))\
:(((fixed_float) < 8192.0) ? (FIXP17_rsmpy((var),FIXP17(fixed_float)))\
:(((fixed_float) < 16384.0) ? (FIXP16_rsmpy((var),FIXP16(fixed_float)))\
:(((fixed_float) < 32768.0) ? (FIXP15_rsmpy((var),FIXP15(fixed_float)))\
:(((fixed_float) < 65536.0) ? (FIXP14_rsmpy((var),FIXP14(fixed_float)))\
:(((fixed_float) < 131072.0) ? (FIXP13_rsmpy((var),FIXP13(fixed_float)))\
:(((fixed_float) < 262144.0) ? (FIXP12_rsmpy((var),FIXP12(fixed_float)))\
:(((fixed_float) < 524288.0) ? (FIXP11_rsmpy((var),FIXP11(fixed_float)))\
:(((fixed_float) < 1048567.0) ? (FIXP10_rsmpy((var),FIXP10(fixed_float)))\
:(((fixed_float) < 2097152.0) ? ( FIXP9_rsmpy((var),FIXP9(fixed_float))) \
:(((fixed_float) < 4194304.0) ? ( FIXP8_rsmpy((var),FIXP8(fixed_float))) \
:(((fixed_float) < 8388608.0) ? ( FIXP7_rsmpy((var),FIXP7(fixed_float))) \
:(((fixed_float) < 16777216.0) ? ( FIXP6_rsmpy((var),FIXP6(fixed_float))) \
:(((fixed_float) < 33554432.0) ? ( FIXP5_rsmpy((var),FIXP5(fixed_float))) \
:(((fixed_float) < 67108864.0) ? ( FIXP4_rsmpy((var),FIXP4(fixed_float))) \
:(((fixed_float) < 134217728.0) ? ( FIXP3_rsmpy((var),FIXP3(fixed_float))) \
:(((fixed_float) < 268435456.0) ? ( FIXP2_rsmpy((var), FIXP2(fixed_float)))\
: ( FIXP1_mpy((var), FIXP1(fixed_float))))))))))))))))))))))))))))))))
#endif /* _FIXPMPYXUFLOAT_H_ */
/* end of fixpmpyxufloat.h */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 3,779 | C | 58.062499 | 112 | 0.518656 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/feed_forward_ctrl.h | /**
******************************************************************************
* @file feed_forward_ctrl.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* Feed Forward Control component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup FeedForwardCtrl
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef FEEDFORWARDCTRL_H
#define FEEDFORWARDCTRL_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
#include "bus_voltage_sensor.h"
#include "speed_pos_fdbk.h"
#include "speed_torq_ctrl.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup FeedForwardCtrl
* @{
*/
/**
* @brief Handle structure of the Feed-forward Component
*/
typedef struct
{
qd_t Vqdff; /**< Feed Forward controller @f$I_{qd}@f$ contribution to @f$V_{qd}@f$ */
qd_t VqdPIout; /**< @f$V_{qd}@f$ as output by PID controller */
qd_t VqdAvPIout; /**< Averaged @f$V_{qd}@f$ as output by PID controller */
int32_t wConstant_1D; /**< Feed forward default constant for the @f$d@f$ axis */
int32_t wConstant_1Q; /**< Feed forward default constant for the @f$q@f$ axis */
int32_t wConstant_2; /**< Default constant value used by Feed-forward algorithm */
BusVoltageSensor_Handle_t *pBus_Sensor; /**< Related bus voltage sensor */
PID_Handle_t *pPID_q; /*!< Related PI for @f$I_{q}@f$ regulator */
PID_Handle_t *pPID_d; /*!< Related PI for @f$I_{d}@f$ regulator */
uint16_t hVqdLowPassFilterBW; /**< Use this parameter to configure the Vqd
first order software filter bandwidth. In
case FULL_MISRA_COMPLIANCY,
hVqdLowPassFilterBW is used and equal to
FOC_CurrController call rate [Hz]/ FilterBandwidth[Hz].
On the contrary, if FULL_MISRA_COMPLIANCY
is not defined, hVqdLowPassFilterBWLOG is
used and equal to log with base two of previous
definition */
int32_t wDefConstant_1D; /**< Feed forward default constant for d axes */
int32_t wDefConstant_1Q; /**< Feed forward default constant for q axes */
int32_t wDefConstant_2; /**< Default constant value used by
Feed-forward algorithm*/
uint16_t hVqdLowPassFilterBWLOG; /**< hVqdLowPassFilterBW expressed as power of 2.
E.g. if gain divisor is 512 the value
must be 9 because 2^9 = 512 */
} FF_Handle_t;
/*
* Initializes all the component variables
*/
void FF_Init(FF_Handle_t *pHandle, BusVoltageSensor_Handle_t *pBusSensor, PID_Handle_t *pPIDId,
PID_Handle_t *pPIDIq);
/*
* It should be called before each motor restart and clears the Feed-forward
* internal variables.
*/
void FF_Clear(FF_Handle_t *pHandle);
/*
* It implements Feed-forward controller by computing new Vqdff value.
* This will be then summed up to PI output in FF_VqdConditioning
* method.
*/
void FF_VqdffComputation(FF_Handle_t *pHandle, qd_t Iqdref, SpeednTorqCtrl_Handle_t *pSTC);
/*
* It returns the Vqd components computed by input plus the Feed-forward
* action and store the last Vqd values in the internal variable.
*/
qd_t FF_VqdConditioning(FF_Handle_t *pHandle, qd_t Vqd);
/*
* It low-pass filters the Vqd voltage coming from the speed PI. Filter
* bandwidth depends on hVqdLowPassFilterBW parameter.
*/
void FF_DataProcess(FF_Handle_t *pHandle);
/*
* Use this method to initialize FF variables in START_TO_RUN state.
*/
void FF_InitFOCAdditionalMethods(FF_Handle_t *pHandle);
/*
* Use this method to set new constants values used by
* Feed-forward algorithm.
*/
void FF_SetFFConstants(FF_Handle_t *pHandle, FF_TuningStruct_t sNewConstants);
/*
* Use this method to get present constants values used by
* Feed-forward algorithm.
*/
FF_TuningStruct_t FF_GetFFConstants(FF_Handle_t *pHandle);
/*
* Use this method to get present values for the Vqd Feed-forward
* components.
*/
qd_t FF_GetVqdff(const FF_Handle_t *pHandle);
/*
* Use this method to get the averaged output values of qd axes
* currents PI regulators.
*/
qd_t FF_GetVqdAvPIout(const FF_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* FEEDFORWARDCTRL_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,596 | C | 34.649681 | 105 | 0.561115 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/pidreg_current.h | /**
******************************************************************************
* @file pidreg_current.h
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* pidreg_current.h */
#ifndef _PIDREG_CURRENT_H_
#define _PIDREG_CURRENT_H_
#include "fixpmath.h"
typedef struct _PIDREG_CURRENT_s_
{
/* configuration */
FIXP_scaled_t Kp_fps;
FIXP_scaled_t Wi_fps;
float current_scale;
float voltage_scale;
float pid_freq_hz;
/* limits */
fixp24_t Max;
fixp24_t Min;
/* process */
fixp24_t Err;
fixp24_t Up;
fixp24_t Ui;
fixp30_t Out;
fixp24_t compensation; /* bus voltage compensation */
bool clipped;
} PIDREG_CURRENT_s;
void PIDREG_CURRENT_init(
PIDREG_CURRENT_s * pHandle,
const float current_scale,
const float voltage_scale,
const float pid_freq_hz
);
fixp30_t PIDREG_CURRENT_run(PIDREG_CURRENT_s* pHandle, const fixp30_t err);
bool PIDREF_CURRENT_getClipped( PIDREG_CURRENT_s* pHandle );
float PIDREF_CURRENT_getKp_si( PIDREG_CURRENT_s* pHandle );
float PIDREF_CURRENT_getWi_si( PIDREG_CURRENT_s* pHandle );
void PIDREG_CURRENT_setKp_si(PIDREG_CURRENT_s* pHandle, const float Kp_si);
void PIDREG_CURRENT_setWi_si(PIDREG_CURRENT_s* pHandle, const float Wi_si);
void PIDREG_CURRENT_setUi_pu( PIDREG_CURRENT_s* pHandle, const fixp30_t Ui);
void PIDREG_CURRENT_setCompensation(PIDREG_CURRENT_s* pHandle, const fixp24_t compensation);
void PIDREG_CURRENT_setOutputLimits(PIDREG_CURRENT_s* pHandle, const fixp30_t max_pu, const fixp30_t min_pu);
#endif /* _PIDREG_CURRENT_H_ */
/* end of pidreg_current.h */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 2,277 | C | 31.542857 | 109 | 0.614405 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/data_scope.h | /**
******************************************************************************
* @file data_scope.h
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* data_scope.h */
#ifndef _DATA_SCOPE_H_
#define _DATA_SCOPE_H_
/* Functionality:
* Read data in RAM in one format, convert to another format, write to another location in RAM
* Used to convert internal motor control signals into the correct format to communicate to the PC, or DAC output
*/
#include "fixpmath.h"
#include <stdbool.h>
#include <stddef.h>
#define DATA_SCOPE_NUMCHANNELS (4)
/* ToDo:
* Remote control support
* - Select pre-defined set of measurements
* - Change single channel;
* - Select variable (implicitly sets data type, qFmt, full scale, address, maybe default display scale)
* - Change display scale (unit/V, e.g. 10A/V, 0.001VpHz/V etc)
* - Optional; Change internal parameters, like data qFmt, full scale -- never address, that's protected
*/
typedef enum _DATA_Datatype_e_
{
DATA_DATATYPE_Int32,
DATA_DATATYPE_Int16,
} DATA_Datatype_e;
typedef struct _DATA_SCOPE_CHANNEL_s_
{
bool enabled; /* Disable channel while adjusting settings, or not yet configured */
/* data description */
void* pData; /* Location of data in memory */
DATA_Datatype_e datatype; /* Data type in memory */
fixpFmt_t data_qFmt; /* Data qFmt in memory */
float data_fullscale; /* Full scale data range for per unit values, 1.0f default */
/* conversion to volts - calculated from data_scale_f and data description above */
float data_scale_f; /* scale factor for data (V/unit), remembered to prevent unnecessary re-calculations */
FIXP_scaled_t data_scale_fixps; /* scale factor for data (V/unit), derived from data_scale_f */
fixp24_t data_fixp24_volt; /* debug, data in volts */
/* DAC calibration */
fixp15_t dac_scale; /* Number of DAC counts for 1V range */
fixp15_t dac_offset; /* DAC value for 0V output */
/* output */
uint16_t dac_value; /* Value written to the DAC */
} DATA_SCOPE_CHANNEL_s;
typedef struct _DATA_SCOPE_Command_s_
{
uint32_t command:8; // 7:0
uint32_t channel:8; // 15:8
uint32_t variable:8; // 23:16
uint32_t parameter:8; // 31:24
} DATA_SCOPE_Command_s;
typedef union _DATA_SCOPE_Command_u_
{
DATA_SCOPE_Command_s bits;
uint32_t all;
} DATA_SCOPE_Command_u;
typedef struct _DATA_SCOPE_Obj_
{
DATA_SCOPE_Command_u command;
DATA_SCOPE_CHANNEL_s channel[DATA_SCOPE_NUMCHANNELS];
} DATA_SCOPE_Obj;
typedef struct _DATA_SCOPE_Obj_* DATA_SCOPE_Handle;
extern DATA_SCOPE_Handle DATA_SCOPE_init(void* pMemory, const size_t numWords);
extern void DATA_SCOPE_setup(DATA_SCOPE_Handle handle);
/* Calculate new values for all active channels */
extern void DATA_SCOPE_run(DATA_SCOPE_Handle handle);
extern uint16_t DATA_SCOPE_getSingleChannelValue(DATA_SCOPE_Handle handle, uint16_t channel);
extern void DATA_SCOPE_setChannelDacScaleAndOffset(DATA_SCOPE_Handle handle, const uint16_t channel, const fixp15_t scale, const fixp15_t offset);
/* Oscilloscope divisions are 1V per division. DataScale is set to x/1V; E.g. dataScale 10.0 would mean 10A/V output. */
extern void DATA_SCOPE_setChannelDataScale(DATA_SCOPE_Handle handle, const uint16_t channel, const float dataScale);
#endif /* _DATA_SCOPE_H_ */
/* end of data_scope.h */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 4,306 | C | 36.12931 | 146 | 0.614259 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/bus_voltage_sensor.h | /**
******************************************************************************
* @file bus_voltage_sensor.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* BusVoltageSensor component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup BusVoltageSensor
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef BUSVOLTAGESENSOR_H
#define BUSVOLTAGESENSOR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup BusVoltageSensor
* @{
*/
/**
* @brief BusVoltageSensor handle definition
*/
typedef struct
{
SensorType_t SensorType; /*!< It contains the information about the type
of instanced bus voltage sensor object.
It can be equal to REAL_SENSOR or
VIRTUAL_SENSOR */
uint16_t ConversionFactor; /*!< It is used to convert bus voltage from
u16Volts into real Volts (V).
1 u16Volt = 65536/ConversionFactor Volts
For real sensors ConversionFactor it is
equal to the product between the expected MCU
voltage and the voltage sensing network
attenuation. For virtual sensors it must
be equal to 500 */
uint16_t LatestConv; /*!< It contains latest Vbus converted value
expressed in u16Volt format */
uint16_t AvBusVoltage_d; /*!< It contains latest available average Vbus
expressed in u16Volt format */
uint16_t FaultState; /*!< It contains latest Fault code (#MC_NO_ERROR,
#MC_OVER_VOLT or #MC_UNDER_VOLT) */
} BusVoltageSensor_Handle_t;
/* Exported functions ------------------------------------------------------- */
uint16_t VBS_GetBusVoltage_d(const BusVoltageSensor_Handle_t *pHandle);
uint16_t VBS_GetAvBusVoltage_d(const BusVoltageSensor_Handle_t *pHandle);
uint16_t VBS_GetAvBusVoltage_V(const BusVoltageSensor_Handle_t *pHandle);
uint16_t VBS_CheckVbus(const BusVoltageSensor_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* BUSVOLTAGESENSOR_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 3,251 | C | 35.539325 | 85 | 0.511227 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/max_torque_per_ampere.h | /**
******************************************************************************
* @file max_torque_per_ampere.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief Maximum torque per ampere (MTPA) control for I-PMSM motors
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup MTPA
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef MAXTORQUEPERAMPERE_H
#define MAXTORQUEPERAMPERE_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup MTPA Maximum Torque Per Ampere Control
* @{
*/
/* Exported types ------------------------------------------------------------*/
#define SEGMENT_NUM 7U /* coeff no. -1 */
#define MTPA_ARRAY_SIZE SEGMENT_NUM + 1U
/**
* @brief Handle structure of max_torque_per_ampere.c
*/
typedef struct
{
int16_t SegDiv; /**< Segments divisor */
int32_t AngCoeff[MTPA_ARRAY_SIZE]; /**< Angular coefficients table */
int32_t Offset[MTPA_ARRAY_SIZE]; /**< Offsets table */
} MTPA_Handle_t;
/* Exported functions ------------------------------------------------------- */
/* Calculates the Id current ref based on input Iq current */
void MTPA_CalcCurrRefFromIq(const MTPA_Handle_t *pHandle, qd_t *Iqdref);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* MAXTORQUEPERAMPERE_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,152 | C | 28.902777 | 85 | 0.48513 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/virtual_bus_voltage_sensor.h | /**
******************************************************************************
* @file virtual_bus_voltage_sensor.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* Virtual Bus Voltage Sensor component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup VirtualBusVoltageSensor
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef VIRTUAL_BUSVOLTAGESENSOR_H
#define VIRTUAL_BUSVOLTAGESENSOR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "bus_voltage_sensor.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup BusVoltageSensor
* @{
*/
/** @addtogroup VirtualBusVoltageSensor
* @{
*/
/**
* @brief Virtual Vbus sensor class parameters definition
*/
typedef struct
{
BusVoltageSensor_Handle_t _Super; /*!< Bus voltage sensor component handle. */
uint16_t ExpectedVbus_d; /*!< Expected Vbus voltage expressed in
digital value
hOverVoltageThreshold(digital value)=
Over Voltage Threshold (V) * 65536
/ 500 */
} VirtualBusVoltageSensor_Handle_t;
/* Exported functions ------------------------------------------------------- */
void VVBS_Init(VirtualBusVoltageSensor_Handle_t *pHandle);
void VVBS_Clear(VirtualBusVoltageSensor_Handle_t *pHandle);
uint16_t VVBS_NoErrors(VirtualBusVoltageSensor_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
/** @} */
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* VIRTUAL_BUSVOLTAGESENSOR_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,438 | C | 28.743902 | 85 | 0.511485 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/virtual_speed_sensor.h | /**
******************************************************************************
* @file virtual_speed_sensor.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* Virtual Speed Sensor component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup VirtualSpeedSensor
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef VIRTUALSPEEDSENSOR_H
#define VIRTUALSPEEDSENSOR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "speed_pos_fdbk.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup SpeednPosFdbk
* @{
*/
/** @addtogroup VirtualSpeedSensor
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief This structure is used to handle an instance of the Virtual Speed
* sensor component.
*/
typedef struct
{
SpeednPosFdbk_Handle_t _Super;
int32_t wElAccDppP32; /*!< Delta electrical speed expressed in [dpp](measurement_units.md) per speed
sampling period to be applied each time is called
SPD_calcAvrgMecSpeedUnit multiplied by scaling
factor of 65536. */
int32_t wElSpeedDpp32; /*!< Electrical speed expressed in [dpp](measurement_units.md) multiplied by
scaling factor 65536. */
uint16_t hRemainingStep; /*!< Number of steps remaining to reach the final
speed. */
int16_t hFinalMecSpeedUnit; /*!< Backup of hFinalMecSpeedUnit to be applied in
the last step.*/
bool bTransitionStarted; /*!< Retaining information about started Transition status.*/
bool bTransitionEnded; /*!< Retaining information about ended transition status.*/
int16_t hTransitionRemainingSteps; /*!< Number of steps remaining to end
transition from Virtual Speed Sensor module to other speed sensor modules */
int16_t hElAngleAccu; /*!< Electrical angle accumulator */
bool bTransitionLocked; /*!< Transition acceleration started */
bool bCopyObserver; /*!< Command to set Virtual Speed Sensor module output same as state observer */
uint16_t hSpeedSamplingFreqHz; /*!< Frequency (Hz) at which motor speed is to
be computed. It must be equal to the frequency
at which function SPD_calcAvrgMecSpeedUnit
is called. */
int16_t hTransitionSteps; /*< Number of steps to perform the transition phase
from from Virtual Speed Sensor module to other speed sensor modules.
If the Transition PHase should last TPH milliseconds, and the FOC Execution
Frequency is set to FEF kHz, then #hTransitionSteps = TPH * FEF */
} VirtualSpeedSensor_Handle_t;
/* It initializes the Virtual Speed Sensor component */
void VSS_Init(VirtualSpeedSensor_Handle_t *pHandle);
/* It clears Virtual Speed Sensor by re-initializing private variables*/
void VSS_Clear(VirtualSpeedSensor_Handle_t *pHandle);
/* It compute a theorical speed and update the theorical electrical angle */
int16_t VSS_CalcElAngle(VirtualSpeedSensor_Handle_t *pHandle, int16_t *pInputVars_str);
/* Computes the rotor average theoretical mechanical speed in the unit defined by SPEED_UNIT and
* returns it in pMecSpeedUnit */
bool VSS_CalcAvrgMecSpeedUnit(VirtualSpeedSensor_Handle_t *pHandle, int16_t *hMecSpeedUnit);
/* It set istantaneous information on VSS mechanical and electrical angle */
void VSS_SetMecAngle(VirtualSpeedSensor_Handle_t *pHandle, int16_t hMecAngle);
/* Set the mechanical acceleration of virtual sensor */
void VSS_SetMecAcceleration(VirtualSpeedSensor_Handle_t *pHandle, int16_t hFinalMecSpeedUnit, uint16_t hDurationms);
/* Checks if the ramp executed after a VSPD_SetMecAcceleration command has been completed */
bool VSS_RampCompleted(VirtualSpeedSensor_Handle_t *pHandle);
/* Get the final speed of last setled ramp of virtual sensor expressed in 0.1Hz */
int16_t VSS_GetLastRampFinalSpeed(VirtualSpeedSensor_Handle_t *pHandle);
/* Set the command to Start the transition phase from VirtualSpeedSensor to other SpeedSensor */
bool VSS_SetStartTransition(VirtualSpeedSensor_Handle_t *pHandle, bool bCommand);
/* Return the status of the transition phase */
bool VSS_IsTransitionOngoing(VirtualSpeedSensor_Handle_t *pHandle);
bool VSS_TransitionEnded(VirtualSpeedSensor_Handle_t *pHandle);
/* It sets istantaneous information on rotor electrical angle copied by state observer */
void VSS_SetCopyObserver(VirtualSpeedSensor_Handle_t *pHandle);
/* It sets istantaneous information on rotor electrical angle */
void VSS_SetElAngle(VirtualSpeedSensor_Handle_t *pHandle, int16_t hElAngle);
/** @} */
/** @} */
/** @} */
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* VIRTUALSPEEDSENSOR_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,995 | C | 45.123077 | 118 | 0.612177 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/sto_cordic_speed_pos_fdbk.h | /**
******************************************************************************
* @file sto_cordic_speed_pos_fdbk.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* State Observer + CORDIC Speed & Position Feedback component of the
* Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup STO_CORDIC_SpeednPosFdbk
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STO_CORDIC_SPEEDNPOSFDBK_H
#define STO_CORDIC_SPEEDNPOSFDBK_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "speed_pos_fdbk.h"
#include "sto_speed_pos_fdbk.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup SpeednPosFdbk
* @{
*/
/** @addtogroup STO_CORDIC_SpeednPosFdbk
* @{
*/
/**
* @brief This structure is used to handle an instance of the STO_CORDIC component
*/
typedef struct
{
SpeednPosFdbk_Handle_t _Super;
int16_t hC1; /*!< State observer constant C1, it can be computed as F1 * Rs(ohm)/(Ls[H] *
State observer execution rate [Hz]). */
int16_t hC2; /*!< Variable containing state observer constant C2, it can be computed as
F1 * K1/ State observer execution rate [Hz] being K1 one of the two
observer gains. */
int16_t hC3; /*!< State observer constant C3, it can be computed as F1 * Max application
speed [rpm] * Motor B-emf constant [Vllrms/krpm] * sqrt(2)/ (Ls [H] *
max measurable current (A) * State observer execution rate [Hz]). */
int16_t hC4; /*!< State Observer constant C4, it can be computed as K2 * max measurable
current (A) / (Max application speed [rpm] * Motor B-emf constant
[Vllrms/krpm] * sqrt(2) * F2 * State observer execution rate [Hz]) being
K2 one of the two observer gains. */
int16_t hC5; /*!< State Observer constant C5, it can be computed as F1 * max measurable
voltage / (2 * Ls [Hz] * max measurable current * State observer
execution rate [Hz]). */
int16_t hC6; /*!< State observer constant C6, computed with a specific procedure starting from
the other constants. */
int16_t hF1; /*!< State observer scaling factor F1. */
int16_t hF2; /*!< State observer scaling factor F2. */
int16_t hF3; /*!< State observer scaling factor F3. */
uint16_t F3POW2; /*!< State observer scaling factor F3 expressed as power of 2. E.g. if gain
divisor is 512 the value must be 9 because 2^9 = 512. */
int32_t Ialfa_est; /*!< Estimated Ialfa current in int32 format. */
int32_t Ibeta_est; /*!< Estimated Ialfa current in int32 format. */
int32_t wBemf_alfa_est; /*!< Estimated B-emf alfa in int32_t format. */
int32_t wBemf_beta_est; /*!< Estimated B-emf beta in int32_t format. */
int16_t hBemf_alfa_est; /*!< Estimated B-emf alfa in int16_t format. */
int16_t hBemf_beta_est; /*!< Estimated B-emf beta in int16_t format. */
int16_t Speed_Buffer[64]; /*!< Estimated speed FIFO, it contains latest bSpeedBufferSize speed
measurements. */
uint8_t Speed_Buffer_Index; /*!< Position of latest speed estimation in estimated speed FIFO. */
bool IsSpeedReliable; /*!< Latest private speed reliability information, updated by the
*_CalcAvrgMecSpeedUnit() functions. It is true if the speed measurement
variance is lower than the threshold corresponding to
hVariancePercentage. */
uint8_t ConsistencyCounter; /*!< Counter of passed tests for start-up validation. */
uint8_t ReliabilityCounter; /*!< Counter for reliability check internal to derived class. */
bool IsAlgorithmConverged; /*!< Boolean variable containing observer convergence information. */
int16_t Orig_Speed_Buffer[64]; /*!< Estimated speed FIFO, it contains latest bSpeedBufferSize speed
measurements, cordic outputs not modified. */
int16_t Orig_ElSpeedDpp;
bool IsBemfConsistent; /*!< Sensor reliability information, updated by the *_CalcAvrgMecSpeedUnit()
functions. It is true if the observed back-emfs are consistent with
expectations. */
int32_t Obs_Bemf_Level; /*!< Observed back-emf Level. */
int32_t Est_Bemf_Level; /*!< Estimated back-emf Level. */
bool EnableDualCheck; /*!< Consistency check enabler. */
int32_t DppBufferSum; /*!< Summation of speed buffer elements [dpp]. */
int32_t DppOrigBufferSum; /*!< Summation of not modified speed buffer elements [dpp]. */
int16_t SpeedBufferOldestEl; /*!< Oldest element of the speed buffer. */
int16_t OrigSpeedBufferOldestEl; /*!< Oldest element of the not modified speed buffer. */
uint8_t SpeedBufferSizeUnit; /*!< Depth of FIFO used to average estimated speed exported by
SPD_GetAvrgMecSpeedUnit. It must be an integer number between 1 and 64. */
uint8_t SpeedBufferSizedpp; /*!< Depth of FIFO used for both averaging estimated speed exported by
SPD_GetElSpeedDpp and state observer equations. It must be an integer number
between 1 and SpeedBufferSizeUnit. */
uint16_t VariancePercentage; /*!< Parameter expressing the maximum allowed variance of speed estimation. */
uint8_t SpeedValidationBand_H; /*!< It expresses how much estimated speed can exceed forced stator electrical
frequency during start-up without being considered wrong. The measurement
unit is 1/16 of forced speed. */
uint8_t SpeedValidationBand_L; /*!< It expresses how much estimated speed can be below forced stator electrical
frequency during start-up without being considered wrong. The measurement
unit is 1/16 of forced speed. */
uint16_t MinStartUpValidSpeed; /*!< Minimum mechanical speed required to validate the start-up. Expressed in the
unit defined by #SPEED_UNIT). */
uint8_t StartUpConsistThreshold; /*!< Number of consecutive tests on speed consistency to be passed before
validating the start-up. */
uint8_t Reliability_hysteresys; /*!< Number of reliability failed consecutive tests before a speed check fault
is returned to base class. */
int16_t MaxInstantElAcceleration; /*!< maximum instantaneous electrical acceleration (dpp per control period). */
uint8_t BemfConsistencyCheck; /*!< Degree of consistency of the observed back-emfs, it must be an integer
number ranging from 1 (very high consistency) down to 64 (very poor
consistency). */
uint8_t BemfConsistencyGain; /*!< Gain to be applied when checking back-emfs consistency; default value
is 64 (neutral), max value 105 (x1.64 amplification), min value 1
(/64 attenuation) */
uint16_t MaxAppPositiveMecSpeedUnit; /*!< Maximum positive value of rotor speed. Expressed in the unit defined by
#SPEED_UNIT. It can be x1.1 greater than max application speed. */
uint16_t F1LOG; /*!< F1 gain divisor expressed as power of 2. E.g. if gain divisor is 512
the value must be 9 because 2^9 = 512. */
uint16_t F2LOG; /*!< F2 gain divisor expressed as power of 2. E.g. if gain divisor is 512 the
value must be 9 because 2^9 = 512. */
uint16_t SpeedBufferSizedppLOG; /*!< bSpeedBufferSizedpp expressed as power of 2.E.g. if gain divisor is 512 the
value must be 9 because 2^9 = 512. */
bool ForceConvergency; /*!< Variable to force observer convergence. */
bool ForceConvergency2; /*!< Variable to force observer convergence. */
} STO_CR_Handle_t;
/* Exported functions ------------------------------------------------------- */
/* It initializes the state observer object */
void STO_CR_Init(STO_CR_Handle_t *pHandle);
/* It clears state observer object by re-initializing private variables */
void STO_CR_Clear(STO_CR_Handle_t *pHandle);
/* It executes Luenberger state observer and calls CORDIC to compute a new speed
* estimation and update the estimated electrical angle
*/
int16_t STO_CR_CalcElAngle(STO_CR_Handle_t *pHandle, Observer_Inputs_t *pInputs);
/* Computes the rotor average mechanical speed in the unit defined by SPEED_UNIT and returns it in pMecSpeedUnit */
bool STO_CR_CalcAvrgMecSpeedUnit(STO_CR_Handle_t *pHandle, int16_t *pMecSpeedUnit);
/* Checks whether the state observer algorithm has converged */
bool STO_CR_IsObserverConverged(STO_CR_Handle_t *pHandle, int16_t hForcedMecSpeedUnit);
/* It exports estimated Bemf alpha-beta in alphabeta_t format */
alphabeta_t STO_CR_GetEstimatedBemf(STO_CR_Handle_t *pHandle);
/* It exports the stator current alpha-beta as estimated by state observer */
alphabeta_t STO_CR_GetEstimatedCurrent(STO_CR_Handle_t *pHandle);
/* It exports current observer gains through parameters hC2 and hC4 */
void STO_CR_GetObserverGains(STO_CR_Handle_t *pHandle, int16_t *phC2, int16_t *phC4);
/* It allows setting new values for observer gains hC1 and hC2 */
void STO_CR_SetObserverGains(STO_CR_Handle_t *pHandle, int16_t hhC1, int16_t hhC2);
/* It computes and update the estimated average electrical speed */
void STO_CR_CalcAvrgElSpeedDpp(STO_CR_Handle_t *pHandle);
/* It exports estimated Bemf squared level */
int32_t STO_CR_GetEstimatedBemfLevel(const STO_CR_Handle_t *pHandle);
/* It exports observed Bemf squared level */
int32_t STO_CR_GetObservedBemfLevel(const STO_CR_Handle_t *pHandle);
/* It enables/disables the bemf consistency check */
void STO_CR_BemfConsistencyCheckSwitch(STO_CR_Handle_t *pHandle, bool bSel);
/* It returns the result of the Bemf consistency check */
bool STO_CR_IsBemfConsistent(const STO_CR_Handle_t *pHandle);
/* It returns the result of the last variance check */
bool STO_CR_IsSpeedReliable(const STO_Handle_t *pHandle);
/* It sets internal ForceConvergency1 to true */
void STO_CR_ForceConvergency1(STO_Handle_t *pHandle);
/* It sets internal ForceConvergency2 to true */
void STO_CR_ForceConvergency2(STO_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
/** @} */
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /*STO_CORDIC_SPEEDNPOSFDBK_H*/
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 12,569 | C | 57.738317 | 120 | 0.574907 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/pwm_common.h | /**
******************************************************************************
* @file pwm_common.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* PWM & Current Feedback component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup pwm_curr_fdbk
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef PWMNCOMMON_H
#define PWMNCOMMON_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
/**
* @brief The maximum number of needed PWM cycles. verif?
*/
#define NB_CONVERSIONS 16u
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk
* @{
*/
/* Exported defines ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
#ifdef TIM2
/*
* Performs the start of all the timers required by the control.
* It uses TIM2 as a temporary timer to achieve synchronization between PWM signals.
* When this function is called, TIM1 and/or TIM8 must be in a frozen state
* with CNT, ARR, REP RATE and trigger correctly set (these settings are
* usually performed in the Init method accordingly with the configuration)
*/
void startTimers(void);
#endif
/*
* Waits for the end of the polarization. If the polarization exceeds
* the number of needed PWM cycles, it reports an error.
*/
void waitForPolarizationEnd(TIM_TypeDef *TIMx, uint16_t *SWerror, uint8_t repCnt, volatile uint8_t *cnt);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* PWMNCOMMON_H */
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,489 | C | 29 | 105 | 0.521896 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/oversampling.h | /**
******************************************************************************
* @file oversampling.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* oversampling component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup oversampling
*/
#ifndef _OVERSAMPLING_H_
#define _OVERSAMPLING_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "fixpmath.h"
#include "drive_parameters.h"
#include "parameters_conversion.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup oversampling
* @{
*/
#define ADC_FIXPFMT (16) /*!< @brief ADC fixp format */
#define DMA_BUFFERS (2) /*!< @brief double buffering constant */
/**
* @brief Sample data structure definition
*/
typedef struct _Samples_t_
{
fixp30_t I_R; /*!< @brief Phase R current sample */
fixp30_t I_S; /*!< @brief Phase S current sample */
fixp30_t I_T; /*!< @brief Phase T current sample */
fixp30_t U_R; /*!< @brief Phase R voltage sample */
fixp30_t U_S; /*!< @brief Phase S voltage sample */
fixp30_t U_T; /*!< @brief Phase T voltage sample */
fixp30_t U_DC; /*!< @brief DC bus voltage sample */
} Samples_t;
/**
* @brief Oversampling channel enum definition
*/
typedef enum _Oversampling_ChannelName_e_
{
OVS_I_R, /*!< @brief index of R current sample */
OVS_I_S, /*!< @brief index of S current sample */
OVS_I_T, /*!< @brief index of T current sample */
OVS_U_R, /*!< @brief index of R voltage sample */
OVS_U_S, /*!< @brief index of S voltage sample */
OVS_U_T, /*!< @brief index of T voltage sample */
OVS_U_DC, /*!< @brief index of DC bus voltage sample */
OVS_THROTTLE, /*!< @brief index of throttle sample */
OVS_TEMP, /*!< @brief index of temperature voltage sample */
OVS_numChannels
} Oversampling_ChannelName_e;
/**
* @brief Oversampling channel data structure definition
*/
typedef struct _Oversampling_Channel_t_
{
uint16_t adc; /*!< @brief ADC for this channel, zero-based */
uint16_t rank; /*!< @brief Rank determines the starting point */
uint16_t tasklen; /*!< @brief Number of ADC Channels this ADC has to sample */
bool single; /*!< @brief Take a single sample at singleIdx, used for low
side current shunt measurements */
} Oversampling_Channel_t;
/**
* @brief DMA double buffering defintion
*
* The instanciated buffer will be used to store the values transfered from ADCs by the DMA
* with double buffering mechanism.
*
*/
typedef uint16_t DMA_ADC_Buffer_t[OVS_LONGEST_TASK * OVS_COUNT * REGULATION_EXECUTION_RATE];
/**
* @brief oversampling data structure definition
*/
typedef struct _Oversampling_t_
{
uint16_t count; /*!< @brief oversampling level */
uint16_t divider; /*!< @brief Number of PWM periods per FOC cycle */
int8_t singleIdx; /*!< @brief Oversampling index of single sample */
int8_t readBuffer; /*!< @brief index of the read buffer (double buffering mechanism) */
int8_t writeBuffer; /*!< @brief index of the write buffer (double buffering mechanism) */
fixp30_t current_factor; /*!< @brief phase current scaling factor that will be applied to the value read from ADC */
fixp30_t voltage_factor; /*!< @brief phase voltage scaling factor that will be applied to the value read from ADC */
fixp30_t busvoltage_factor; /*!< @brief DC bus scaling factor that will be applied to the value read from ADC */
DMA_ADC_Buffer_t DMABuffer[DMA_BUFFERS][OVS_NUM_ADCS]; /*!< @brief One DMA buffer per ADC.
These are all the same size as the largest required buffer. */
Oversampling_Channel_t Channel[OVS_numChannels]; /*!< @brief Each measurement has an oversampling channel*/
} Oversampling_t;
extern Oversampling_t oversampling;
void OVERSAMPLING_getMeasurements(Currents_Irst_t* pCurrents_Irst, Voltages_Urst_t* pVoltages_Urst);
void OVERSAMPLING_getPotentiometerMeasurements( fixp30_t *value);
void OVERSAMPLING_getVbusMeasurements( fixp30_t *value);
void OVERSAMPLING_getTempMeasurements( fixp30_t *value);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* _OVERSAMPLING_H_ */
| 4,972 | C | 36.11194 | 121 | 0.613033 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/mc_cordic.h | /**
******************************************************************************
* @file mc_cordic.h
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* mc_cordic.h */
#ifndef _MC_CORDIC_H_
#define _MC_CORDIC_H_
#include <stdint.h>
#include "cordic_defs.h"
// Number of cycles can be tuned as a compromise between calculation time and precision
#define CORDIC_CONFIG_BASE_COSSIN (LL_CORDIC_PRECISION_6CYCLES | LL_CORDIC_SCALE_0 | LL_CORDIC_NBWRITE_2 |\
LL_CORDIC_INSIZE_32BITS | LL_CORDIC_OUTSIZE_32BITS)
/* CORDIC FUNCTION: COSINE only q1.31 */
#define CORDIC_CONFIG_COSINE (CORDIC_CONFIG_BASE_COSSIN | LL_CORDIC_FUNCTION_COSINE)
/* CORDIC FUNCTION: SINE only q1.31 */
#define CORDIC_CONFIG_SINE (CORDIC_CONFIG_BASE_COSSIN | LL_CORDIC_FUNCTION_SINE)
/* CORDIC FUNCTION: COSINE and SINE q1.31 */
#define CORDIC_CONFIG_COSINE_AND_SINE (CORDIC_CONFIG_BASE_COSSIN | LL_CORDIC_FUNCTION_COSINE | LL_CORDIC_NBREAD_2)
/* CORDIC FUNCTION: PHASE q1.31 (Angle and magnitude computation) */
#define CORDIC_CONFIG_PHASE (LL_CORDIC_FUNCTION_PHASE | LL_CORDIC_PRECISION_15CYCLES | LL_CORDIC_SCALE_0 |\
LL_CORDIC_NBWRITE_2 | LL_CORDIC_NBREAD_2 |\
LL_CORDIC_INSIZE_32BITS | LL_CORDIC_OUTSIZE_32BITS)
/* CORDIC FUNCTION: SQUAREROOT q1.31 */
#define CORDIC_CONFIG_SQRT (LL_CORDIC_FUNCTION_SQUAREROOT | LL_CORDIC_PRECISION_3CYCLES | LL_CORDIC_SCALE_1 |\
LL_CORDIC_NBWRITE_1 | LL_CORDIC_NBREAD_1 |\
LL_CORDIC_INSIZE_32BITS | LL_CORDIC_OUTSIZE_32BITS)
#define _FIXP30local(A) (int32_t) ((A) * 1073741824.0f) // local macro
#define C_ANGLE_CORDIC_TO_PU(angle_cordic) (angle_cordic >> 2) & (_FIXP30local(1.0f)-1) /* scale and wrap cordic angle to per unit */
#define C_ANGLE_PU_TO_CORDIC(angle_pu) (angle_pu << 2)
#define C_ANGLE_FP24_PU_TO_CORDIC(angle_pu) (angle_pu << 8)
static inline void _CORDIC_polar(const int32_t x, const int32_t y, int32_t *pAngle_pu, int32_t *pMagnitude)
{
// __disable_irq();
__asm volatile ("cpsid i" : : : "memory");
// WRITE_REG(LCORDIC->CSR, CORDIC_CONFIG_PHASE);
LCORDIC->CSR = CORDIC_CONFIG_PHASE;
// LL_CORDIC_WriteData(CORDIC, x);
// WRITE_REG(CORDICx->WDATA, InData);
LCORDIC->WDATA = x;
// LL_CORDIC_WriteData(CORDIC, y);
// WRITE_REG(CORDICx->WDATA, InData);
LCORDIC->WDATA = y;
// while (HAL_IS_BIT_CLR(LCORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
while ((LCORDIC->CSR & CORDIC_CSR_RRDY) == 0U); /* Wait for result */
// *pAngle_pu = ANGLE_CORDIC_TO_PU(LL_CORDIC_ReadData(CORDIC));
*pAngle_pu = C_ANGLE_CORDIC_TO_PU(LCORDIC->RDATA);
// *pMagnitude = LL_CORDIC_ReadData(CORDIC);
*pMagnitude = LCORDIC->RDATA;
// __enable_irq();
__asm volatile ("cpsie i" : : : "memory");
}
// bit of a mutual inclusion problem for cossin struct type
typedef struct
{
int32_t cos;
int32_t sin;
} int32_cossin_s;
static inline void _CORDIC_30CosSinPU(const int32_t angle_pu, int32_cossin_s *pCosSin)
{
// __disable_irq();
__asm volatile ("cpsid i" : : : "memory");
// WRITE_REG(LCORDIC->CSR, CORDIC_CONFIG_COSINE_AND_SINE);
LCORDIC->CSR = CORDIC_CONFIG_COSINE_AND_SINE;
// LL_CORDIC_WriteData(CORDIC, ANGLE_PU_TO_CORDIC(angle_pu));
LCORDIC->WDATA = C_ANGLE_PU_TO_CORDIC(angle_pu);
// LL_CORDIC_WriteData(CORDIC, FIXP30(1.0f));
LCORDIC->WDATA = _FIXP30local(1.0f);
// while (HAL_IS_BIT_CLR(LCORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
while ((LCORDIC->CSR & CORDIC_CSR_RRDY) == 0U); /* Wait for result */
// pCosSin->cos = LL_CORDIC_ReadData(CORDIC);
pCosSin->cos = LCORDIC->RDATA;
// pCosSin->sin = LL_CORDIC_ReadData(CORDIC);
pCosSin->sin = LCORDIC->RDATA;
// __enable_irq();
__asm volatile ("cpsie i" : : : "memory");
}
#if 0 // Not implemented yet; will be used in DEMODULATOR_calculateParameters, angle in radians q24, output in q24
static inline void _CORDIC_cos(const int32_t angle_pu, int32_cossin_s *pCosSin)
{
#if 0
fixp30_t angle_pu = FIXP24_mpy(angle_rad, FIXP30(1.0/M_TWOPI));
WRITE_REG(LCORDIC->CSR, CORDIC_CONFIG_COSINE);
LL_CORDIC_WriteData(CORDIC, ANGLE_PU_TO_CORDIC(angle_pu));
LL_CORDIC_WriteData(CORDIC, FIXP24(1.0f));
while (HAL_IS_BIT_CLR(LCORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
return LL_CORDIC_ReadData(CORDIC);
#else
#warning unchanged cossin code
// __disable_irq();
__asm volatile ("cpsid i" : : : "memory");
// WRITE_REG(LCORDIC->CSR, CORDIC_CONFIG_COSINE_AND_SINE);
LCORDIC->CSR = CORDIC_CONFIG_COSINE_AND_SINE;
// LL_CORDIC_WriteData(CORDIC, ANGLE_PU_TO_CORDIC(angle_pu));
LCORDIC->WDATA = C_ANGLE_PU_TO_CORDIC(angle_pu);
// LL_CORDIC_WriteData(CORDIC, FIXP30(1.0f));
LCORDIC->WDATA = _FIXP30local(1.0f);
// while (HAL_IS_BIT_CLR(LCORDIC->CSR, CORDIC_CSR_RRDY)); /* Wait for result */
while ((LCORDIC->CSR & CORDIC_CSR_RRDY) == 0U); /* Wait for result */
// pCosSin->cos = LL_CORDIC_ReadData(CORDIC);
pCosSin->cos = LCORDIC->RDATA;
// pCosSin->sin = LL_CORDIC_ReadData(CORDIC);
pCosSin->sin = LCORDIC->RDATA;
// __enable_irq();
__asm volatile ("cpsie i" : : : "memory");
#endif
}
#endif
#endif /* _MC_CORDIC_H_ */
/* end of mc_cordic.h */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 5,762 | C | 33.716867 | 133 | 0.645089 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/usart_aspep_driver.h | /**
******************************************************************************
* @file usart_aspep_driver.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* uart driver for the aspep protocol.
*
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
#ifndef usart_aspep_driver_h
#define usart_aspep_driver_h
#include <stdint.h>
#include <stdbool.h>
/* To be removed no protocol awarness at this level */
typedef struct
{
USART_TypeDef *USARTx;
DMA_TypeDef *rxDMA;
DMA_TypeDef *txDMA;
uint32_t rxChannel;
uint32_t txChannel;
} UASPEP_Handle_t;
bool UASPEP_SEND_PACKET(void *pHWHandle, void *data, uint16_t length);
void UASPEP_RECEIVE_BUFFER(void *pHWHandle, void *buffer, uint16_t length);
void UASPEP_INIT(void *pHWHandle);
void UASPEP_IDLE_ENABLE(void *pHWHandle);
#endif
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 1,501 | C | 31.652173 | 85 | 0.566955 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/speed_torq_ctrl.h | /**
******************************************************************************
* @file speed_torq_ctrl.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* Speed & Torque Control component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup SpeednTorqCtrlClassic
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef SPEEDNTORQCTRLCLASS_H
#define SPEEDNTORQCTRLCLASS_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
#include "pid_regulator.h"
#include "speed_pos_fdbk.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup SpeednTorqCtrl
* @{
*/
/** @addtogroup SpeednTorqCtrlClassic
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief Speed & Torque Control parameters definition
*/
typedef struct
{
MC_ControlMode_t Mode; /*!< Modality of STC. It can be one of these two settings:
MCM_TORQUE_MODE to enable the Torque mode or
MCM_SPEED_MODE to enable the Speed mode. */
int16_t TargetFinal; /*!< Backup of #hTargetFinal to be applied in the last step. */
int32_t SpeedRefUnitExt; /*!< Current mechanical rotor speed reference expressed in
[SPEED_UNIT](measurement_units.md) multiplied by 65536.*/
int32_t TorqueRef; /*!< Current motor torque reference. This value represents actually
the Iq current expressed in digit multiplied by 65536. */
uint32_t RampRemainingStep; /*!< Number of steps remaining to complete the ramp. */
PID_Handle_t *PISpeed; /*!< The regulator used to perform the speed control loop. */
SpeednPosFdbk_Handle_t *SPD; /*!< The speed sensor used to perform the speed regulation. */
int32_t IncDecAmount; /*!< Increment/decrement amount to be applied to the reference value at each
#CalcTorqueReference. */
uint16_t STCFrequencyHz; /*!< Frequency on which the user updates the torque reference calling
#STC_CalcTorqueReference method expressed in Hz */
uint16_t MaxAppPositiveMecSpeedUnit; /*!< Application maximum positive value of the rotor mechanical speed.
Expressed in the unit defined by [SPEED_UNIT](measurement_units.md). */
uint16_t MinAppPositiveMecSpeedUnit; /*!< Application minimum positive value of the rotor mechanical speed.
Expressed in the unit defined by [SPEED_UNIT](measurement_units.md). */
int16_t MaxAppNegativeMecSpeedUnit; /*!< Application maximum negative value of the rotor mechanical speed.
Expressed in the unit defined by [SPEED_UNIT](measurement_units.md). */
int16_t MinAppNegativeMecSpeedUnit; /*!< Application minimum negative value of the rotor mechanical speed.
Expressed in the unit defined by [SPEED_UNIT](measurement_units.md). */
uint16_t MaxPositiveTorque; /*!< Maximum positive value of motor torque. This value represents actually
the maximum Iq current expressed in digit. */
int16_t MinNegativeTorque; /*!< Minimum negative value of motor torque. This value represents actually
the maximum Iq current expressed in digit. */
MC_ControlMode_t ModeDefault; /*!< Default STC modality. */
int16_t MecSpeedRefUnitDefault; /*!< Default mechanical rotor speed reference expressed in the unit defined by
[SPEED_UNIT](measurement_units.md). */
int16_t TorqueRefDefault; /*!< Default motor torque reference. This value represents actually the Iq
current reference expressed in digit. */
int16_t IdrefDefault; /*!< Default Id current reference expressed in digit. */
} SpeednTorqCtrl_Handle_t;
/* Initializes all the object variables */
void STC_Init(SpeednTorqCtrl_Handle_t *pHandle, PID_Handle_t *pPI, SpeednPosFdbk_Handle_t *SPD_Handle);
/* Resets the integral term of speed regulator */
void STC_Clear(SpeednTorqCtrl_Handle_t *pHandle);
/* Gets the current mechanical rotor speed reference */
int16_t STC_GetMecSpeedRefUnit(SpeednTorqCtrl_Handle_t *pHandle);
/* Gets the current motor torque reference */
int16_t STC_GetTorqueRef(SpeednTorqCtrl_Handle_t *pHandle);
/* Sets the mode of the speed and torque controller (Torque mode or Speed mode) */
void STC_SetControlMode(SpeednTorqCtrl_Handle_t *pHandle, MC_ControlMode_t bMode);
/* Gets the mode of the speed and torque controller */
MC_ControlMode_t STC_GetControlMode(SpeednTorqCtrl_Handle_t *pHandle);
/* Starts the execution of a ramp using new target and duration */
bool STC_ExecRamp(SpeednTorqCtrl_Handle_t *pHandle, int16_t hTargetFinal, uint32_t hDurationms);
/* Interrupts the execution of any previous ramp command */
void STC_StopRamp(SpeednTorqCtrl_Handle_t *pHandle);
/* Computes the new value of motor torque reference */
int16_t STC_CalcTorqueReference(SpeednTorqCtrl_Handle_t *pHandle);
/* Gets the Default mechanical rotor speed reference */
int16_t STC_GetMecSpeedRefUnitDefault(SpeednTorqCtrl_Handle_t *pHandle);
/* Returns the Application maximum positive rotor mechanical speed */
uint16_t STC_GetMaxAppPositiveMecSpeedUnit(SpeednTorqCtrl_Handle_t *pHandle);
/* Returns the Application minimum negative rotor mechanical speed */
int16_t STC_GetMinAppNegativeMecSpeedUnit(SpeednTorqCtrl_Handle_t *pHandle);
/* Checks if the settled speed or torque ramp has been completed */
bool STC_RampCompleted(SpeednTorqCtrl_Handle_t *pHandle);
/* Stops the execution of speed ramp */
bool STC_StopSpeedRamp(SpeednTorqCtrl_Handle_t *pHandle);
/* Sets in real time the speed sensor utilized by the FOC */
void STC_SetSpeedSensor(SpeednTorqCtrl_Handle_t *pHandle, SpeednPosFdbk_Handle_t *SPD_Handle);
/* Returns the speed sensor utilized by the FOC */
SpeednPosFdbk_Handle_t *STC_GetSpeedSensor(SpeednTorqCtrl_Handle_t *pHandle);
/* It returns the default values of Iqdref */
qd_t STC_GetDefaultIqdref(SpeednTorqCtrl_Handle_t *pHandle);
/* Sets the nominal current */
void STC_SetNominalCurrent(SpeednTorqCtrl_Handle_t *pHandle, uint16_t hNominalCurrent);
/* Forces the speed reference to the current speed */
void STC_ForceSpeedReferenceToCurrentSpeed(SpeednTorqCtrl_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* SPEEDNTORQCTRLCLASS_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 7,653 | C | 44.559524 | 117 | 0.626944 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/ramp_ext_mngr.h | /**
******************************************************************************
* @file ramp_ext_mngr.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* Ramp Extended Manager component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup RampExtMngr
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef RAMPEXTMNGR_H
#define RAMPEXTMNGR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup RampExtMngr
* @{
*/
/**
* @brief RampExtMngr Handle Definition.
*/
typedef struct
{
uint32_t FrequencyHz; /*!< Execution frequency expressed in Hz */
int32_t TargetFinal; /*!< Backup of hTargetFinal to be applied in the last step. */
int32_t Ext; /*!< Current state variable multiplied by 32768. */
uint32_t RampRemainingStep; /*!< Number of steps remaining to complete the ramp. */
int32_t IncDecAmount; /*!< Increment/decrement amount to be applied to the reference value at each
CalcTorqueReference. */
uint32_t ScalingFactor; /*!< Scaling factor between output value and its internal representation. */
} RampExtMngr_Handle_t;
/* Exported functions ------------------------------------------------------- */
void REMNG_Init(RampExtMngr_Handle_t *pHandle);
int32_t REMNG_Calc(RampExtMngr_Handle_t *pHandle);
bool REMNG_ExecRamp(RampExtMngr_Handle_t *pHandle, int32_t TargetFinal, uint32_t Durationms);
int32_t REMNG_GetValue(const RampExtMngr_Handle_t *pHandle);
bool REMNG_RampCompleted(const RampExtMngr_Handle_t *pHandle);
void REMNG_StopRamp(RampExtMngr_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* RAMPEXTMNGR_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 2,663 | C | 32.721519 | 112 | 0.549005 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/current_ref_ctrl.h | /**
******************************************************************************
* @file current_ref_ctrl.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* six-step current mode current reference PWM generation component of
* the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup current_ref_ctrl
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef CURRENTREF_H
#define CURRENTREF_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup current_ref_ctrl
* @{
*/
/* Exported defines ------------------------------------------------------------*/
/* Exported defines ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief CurrentRef pulse polarity definition
*/
typedef enum
{
UP = 0,
DOWN = 1,
} CurrentRef_PulsePolarity;
/**
* @brief CurrentRef parameters definition
*/
typedef struct
{
TIM_TypeDef * TIMx; /*!< It contains the pointer to the timer
used for current reference PWM generation. */
uint32_t RefTimerChannel; /*!< Channel of the timer used the generation. */
} CurrentRef_Params_t;
/**
* @brief This structure is used to handle the data of an instance of the Current Reference component
*
*/
typedef struct
{
CurrentRef_Params_t const * pParams_str;
uint16_t Cnt; /**< PWM Duty cycle. */
uint16_t StartCntPh;
uint16_t PWMperiod; /**< PWM period expressed in timer clock cycles unit:
* @f$hPWMPeriod = TimerFreq_{CLK} / F_{PWM}@f$ */
CurrentRef_PulsePolarity pPolarity;
} CurrentRef_Handle_t;
/* Exported functions --------------------------------------------------------*/
void CRM_Init(CurrentRef_Handle_t *pHandle);
void CRM_Clear (CurrentRef_Handle_t *pHandle);
void CRM_SetReference(CurrentRef_Handle_t *pHandle, uint16_t hCnt);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* CURRENTREF_H */
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 3,046 | C | 28.582524 | 108 | 0.48851 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/impedcorr.h | /**
******************************************************************************
* @file impedcorr.h
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* impedcorr.h */
#ifndef _IMPEDCORR_H_
#define _IMPEDCORR_H_
#include "fixpmath.h"
#include <stddef.h>
typedef struct _IMPEDCORR_Params_
{
float_t voltageFilterPole_rps;
float_t cycleFreq_Hz;
float_t fullScaleFreq_Hz;
float_t KsampleDelay;
float_t fullScaleCurrent_A;
float_t fullScaleVoltage_V;
} IMPEDCORR_Params;
#define IMPEDCORR_SIZE_WORDS (50) /* Size in words, plus a margin */
typedef struct _IMPEDCORR_Obj_
{
/* Contents of this structure is not public */
uint16_t reserved[IMPEDCORR_SIZE_WORDS];
} IMPEDCORR_Obj;
typedef IMPEDCORR_Obj* IMPEDCORR_Handle;
/* Initialization */
extern IMPEDCORR_Handle IMPEDCORR_init(void *pMemory, const size_t size);
extern void IMPEDCORR_setParams(IMPEDCORR_Handle pHandle, const IMPEDCORR_Params *pParams);
/* Functional */
extern Voltages_Uab_t IMPEDCORR_run(IMPEDCORR_Handle pHandle,
const Currents_Iab_t* pIab_pu,
const Voltages_Uab_t* pUab_pu,
const fixp30_t Fe_pu
);
/* Accessors */
extern void IMPEDCORR_getEmf_ab_pu(const IMPEDCORR_Handle handle, Voltages_Uab_t* pEmf_ab);
extern void IMPEDCORR_getEmf_ab_filt_pu(const IMPEDCORR_Handle handle, Voltages_Uab_t* pE_ab);
extern Voltages_Uab_t IMPEDCORR_getEmf_ab_filt(const IMPEDCORR_Handle handle);
extern void IMPEDCORR_getIab_filt_pu(const IMPEDCORR_Handle handle, Currents_Iab_t* pIab_filt);
extern Currents_Iab_t IMPEDCORR_getIab_filt(const IMPEDCORR_Handle handle);
extern float_t IMPEDCORR_getKSampleDelay(const IMPEDCORR_Handle handle);
extern float_t IMPEDCORR_getLs_si(const IMPEDCORR_Handle pHandle);
extern FIXP_scaled_t IMPEDCORR_getRs_pu_fps(const IMPEDCORR_Handle handle);
extern float_t IMPEDCORR_getRs_si(const IMPEDCORR_Handle pHandle);
extern void IMPEDCORR_setKSampleDelay(IMPEDCORR_Handle handle, const float_t value);
extern void IMPEDCORR_setLs(IMPEDCORR_Handle handle, const fixp_t Ls_pu, const fixpFmt_t fmt);
extern void IMPEDCORR_setRs(IMPEDCORR_Handle handle, const fixp_t Rs_pu, const fixpFmt_t fmt);
extern void IMPEDCORR_setLs_si(IMPEDCORR_Handle pHandle, const float_t Ls_H);
extern void IMPEDCORR_setRs_si(IMPEDCORR_Handle pHandle, const float_t Rs_Ohm);
#endif /* _IMPEDCORR_H_ */
/* end of impedcorr.h */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 3,081 | C | 36.13253 | 95 | 0.668939 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/rsest.h | /**
******************************************************************************
* @file rsest.h
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* rsest.h */
#ifndef _RSEST_H_
#define _RSEST_H_
#include "fixpmath.h"
#include <stddef.h>
#include <stdbool.h>
typedef struct _RSEST_Params_
{
float_t FullScaleCurrent_A;
float_t FullScaleVoltage_V;
float_t RatedCelcius; /* Temperature @ Rated resistance value (deg C) */
float_t AmbientCelcius; /* Ambient Temperature (deg C) */
float_t RsRatedOhm;
float_t MotorSkinFactor; /* Motor skin-factor at choosen injection frequency */
float_t F_calculate_Hz;
float_t m_copper_kg; /* Total copper mass for heating estimation */
float_t coolingTau_s;
float_t correctionGain;
float_t injectGain;
} RSEST_Params;
typedef struct _RSEST_Obj_
{
float_t Tbackground; /* s */
float_t FullScaleImpedance_OHM; /* FullScaleVoltage/FullScaleCurrent */
float_t FullScaleAdmittance_MHO; /* FullScaleCurrent/FullScaleVoltage */
float_t FullScalePower_3ph_W; /* 1.5 * FullScaleCurrent * FullScaleVoltage */
float_t oneoverRs_rated_Mho; /* updated when rated value is changed */
uint16_t decimationCounter;
bool update_on;
bool current_is_low;
bool doBackground; // go command to achieve decimation
float_t rs_rated_ohm; //
float_t rs_ohm; // read/write in _runBackground
FIXP_scaled_t Rs_pu_fps; /* output in pu_fps format */
float_t rs_inject_ohm; // read/write in _runBackground
fixp30_t rs_inject_pur; // relative to Rrated
fixp_t correctionGain;
fixp_t injectGain;
/* Skin factor */
fixp_t SkinFactor; // Skinfactor Rac/Rdc normally slightly larger than 1.
fixp30_t T_calc; // 1/fBackground = backgroundinterval in seconds, used by _setRsBandwidth_Hz()
fixp30_t incRateLimit;
fixp30_t incRfactor;
uint16_t lpShiftVI; // Low pass filter bitshift for 'VI', voltage x current, used in power calculation
uint16_t lpShiftI2t;
/* Power-based resistance estimation */
// PowerLP and IsquaredLP are calculated in the interrupt and used in the background to
// calculate rs_power_ohm/rs_power_pu_fps. Both are updated only when current is above IsquaredThreshold_pu
fixp30_t PowerLP; // Power, low pass filtered (two phase: 2/3 of total power)
fixp30_t IsquaredLP; // Squared current, Low pass filtered, required for R = P/I^2 estimation.
fixp30_t IsquaredLPt; // faster version of squared current filtered
float_t TerminalPowerWatt; // total Terminal Power for all three phases
float_t rs_power_ohm; // power-based resistance
/* */
fixp20_t ratCelcius_pu; // ambiant temperature (deg C) this is where Rs=Rrated.
fixp20_t ambCelcius_pu;
fixp30_t ambRfactor;
fixp30_t deltaRfactor; /* TempRfactor increment */
fixp30_t maxRfactor; /* Limit outside ZEST operation */
fixp30_t TempRfactor; /* Active Rs/Rrated value */
fixp20_t TempCelcius; // approximate temperature guess
fixp30_t Thermal_K;
fixp30_t Thermal_Leak;
fixp30_t dither;
uint32_t debugTestCounter; /* should increase by 1000 counts per second (when flag_debug=true)*/
bool flag_debug;
bool synchTemp;
fixp20_t debug_TempCelcius;
fixp30_t debug_deltaRfactor;
fixp30_t debug_TempRfactor;
fixp30_t incRfactor_LP;
} RSEST_Obj;
typedef RSEST_Obj* RSEST_Handle;
extern RSEST_Handle RSEST_init(void *pMemory, const size_t size);
extern void RSEST_setParams(RSEST_Handle handle, const RSEST_Params *pParams);
/* Interrupt function (synchronous with sensorless algorithm) */
extern void RSEST_run(RSEST_Handle handle, const Currents_Iab_t *pIab_pu, const Voltages_Uab_t *pUab_pu);
/* Background function (~1 kHz) now spread out in mainloop */
extern void RSEST_runBackground(RSEST_Handle handle);
extern void RSEST_runBackSlowed(RSEST_Handle handle, const bool injectActive, const fixp30_t CheckRs, const float_t Rsdelta);
/* Getters */
extern bool RSEST_getCurrentIsLow(const RSEST_Handle handle);
extern bool RSEST_getDoBackGround(const RSEST_Handle handle);
extern fixp30_t RSEST_getRsInjectGainTs(const RSEST_Handle handle);
extern float RSEST_getRsInjectOhm(const RSEST_Handle handle);
extern float RSEST_getRsOhm(const RSEST_Handle handle);
extern float RSEST_getRsPowerOhm(const RSEST_Handle handle);
extern FIXP_scaled_t RSEST_getRsRated_fps(const RSEST_Handle handle);
extern FIXP_scaled_t RSEST_getRs_pu_fps(const RSEST_Handle handle);
extern fixp_t RSEST_getSkinFactor(const RSEST_Handle handle);
extern fixp20_t RSEST_getTempCelcius_pu(const RSEST_Handle handle);
/* Setters */
extern void RSEST_setAmbientCelcius_pu(RSEST_Handle handle, const fixp20_t value);
extern void RSEST_setInjectGain(RSEST_Handle handle, const fixp_t value);
extern void RSEST_setRsOhm(RSEST_Handle handle, const float_t rs_ohm);
extern void RSEST_setRsRatedOhm(RSEST_Handle handle, const float_t value);
extern void RSEST_setRsToRated(RSEST_Handle handle);
extern void RSEST_setRs_pu_fps(RSEST_Handle handle, const FIXP_scaled_t rs_pu_fps);
extern void RSEST_setSkinFactor(RSEST_Handle handle, const float_t value);
extern void RSEST_setTempRfactor(RSEST_Handle handle, const float_t value);
extern void RSEST_setUpdate_ON(RSEST_Handle handle, const bool value);
#endif /* _RSEST_H_ */
/* end of rsest.h */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 6,969 | C | 40.488095 | 160 | 0.602095 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/inrush_current_limiter.h | /**
******************************************************************************
* @file inrush_current_limiter.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* Inrush Current Limiter component featuring the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup ICL
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __INRUSHCURRENTLIMITER_H
#define __INRUSHCURRENTLIMITER_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
#include "bus_voltage_sensor.h"
#include "digital_output.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup ICL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief ICL_State_t defines all the existing ICL states of the state machine
*/
typedef enum
{
ICL_IDLE, /**< @brief stable state */
ICL_ACTIVATION, /**< @brief transition state */
ICL_ACTIVE, /**< @brief stable state */
ICL_DEACTIVATION, /**< @brief transition state */
ICL_INACTIVE /**< @brief stable state */
} ICL_State_t;
/**
* @brief ICL_Handle_t is used to handle an instance of the InrushCurrentLimiter component
*/
typedef struct
{
BusVoltageSensor_Handle_t *pVBS; /**< @brief Vbus handler used for the automatic ICL component activation/deactivation */
DOUT_handle_t *pDOUT; /**< @brief digital output handler used to physically activate/deactivate the ICL component */
ICL_State_t ICLstate; /**< @brief Current state of the ICL state machine */
uint16_t hICLTicksCounter; /**< @brief Buffer variable containing the number of clock events remaining for next state transition */
uint16_t hICLSwitchDelayTicks; /**< @brief ICL activation/deactivation delay due to switching action of relay (expressed in ICL FSM execution ticks) */
uint16_t hICLChargingDelayTicks; /**< @brief Input capacitors charging delay to be waited before closing relay (expressed in ICL FSM execution ticks)*/
uint16_t hICLVoltageThreshold; /**< @brief Voltage threshold to be reached on Vbus before closing the relay */
} ICL_Handle_t;
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Initializes all the needed ICL component variables */
void ICL_Init(ICL_Handle_t *pHandle, BusVoltageSensor_Handle_t *pVBS, DOUT_handle_t *pDOUT);
/* Executes the Inrush Current Limiter state machine */
ICL_State_t ICL_Exec(ICL_Handle_t *pHandle);
/* Returns the current state of the ICL state machine. */
ICL_State_t ICL_GetState(ICL_Handle_t *pHandle);
/**
* @brief Converts the VoltageThreshold configured by the user and updates the
* passed ICL's component threshold value in u16V (bus sensor units)
* @param pHandle: handler of the current instance of the ICL component
* @param hVoltageThreshold : threshold configured by the user to be applied in ICL FSM (expressed in Volts)
*/
inline static void ICL_SetVoltageThreshold(ICL_Handle_t *pHandle, int16_t hVoltageThreshold)
{
uint32_t temp;
temp = (uint32_t)hVoltageThreshold;
temp *= 65536U;
temp /= pHandle->pVBS->ConversionFactor;
pHandle->hICLVoltageThreshold = (uint16_t)temp;
}
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* __INRUSHCURRENTLIMITER_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 4,313 | C | 35.559322 | 156 | 0.588685 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/profiler.h | /**
******************************************************************************
* @file profiler.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* profiler component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup Profiler
*/
#ifndef _PROFILER_H_
#define _PROFILER_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "profiler_types.h"
#include "profiler_dcac.h"
#include "profiler_fluxestim.h"
#include "flash_parameters.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup Profiler
* @{
*/
/**
* @brief Profiler States, lists all the possible profiler state machine states
*
*/
typedef enum _PROFILER_State_e_
{
PROFILER_STATE_Idle, /*!< @brief Profiler Idle state */
PROFILER_STATE_DCandACcheck, /*!< @brief DC and AC measurement step */
PROFILER_STATE_FluxEstim, /*!< @brief Flux estimation step after DCAC step complete whitout error */
PROFILER_STATE_Complete, /*!< @brief Profiler complete state set when procedure is finished */
PROFILER_STATE_Error, /*!< @brief Error occurs when profiler procedure is not ready to start, mainly in two cases:
- Control Mode is not in Profiling mode
- or PWM are not in state forced to zero */
PROFILER_STATE_DCAC_Error, /*!< @brief Error occurs when DCAC profiler step failed, when measured Rs or Ls are out of expected ranges. */
PROFILER_STATE_FluxEstim_Error, /*!< @brief Error occurs when motor fails to spin during profiling */
} PROFILER_State_e;
/**
* @brief Profiler errors list
*
*/
typedef enum _PROFILER_Error_e_
{
PROFILER_ERROR_None, /*!< @brief No error detected */
PROFILER_ERROR_DCAC, /*!< @brief Measured motor parameters are out of expected ranges */
PROFILER_ERROR_FluxEstim, /*!< @brief Resulting speed from the flux observer (HSO) and the open loop frequency does not match */
PROFILER_ERROR_NotReady, /*!< @brief Profiling not ready to start, the procedure is not in a suitable state */
} PROFILER_Error_e;
/**
* @brief Profiler user commands list
*
*/
typedef enum _PROFILER_Command_e_
{
PROFILER_COMMAND_None, /*!< @brief Default state when no user command */
PROFILER_COMMAND_Start, /*!< @brief User command to start the profiler */
PROFILER_COMMAND_Reset, /*!< @brief User command to reset the profiler */
} PROFILER_Command_e;
/**
* @brief Handle of profiler component
*
* This structure holds all the parameters needed to implement the profiler
*
* A pointer on a structure of this type is passed to each
* function of the @ref Profiler.
*/
typedef struct _PROFILER_Obj_
{
PROFILER_State_e state; /*!< @brief Profiler state machine */
PROFILER_Command_e command; /*!< @brief User command state */
PROFILER_Error_e error; /*!< @brief Error message to report */
/* Profiler components */
PROFILER_DCAC_Obj dcacObj; /*!< @brief Handle of DCAC object */
PROFILER_FLUXESTIM_Obj fluxestimObj; /*!< @brief Handle of FluxEstim object */
/* Configuration */
float_t PolePairs; /*!< @brief Number of polepairs, for motors without gearbox this is the number of magnets divided by two.
For motors with gearbox, this is the number of magnets divided by two, multiplied by the reduction. */
float_t PowerDC_goal_W; /*!< @brief Profiler attempts to reach this power goal during DC ramp-up */
float_t dutyDC; /*!< @brief DC duty applied during profiling */
float_t Idc_A; /*!< @brief DC current (A) used during profiling */
float_t freqEst_Hz; /*!< @brief Open-loop estimated speed */
float_t freqHSO_Hz; /*!< @brief Estimated observer (HSO) speed */
float_t debug_Flux_VpHz; /*!< @brief Estimated flux in V/Hz (for debug only) */
float_t debug_kV; /*!< @brief rpm per Volt DC (for debug only) */
float_t CritFreq_Hz; /*!< @brief Frequency where Rs voltage drop would equal emf at used current level (for debug only) */
float_t injectFreq_Hz; /*!< @brief Injected AC frequency (Hz) during profiling */
float_t fullScaleFreq_Hz; /*!< @brief Full scale frequency (Hz) */
float_t fullScaleVoltage_V; /*!< @brief Full scale voltage (V) */
/* Levels reached */
float_t PowerDC_W; /*!< @brief Power actually reached during DC phase */
/* Identified values */
float_t Rs_dc; /*!< @brief Stator resistance measured using DC duty */
float_t Rs_ac; /*!< @brief Stator resistance measured using AC duty */
float_t R_factor; /*!< @brief Resitance factor = Rs_dc/Rs_ac */
float_t Ld_H; /*!< @brief D-axis inductance measured using AC duty */
float_t Lq_H; /*!< @brief Q-axis inductance is not seperately measured */
float_t Flux_Wb; /*!< @brief Flux measured while running motor */
/* Motor characteristics */
float_t KT_Nm_A; /*!< @brief Torque per Amp (Nm/Apeak) */
float_t Isc_A; /*!< @brief Short circuit current, Flux/Inductance */
/* inital value */
fixp30_t injectFreq_HzZest; /*!< @brief ZeST injected frequency stored before to start profiling */
fixp30_t injectIdZest; /*!< @brief ZeST Injection D current stored before to start profiling */
fixp30_t gainDZest; /*!< @brief ZeST Gain D stored before to start profiling */
fixp30_t gainQZest; /*!< @brief ZeST Gain Q stored before to start profiling */
} PROFILER_Obj;
#include "profiler_handle.h"
void PROFILER_init(PROFILER_Handle handle,
PROFILER_Params* pParams,
FLASH_Params_t const *flashParams);
void PROFILER_reset(PROFILER_Handle handle, MOTOR_Handle motor);
void PROFILER_run(PROFILER_Handle handle, MOTOR_Handle motor);
void PROFILER_runBackground(PROFILER_Handle handle, MOTOR_Handle motor);
/* Accessors */
float_t PROFILER_getDcAcMeasurementTime(PROFILER_Handle handle);
float_t PROFILER_getFlux_Wb(const PROFILER_Handle handle);
float_t PROFILER_getFluxEstFreq_Hz(const PROFILER_Handle handle);
float_t PROFILER_getFluxEstMeasurementTime(PROFILER_Handle handle);
float_t PROFILER_getLd_H(const PROFILER_Handle handle);
float_t PROFILER_getPowerGoal_W(const PROFILER_Handle handle);
float_t PROFILER_getRs_ac(const PROFILER_Handle handle);
float_t PROFILER_getRs_dc(const PROFILER_Handle handle);
void PROFILER_setCommand(PROFILER_Handle handle, const PROFILER_Command_e command);
void PROFILER_setDcAcMeasurementTime(PROFILER_Handle handle, const float_t time_seconds);
void PROFILER_setFluxEstFreq_Hz(PROFILER_Handle handle, const float_t fluxEstFreq_Hz);
void PROFILER_setFluxEstMeasurementTime(PROFILER_Handle handle, const float_t time_seconds);
void PROFILER_setPolePairs(PROFILER_Handle handle, const float_t polepairs);
void PROFILER_setPowerGoal_W(PROFILER_Handle handle, const float_t powerGoal_W);
void PROFILER_resetEstimates(PROFILER_Handle handle);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* _PROFILER_H_ */
| 7,928 | C | 42.092391 | 144 | 0.637235 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/flux_weakening_ctrl.h | /**
******************************************************************************
* @file flux_weakening_ctrl.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file provides all definitions and functions prototypes for the
* Flux Weakening Control component of the Motor Control SDK.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup FluxWeakeningCtrl
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef FLUXWEAKENINGCTRL_H
#define FLUXWEAKENINGCTRL_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
#include "pid_regulator.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup FluxWeakeningCtrl
* @{
*/
/**
* @brief Flux Weakening Control Component handle structure
*/
typedef struct
{
PID_Handle_t *pFluxWeakeningPID; /**< @brief PI object used for flux weakening. */
PID_Handle_t *pSpeedPID; /**< @brief PI object used for speed control. */
uint16_t hFW_V_Ref; /**< @brief Voltage reference, expressed in tenth ofpercentage points. */
qd_t AvVolt_qd; /**< @brief Average stator voltage in qd reference frame. */
int16_t AvVoltAmpl; /**< @brief Average stator voltage amplitude. */
int16_t hIdRefOffset; /**< @brief Id reference offset. */
uint16_t hMaxModule; /**< @brief Circle limitation maximum allowed module. */
uint16_t hDefaultFW_V_Ref; /**< @brief Default flux weakening voltage reference,tenth of percentage
points. */
int16_t hDemagCurrent; /**< @brief Demagnetization current in s16A:
Current(Amp) = [Current(s16A) * Vdd micro] / [65536 * Rshunt * Aop]. */
int32_t wNominalSqCurr; /**< @brief Squared motor nominal current in (s16A)^2
where:
Current(Amp) = [Current(s16A) * Vdd micro] / [65536 * Rshunt * Aop]. */
uint16_t hVqdLowPassFilterBW; /**< @brief Use this parameter to configure the Vqd first order software
filter bandwidth. hVqdLowPassFilterBW = FOC_CurrController call rate
[Hz]/ FilterBandwidth[Hz] in case FULL_MISRA_COMPLIANCY is defined.
On the contrary, if FULL_MISRA_COMPLIANCY is not defined,
hVqdLowPassFilterBW is equal to log with base two of previous
definition. */
uint16_t hVqdLowPassFilterBWLOG; /**< @brief hVqdLowPassFilterBW expressed as power of 2.
E.g. if gain divisor is 512 the value must be 9 because 2^9 = 512. */
} FW_Handle_t;
/* Exported functions ------------------------------------------------------- */
/**
* Initializes flux weakening component handler
*/
void FW_Init(FW_Handle_t *pHandle, PID_Handle_t *pPIDSpeed, PID_Handle_t *pPIDFluxWeakeningHandle);
/**
* Clears the flux weakening internal variables
*/
void FW_Clear(FW_Handle_t *pHandle);
/**
* Computes Iqdref according the flux weakening algorithm
*/
qd_t FW_CalcCurrRef(FW_Handle_t *pHandle, qd_t Iqdref);
/**
* Applies a low-pass filter on both Vqd voltage components
*/
void FW_DataProcess(FW_Handle_t *pHandle, qd_t Vqd);
/**
* Sets a new value for the voltage reference used by
* flux weakening algorithm
*/
void FW_SetVref(FW_Handle_t *pHandle, uint16_t hNewVref);
/**
* Returns the present value of target voltage used by flux
* weakening algorihtm
*/
uint16_t FW_GetVref(FW_Handle_t *pHandle);
/**
* Returns the present value of voltage actually used by flux
* weakening algorihtm
*/
int16_t FW_GetAvVAmplitude(FW_Handle_t *pHandle);
/**
* Returns the measure of present voltage actually used by flux
* weakening algorihtm as percentage of available voltage
*/
uint16_t FW_GetAvVPercentage(FW_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* FLUXWEAKENINGCTRL_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,004 | C | 37.206107 | 118 | 0.546163 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/mathlib.h | /**
******************************************************************************
* @file mathlib.h
* @author Piak Electronic Design B.V.
* @brief This file is part of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 Piak Electronic Design B.V.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* mathlib.h */
#ifndef _MATHLIB_H_
#define _MATHLIB_H_
#include <stdint.h>
typedef struct _Vector_cossin_s_
{
int32_t cos;
int32_t sin;
} Vector_cossin_s;
/* Initialize mathlib by calculating/loading tables */
void MATHLIB_init(void);
/* Convert to polar form, calculating angle and magnitude of vector */
void MATHLIB_polar(const int32_t x, const int32_t y, int32_t *angle_pu, int32_t *magnitude);
/* Calculate cosine and sine from angle in per-unit */
Vector_cossin_s MATHLIB_cossin(int32_t angle_pu);
#endif /* _MATHLIB_H_ */
/* end of mathlib.h */
/************************ (C) COPYRIGHT 2023 Piak Electronic Design B.V. *****END OF FILE****/
| 1,435 | C | 29.553191 | 94 | 0.542857 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/ntc_temperature_sensor.h | /**
******************************************************************************
* @file ntc_temperature_sensor.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains all definitions and functions prototypes for the
* Temperature Sensor component of the Motor Control SDK.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup TemperatureSensor
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef TEMPERATURESENSOR_H
#define TEMPERATURESENSOR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "mc_type.h"
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup TemperatureSensor
* @{
*/
/**
* @brief Structure used for temperature monitoring
*
*/
typedef struct
{
SensorType_t bSensorType; /**< Type of instanced temperature.
This parameter can be REAL_SENSOR or VIRTUAL_SENSOR. */
uint16_t hAvTemp_d; /**< It contains latest available average Vbus.
This parameter is expressed in u16Celsius. */
uint16_t hExpectedTemp_d; /**< Default set when no sensor available (ie virtual sensor) */
uint16_t hExpectedTemp_C; /**< Default value when no sensor available (ie virtual sensor).
This parameter is expressed in Celsius. */
uint16_t hFaultState; /**< Contains latest Fault code.
This parameter is set to #MC_OVER_TEMP or #MC_NO_ERROR. */
uint16_t hLowPassFilterBW; /**< used to configure the first order software filter bandwidth.
hLowPassFilterBW = NTC_CalcBusReading
call rate [Hz]/ FilterBandwidth[Hz]. */
uint16_t hOverTempThreshold; /**< Represents the over voltage protection intervention threshold.
This parameter is expressed in u16Celsius through formula:
hOverTempThreshold =
(V0[V]+dV/dT[V/°C]*(OverTempThreshold[°C] - T0[°C]))* 65536 /
MCU supply voltage. */
uint16_t hOverTempDeactThreshold; /**< Temperature threshold below which an active over temperature fault is cleared.
This parameter is expressed in u16Celsius through formula:
hOverTempDeactThreshold =
(V0[V]+dV/dT[V/°C]*(OverTempDeactThresh[°C] - T0[°C]))* 65536 /
MCU supply voltage. */
int16_t hSensitivity; /**< NTC sensitivity
This parameter is equal to MCU supply voltage [V] / dV/dT [V/°C] */
uint32_t wV0; /**< V0 voltage constant value used to convert the temperature into Volts.
This parameter is equal V0*65536/MCU supply
Used in through formula: V[V]=V0+dV/dT[V/°C]*(T-T0)[°C] */
uint16_t hT0; /**< T0 temperature constant value used to convert the temperature into Volts
Used in through formula: V[V]=V0+dV/dT[V/°C]*(T-T0)[°C] */
uint8_t convHandle; /*!< handle to the regular conversion. */
} NTC_Handle_t;
/* Initialize temperature sensing parameters */
void NTC_Init(NTC_Handle_t *pHandle);
/* Clear static average temperature value */
void NTC_Clear(NTC_Handle_t *pHandle);
/* Temperature sensing computation */
uint16_t NTC_CalcAvTemp(NTC_Handle_t *pHandle, uint16_t rawValue);
/* Get averaged temperature measurement expressed in u16Celsius */
uint16_t NTC_GetAvTemp_d(const NTC_Handle_t *pHandle);
/* Get averaged temperature measurement expressed in Celsius degrees */
int16_t NTC_GetAvTemp_C(NTC_Handle_t *pHandle);
/* Get the temperature measurement fault status */
uint16_t NTC_CheckTemp(const NTC_Handle_t *pHandle);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cpluplus */
#endif /* TEMPERATURESENSOR_H */
/************************ (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 4,939 | C | 40.512605 | 119 | 0.530877 |
Tbarkin121/GuardDog/stm32/MotorDrive/MCSDK_v6.2.0-Full/MotorControl/MCSDK/MCLib/Any/Inc/r1_dd_pwm_curr_fdbk.h | /**
******************************************************************************
* @file r1_dd_pwm_curr_fdbk.h
* @author Motor Control SDK Team, ST Microelectronics
* @brief This file contains common definitions for Single Shunt, Dual Drives
* PWM and Current Feedback components.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2023 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
* @ingroup PWMnCurrFdbk_R1_DD
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __R1_DD_PWM_CURR_FDBK_H
#define __R1_DD_PWM_CURR_FDBK_H
#define GPIO_NoRemap_TIM1 ((uint32_t)(0))
#define SAME_FREQ 0u
/** @addtogroup MCSDK
* @{
*/
/** @addtogroup pwm_curr_fdbk
* @{
*/
/** @defgroup PWMnCurrFdbk_R1_DD Single Shunt Dual Drive Parameters
*
* @brief Common definitions for Single Shunt, Dual Drives PWM and Current Feedback components
*
* @{
*/
/**
* @brief R1 DD parameters definition
*/
typedef struct
{
TIM_TypeDef *TIMx; /*!< Timer used for PWM generation. It should be
TIM1 or TIM8*/
TIM_TypeDef *TIMx_2; /*!< Auxiliary timer used for single shunt */
ADC_TypeDef *ADCx_Inj; /*!< ADC Peripheral used for phase current sampling */
ADC_TypeDef *ADCx_Reg; /*!< ADC Peripheral used for regular conversion */
GPIO_TypeDef *pwm_en_u_port;
GPIO_TypeDef *pwm_en_v_port;
GPIO_TypeDef *pwm_en_w_port;
uint32_t pwm_en_u_pin;
uint32_t pwm_en_v_pin;
uint32_t pwm_en_w_pin;
uint16_t Tafter; /*!< It is the sum of dead time plus rise time
express in number of TIM clocks.*/
uint16_t Tbefore; /*!< It is the value of sampling time
expressed in numbers of TIM clocks.*/
uint16_t TMin; /*!< It is the sum of dead time plus rise time
plus sampling time express in numbers of
TIM clocks.*/
uint16_t HTMin; /*!< It is the half of TMin value.*/
uint16_t TSample; /*!< It is the sampling time express in
numbers of TIM clocks.*/
uint16_t MaxTrTs; /*!< It is the maximum between twice of rise
time express in number of TIM clocks and
twice of sampling time express in numbers
of TIM clocks.*/
uint16_t DeadTime; /*!< Dead time in number of TIM clock
cycles. If CHxN are enabled, it must
contain the dead time to be generated
by the microcontroller, otherwise it
expresses the maximum dead time
generated by driving network*/
uint8_t FreqRatio; /*!< It is used in case of dual MC to
synchronize times. It must be equal
to the ratio between the two PWM
frequencies (higher/lower).
Supported values are 1, 2 or 3 */
uint8_t IsHigherFreqTim; /*!< When bFreqRatio is greather than 1
this param is used to indicate if this
instance is the one with the highest
frequency. Allowed value are: HIGHER_FREQ
or LOWER_FREQ */
uint8_t InstanceNbr; /*!< Instance number with reference to PWMC
base class. It is necessary to properly
synchronize TIM8 with TIM1 at peripheral
initializations */
uint8_t IChannel; /*!< ADC channel used for conversion of
current. It must be equal to
ADC_CHANNEL_x x= 0, ..., 15*/
uint8_t RepetitionCounter; /*!< It expresses the number of PWM
periods to be elapsed before compare
registers are updated again. In
particular:
RepetitionCounter= (2* PWM periods) -1*/
bool IsFirstR1DDInstance; /*!< Specifies whether this object is the first
R1DD instance or not.*/
LowSideOutputsFunction_t LowSideOutputs; /*!< Low side or enabling signals
generation method are defined
here.*/
} R1_DDParams_t;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /*__R1_DD_PWM_CURR_FDBK_H*/
/******************* (C) COPYRIGHT 2023 STMicroelectronics *****END OF FILE****/
| 5,608 | C | 43.515873 | 95 | 0.465763 |
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