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Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
} | module BranchKillableQueue_5(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [6:0] io_enq_bits_uop_uopc,
input [31:0] io_enq_bits_uop_inst,
input [31:0] io_enq_bits_uop_debug_inst,
input io_enq_bits_uop_is_rvc,
input [39:0] io_enq_bits_uop_debug_pc,
input [2:0] io_enq_bits_uop_iq_type,
input [9:0] io_enq_bits_uop_fu_code,
input [3:0] io_enq_bits_uop_ctrl_br_type,
input [1:0] io_enq_bits_uop_ctrl_op1_sel,
input [2:0] io_enq_bits_uop_ctrl_op2_sel,
input [2:0] io_enq_bits_uop_ctrl_imm_sel,
input [4:0] io_enq_bits_uop_ctrl_op_fcn,
input io_enq_bits_uop_ctrl_fcn_dw,
input [2:0] io_enq_bits_uop_ctrl_csr_cmd,
input io_enq_bits_uop_ctrl_is_load,
input io_enq_bits_uop_ctrl_is_sta,
input io_enq_bits_uop_ctrl_is_std,
input [1:0] io_enq_bits_uop_iw_state,
input io_enq_bits_uop_iw_p1_poisoned,
input io_enq_bits_uop_iw_p2_poisoned,
input io_enq_bits_uop_is_br,
input io_enq_bits_uop_is_jalr,
input io_enq_bits_uop_is_jal,
input io_enq_bits_uop_is_sfb,
input [7:0] io_enq_bits_uop_br_mask,
input [2:0] io_enq_bits_uop_br_tag,
input [3:0] io_enq_bits_uop_ftq_idx,
input io_enq_bits_uop_edge_inst,
input [5:0] io_enq_bits_uop_pc_lob,
input io_enq_bits_uop_taken,
input [19:0] io_enq_bits_uop_imm_packed,
input [11:0] io_enq_bits_uop_csr_addr,
input [4:0] io_enq_bits_uop_rob_idx,
input [2:0] io_enq_bits_uop_ldq_idx,
input [2:0] io_enq_bits_uop_stq_idx,
input [1:0] io_enq_bits_uop_rxq_idx,
input [5:0] io_enq_bits_uop_pdst,
input [5:0] io_enq_bits_uop_prs1,
input [5:0] io_enq_bits_uop_prs2,
input [5:0] io_enq_bits_uop_prs3,
input [3:0] io_enq_bits_uop_ppred,
input io_enq_bits_uop_prs1_busy,
input io_enq_bits_uop_prs2_busy,
input io_enq_bits_uop_prs3_busy,
input io_enq_bits_uop_ppred_busy,
input [5:0] io_enq_bits_uop_stale_pdst,
input io_enq_bits_uop_exception,
input [63:0] io_enq_bits_uop_exc_cause,
input io_enq_bits_uop_bypassable,
input [4:0] io_enq_bits_uop_mem_cmd,
input [1:0] io_enq_bits_uop_mem_size,
input io_enq_bits_uop_mem_signed,
input io_enq_bits_uop_is_fence,
input io_enq_bits_uop_is_fencei,
input io_enq_bits_uop_is_amo,
input io_enq_bits_uop_uses_ldq,
input io_enq_bits_uop_uses_stq,
input io_enq_bits_uop_is_sys_pc2epc,
input io_enq_bits_uop_is_unique,
input io_enq_bits_uop_flush_on_commit,
input io_enq_bits_uop_ldst_is_rs1,
input [5:0] io_enq_bits_uop_ldst,
input [5:0] io_enq_bits_uop_lrs1,
input [5:0] io_enq_bits_uop_lrs2,
input [5:0] io_enq_bits_uop_lrs3,
input io_enq_bits_uop_ldst_val,
input [1:0] io_enq_bits_uop_dst_rtype,
input [1:0] io_enq_bits_uop_lrs1_rtype,
input [1:0] io_enq_bits_uop_lrs2_rtype,
input io_enq_bits_uop_frs3_en,
input io_enq_bits_uop_fp_val,
input io_enq_bits_uop_fp_single,
input io_enq_bits_uop_xcpt_pf_if,
input io_enq_bits_uop_xcpt_ae_if,
input io_enq_bits_uop_xcpt_ma_if,
input io_enq_bits_uop_bp_debug_if,
input io_enq_bits_uop_bp_xcpt_if,
input [1:0] io_enq_bits_uop_debug_fsrc,
input [1:0] io_enq_bits_uop_debug_tsrc,
input [64:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [6:0] io_deq_bits_uop_uopc,
output [7:0] io_deq_bits_uop_br_mask,
output [4:0] io_deq_bits_uop_rob_idx,
output [2:0] io_deq_bits_uop_stq_idx,
output [5:0] io_deq_bits_uop_pdst,
output io_deq_bits_uop_is_amo,
output io_deq_bits_uop_uses_stq,
output [1:0] io_deq_bits_uop_dst_rtype,
output io_deq_bits_uop_fp_val,
output [64:0] io_deq_bits_data,
output io_deq_bits_predicated,
output io_deq_bits_fflags_valid,
output [4:0] io_deq_bits_fflags_bits_uop_rob_idx,
output [4:0] io_deq_bits_fflags_bits_flags,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask,
input io_flush,
output io_empty
);
wire [76:0] _ram_ext_R0_data;
reg valids_0;
reg valids_1;
reg valids_2;
reg [6:0] uops_0_uopc;
reg [7:0] uops_0_br_mask;
reg [4:0] uops_0_rob_idx;
reg [2:0] uops_0_stq_idx;
reg [5:0] uops_0_pdst;
reg uops_0_is_amo;
reg uops_0_uses_stq;
reg [1:0] uops_0_dst_rtype;
reg uops_0_fp_val;
reg [6:0] uops_1_uopc;
reg [7:0] uops_1_br_mask;
reg [4:0] uops_1_rob_idx;
reg [2:0] uops_1_stq_idx;
reg [5:0] uops_1_pdst;
reg uops_1_is_amo;
reg uops_1_uses_stq;
reg [1:0] uops_1_dst_rtype;
reg uops_1_fp_val;
reg [6:0] uops_2_uopc;
reg [7:0] uops_2_br_mask;
reg [4:0] uops_2_rob_idx;
reg [2:0] uops_2_stq_idx;
reg [5:0] uops_2_pdst;
reg uops_2_is_amo;
reg uops_2_uses_stq;
reg [1:0] uops_2_dst_rtype;
reg uops_2_fp_val;
reg [1:0] enq_ptr_value;
reg [1:0] deq_ptr_value;
reg maybe_full;
wire ptr_match = enq_ptr_value == deq_ptr_value;
wire io_empty_0 = ptr_match & ~maybe_full;
wire full = ptr_match & maybe_full;
wire [3:0] _GEN = {{valids_0}, {valids_2}, {valids_1}, {valids_0}};
wire _GEN_0 = _GEN[deq_ptr_value];
wire [3:0][6:0] _GEN_1 = {{uops_0_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}};
wire [3:0][7:0] _GEN_2 = {{uops_0_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}};
wire [7:0] out_uop_br_mask = _GEN_2[deq_ptr_value];
wire [3:0][4:0] _GEN_3 = {{uops_0_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}};
wire [3:0][2:0] _GEN_4 = {{uops_0_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}};
wire [3:0][5:0] _GEN_5 = {{uops_0_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}};
wire [3:0] _GEN_6 = {{uops_0_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}};
wire [3:0] _GEN_7 = {{uops_0_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}};
wire [3:0][1:0] _GEN_8 = {{uops_0_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}};
wire [3:0] _GEN_9 = {{uops_0_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}};
wire do_deq = ~io_empty_0 & (io_deq_ready | ~_GEN_0) & ~io_empty_0;
wire do_enq = ~(io_empty_0 & io_deq_ready) & ~full & io_enq_valid;
wire _GEN_10 = enq_ptr_value == 2'h0;
wire _GEN_11 = do_enq & _GEN_10;
wire _GEN_12 = enq_ptr_value == 2'h1;
wire _GEN_13 = do_enq & _GEN_12;
wire _GEN_14 = enq_ptr_value == 2'h2;
wire _GEN_15 = do_enq & _GEN_14;
wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;
always @(posedge clock) begin
if (reset) begin
valids_0 <= 1'h0;
valids_1 <= 1'h0;
valids_2 <= 1'h0;
enq_ptr_value <= 2'h0;
deq_ptr_value <= 2'h0;
maybe_full <= 1'h0;
end
else begin
valids_0 <= ~(do_deq & deq_ptr_value == 2'h0) & (_GEN_11 | valids_0 & (io_brupdate_b1_mispredict_mask & uops_0_br_mask) == 8'h0 & ~io_flush);
valids_1 <= ~(do_deq & deq_ptr_value == 2'h1) & (_GEN_13 | valids_1 & (io_brupdate_b1_mispredict_mask & uops_1_br_mask) == 8'h0 & ~io_flush);
valids_2 <= ~(do_deq & deq_ptr_value == 2'h2) & (_GEN_15 | valids_2 & (io_brupdate_b1_mispredict_mask & uops_2_br_mask) == 8'h0 & ~io_flush);
if (do_enq)
enq_ptr_value <= enq_ptr_value == 2'h2 ? 2'h0 : enq_ptr_value + 2'h1;
if (do_deq)
deq_ptr_value <= deq_ptr_value == 2'h2 ? 2'h0 : deq_ptr_value + 2'h1;
if (~(do_enq == do_deq))
maybe_full <= do_enq;
end
if (_GEN_11) begin
uops_0_uopc <= io_enq_bits_uop_uopc;
uops_0_rob_idx <= io_enq_bits_uop_rob_idx;
uops_0_stq_idx <= io_enq_bits_uop_stq_idx;
uops_0_pdst <= io_enq_bits_uop_pdst;
uops_0_is_amo <= io_enq_bits_uop_is_amo;
uops_0_uses_stq <= io_enq_bits_uop_uses_stq;
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_0_fp_val <= io_enq_bits_uop_fp_val;
end
uops_0_br_mask <= do_enq & _GEN_10 ? _uops_br_mask_T_1 : ({8{~valids_0}} | ~io_brupdate_b1_resolve_mask) & uops_0_br_mask;
if (_GEN_13) begin
uops_1_uopc <= io_enq_bits_uop_uopc;
uops_1_rob_idx <= io_enq_bits_uop_rob_idx;
uops_1_stq_idx <= io_enq_bits_uop_stq_idx;
uops_1_pdst <= io_enq_bits_uop_pdst;
uops_1_is_amo <= io_enq_bits_uop_is_amo;
uops_1_uses_stq <= io_enq_bits_uop_uses_stq;
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_1_fp_val <= io_enq_bits_uop_fp_val;
end
uops_1_br_mask <= do_enq & _GEN_12 ? _uops_br_mask_T_1 : ({8{~valids_1}} | ~io_brupdate_b1_resolve_mask) & uops_1_br_mask;
if (_GEN_15) begin
uops_2_uopc <= io_enq_bits_uop_uopc;
uops_2_rob_idx <= io_enq_bits_uop_rob_idx;
uops_2_stq_idx <= io_enq_bits_uop_stq_idx;
uops_2_pdst <= io_enq_bits_uop_pdst;
uops_2_is_amo <= io_enq_bits_uop_is_amo;
uops_2_uses_stq <= io_enq_bits_uop_uses_stq;
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_2_fp_val <= io_enq_bits_uop_fp_val;
end
uops_2_br_mask <= do_enq & _GEN_14 ? _uops_br_mask_T_1 : ({8{~valids_2}} | ~io_brupdate_b1_resolve_mask) & uops_2_br_mask;
end
ram_3x77 ram_ext (
.R0_addr (deq_ptr_value),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value),
.W0_en (do_enq),
.W0_clk (clock),
.W0_data ({12'h0, io_enq_bits_data})
);
assign io_enq_ready = ~full;
assign io_deq_valid = io_empty_0 ? io_enq_valid : ~io_empty_0 & _GEN_0 & (io_brupdate_b1_mispredict_mask & out_uop_br_mask) == 8'h0 & ~io_flush;
assign io_deq_bits_uop_uopc = io_empty_0 ? io_enq_bits_uop_uopc : _GEN_1[deq_ptr_value];
assign io_deq_bits_uop_br_mask = io_empty_0 ? io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask : out_uop_br_mask & ~io_brupdate_b1_resolve_mask;
assign io_deq_bits_uop_rob_idx = io_empty_0 ? io_enq_bits_uop_rob_idx : _GEN_3[deq_ptr_value];
assign io_deq_bits_uop_stq_idx = io_empty_0 ? io_enq_bits_uop_stq_idx : _GEN_4[deq_ptr_value];
assign io_deq_bits_uop_pdst = io_empty_0 ? io_enq_bits_uop_pdst : _GEN_5[deq_ptr_value];
assign io_deq_bits_uop_is_amo = io_empty_0 ? io_enq_bits_uop_is_amo : _GEN_6[deq_ptr_value];
assign io_deq_bits_uop_uses_stq = io_empty_0 ? io_enq_bits_uop_uses_stq : _GEN_7[deq_ptr_value];
assign io_deq_bits_uop_dst_rtype = io_empty_0 ? io_enq_bits_uop_dst_rtype : _GEN_8[deq_ptr_value];
assign io_deq_bits_uop_fp_val = io_empty_0 ? io_enq_bits_uop_fp_val : _GEN_9[deq_ptr_value];
assign io_deq_bits_data = io_empty_0 ? io_enq_bits_data : _ram_ext_R0_data[64:0];
assign io_deq_bits_predicated = ~io_empty_0 & _ram_ext_R0_data[65];
assign io_deq_bits_fflags_valid = ~io_empty_0 & _ram_ext_R0_data[66];
assign io_deq_bits_fflags_bits_uop_rob_idx = io_empty_0 ? 5'h0 : _ram_ext_R0_data[71:67];
assign io_deq_bits_fflags_bits_flags = io_empty_0 ? 5'h0 : _ram_ext_R0_data[76:72];
assign io_empty = io_empty_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
} | module ClockCrossingReg_w43(
input clock,
input [42:0] io_d,
output [42:0] io_q,
input io_en
);
reg [42:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat,log2Up}
import org.chipsalliance.cde.config.Parameters
class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
{
val io = IO(new Bundle {
val requestor = Flipped(Vec(n, new HellaCacheIO))
val mem = new HellaCacheIO
})
if (n == 1) {
io.mem <> io.requestor.head
} else {
val s1_id = Reg(UInt())
val s2_id = RegNext(s1_id)
io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_||_)
io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
io.requestor(0).req.ready := io.mem.req.ready
for (i <- 1 until n)
io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid
for (i <- n-1 to 0 by -1) {
val req = io.requestor(i).req
def connect_s0() = {
io.mem.req.bits := req.bits
io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W))
s1_id := i.U
}
def connect_s1() = {
io.mem.s1_kill := io.requestor(i).s1_kill
io.mem.s1_data := io.requestor(i).s1_data
}
def connect_s2() = {
io.mem.s2_kill := io.requestor(i).s2_kill
}
if (i == n-1) {
connect_s0()
connect_s1()
connect_s2()
} else {
when (req.valid) { connect_s0() }
when (s1_id === i.U) { connect_s1() }
when (s2_id === i.U) { connect_s2() }
}
}
io.mem.uncached_resp.foreach(_.ready := false.B)
for (i <- 0 until n) {
val resp = io.requestor(i).resp
val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U
resp.valid := io.mem.resp.valid && tag_hit
io.requestor(i).s2_xcpt := io.mem.s2_xcpt
io.requestor(i).s2_gpa := io.mem.s2_gpa
io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte
io.requestor(i).ordered := io.mem.ordered
io.requestor(i).store_pending := io.mem.store_pending
io.requestor(i).perf := io.mem.perf
io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U
io.requestor(i).s2_nack_cause_raw := io.mem.s2_nack_cause_raw
io.requestor(i).s2_uncached := io.mem.s2_uncached
io.requestor(i).s2_paddr := io.mem.s2_paddr
io.requestor(i).clock_enabled := io.mem.clock_enabled
resp.bits := io.mem.resp.bits
resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
io.requestor(i).replay_next := io.mem.replay_next
io.requestor(i).uncached_resp.map { uncached_resp =>
val uncached_tag_hit = io.mem.uncached_resp.get.bits.tag(log2Up(n)-1,0) === i.U
uncached_resp.valid := io.mem.uncached_resp.get.valid && uncached_tag_hit
when (uncached_resp.ready && uncached_tag_hit) {
io.mem.uncached_resp.get.ready := true.B
}
uncached_resp.bits := io.mem.uncached_resp.get.bits
uncached_resp.bits.tag := io.mem.uncached_resp.get.bits.tag >> log2Up(n)
}
}
}
} | module HellaCacheArbiter(
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [39:0] io_requestor_0_req_bits_addr,
input io_requestor_0_s1_kill,
output io_requestor_0_s2_nack,
output io_requestor_0_resp_valid,
output [63:0] io_requestor_0_resp_bits_data,
output io_requestor_0_s2_xcpt_ae_ld,
input io_mem_req_ready,
output io_mem_req_valid,
output [39:0] io_mem_req_bits_addr,
output io_mem_s1_kill,
input io_mem_s2_nack,
input io_mem_resp_valid,
input [63:0] io_mem_resp_bits_data,
input io_mem_s2_xcpt_ae_ld
);
assign io_requestor_0_req_ready = io_mem_req_ready;
assign io_requestor_0_s2_nack = io_mem_s2_nack;
assign io_requestor_0_resp_valid = io_mem_resp_valid;
assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data;
assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld;
assign io_mem_req_valid = io_requestor_0_req_valid;
assign io_mem_req_bits_addr = io_requestor_0_req_bits_addr;
assign io_mem_s1_kill = io_requestor_0_s1_kill;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module table_2(
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [47:0] R0_data,
input [7:0] W0_addr,
input W0_clk,
input [47:0] W0_data,
input [3:0] W0_mask
);
table_0_ext table_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Rename Map Table
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import boom.v3.common._
import boom.v3.util._
import org.chipsalliance.cde.config.Parameters
class MapReq(val lregSz: Int) extends Bundle
{
val lrs1 = UInt(lregSz.W)
val lrs2 = UInt(lregSz.W)
val lrs3 = UInt(lregSz.W)
val ldst = UInt(lregSz.W)
}
class MapResp(val pregSz: Int) extends Bundle
{
val prs1 = UInt(pregSz.W)
val prs2 = UInt(pregSz.W)
val prs3 = UInt(pregSz.W)
val stale_pdst = UInt(pregSz.W)
}
class RemapReq(val lregSz: Int, val pregSz: Int) extends Bundle
{
val ldst = UInt(lregSz.W)
val pdst = UInt(pregSz.W)
val valid = Bool()
}
class RenameMapTable(
val plWidth: Int,
val numLregs: Int,
val numPregs: Int,
val bypass: Boolean,
val float: Boolean)
(implicit p: Parameters) extends BoomModule
{
val pregSz = log2Ceil(numPregs)
val io = IO(new BoomBundle()(p) {
// Logical sources -> physical sources.
val map_reqs = Input(Vec(plWidth, new MapReq(lregSz)))
val map_resps = Output(Vec(plWidth, new MapResp(pregSz)))
// Remapping an ldst to a newly allocated pdst?
val remap_reqs = Input(Vec(plWidth, new RemapReq(lregSz, pregSz)))
// Dispatching branches: need to take snapshots of table state.
val ren_br_tags = Input(Vec(plWidth, Valid(UInt(brTagSz.W))))
// Signals for restoring state following misspeculation.
val brupdate = Input(new BrUpdateInfo)
val rollback = Input(Bool())
})
// The map table register array and its branch snapshots.
val map_table = RegInit(VecInit(Seq.fill(numLregs){0.U(pregSz.W)}))
val br_snapshots = Reg(Vec(maxBrCount, Vec(numLregs, UInt(pregSz.W))))
// The intermediate states of the map table following modification by each pipeline slot.
val remap_table = Wire(Vec(plWidth+1, Vec(numLregs, UInt(pregSz.W))))
// Uops requesting changes to the map table.
val remap_pdsts = io.remap_reqs map (_.pdst)
val remap_ldsts_oh = io.remap_reqs map (req => UIntToOH(req.ldst) & Fill(numLregs, req.valid.asUInt))
// Figure out the new mappings seen by each pipeline slot.
for (i <- 0 until numLregs) {
if (i == 0 && !float) {
for (j <- 0 until plWidth+1) {
remap_table(j)(i) := 0.U
}
} else {
val remapped_row = (remap_ldsts_oh.map(ldst => ldst(i)) zip remap_pdsts)
.scanLeft(map_table(i)) {case (pdst, (ldst, new_pdst)) => Mux(ldst, new_pdst, pdst)}
for (j <- 0 until plWidth+1) {
remap_table(j)(i) := remapped_row(j)
}
}
}
// Create snapshots of new mappings.
for (i <- 0 until plWidth) {
when (io.ren_br_tags(i).valid) {
br_snapshots(io.ren_br_tags(i).bits) := remap_table(i+1)
}
}
when (io.brupdate.b2.mispredict) {
// Restore the map table to a branch snapshot.
map_table := br_snapshots(io.brupdate.b2.uop.br_tag)
} .otherwise {
// Update mappings.
map_table := remap_table(plWidth)
}
// Read out mappings.
for (i <- 0 until plWidth) {
io.map_resps(i).prs1 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs1)) ((p,k) =>
Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs1, io.remap_reqs(k).pdst, p))
io.map_resps(i).prs2 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs2)) ((p,k) =>
Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs2, io.remap_reqs(k).pdst, p))
io.map_resps(i).prs3 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs3)) ((p,k) =>
Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs3, io.remap_reqs(k).pdst, p))
io.map_resps(i).stale_pdst := (0 until i).foldLeft(map_table(io.map_reqs(i).ldst)) ((p,k) =>
Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).ldst, io.remap_reqs(k).pdst, p))
if (!float) io.map_resps(i).prs3 := DontCare
}
// Don't flag the creation of duplicate 'p0' mappings during rollback.
// These cases may occur soon after reset, as all maptable entries are initialized to 'p0'.
io.remap_reqs map (req => (req.pdst, req.valid)) foreach {case (p,r) =>
assert (!r || !map_table.contains(p) || p === 0.U && io.rollback, "[maptable] Trying to write a duplicate mapping.")}
} | module RenameMapTable(
input clock,
input reset,
input [5:0] io_map_reqs_0_lrs1,
input [5:0] io_map_reqs_0_lrs2,
input [5:0] io_map_reqs_0_ldst,
output [5:0] io_map_resps_0_prs1,
output [5:0] io_map_resps_0_prs2,
output [5:0] io_map_resps_0_stale_pdst,
input [5:0] io_remap_reqs_0_ldst,
input [5:0] io_remap_reqs_0_pdst,
input io_remap_reqs_0_valid,
input io_ren_br_tags_0_valid,
input [2:0] io_ren_br_tags_0_bits,
input [2:0] io_brupdate_b2_uop_br_tag,
input io_brupdate_b2_mispredict,
input io_rollback
);
reg [5:0] map_table_1;
reg [5:0] map_table_2;
reg [5:0] map_table_3;
reg [5:0] map_table_4;
reg [5:0] map_table_5;
reg [5:0] map_table_6;
reg [5:0] map_table_7;
reg [5:0] map_table_8;
reg [5:0] map_table_9;
reg [5:0] map_table_10;
reg [5:0] map_table_11;
reg [5:0] map_table_12;
reg [5:0] map_table_13;
reg [5:0] map_table_14;
reg [5:0] map_table_15;
reg [5:0] map_table_16;
reg [5:0] map_table_17;
reg [5:0] map_table_18;
reg [5:0] map_table_19;
reg [5:0] map_table_20;
reg [5:0] map_table_21;
reg [5:0] map_table_22;
reg [5:0] map_table_23;
reg [5:0] map_table_24;
reg [5:0] map_table_25;
reg [5:0] map_table_26;
reg [5:0] map_table_27;
reg [5:0] map_table_28;
reg [5:0] map_table_29;
reg [5:0] map_table_30;
reg [5:0] map_table_31;
reg [5:0] br_snapshots_0_1;
reg [5:0] br_snapshots_0_2;
reg [5:0] br_snapshots_0_3;
reg [5:0] br_snapshots_0_4;
reg [5:0] br_snapshots_0_5;
reg [5:0] br_snapshots_0_6;
reg [5:0] br_snapshots_0_7;
reg [5:0] br_snapshots_0_8;
reg [5:0] br_snapshots_0_9;
reg [5:0] br_snapshots_0_10;
reg [5:0] br_snapshots_0_11;
reg [5:0] br_snapshots_0_12;
reg [5:0] br_snapshots_0_13;
reg [5:0] br_snapshots_0_14;
reg [5:0] br_snapshots_0_15;
reg [5:0] br_snapshots_0_16;
reg [5:0] br_snapshots_0_17;
reg [5:0] br_snapshots_0_18;
reg [5:0] br_snapshots_0_19;
reg [5:0] br_snapshots_0_20;
reg [5:0] br_snapshots_0_21;
reg [5:0] br_snapshots_0_22;
reg [5:0] br_snapshots_0_23;
reg [5:0] br_snapshots_0_24;
reg [5:0] br_snapshots_0_25;
reg [5:0] br_snapshots_0_26;
reg [5:0] br_snapshots_0_27;
reg [5:0] br_snapshots_0_28;
reg [5:0] br_snapshots_0_29;
reg [5:0] br_snapshots_0_30;
reg [5:0] br_snapshots_0_31;
reg [5:0] br_snapshots_1_1;
reg [5:0] br_snapshots_1_2;
reg [5:0] br_snapshots_1_3;
reg [5:0] br_snapshots_1_4;
reg [5:0] br_snapshots_1_5;
reg [5:0] br_snapshots_1_6;
reg [5:0] br_snapshots_1_7;
reg [5:0] br_snapshots_1_8;
reg [5:0] br_snapshots_1_9;
reg [5:0] br_snapshots_1_10;
reg [5:0] br_snapshots_1_11;
reg [5:0] br_snapshots_1_12;
reg [5:0] br_snapshots_1_13;
reg [5:0] br_snapshots_1_14;
reg [5:0] br_snapshots_1_15;
reg [5:0] br_snapshots_1_16;
reg [5:0] br_snapshots_1_17;
reg [5:0] br_snapshots_1_18;
reg [5:0] br_snapshots_1_19;
reg [5:0] br_snapshots_1_20;
reg [5:0] br_snapshots_1_21;
reg [5:0] br_snapshots_1_22;
reg [5:0] br_snapshots_1_23;
reg [5:0] br_snapshots_1_24;
reg [5:0] br_snapshots_1_25;
reg [5:0] br_snapshots_1_26;
reg [5:0] br_snapshots_1_27;
reg [5:0] br_snapshots_1_28;
reg [5:0] br_snapshots_1_29;
reg [5:0] br_snapshots_1_30;
reg [5:0] br_snapshots_1_31;
reg [5:0] br_snapshots_2_1;
reg [5:0] br_snapshots_2_2;
reg [5:0] br_snapshots_2_3;
reg [5:0] br_snapshots_2_4;
reg [5:0] br_snapshots_2_5;
reg [5:0] br_snapshots_2_6;
reg [5:0] br_snapshots_2_7;
reg [5:0] br_snapshots_2_8;
reg [5:0] br_snapshots_2_9;
reg [5:0] br_snapshots_2_10;
reg [5:0] br_snapshots_2_11;
reg [5:0] br_snapshots_2_12;
reg [5:0] br_snapshots_2_13;
reg [5:0] br_snapshots_2_14;
reg [5:0] br_snapshots_2_15;
reg [5:0] br_snapshots_2_16;
reg [5:0] br_snapshots_2_17;
reg [5:0] br_snapshots_2_18;
reg [5:0] br_snapshots_2_19;
reg [5:0] br_snapshots_2_20;
reg [5:0] br_snapshots_2_21;
reg [5:0] br_snapshots_2_22;
reg [5:0] br_snapshots_2_23;
reg [5:0] br_snapshots_2_24;
reg [5:0] br_snapshots_2_25;
reg [5:0] br_snapshots_2_26;
reg [5:0] br_snapshots_2_27;
reg [5:0] br_snapshots_2_28;
reg [5:0] br_snapshots_2_29;
reg [5:0] br_snapshots_2_30;
reg [5:0] br_snapshots_2_31;
reg [5:0] br_snapshots_3_1;
reg [5:0] br_snapshots_3_2;
reg [5:0] br_snapshots_3_3;
reg [5:0] br_snapshots_3_4;
reg [5:0] br_snapshots_3_5;
reg [5:0] br_snapshots_3_6;
reg [5:0] br_snapshots_3_7;
reg [5:0] br_snapshots_3_8;
reg [5:0] br_snapshots_3_9;
reg [5:0] br_snapshots_3_10;
reg [5:0] br_snapshots_3_11;
reg [5:0] br_snapshots_3_12;
reg [5:0] br_snapshots_3_13;
reg [5:0] br_snapshots_3_14;
reg [5:0] br_snapshots_3_15;
reg [5:0] br_snapshots_3_16;
reg [5:0] br_snapshots_3_17;
reg [5:0] br_snapshots_3_18;
reg [5:0] br_snapshots_3_19;
reg [5:0] br_snapshots_3_20;
reg [5:0] br_snapshots_3_21;
reg [5:0] br_snapshots_3_22;
reg [5:0] br_snapshots_3_23;
reg [5:0] br_snapshots_3_24;
reg [5:0] br_snapshots_3_25;
reg [5:0] br_snapshots_3_26;
reg [5:0] br_snapshots_3_27;
reg [5:0] br_snapshots_3_28;
reg [5:0] br_snapshots_3_29;
reg [5:0] br_snapshots_3_30;
reg [5:0] br_snapshots_3_31;
reg [5:0] br_snapshots_4_1;
reg [5:0] br_snapshots_4_2;
reg [5:0] br_snapshots_4_3;
reg [5:0] br_snapshots_4_4;
reg [5:0] br_snapshots_4_5;
reg [5:0] br_snapshots_4_6;
reg [5:0] br_snapshots_4_7;
reg [5:0] br_snapshots_4_8;
reg [5:0] br_snapshots_4_9;
reg [5:0] br_snapshots_4_10;
reg [5:0] br_snapshots_4_11;
reg [5:0] br_snapshots_4_12;
reg [5:0] br_snapshots_4_13;
reg [5:0] br_snapshots_4_14;
reg [5:0] br_snapshots_4_15;
reg [5:0] br_snapshots_4_16;
reg [5:0] br_snapshots_4_17;
reg [5:0] br_snapshots_4_18;
reg [5:0] br_snapshots_4_19;
reg [5:0] br_snapshots_4_20;
reg [5:0] br_snapshots_4_21;
reg [5:0] br_snapshots_4_22;
reg [5:0] br_snapshots_4_23;
reg [5:0] br_snapshots_4_24;
reg [5:0] br_snapshots_4_25;
reg [5:0] br_snapshots_4_26;
reg [5:0] br_snapshots_4_27;
reg [5:0] br_snapshots_4_28;
reg [5:0] br_snapshots_4_29;
reg [5:0] br_snapshots_4_30;
reg [5:0] br_snapshots_4_31;
reg [5:0] br_snapshots_5_1;
reg [5:0] br_snapshots_5_2;
reg [5:0] br_snapshots_5_3;
reg [5:0] br_snapshots_5_4;
reg [5:0] br_snapshots_5_5;
reg [5:0] br_snapshots_5_6;
reg [5:0] br_snapshots_5_7;
reg [5:0] br_snapshots_5_8;
reg [5:0] br_snapshots_5_9;
reg [5:0] br_snapshots_5_10;
reg [5:0] br_snapshots_5_11;
reg [5:0] br_snapshots_5_12;
reg [5:0] br_snapshots_5_13;
reg [5:0] br_snapshots_5_14;
reg [5:0] br_snapshots_5_15;
reg [5:0] br_snapshots_5_16;
reg [5:0] br_snapshots_5_17;
reg [5:0] br_snapshots_5_18;
reg [5:0] br_snapshots_5_19;
reg [5:0] br_snapshots_5_20;
reg [5:0] br_snapshots_5_21;
reg [5:0] br_snapshots_5_22;
reg [5:0] br_snapshots_5_23;
reg [5:0] br_snapshots_5_24;
reg [5:0] br_snapshots_5_25;
reg [5:0] br_snapshots_5_26;
reg [5:0] br_snapshots_5_27;
reg [5:0] br_snapshots_5_28;
reg [5:0] br_snapshots_5_29;
reg [5:0] br_snapshots_5_30;
reg [5:0] br_snapshots_5_31;
reg [5:0] br_snapshots_6_1;
reg [5:0] br_snapshots_6_2;
reg [5:0] br_snapshots_6_3;
reg [5:0] br_snapshots_6_4;
reg [5:0] br_snapshots_6_5;
reg [5:0] br_snapshots_6_6;
reg [5:0] br_snapshots_6_7;
reg [5:0] br_snapshots_6_8;
reg [5:0] br_snapshots_6_9;
reg [5:0] br_snapshots_6_10;
reg [5:0] br_snapshots_6_11;
reg [5:0] br_snapshots_6_12;
reg [5:0] br_snapshots_6_13;
reg [5:0] br_snapshots_6_14;
reg [5:0] br_snapshots_6_15;
reg [5:0] br_snapshots_6_16;
reg [5:0] br_snapshots_6_17;
reg [5:0] br_snapshots_6_18;
reg [5:0] br_snapshots_6_19;
reg [5:0] br_snapshots_6_20;
reg [5:0] br_snapshots_6_21;
reg [5:0] br_snapshots_6_22;
reg [5:0] br_snapshots_6_23;
reg [5:0] br_snapshots_6_24;
reg [5:0] br_snapshots_6_25;
reg [5:0] br_snapshots_6_26;
reg [5:0] br_snapshots_6_27;
reg [5:0] br_snapshots_6_28;
reg [5:0] br_snapshots_6_29;
reg [5:0] br_snapshots_6_30;
reg [5:0] br_snapshots_6_31;
reg [5:0] br_snapshots_7_1;
reg [5:0] br_snapshots_7_2;
reg [5:0] br_snapshots_7_3;
reg [5:0] br_snapshots_7_4;
reg [5:0] br_snapshots_7_5;
reg [5:0] br_snapshots_7_6;
reg [5:0] br_snapshots_7_7;
reg [5:0] br_snapshots_7_8;
reg [5:0] br_snapshots_7_9;
reg [5:0] br_snapshots_7_10;
reg [5:0] br_snapshots_7_11;
reg [5:0] br_snapshots_7_12;
reg [5:0] br_snapshots_7_13;
reg [5:0] br_snapshots_7_14;
reg [5:0] br_snapshots_7_15;
reg [5:0] br_snapshots_7_16;
reg [5:0] br_snapshots_7_17;
reg [5:0] br_snapshots_7_18;
reg [5:0] br_snapshots_7_19;
reg [5:0] br_snapshots_7_20;
reg [5:0] br_snapshots_7_21;
reg [5:0] br_snapshots_7_22;
reg [5:0] br_snapshots_7_23;
reg [5:0] br_snapshots_7_24;
reg [5:0] br_snapshots_7_25;
reg [5:0] br_snapshots_7_26;
reg [5:0] br_snapshots_7_27;
reg [5:0] br_snapshots_7_28;
reg [5:0] br_snapshots_7_29;
reg [5:0] br_snapshots_7_30;
reg [5:0] br_snapshots_7_31;
wire [31:0][5:0] _GEN = {{map_table_31}, {map_table_30}, {map_table_29}, {map_table_28}, {map_table_27}, {map_table_26}, {map_table_25}, {map_table_24}, {map_table_23}, {map_table_22}, {map_table_21}, {map_table_20}, {map_table_19}, {map_table_18}, {map_table_17}, {map_table_16}, {map_table_15}, {map_table_14}, {map_table_13}, {map_table_12}, {map_table_11}, {map_table_10}, {map_table_9}, {map_table_8}, {map_table_7}, {map_table_6}, {map_table_5}, {map_table_4}, {map_table_3}, {map_table_2}, {map_table_1}, {6'h0}};
wire [7:0][5:0] _GEN_1 = {{br_snapshots_7_1}, {br_snapshots_6_1}, {br_snapshots_5_1}, {br_snapshots_4_1}, {br_snapshots_3_1}, {br_snapshots_2_1}, {br_snapshots_1_1}, {br_snapshots_0_1}};
wire [7:0][5:0] _GEN_2 = {{br_snapshots_7_2}, {br_snapshots_6_2}, {br_snapshots_5_2}, {br_snapshots_4_2}, {br_snapshots_3_2}, {br_snapshots_2_2}, {br_snapshots_1_2}, {br_snapshots_0_2}};
wire [7:0][5:0] _GEN_3 = {{br_snapshots_7_3}, {br_snapshots_6_3}, {br_snapshots_5_3}, {br_snapshots_4_3}, {br_snapshots_3_3}, {br_snapshots_2_3}, {br_snapshots_1_3}, {br_snapshots_0_3}};
wire [7:0][5:0] _GEN_4 = {{br_snapshots_7_4}, {br_snapshots_6_4}, {br_snapshots_5_4}, {br_snapshots_4_4}, {br_snapshots_3_4}, {br_snapshots_2_4}, {br_snapshots_1_4}, {br_snapshots_0_4}};
wire [7:0][5:0] _GEN_5 = {{br_snapshots_7_5}, {br_snapshots_6_5}, {br_snapshots_5_5}, {br_snapshots_4_5}, {br_snapshots_3_5}, {br_snapshots_2_5}, {br_snapshots_1_5}, {br_snapshots_0_5}};
wire [7:0][5:0] _GEN_6 = {{br_snapshots_7_6}, {br_snapshots_6_6}, {br_snapshots_5_6}, {br_snapshots_4_6}, {br_snapshots_3_6}, {br_snapshots_2_6}, {br_snapshots_1_6}, {br_snapshots_0_6}};
wire [7:0][5:0] _GEN_7 = {{br_snapshots_7_7}, {br_snapshots_6_7}, {br_snapshots_5_7}, {br_snapshots_4_7}, {br_snapshots_3_7}, {br_snapshots_2_7}, {br_snapshots_1_7}, {br_snapshots_0_7}};
wire [7:0][5:0] _GEN_8 = {{br_snapshots_7_8}, {br_snapshots_6_8}, {br_snapshots_5_8}, {br_snapshots_4_8}, {br_snapshots_3_8}, {br_snapshots_2_8}, {br_snapshots_1_8}, {br_snapshots_0_8}};
wire [7:0][5:0] _GEN_9 = {{br_snapshots_7_9}, {br_snapshots_6_9}, {br_snapshots_5_9}, {br_snapshots_4_9}, {br_snapshots_3_9}, {br_snapshots_2_9}, {br_snapshots_1_9}, {br_snapshots_0_9}};
wire [7:0][5:0] _GEN_10 = {{br_snapshots_7_10}, {br_snapshots_6_10}, {br_snapshots_5_10}, {br_snapshots_4_10}, {br_snapshots_3_10}, {br_snapshots_2_10}, {br_snapshots_1_10}, {br_snapshots_0_10}};
wire [7:0][5:0] _GEN_11 = {{br_snapshots_7_11}, {br_snapshots_6_11}, {br_snapshots_5_11}, {br_snapshots_4_11}, {br_snapshots_3_11}, {br_snapshots_2_11}, {br_snapshots_1_11}, {br_snapshots_0_11}};
wire [7:0][5:0] _GEN_12 = {{br_snapshots_7_12}, {br_snapshots_6_12}, {br_snapshots_5_12}, {br_snapshots_4_12}, {br_snapshots_3_12}, {br_snapshots_2_12}, {br_snapshots_1_12}, {br_snapshots_0_12}};
wire [7:0][5:0] _GEN_13 = {{br_snapshots_7_13}, {br_snapshots_6_13}, {br_snapshots_5_13}, {br_snapshots_4_13}, {br_snapshots_3_13}, {br_snapshots_2_13}, {br_snapshots_1_13}, {br_snapshots_0_13}};
wire [7:0][5:0] _GEN_14 = {{br_snapshots_7_14}, {br_snapshots_6_14}, {br_snapshots_5_14}, {br_snapshots_4_14}, {br_snapshots_3_14}, {br_snapshots_2_14}, {br_snapshots_1_14}, {br_snapshots_0_14}};
wire [7:0][5:0] _GEN_15 = {{br_snapshots_7_15}, {br_snapshots_6_15}, {br_snapshots_5_15}, {br_snapshots_4_15}, {br_snapshots_3_15}, {br_snapshots_2_15}, {br_snapshots_1_15}, {br_snapshots_0_15}};
wire [7:0][5:0] _GEN_16 = {{br_snapshots_7_16}, {br_snapshots_6_16}, {br_snapshots_5_16}, {br_snapshots_4_16}, {br_snapshots_3_16}, {br_snapshots_2_16}, {br_snapshots_1_16}, {br_snapshots_0_16}};
wire [7:0][5:0] _GEN_17 = {{br_snapshots_7_17}, {br_snapshots_6_17}, {br_snapshots_5_17}, {br_snapshots_4_17}, {br_snapshots_3_17}, {br_snapshots_2_17}, {br_snapshots_1_17}, {br_snapshots_0_17}};
wire [7:0][5:0] _GEN_18 = {{br_snapshots_7_18}, {br_snapshots_6_18}, {br_snapshots_5_18}, {br_snapshots_4_18}, {br_snapshots_3_18}, {br_snapshots_2_18}, {br_snapshots_1_18}, {br_snapshots_0_18}};
wire [7:0][5:0] _GEN_19 = {{br_snapshots_7_19}, {br_snapshots_6_19}, {br_snapshots_5_19}, {br_snapshots_4_19}, {br_snapshots_3_19}, {br_snapshots_2_19}, {br_snapshots_1_19}, {br_snapshots_0_19}};
wire [7:0][5:0] _GEN_20 = {{br_snapshots_7_20}, {br_snapshots_6_20}, {br_snapshots_5_20}, {br_snapshots_4_20}, {br_snapshots_3_20}, {br_snapshots_2_20}, {br_snapshots_1_20}, {br_snapshots_0_20}};
wire [7:0][5:0] _GEN_21 = {{br_snapshots_7_21}, {br_snapshots_6_21}, {br_snapshots_5_21}, {br_snapshots_4_21}, {br_snapshots_3_21}, {br_snapshots_2_21}, {br_snapshots_1_21}, {br_snapshots_0_21}};
wire [7:0][5:0] _GEN_22 = {{br_snapshots_7_22}, {br_snapshots_6_22}, {br_snapshots_5_22}, {br_snapshots_4_22}, {br_snapshots_3_22}, {br_snapshots_2_22}, {br_snapshots_1_22}, {br_snapshots_0_22}};
wire [7:0][5:0] _GEN_23 = {{br_snapshots_7_23}, {br_snapshots_6_23}, {br_snapshots_5_23}, {br_snapshots_4_23}, {br_snapshots_3_23}, {br_snapshots_2_23}, {br_snapshots_1_23}, {br_snapshots_0_23}};
wire [7:0][5:0] _GEN_24 = {{br_snapshots_7_24}, {br_snapshots_6_24}, {br_snapshots_5_24}, {br_snapshots_4_24}, {br_snapshots_3_24}, {br_snapshots_2_24}, {br_snapshots_1_24}, {br_snapshots_0_24}};
wire [7:0][5:0] _GEN_25 = {{br_snapshots_7_25}, {br_snapshots_6_25}, {br_snapshots_5_25}, {br_snapshots_4_25}, {br_snapshots_3_25}, {br_snapshots_2_25}, {br_snapshots_1_25}, {br_snapshots_0_25}};
wire [7:0][5:0] _GEN_26 = {{br_snapshots_7_26}, {br_snapshots_6_26}, {br_snapshots_5_26}, {br_snapshots_4_26}, {br_snapshots_3_26}, {br_snapshots_2_26}, {br_snapshots_1_26}, {br_snapshots_0_26}};
wire [7:0][5:0] _GEN_27 = {{br_snapshots_7_27}, {br_snapshots_6_27}, {br_snapshots_5_27}, {br_snapshots_4_27}, {br_snapshots_3_27}, {br_snapshots_2_27}, {br_snapshots_1_27}, {br_snapshots_0_27}};
wire [7:0][5:0] _GEN_28 = {{br_snapshots_7_28}, {br_snapshots_6_28}, {br_snapshots_5_28}, {br_snapshots_4_28}, {br_snapshots_3_28}, {br_snapshots_2_28}, {br_snapshots_1_28}, {br_snapshots_0_28}};
wire [7:0][5:0] _GEN_29 = {{br_snapshots_7_29}, {br_snapshots_6_29}, {br_snapshots_5_29}, {br_snapshots_4_29}, {br_snapshots_3_29}, {br_snapshots_2_29}, {br_snapshots_1_29}, {br_snapshots_0_29}};
wire [7:0][5:0] _GEN_30 = {{br_snapshots_7_30}, {br_snapshots_6_30}, {br_snapshots_5_30}, {br_snapshots_4_30}, {br_snapshots_3_30}, {br_snapshots_2_30}, {br_snapshots_1_30}, {br_snapshots_0_30}};
wire [7:0][5:0] _GEN_31 = {{br_snapshots_7_31}, {br_snapshots_6_31}, {br_snapshots_5_31}, {br_snapshots_4_31}, {br_snapshots_3_31}, {br_snapshots_2_31}, {br_snapshots_1_31}, {br_snapshots_0_31}};
wire [63:0] _remap_ldsts_oh_T = 64'h1 << io_remap_reqs_0_ldst;
wire [30:0] _GEN_32 = _remap_ldsts_oh_T[31:1] & {31{io_remap_reqs_0_valid}};
wire [5:0] remapped_row_1 = _GEN_32[0] ? io_remap_reqs_0_pdst : map_table_1;
wire [5:0] remap_table_1_2 = _GEN_32[1] ? io_remap_reqs_0_pdst : map_table_2;
wire [5:0] remap_table_1_3 = _GEN_32[2] ? io_remap_reqs_0_pdst : map_table_3;
wire [5:0] remap_table_1_4 = _GEN_32[3] ? io_remap_reqs_0_pdst : map_table_4;
wire [5:0] remap_table_1_5 = _GEN_32[4] ? io_remap_reqs_0_pdst : map_table_5;
wire [5:0] remap_table_1_6 = _GEN_32[5] ? io_remap_reqs_0_pdst : map_table_6;
wire [5:0] remap_table_1_7 = _GEN_32[6] ? io_remap_reqs_0_pdst : map_table_7;
wire [5:0] remap_table_1_8 = _GEN_32[7] ? io_remap_reqs_0_pdst : map_table_8;
wire [5:0] remap_table_1_9 = _GEN_32[8] ? io_remap_reqs_0_pdst : map_table_9;
wire [5:0] remap_table_1_10 = _GEN_32[9] ? io_remap_reqs_0_pdst : map_table_10;
wire [5:0] remap_table_1_11 = _GEN_32[10] ? io_remap_reqs_0_pdst : map_table_11;
wire [5:0] remap_table_1_12 = _GEN_32[11] ? io_remap_reqs_0_pdst : map_table_12;
wire [5:0] remap_table_1_13 = _GEN_32[12] ? io_remap_reqs_0_pdst : map_table_13;
wire [5:0] remap_table_1_14 = _GEN_32[13] ? io_remap_reqs_0_pdst : map_table_14;
wire [5:0] remap_table_1_15 = _GEN_32[14] ? io_remap_reqs_0_pdst : map_table_15;
wire [5:0] remap_table_1_16 = _GEN_32[15] ? io_remap_reqs_0_pdst : map_table_16;
wire [5:0] remap_table_1_17 = _GEN_32[16] ? io_remap_reqs_0_pdst : map_table_17;
wire [5:0] remap_table_1_18 = _GEN_32[17] ? io_remap_reqs_0_pdst : map_table_18;
wire [5:0] remap_table_1_19 = _GEN_32[18] ? io_remap_reqs_0_pdst : map_table_19;
wire [5:0] remap_table_1_20 = _GEN_32[19] ? io_remap_reqs_0_pdst : map_table_20;
wire [5:0] remap_table_1_21 = _GEN_32[20] ? io_remap_reqs_0_pdst : map_table_21;
wire [5:0] remap_table_1_22 = _GEN_32[21] ? io_remap_reqs_0_pdst : map_table_22;
wire [5:0] remap_table_1_23 = _GEN_32[22] ? io_remap_reqs_0_pdst : map_table_23;
wire [5:0] remap_table_1_24 = _GEN_32[23] ? io_remap_reqs_0_pdst : map_table_24;
wire [5:0] remap_table_1_25 = _GEN_32[24] ? io_remap_reqs_0_pdst : map_table_25;
wire [5:0] remap_table_1_26 = _GEN_32[25] ? io_remap_reqs_0_pdst : map_table_26;
wire [5:0] remap_table_1_27 = _GEN_32[26] ? io_remap_reqs_0_pdst : map_table_27;
wire [5:0] remap_table_1_28 = _GEN_32[27] ? io_remap_reqs_0_pdst : map_table_28;
wire [5:0] remap_table_1_29 = _GEN_32[28] ? io_remap_reqs_0_pdst : map_table_29;
wire [5:0] remap_table_1_30 = _GEN_32[29] ? io_remap_reqs_0_pdst : map_table_30;
wire [5:0] remap_table_1_31 = _GEN_32[30] ? io_remap_reqs_0_pdst : map_table_31;
always @(posedge clock) begin
if (reset) begin
map_table_1 <= 6'h0;
map_table_2 <= 6'h0;
map_table_3 <= 6'h0;
map_table_4 <= 6'h0;
map_table_5 <= 6'h0;
map_table_6 <= 6'h0;
map_table_7 <= 6'h0;
map_table_8 <= 6'h0;
map_table_9 <= 6'h0;
map_table_10 <= 6'h0;
map_table_11 <= 6'h0;
map_table_12 <= 6'h0;
map_table_13 <= 6'h0;
map_table_14 <= 6'h0;
map_table_15 <= 6'h0;
map_table_16 <= 6'h0;
map_table_17 <= 6'h0;
map_table_18 <= 6'h0;
map_table_19 <= 6'h0;
map_table_20 <= 6'h0;
map_table_21 <= 6'h0;
map_table_22 <= 6'h0;
map_table_23 <= 6'h0;
map_table_24 <= 6'h0;
map_table_25 <= 6'h0;
map_table_26 <= 6'h0;
map_table_27 <= 6'h0;
map_table_28 <= 6'h0;
map_table_29 <= 6'h0;
map_table_30 <= 6'h0;
map_table_31 <= 6'h0;
end
else if (io_brupdate_b2_mispredict) begin
map_table_1 <= _GEN_1[io_brupdate_b2_uop_br_tag];
map_table_2 <= _GEN_2[io_brupdate_b2_uop_br_tag];
map_table_3 <= _GEN_3[io_brupdate_b2_uop_br_tag];
map_table_4 <= _GEN_4[io_brupdate_b2_uop_br_tag];
map_table_5 <= _GEN_5[io_brupdate_b2_uop_br_tag];
map_table_6 <= _GEN_6[io_brupdate_b2_uop_br_tag];
map_table_7 <= _GEN_7[io_brupdate_b2_uop_br_tag];
map_table_8 <= _GEN_8[io_brupdate_b2_uop_br_tag];
map_table_9 <= _GEN_9[io_brupdate_b2_uop_br_tag];
map_table_10 <= _GEN_10[io_brupdate_b2_uop_br_tag];
map_table_11 <= _GEN_11[io_brupdate_b2_uop_br_tag];
map_table_12 <= _GEN_12[io_brupdate_b2_uop_br_tag];
map_table_13 <= _GEN_13[io_brupdate_b2_uop_br_tag];
map_table_14 <= _GEN_14[io_brupdate_b2_uop_br_tag];
map_table_15 <= _GEN_15[io_brupdate_b2_uop_br_tag];
map_table_16 <= _GEN_16[io_brupdate_b2_uop_br_tag];
map_table_17 <= _GEN_17[io_brupdate_b2_uop_br_tag];
map_table_18 <= _GEN_18[io_brupdate_b2_uop_br_tag];
map_table_19 <= _GEN_19[io_brupdate_b2_uop_br_tag];
map_table_20 <= _GEN_20[io_brupdate_b2_uop_br_tag];
map_table_21 <= _GEN_21[io_brupdate_b2_uop_br_tag];
map_table_22 <= _GEN_22[io_brupdate_b2_uop_br_tag];
map_table_23 <= _GEN_23[io_brupdate_b2_uop_br_tag];
map_table_24 <= _GEN_24[io_brupdate_b2_uop_br_tag];
map_table_25 <= _GEN_25[io_brupdate_b2_uop_br_tag];
map_table_26 <= _GEN_26[io_brupdate_b2_uop_br_tag];
map_table_27 <= _GEN_27[io_brupdate_b2_uop_br_tag];
map_table_28 <= _GEN_28[io_brupdate_b2_uop_br_tag];
map_table_29 <= _GEN_29[io_brupdate_b2_uop_br_tag];
map_table_30 <= _GEN_30[io_brupdate_b2_uop_br_tag];
map_table_31 <= _GEN_31[io_brupdate_b2_uop_br_tag];
end
else begin
if (_GEN_32[0])
map_table_1 <= io_remap_reqs_0_pdst;
if (_GEN_32[1])
map_table_2 <= io_remap_reqs_0_pdst;
if (_GEN_32[2])
map_table_3 <= io_remap_reqs_0_pdst;
if (_GEN_32[3])
map_table_4 <= io_remap_reqs_0_pdst;
if (_GEN_32[4])
map_table_5 <= io_remap_reqs_0_pdst;
if (_GEN_32[5])
map_table_6 <= io_remap_reqs_0_pdst;
if (_GEN_32[6])
map_table_7 <= io_remap_reqs_0_pdst;
if (_GEN_32[7])
map_table_8 <= io_remap_reqs_0_pdst;
if (_GEN_32[8])
map_table_9 <= io_remap_reqs_0_pdst;
if (_GEN_32[9])
map_table_10 <= io_remap_reqs_0_pdst;
if (_GEN_32[10])
map_table_11 <= io_remap_reqs_0_pdst;
if (_GEN_32[11])
map_table_12 <= io_remap_reqs_0_pdst;
if (_GEN_32[12])
map_table_13 <= io_remap_reqs_0_pdst;
if (_GEN_32[13])
map_table_14 <= io_remap_reqs_0_pdst;
if (_GEN_32[14])
map_table_15 <= io_remap_reqs_0_pdst;
if (_GEN_32[15])
map_table_16 <= io_remap_reqs_0_pdst;
if (_GEN_32[16])
map_table_17 <= io_remap_reqs_0_pdst;
if (_GEN_32[17])
map_table_18 <= io_remap_reqs_0_pdst;
if (_GEN_32[18])
map_table_19 <= io_remap_reqs_0_pdst;
if (_GEN_32[19])
map_table_20 <= io_remap_reqs_0_pdst;
if (_GEN_32[20])
map_table_21 <= io_remap_reqs_0_pdst;
if (_GEN_32[21])
map_table_22 <= io_remap_reqs_0_pdst;
if (_GEN_32[22])
map_table_23 <= io_remap_reqs_0_pdst;
if (_GEN_32[23])
map_table_24 <= io_remap_reqs_0_pdst;
if (_GEN_32[24])
map_table_25 <= io_remap_reqs_0_pdst;
if (_GEN_32[25])
map_table_26 <= io_remap_reqs_0_pdst;
if (_GEN_32[26])
map_table_27 <= io_remap_reqs_0_pdst;
if (_GEN_32[27])
map_table_28 <= io_remap_reqs_0_pdst;
if (_GEN_32[28])
map_table_29 <= io_remap_reqs_0_pdst;
if (_GEN_32[29])
map_table_30 <= io_remap_reqs_0_pdst;
if (_GEN_32[30])
map_table_31 <= io_remap_reqs_0_pdst;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h0) begin
br_snapshots_0_1 <= remapped_row_1;
br_snapshots_0_2 <= remap_table_1_2;
br_snapshots_0_3 <= remap_table_1_3;
br_snapshots_0_4 <= remap_table_1_4;
br_snapshots_0_5 <= remap_table_1_5;
br_snapshots_0_6 <= remap_table_1_6;
br_snapshots_0_7 <= remap_table_1_7;
br_snapshots_0_8 <= remap_table_1_8;
br_snapshots_0_9 <= remap_table_1_9;
br_snapshots_0_10 <= remap_table_1_10;
br_snapshots_0_11 <= remap_table_1_11;
br_snapshots_0_12 <= remap_table_1_12;
br_snapshots_0_13 <= remap_table_1_13;
br_snapshots_0_14 <= remap_table_1_14;
br_snapshots_0_15 <= remap_table_1_15;
br_snapshots_0_16 <= remap_table_1_16;
br_snapshots_0_17 <= remap_table_1_17;
br_snapshots_0_18 <= remap_table_1_18;
br_snapshots_0_19 <= remap_table_1_19;
br_snapshots_0_20 <= remap_table_1_20;
br_snapshots_0_21 <= remap_table_1_21;
br_snapshots_0_22 <= remap_table_1_22;
br_snapshots_0_23 <= remap_table_1_23;
br_snapshots_0_24 <= remap_table_1_24;
br_snapshots_0_25 <= remap_table_1_25;
br_snapshots_0_26 <= remap_table_1_26;
br_snapshots_0_27 <= remap_table_1_27;
br_snapshots_0_28 <= remap_table_1_28;
br_snapshots_0_29 <= remap_table_1_29;
br_snapshots_0_30 <= remap_table_1_30;
br_snapshots_0_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h1) begin
br_snapshots_1_1 <= remapped_row_1;
br_snapshots_1_2 <= remap_table_1_2;
br_snapshots_1_3 <= remap_table_1_3;
br_snapshots_1_4 <= remap_table_1_4;
br_snapshots_1_5 <= remap_table_1_5;
br_snapshots_1_6 <= remap_table_1_6;
br_snapshots_1_7 <= remap_table_1_7;
br_snapshots_1_8 <= remap_table_1_8;
br_snapshots_1_9 <= remap_table_1_9;
br_snapshots_1_10 <= remap_table_1_10;
br_snapshots_1_11 <= remap_table_1_11;
br_snapshots_1_12 <= remap_table_1_12;
br_snapshots_1_13 <= remap_table_1_13;
br_snapshots_1_14 <= remap_table_1_14;
br_snapshots_1_15 <= remap_table_1_15;
br_snapshots_1_16 <= remap_table_1_16;
br_snapshots_1_17 <= remap_table_1_17;
br_snapshots_1_18 <= remap_table_1_18;
br_snapshots_1_19 <= remap_table_1_19;
br_snapshots_1_20 <= remap_table_1_20;
br_snapshots_1_21 <= remap_table_1_21;
br_snapshots_1_22 <= remap_table_1_22;
br_snapshots_1_23 <= remap_table_1_23;
br_snapshots_1_24 <= remap_table_1_24;
br_snapshots_1_25 <= remap_table_1_25;
br_snapshots_1_26 <= remap_table_1_26;
br_snapshots_1_27 <= remap_table_1_27;
br_snapshots_1_28 <= remap_table_1_28;
br_snapshots_1_29 <= remap_table_1_29;
br_snapshots_1_30 <= remap_table_1_30;
br_snapshots_1_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h2) begin
br_snapshots_2_1 <= remapped_row_1;
br_snapshots_2_2 <= remap_table_1_2;
br_snapshots_2_3 <= remap_table_1_3;
br_snapshots_2_4 <= remap_table_1_4;
br_snapshots_2_5 <= remap_table_1_5;
br_snapshots_2_6 <= remap_table_1_6;
br_snapshots_2_7 <= remap_table_1_7;
br_snapshots_2_8 <= remap_table_1_8;
br_snapshots_2_9 <= remap_table_1_9;
br_snapshots_2_10 <= remap_table_1_10;
br_snapshots_2_11 <= remap_table_1_11;
br_snapshots_2_12 <= remap_table_1_12;
br_snapshots_2_13 <= remap_table_1_13;
br_snapshots_2_14 <= remap_table_1_14;
br_snapshots_2_15 <= remap_table_1_15;
br_snapshots_2_16 <= remap_table_1_16;
br_snapshots_2_17 <= remap_table_1_17;
br_snapshots_2_18 <= remap_table_1_18;
br_snapshots_2_19 <= remap_table_1_19;
br_snapshots_2_20 <= remap_table_1_20;
br_snapshots_2_21 <= remap_table_1_21;
br_snapshots_2_22 <= remap_table_1_22;
br_snapshots_2_23 <= remap_table_1_23;
br_snapshots_2_24 <= remap_table_1_24;
br_snapshots_2_25 <= remap_table_1_25;
br_snapshots_2_26 <= remap_table_1_26;
br_snapshots_2_27 <= remap_table_1_27;
br_snapshots_2_28 <= remap_table_1_28;
br_snapshots_2_29 <= remap_table_1_29;
br_snapshots_2_30 <= remap_table_1_30;
br_snapshots_2_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h3) begin
br_snapshots_3_1 <= remapped_row_1;
br_snapshots_3_2 <= remap_table_1_2;
br_snapshots_3_3 <= remap_table_1_3;
br_snapshots_3_4 <= remap_table_1_4;
br_snapshots_3_5 <= remap_table_1_5;
br_snapshots_3_6 <= remap_table_1_6;
br_snapshots_3_7 <= remap_table_1_7;
br_snapshots_3_8 <= remap_table_1_8;
br_snapshots_3_9 <= remap_table_1_9;
br_snapshots_3_10 <= remap_table_1_10;
br_snapshots_3_11 <= remap_table_1_11;
br_snapshots_3_12 <= remap_table_1_12;
br_snapshots_3_13 <= remap_table_1_13;
br_snapshots_3_14 <= remap_table_1_14;
br_snapshots_3_15 <= remap_table_1_15;
br_snapshots_3_16 <= remap_table_1_16;
br_snapshots_3_17 <= remap_table_1_17;
br_snapshots_3_18 <= remap_table_1_18;
br_snapshots_3_19 <= remap_table_1_19;
br_snapshots_3_20 <= remap_table_1_20;
br_snapshots_3_21 <= remap_table_1_21;
br_snapshots_3_22 <= remap_table_1_22;
br_snapshots_3_23 <= remap_table_1_23;
br_snapshots_3_24 <= remap_table_1_24;
br_snapshots_3_25 <= remap_table_1_25;
br_snapshots_3_26 <= remap_table_1_26;
br_snapshots_3_27 <= remap_table_1_27;
br_snapshots_3_28 <= remap_table_1_28;
br_snapshots_3_29 <= remap_table_1_29;
br_snapshots_3_30 <= remap_table_1_30;
br_snapshots_3_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h4) begin
br_snapshots_4_1 <= remapped_row_1;
br_snapshots_4_2 <= remap_table_1_2;
br_snapshots_4_3 <= remap_table_1_3;
br_snapshots_4_4 <= remap_table_1_4;
br_snapshots_4_5 <= remap_table_1_5;
br_snapshots_4_6 <= remap_table_1_6;
br_snapshots_4_7 <= remap_table_1_7;
br_snapshots_4_8 <= remap_table_1_8;
br_snapshots_4_9 <= remap_table_1_9;
br_snapshots_4_10 <= remap_table_1_10;
br_snapshots_4_11 <= remap_table_1_11;
br_snapshots_4_12 <= remap_table_1_12;
br_snapshots_4_13 <= remap_table_1_13;
br_snapshots_4_14 <= remap_table_1_14;
br_snapshots_4_15 <= remap_table_1_15;
br_snapshots_4_16 <= remap_table_1_16;
br_snapshots_4_17 <= remap_table_1_17;
br_snapshots_4_18 <= remap_table_1_18;
br_snapshots_4_19 <= remap_table_1_19;
br_snapshots_4_20 <= remap_table_1_20;
br_snapshots_4_21 <= remap_table_1_21;
br_snapshots_4_22 <= remap_table_1_22;
br_snapshots_4_23 <= remap_table_1_23;
br_snapshots_4_24 <= remap_table_1_24;
br_snapshots_4_25 <= remap_table_1_25;
br_snapshots_4_26 <= remap_table_1_26;
br_snapshots_4_27 <= remap_table_1_27;
br_snapshots_4_28 <= remap_table_1_28;
br_snapshots_4_29 <= remap_table_1_29;
br_snapshots_4_30 <= remap_table_1_30;
br_snapshots_4_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h5) begin
br_snapshots_5_1 <= remapped_row_1;
br_snapshots_5_2 <= remap_table_1_2;
br_snapshots_5_3 <= remap_table_1_3;
br_snapshots_5_4 <= remap_table_1_4;
br_snapshots_5_5 <= remap_table_1_5;
br_snapshots_5_6 <= remap_table_1_6;
br_snapshots_5_7 <= remap_table_1_7;
br_snapshots_5_8 <= remap_table_1_8;
br_snapshots_5_9 <= remap_table_1_9;
br_snapshots_5_10 <= remap_table_1_10;
br_snapshots_5_11 <= remap_table_1_11;
br_snapshots_5_12 <= remap_table_1_12;
br_snapshots_5_13 <= remap_table_1_13;
br_snapshots_5_14 <= remap_table_1_14;
br_snapshots_5_15 <= remap_table_1_15;
br_snapshots_5_16 <= remap_table_1_16;
br_snapshots_5_17 <= remap_table_1_17;
br_snapshots_5_18 <= remap_table_1_18;
br_snapshots_5_19 <= remap_table_1_19;
br_snapshots_5_20 <= remap_table_1_20;
br_snapshots_5_21 <= remap_table_1_21;
br_snapshots_5_22 <= remap_table_1_22;
br_snapshots_5_23 <= remap_table_1_23;
br_snapshots_5_24 <= remap_table_1_24;
br_snapshots_5_25 <= remap_table_1_25;
br_snapshots_5_26 <= remap_table_1_26;
br_snapshots_5_27 <= remap_table_1_27;
br_snapshots_5_28 <= remap_table_1_28;
br_snapshots_5_29 <= remap_table_1_29;
br_snapshots_5_30 <= remap_table_1_30;
br_snapshots_5_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h6) begin
br_snapshots_6_1 <= remapped_row_1;
br_snapshots_6_2 <= remap_table_1_2;
br_snapshots_6_3 <= remap_table_1_3;
br_snapshots_6_4 <= remap_table_1_4;
br_snapshots_6_5 <= remap_table_1_5;
br_snapshots_6_6 <= remap_table_1_6;
br_snapshots_6_7 <= remap_table_1_7;
br_snapshots_6_8 <= remap_table_1_8;
br_snapshots_6_9 <= remap_table_1_9;
br_snapshots_6_10 <= remap_table_1_10;
br_snapshots_6_11 <= remap_table_1_11;
br_snapshots_6_12 <= remap_table_1_12;
br_snapshots_6_13 <= remap_table_1_13;
br_snapshots_6_14 <= remap_table_1_14;
br_snapshots_6_15 <= remap_table_1_15;
br_snapshots_6_16 <= remap_table_1_16;
br_snapshots_6_17 <= remap_table_1_17;
br_snapshots_6_18 <= remap_table_1_18;
br_snapshots_6_19 <= remap_table_1_19;
br_snapshots_6_20 <= remap_table_1_20;
br_snapshots_6_21 <= remap_table_1_21;
br_snapshots_6_22 <= remap_table_1_22;
br_snapshots_6_23 <= remap_table_1_23;
br_snapshots_6_24 <= remap_table_1_24;
br_snapshots_6_25 <= remap_table_1_25;
br_snapshots_6_26 <= remap_table_1_26;
br_snapshots_6_27 <= remap_table_1_27;
br_snapshots_6_28 <= remap_table_1_28;
br_snapshots_6_29 <= remap_table_1_29;
br_snapshots_6_30 <= remap_table_1_30;
br_snapshots_6_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & (&io_ren_br_tags_0_bits)) begin
br_snapshots_7_1 <= remapped_row_1;
br_snapshots_7_2 <= remap_table_1_2;
br_snapshots_7_3 <= remap_table_1_3;
br_snapshots_7_4 <= remap_table_1_4;
br_snapshots_7_5 <= remap_table_1_5;
br_snapshots_7_6 <= remap_table_1_6;
br_snapshots_7_7 <= remap_table_1_7;
br_snapshots_7_8 <= remap_table_1_8;
br_snapshots_7_9 <= remap_table_1_9;
br_snapshots_7_10 <= remap_table_1_10;
br_snapshots_7_11 <= remap_table_1_11;
br_snapshots_7_12 <= remap_table_1_12;
br_snapshots_7_13 <= remap_table_1_13;
br_snapshots_7_14 <= remap_table_1_14;
br_snapshots_7_15 <= remap_table_1_15;
br_snapshots_7_16 <= remap_table_1_16;
br_snapshots_7_17 <= remap_table_1_17;
br_snapshots_7_18 <= remap_table_1_18;
br_snapshots_7_19 <= remap_table_1_19;
br_snapshots_7_20 <= remap_table_1_20;
br_snapshots_7_21 <= remap_table_1_21;
br_snapshots_7_22 <= remap_table_1_22;
br_snapshots_7_23 <= remap_table_1_23;
br_snapshots_7_24 <= remap_table_1_24;
br_snapshots_7_25 <= remap_table_1_25;
br_snapshots_7_26 <= remap_table_1_26;
br_snapshots_7_27 <= remap_table_1_27;
br_snapshots_7_28 <= remap_table_1_28;
br_snapshots_7_29 <= remap_table_1_29;
br_snapshots_7_30 <= remap_table_1_30;
br_snapshots_7_31 <= remap_table_1_31;
end
end
assign io_map_resps_0_prs1 = _GEN[io_map_reqs_0_lrs1[4:0]];
assign io_map_resps_0_prs2 = _GEN[io_map_reqs_0_lrs2[4:0]];
assign io_map_resps_0_stale_pdst = _GEN[io_map_reqs_0_ldst[4:0]];
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
} | module ram_4x65(
input [1:0] R0_addr,
input R0_en,
input R0_clk,
output [64:0] R0_data,
input [1:0] W0_addr,
input W0_en,
input W0_clk,
input [64:0] W0_data
);
reg [64:0] Memory[0:3];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLBToBeat_serial_tl_0_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_bits_head,
output io_beat_bits_tail
);
assign io_beat_bits_head = 1'h1;
assign io_beat_bits_tail = 1'h0;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module mem(
input [12:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata,
input [7:0] RW0_wmask
);
mem_ext mem_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.withClock
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ArrayBuffer
case class RocketCoreParams(
xLen: Int = 64,
pgLevels: Int = 3, // sv39 default
bootFreqHz: BigInt = 0,
useVM: Boolean = true,
useUser: Boolean = false,
useSupervisor: Boolean = false,
useHypervisor: Boolean = false,
useDebug: Boolean = true,
useAtomics: Boolean = true,
useAtomicsOnlyForIO: Boolean = false,
useCompressed: Boolean = true,
useRVE: Boolean = false,
useConditionalZero: Boolean = false,
useZba: Boolean = false,
useZbb: Boolean = false,
useZbs: Boolean = false,
nLocalInterrupts: Int = 0,
useNMI: Boolean = false,
nBreakpoints: Int = 1,
useBPWatch: Boolean = false,
mcontextWidth: Int = 0,
scontextWidth: Int = 0,
nPMPs: Int = 8,
nPerfCounters: Int = 0,
haveBasicCounters: Boolean = true,
haveCFlush: Boolean = false,
misaWritable: Boolean = true,
nL2TLBEntries: Int = 0,
nL2TLBWays: Int = 1,
nPTECacheEntries: Int = 8,
mtvecInit: Option[BigInt] = Some(BigInt(0)),
mtvecWritable: Boolean = true,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
branchPredictionModeCSR: Boolean = false,
clockGate: Boolean = false,
mvendorid: Int = 0, // 0 means non-commercial implementation
mimpid: Int = 0x20181004, // release date in BCD
mulDiv: Option[MulDivParams] = Some(MulDivParams()),
fpu: Option[FPUParams] = Some(FPUParams()),
debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB
haveCease: Boolean = true, // non-standard CEASE instruction
haveSimTimeout: Boolean = true, // add plusarg for simulation timeout
vector: Option[RocketCoreVectorParams] = None
) extends CoreParams {
val lgPauseCycles = 5
val haveFSDirty = false
val pmpGranularity: Int = if (useHypervisor) 4096 else 4
val fetchWidth: Int = if (useCompressed) 2 else 1
// fetchWidth doubled, but coreInstBytes halved, for RVC:
val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1)
val retireWidth: Int = 1
val instBits: Int = if (useCompressed) 16 else 32
val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop
val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace
override val useVector = vector.isDefined
override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false)
override def vLen = vector.map(_.vLen).getOrElse(0)
override def eLen = vector.map(_.eLen).getOrElse(0)
override def vfLen = vector.map(_.vfLen).getOrElse(0)
override def vfh = vector.map(_.vfh).getOrElse(false)
override def vExts = vector.map(_.vExts).getOrElse(Nil)
override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0)
override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction
override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)
override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs
}
trait HasRocketCoreParameters extends HasCoreParameters {
lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams]
val fastLoadWord = rocketParams.fastLoadWord
val fastLoadByte = rocketParams.fastLoadByte
val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this
require(!fastLoadByte || fastLoadWord)
require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty")
}
class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters {
override def bpmCSR = {
rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0))))
}
private def haveDCache = tileParams.dcache.get.scratch.isEmpty
override def chickenCSR = {
val mask = BigInt(
tileParams.dcache.get.clockGate.toInt << 0 |
rocketParams.clockGate.toInt << 1 |
rocketParams.clockGate.toInt << 2 |
1 << 3 | // disableSpeculativeICacheRefill
haveDCache.toInt << 9 | // suppressCorruptOnGrantData
tileParams.icache.get.prefetch.toInt << 17
)
Some(CustomCSR(chickenCSRId, mask, Some(mask)))
}
def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B)
def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1))
def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid))
// mimpid encodes a release version in the form of a BCD-encoded datestamp.
def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid))
override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
}
class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) {
val buserror = Option.when(hasBeu)(Bool())
}
trait HasRocketCoreIO extends HasRocketCoreParameters {
implicit val p: Parameters
def nTotalRoCCCSRs: Int
val io = IO(new CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val reset_vector = Input(UInt(resetVectorLen.W))
val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined))
val imem = new FrontendIO
val dmem = new HellaCacheIO
val ptw = Flipped(new DatapathPTWIO())
val fpu = Flipped(new FPUCoreIO())
val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
val trace = Output(new TraceBundle)
val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
val cease = Output(Bool())
val wfi = Output(Bool())
val traceStall = Input(Bool())
val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None
})
}
class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
with HasRocketCoreParameters
with HasRocketCoreIO {
def nTotalRoCCCSRs = tile.roccCSRs.flatten.size
import ALU._
val clock_en_reg = RegInit(true.B)
val long_latency_stall = Reg(Bool())
val id_reg_pause = Reg(Bool())
val imem_might_request_reg = Reg(Bool())
val clock_en = WireDefault(true.B)
val gated_clock =
if (!rocketParams.clockGate) clock
else ClockGate(clock, clock_en, "rocket_clock_gate")
class RocketImpl { // entering gated-clock domain
// performance counters
def pipelineIDToWB[T <: Data](x: T): T =
RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid)
val perfEvents = new EventSets(Seq(
new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq(
("exception", () => false.B),
("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),
("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),
("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),
("system", () => id_ctrl.csr =/= CSR.N),
("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),
("branch", () => id_ctrl.branch),
("jal", () => id_ctrl.jal),
("jalr", () => id_ctrl.jalr))
++ (if (!usingMulDiv) Seq() else Seq(
("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV),
("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV)))
++ (if (!usingFPU) Seq() else Seq(
("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen),
("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen),
("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23),
("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3),
("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3),
("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)),
("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem),
("long-latency interlock", () => id_sboard_hazard),
("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N),
("I$ blocked", () => icache_blocked),
("D$ blocked", () => id_ctrl.mem && dcache_blocked),
("branch misprediction", () => take_pc_mem && mem_direction_misprediction),
("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked),
("flush", () => wb_reg_flush_pipe),
("replay", () => replay_wb))
++ (if (!usingMulDiv) Seq() else Seq(
("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div)))
++ (if (!usingFPU) Seq() else Seq(
("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
("I$ miss", () => io.imem.perf.acquire),
("D$ miss", () => io.dmem.perf.acquire),
("D$ release", () => io.dmem.perf.release),
("ITLB miss", () => io.imem.perf.tlbMiss),
("DTLB miss", () => io.dmem.perf.tlbMiss),
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen
val decode_table = {
(if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++:
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
(if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
(if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
(if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++:
(usingRoCC.option(new RoCCDecode)) ++:
(if (xLen == 32) new I32Decode else new I64Decode) +:
(usingVM.option(new SVMDecode)) ++:
(usingSupervisor.option(new SDecode)) ++:
(usingHypervisor.option(new HypervisorDecode)) ++:
((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++:
(usingDebug.option(new DebugDecode)) ++:
(usingNMI.option(new NMIDecode)) ++:
(usingConditionalZero.option(new ConditionalZeroDecode)) ++:
Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++:
coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++:
rocketParams.haveCease.option(new CeaseDecode) ++:
usingVector.option(new VCFGDecode) ++:
(if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++:
(if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++:
coreParams.useZbs.option(new ZbsDecode) ++:
Seq(new IDecode)
} flatMap(_.table)
val ex_ctrl = Reg(new IntCtrlSigs)
val mem_ctrl = Reg(new IntCtrlSigs)
val wb_ctrl = Reg(new IntCtrlSigs)
val ex_reg_xcpt_interrupt = Reg(Bool())
val ex_reg_valid = Reg(Bool())
val ex_reg_rvc = Reg(Bool())
val ex_reg_btb_resp = Reg(new BTBResp)
val ex_reg_xcpt = Reg(Bool())
val ex_reg_flush_pipe = Reg(Bool())
val ex_reg_load_use = Reg(Bool())
val ex_reg_cause = Reg(UInt())
val ex_reg_replay = Reg(Bool())
val ex_reg_pc = Reg(UInt())
val ex_reg_mem_size = Reg(UInt())
val ex_reg_hls = Reg(Bool())
val ex_reg_inst = Reg(Bits())
val ex_reg_raw_inst = Reg(UInt())
val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val ex_reg_set_vconfig = Reg(Bool())
val mem_reg_xcpt_interrupt = Reg(Bool())
val mem_reg_valid = Reg(Bool())
val mem_reg_rvc = Reg(Bool())
val mem_reg_btb_resp = Reg(new BTBResp)
val mem_reg_xcpt = Reg(Bool())
val mem_reg_replay = Reg(Bool())
val mem_reg_flush_pipe = Reg(Bool())
val mem_reg_cause = Reg(UInt())
val mem_reg_slow_bypass = Reg(Bool())
val mem_reg_load = Reg(Bool())
val mem_reg_store = Reg(Bool())
val mem_reg_set_vconfig = Reg(Bool())
val mem_reg_sfence = Reg(Bool())
val mem_reg_pc = Reg(UInt())
val mem_reg_inst = Reg(Bits())
val mem_reg_mem_size = Reg(UInt())
val mem_reg_hls_or_dv = Reg(Bool())
val mem_reg_raw_inst = Reg(UInt())
val mem_reg_wdata = Reg(Bits())
val mem_reg_rs2 = Reg(Bits())
val mem_br_taken = Reg(Bool())
val take_pc_mem = Wire(Bool())
val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val wb_reg_valid = Reg(Bool())
val wb_reg_xcpt = Reg(Bool())
val wb_reg_replay = Reg(Bool())
val wb_reg_flush_pipe = Reg(Bool())
val wb_reg_cause = Reg(UInt())
val wb_reg_set_vconfig = Reg(Bool())
val wb_reg_sfence = Reg(Bool())
val wb_reg_pc = Reg(UInt())
val wb_reg_mem_size = Reg(UInt())
val wb_reg_hls_or_dv = Reg(Bool())
val wb_reg_hfence_v = Reg(Bool())
val wb_reg_hfence_g = Reg(Bool())
val wb_reg_inst = Reg(Bits())
val wb_reg_raw_inst = Reg(UInt())
val wb_reg_wdata = Reg(Bits())
val wb_reg_rs2 = Reg(Bits())
val take_pc_wb = Wire(Bool())
val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val take_pc_mem_wb = take_pc_wb || take_pc_mem
val take_pc = take_pc_mem_wb
// decode stage
val ibuf = Module(new IBuf)
val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
val id_raw_inst = ibuf.io.inst.map(_.bits.raw)
val id_inst = id_expanded_inst.map(_.bits)
ibuf.io.imem <> io.imem.resp
ibuf.io.kill := take_pc
require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth)
require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point")
require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor")
val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table)
val lgNXRegs = if (coreParams.useRVE) 4 else 5
val regAddrMask = (1 << lgNXRegs) - 1
def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0))
val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3)
val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2)
val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1)
val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd)
val id_load_use = Wire(Bool())
val id_reg_fence = RegInit(false.B)
val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2)
val id_raddr = IndexedSeq(id_raddr1, id_raddr2)
val rf = new RegFile(regAddrMask, xLen)
val id_rs = id_raddr.map(rf.read _)
val ctrl_killd = Wire(Bool())
val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt
val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined))
val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W)
val id_system_insn = id_ctrl.csr === CSR.I
val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U
val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr))
val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush)
val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B
id_ctrl.vec := false.B
if (usingVector) {
val v_decode = rocketParams.vector.get.decoder(p)
v_decode.io.inst := id_inst(0)
v_decode.io.vconfig := csr.io.vector.get.vconfig
when (v_decode.io.legal) {
id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill
id_ctrl.fp := v_decode.io.fp
id_ctrl.rocc := false.B
id_ctrl.branch := false.B
id_ctrl.jal := false.B
id_ctrl.jalr := false.B
id_ctrl.rxs2 := v_decode.io.read_rs2
id_ctrl.rxs1 := v_decode.io.read_rs1
id_ctrl.mem := false.B
id_ctrl.rfs1 := v_decode.io.read_frs1
id_ctrl.rfs2 := false.B
id_ctrl.rfs3 := false.B
id_ctrl.wfd := v_decode.io.write_frd
id_ctrl.mul := false.B
id_ctrl.div := false.B
id_ctrl.wxd := v_decode.io.write_rd
id_ctrl.csr := CSR.N
id_ctrl.fence_i := false.B
id_ctrl.fence := false.B
id_ctrl.amo := false.B
id_ctrl.dp := false.B
id_ctrl.vec := true.B
}
}
val id_illegal_insn = !id_ctrl.legal ||
(id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) ||
(id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||
id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
id_raddr2_illegal && id_ctrl.rxs2 ||
id_raddr1_illegal && id_ctrl.rxs1 ||
id_waddr_illegal && id_ctrl.wxd ||
id_ctrl.rocc && csr.io.decode(0).rocc_illegal ||
id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) ||
!ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal)
val id_virtual_insn = id_ctrl.legal &&
((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) ||
(!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal))
// stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE)
val id_amo_aq = id_inst(0)(26)
val id_amo_rl = id_inst(0)(25)
val id_fence_pred = id_inst(0)(27,24)
val id_fence_succ = id_inst(0)(23,20)
val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq
val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
when (!id_mem_busy) { id_reg_fence := false.B }
val id_rocc_busy = usingRoCC.B &&
(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren
val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B)
val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) ||
id_vec_busy && id_ctrl.fence ||
id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)))
val bpu = Module(new BreakpointUnit(nBreakpoints))
bpu.io.status := csr.io.status
bpu.io.bp := csr.io.bp
bpu.io.pc := ibuf.io.pc
bpu.io.ea := mem_reg_wdata
bpu.io.mcontext := csr.io.mcontext
bpu.io.scontext := csr.io.scontext
val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0
val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1
val (id_xcpt, id_cause) = checkExceptions(List(
(csr.io.interrupt, csr.io.interrupt_cause),
(bpu.io.debug_if, CSR.debugTriggerCause.U),
(bpu.io.xcpt_if, Causes.breakpoint.U),
(id_xcpt0.pf.inst, Causes.fetch_page_fault.U),
(id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U),
(id_xcpt0.ae.inst, Causes.fetch_access.U),
(id_xcpt1.pf.inst, Causes.fetch_page_fault.U),
(id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U),
(id_xcpt1.ae.inst, Causes.fetch_access.U),
(id_virtual_insn, Causes.virtual_instruction.U),
(id_illegal_insn, Causes.illegal_instruction.U)))
val idCoverCauses = List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREAKPOINT"),
(Causes.fetch_access, "FETCH_ACCESS"),
(Causes.illegal_instruction, "ILLEGAL_INSTRUCTION")
) ++ (if (usingVM) List(
(Causes.fetch_page_fault, "FETCH_PAGE_FAULT")
) else Nil)
coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses)
val dcache_bypass_data =
if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0)
else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0)
else wb_reg_wdata
// detect bypass opportunities
val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U
val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U
val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U
val bypass_sources = IndexedSeq(
(true.B, 0.U, 0.U), // treat reading x0 as a bypass
(ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data))
val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr))
// execute stage
val bypass_mux = bypass_sources.map(_._3)
val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool()))
val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W)))
val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt()))
val ex_rs = for (i <- 0 until id_raddr.size)
yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst)
val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13)
val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq(
A1_RS1 -> ex_rs(0).asSInt,
A1_PC -> ex_reg_pc.asSInt,
A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S)
))
val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt
val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq(
A2_RS2 -> ex_rs(1).asSInt,
A2_IMM -> ex_imm,
A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S),
) ++ (if (coreParams.useZbs) Seq(
A2_RS2OH -> ex_op2_oh,
A2_IMMOH -> ex_op2_oh,
) else Nil))
val (ex_new_vl, ex_new_vconfig) = if (usingVector) {
val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq(
ex_reg_inst(31,30).andR -> ex_reg_inst(29,20),
!ex_reg_inst(31) -> ex_reg_inst(30,20))))
val ex_avl = Mux(ex_ctrl.rxs1,
Mux(ex_reg_inst(19,15) === 0.U,
Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax),
ex_rs(0)
),
ex_reg_inst(19,15))
val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B)
val ex_new_vconfig = Wire(new VConfig)
ex_new_vconfig.vtype := ex_new_vtype
ex_new_vconfig.vl := ex_new_vl
(Some(ex_new_vl), Some(ex_new_vconfig))
} else { (None, None) }
val alu = Module(new ALU)
alu.io.dw := ex_ctrl.alu_dw
alu.io.fn := ex_ctrl.alu_fn
alu.io.in2 := ex_op2.asUInt
alu.io.in1 := ex_op1.asUInt
// multiplier and divider
val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen))
div.io.req.valid := ex_reg_valid && ex_ctrl.div
div.io.req.bits.dw := ex_ctrl.alu_dw
div.io.req.bits.fn := ex_ctrl.alu_fn
div.io.req.bits.in1 := ex_rs(0)
div.io.req.bits.in2 := ex_rs(1)
div.io.req.bits.tag := ex_waddr
val mul = pipelinedMul.option {
val m = Module(new PipelinedMultiplier(xLen, 2))
m.io.req.valid := ex_reg_valid && ex_ctrl.mul
m.io.req.bits := div.io.req.bits
m
}
ex_reg_valid := !ctrl_killd
ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay
ex_reg_xcpt := !ctrl_killd && id_xcpt
ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt
when (!ctrl_killd) {
ex_ctrl := id_ctrl
ex_reg_rvc := ibuf.io.inst(0).bits.rvc
ex_ctrl.csr := id_csr
when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B }
when (id_fence_next) { id_reg_fence := true.B }
when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
ex_ctrl.alu_fn := FN_ADD
ex_ctrl.alu_dw := DW_XPR
ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction
ex_ctrl.sel_alu2 := A2_ZERO
when (id_xcpt1.asUInt.orR) { // badaddr := PC+2
ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_SIZE
ex_reg_rvc := true.B
}
when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC
ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_ZERO
}
}
ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush
ex_reg_load_use := id_load_use
ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX)
ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12))
when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) {
ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U)
}
when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) {
ex_ctrl.mem_cmd := M_HFENCEV
}
if (tile.dcache.flushOnFenceI) {
when (id_ctrl.fence_i) {
ex_reg_mem_size := 0.U
}
}
for (i <- 0 until id_raddr.size) {
val do_bypass = id_bypass_src(i).reduce(_||_)
val bypass_src = PriorityEncoder(id_bypass_src(i))
ex_reg_rs_bypass(i) := do_bypass
ex_reg_rs_lsb(i) := bypass_src
when (id_ren(i) && !do_bypass) {
ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size)
}
}
when (id_illegal_insn || id_virtual_insn) {
val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0))
ex_reg_rs_bypass(0) := false.B
ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size)
}
}
when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {
ex_reg_cause := id_cause
ex_reg_inst := id_inst(0)
ex_reg_raw_inst := id_raw_inst(0)
ex_reg_pc := ibuf.io.pc
ex_reg_btb_resp := ibuf.io.btb_resp
ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) }
ex_reg_set_vconfig := id_set_vconfig && !id_xcpt
}
// replay inst in ex stage?
val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt
val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid
val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready ||
ex_ctrl.div && !div.io.req.ready ||
ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B)
val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use
val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use))
val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid
// detect 2-cycle load-use delay for LB/LH/SC
val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U
val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG)
val (ex_xcpt, ex_cause) = checkExceptions(List(
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause)))
val exCoverCauses = idCoverCauses
coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses)
// memory stage
val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt
val mem_br_target = mem_reg_pc.asSInt +
Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
Mux(mem_reg_rvc, 2.S, 4.S)))
val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt
val mem_wrong_npc =
Mux(ex_pc_valid, mem_npc =/= ex_reg_pc,
Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B))
val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence
val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt
val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal
val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal
val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken)
val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken
take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence)
mem_reg_valid := !ctrl_killx
mem_reg_replay := !take_pc_mem_wb && replay_ex
mem_reg_xcpt := !ctrl_killx && ex_xcpt
mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt
// on pipeline flushes, cause mem_npc to hold the sequential npc, which
// will drive the W-stage npc mux
when (mem_reg_valid && mem_reg_flush_pipe) {
mem_reg_sfence := false.B
}.elsewhen (ex_pc_valid) {
mem_ctrl := ex_ctrl
mem_reg_rvc := ex_reg_rvc
mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd)
mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)
mem_reg_sfence := ex_sfence
mem_reg_btb_resp := ex_reg_btb_resp
mem_reg_flush_pipe := ex_reg_flush_pipe
mem_reg_slow_bypass := ex_slow_bypass
mem_reg_wphit := ex_reg_wphit
mem_reg_set_vconfig := ex_reg_set_vconfig
mem_reg_cause := ex_cause
mem_reg_inst := ex_reg_inst
mem_reg_raw_inst := ex_reg_raw_inst
mem_reg_mem_size := ex_reg_mem_size
mem_reg_hls_or_dv := io.dmem.req.bits.dv
mem_reg_pc := ex_reg_pc
// IDecode ensured they are 1H
mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out)
mem_br_taken := alu.io.cmp_out
when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {
val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size)
mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data
}
if (usingVector) { when (ex_reg_set_vconfig) {
mem_reg_rs2 := ex_new_vconfig.get.asUInt
} }
when (ex_ctrl.jalr && csr.io.status.debug) {
// flush I$ on D-mode JALR to effect uncached fetch without D$ flush
mem_ctrl.fence_i := true.B
mem_reg_flush_pipe := true.B
}
}
val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)
val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List(
(mem_debug_breakpoint, CSR.debugTriggerCause.U),
(mem_breakpoint, Causes.breakpoint.U)))
val (mem_xcpt, mem_cause) = checkExceptions(List(
(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
(mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U),
(mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause)))
val memCoverCauses = (exCoverCauses ++ List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREAKPOINT"),
(Causes.misaligned_fetch, "MISALIGNED_FETCH")
)).distinct
coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses)
val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port
val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem
val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B)
val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B)
val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all
val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
div.io.kill := killm_common && RegNext(div.io.req.fire)
val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem
// writeback stage
wb_reg_valid := !ctrl_killm
wb_reg_replay := replay_mem && !take_pc_wb
wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B)
wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe
when (mem_pc_valid) {
wb_ctrl := mem_ctrl
wb_reg_sfence := mem_reg_sfence
wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)
when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) {
wb_reg_rs2 := mem_reg_rs2
}
wb_reg_cause := mem_cause
wb_reg_inst := mem_reg_inst
wb_reg_raw_inst := mem_reg_raw_inst
wb_reg_mem_size := mem_reg_mem_size
wb_reg_hls_or_dv := mem_reg_hls_or_dv
wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV
wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG
wb_reg_pc := mem_reg_pc
wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) }
wb_reg_set_vconfig := mem_reg_set_vconfig
}
val (wb_xcpt, wb_cause) = checkExceptions(List(
(wb_reg_xcpt, wb_reg_cause),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U)
))
val wbCoverCauses = List(
(Causes.misaligned_store, "MISALIGNED_STORE"),
(Causes.misaligned_load, "MISALIGNED_LOAD"),
(Causes.store_access, "STORE_ACCESS"),
(Causes.load_access, "LOAD_ACCESS")
) ++ (if(usingVM) List(
(Causes.store_page_fault, "STORE_PAGE_FAULT"),
(Causes.load_page_fault, "LOAD_PAGE_FAULT")
) else Nil) ++ (if (usingHypervisor) List(
(Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"),
(Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"),
) else Nil)
coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses)
val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt
val wb_wxd = wb_reg_valid && wb_ctrl.wxd
val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec
val replay_wb_common = io.dmem.s2_nack || wb_reg_replay
val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall
val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B)
val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec
take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe
// writeback arbitration
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool
val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool
val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1)
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay
class LLWB extends Bundle {
val data = UInt(xLen.W)
val tag = UInt(5.W)
}
val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec
ll_arb.io.in.foreach(_.valid := false.B)
ll_arb.io.in.foreach(_.bits := DontCare)
val ll_wdata = WireInit(ll_arb.io.out.bits.data)
val ll_waddr = WireInit(ll_arb.io.out.bits.tag)
val ll_wen = WireInit(ll_arb.io.out.fire)
ll_arb.io.out.ready := !wb_wxd
div.io.resp.ready := ll_arb.io.in(0).ready
ll_arb.io.in(0).valid := div.io.resp.valid
ll_arb.io.in(0).bits.data := div.io.resp.bits.data
ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag
if (usingRoCC) {
io.rocc.resp.ready := ll_arb.io.in(1).ready
ll_arb.io.in(1).valid := io.rocc.resp.valid
ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data
ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd
} else {
// tie off RoCC
io.rocc.resp.ready := false.B
io.rocc.mem.req.ready := false.B
}
io.vector.map { v =>
v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready)
ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp
ll_arb.io.in(2).bits.data := v.resp.bits.data
ll_arb.io.in(2).bits.tag := v.resp.bits.rd
}
// Dont care mem since not all RoCC need accessing memory
io.rocc.mem := DontCare
when (dmem_resp_replay && dmem_resp_xpu) {
ll_arb.io.out.ready := false.B
ll_waddr := dmem_resp_waddr
ll_wen := true.B
}
val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt
val wb_wen = wb_valid && wb_ctrl.wxd
val rf_wen = wb_wen || ll_wen
val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0),
Mux(ll_wen, ll_wdata,
Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata),
wb_reg_wdata))))
when (rf_wen) { rf.write(rf_waddr, rf_wdata) }
// hook up control/status regfile
csr.io.ungated_clock := clock
csr.io.decode(0).inst := id_inst(0)
csr.io.exception := wb_xcpt
csr.io.cause := wb_cause
csr.io.retire := wb_valid
csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst)
csr.io.interrupts := io.interrupts
csr.io.hartid := io.hartid
io.fpu.fcsr_rm := csr.io.fcsr_rm
val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W))
val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B)
csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid
csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid))
io.fpu.time := csr.io.time(31,0)
io.fpu.hartid := io.hartid
csr.io.rocc_interrupt := io.rocc.interrupt
csr.io.pc := wb_reg_pc
val tval_dmem_addr = !wb_reg_xcpt
val tval_any_addr = tval_dmem_addr ||
wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U)
val tval_inst = wb_reg_cause === Causes.illegal_instruction.U
val tval_valid = wb_xcpt && (tval_any_addr || tval_inst)
csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv)
csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)
val (htval, mhtinst_read_pseudo) = {
val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U
val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U)
assert(!htval_valid_imem || io.imem.gpa.valid)
val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR
val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U)
val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits
// read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation
val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem)
(htval, mhtinst_read_pseudo)
}
csr.io.vector.foreach { v =>
v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid
v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig)
v.set_vs_dirty := wb_valid && wb_ctrl.vec
v.set_vstart.valid := wb_valid && wb_reg_set_vconfig
v.set_vstart.bits := 0.U
}
io.vector.foreach { v =>
when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) {
csr.io.pc := v.wb.pc
csr.io.retire := v.wb.retire
csr.io.inst(0) := v.wb.inst
when (v.wb.xcpt && !wb_reg_xcpt) {
wb_xcpt := true.B
wb_cause := v.wb.cause
csr.io.tval := v.wb.tval
}
}
v.wb.store_pending := io.dmem.store_pending
v.wb.vxrm := csr.io.vector.get.vxrm
v.wb.frm := csr.io.fcsr_rm
csr.io.vector.get.set_vxsat := v.set_vxsat
when (v.set_vconfig.valid) {
csr.io.vector.get.set_vconfig.valid := true.B
csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits
}
when (v.set_vstart.valid) {
csr.io.vector.get.set_vstart.valid := true.B
csr.io.vector.get.set_vstart.bits := v.set_vstart.bits
}
}
csr.io.htval := htval
csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo
io.ptw.ptbr := csr.io.ptbr
io.ptw.hgatp := csr.io.hgatp
io.ptw.vsatp := csr.io.vsatp
(io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs }
io.ptw.status := csr.io.status
io.ptw.hstatus := csr.io.hstatus
io.ptw.gstatus := csr.io.gstatus
io.ptw.pmp := csr.io.pmp
csr.io.rw.addr := wb_reg_inst(31,20)
csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr)
csr.io.rw.wdata := wb_reg_wdata
io.rocc.csrs <> csr.io.roccCSRs
io.trace.time := csr.io.time
io.trace.insns := csr.io.trace
if (rocketParams.debugROB.isDefined) {
val sz = rocketParams.debugROB.get.size
if (sz < 1) { // use unsynthesizable ROB
val csr_trace_with_wdata = WireInit(csr.io.trace(0))
csr_trace_with_wdata.wdata.get := rf_wdata
val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception)
val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard)
val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U))
io.vector.foreach { v => when (v.wb.retire) {
should_wb := v.wb.rob_should_wb
has_wb := false.B
wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7))
}}
DebugROB.pushTrace(clock, reset,
io.hartid, csr_trace_with_wdata,
should_wb, has_wb, wb_addr)
io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid)
DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata)
} else { // synthesizable ROB (no FPRs)
require(!usingVector, "Synthesizable ROB does not support vector implementations")
val csr_trace_with_wdata = WireInit(csr.io.trace(0))
csr_trace_with_wdata.wdata.get := rf_wdata
val debug_rob = Module(new HardDebugROB(sz, 32))
debug_rob.io.i_insn := csr_trace_with_wdata
debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) &&
!csr.io.trace(0).exception
debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard
debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)
debug_rob.io.wb_val := ll_wen
debug_rob.io.wb_tag := rf_waddr
debug_rob.io.wb_data := rf_wdata
io.trace.insns(0) := debug_rob.io.o_insn
}
} else {
io.trace.insns := csr.io.trace
}
for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) {
iobpw.valid(0) := wphit
iobpw.action := bp.control.action
// tie off bpwatch valids
iobpw.rvalid.foreach(_ := false.B)
iobpw.wvalid.foreach(_ := false.B)
iobpw.ivalid.foreach(_ := false.B)
}
val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1),
(id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2),
(id_ctrl.wxd && id_waddr =/= 0.U, id_waddr))
val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1),
(io.fpu.dec.ren2, id_raddr2),
(io.fpu.dec.ren3, id_raddr3),
(io.fpu.dec.wen, id_waddr))
val sboard = new Scoreboard(32, true)
sboard.clear(ll_wen, ll_waddr)
def id_sboard_clear_bypass(r: UInt) = {
// ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check
if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r
else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r
}
val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd))
sboard.set(wb_set_sboard && wb_wen, wb_waddr)
// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec
val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr)
val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr)
val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)
// stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.
val mem_mem_cmd_bh =
if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass
else true.B
val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec
val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)
val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr)
val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem)
id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem
val id_vconfig_hazard = id_ctrl.vec && (
(ex_reg_valid && ex_reg_set_vconfig) ||
(mem_reg_valid && mem_reg_set_vconfig) ||
(wb_reg_valid && wb_reg_set_vconfig))
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr)
val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr)
val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb)
val id_stall_fpu = if (usingFPU) {
val fp_sboard = new Scoreboard(32)
fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr)
val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B)
fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag)
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
checkHazards(fp_hazard_targets, fp_sboard.read _)
} else false.B
val dcache_blocked = {
// speculate that a blocked D$ will unblock the cycle after a Grant
val blocked = Reg(Bool())
blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack)
blocked && !io.dmem.perf.grant
}
val rocc_blocked = Reg(Bool())
rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked)
val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
id_vconfig_hazard ||
csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) ||
id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy ||
id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy ||
id_ctrl.fp && id_stall_fpu ||
id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses
id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy
id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay
!clock_en ||
id_do_fence ||
csr.io.csr_stall ||
id_reg_pause ||
io.traceStall
ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt
io.imem.req.valid := take_pc
io.imem.req.bits.speculative := !take_pc_wb
io.imem.req.bits.pc :=
Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
Mux(replay_wb, wb_reg_pc, // replay
mem_npc)) // flush or branch misprediction
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack
io.imem.might_request := {
imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B)
imem_might_request_reg
}
io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common)
io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence
io.imem.sfence.bits.rs1 := wb_reg_mem_size(0)
io.imem.sfence.bits.rs2 := wb_reg_mem_size(1)
io.imem.sfence.bits.addr := wb_reg_wdata
io.imem.sfence.bits.asid := wb_reg_rs2
io.imem.sfence.bits.hv := wb_reg_hfence_v
io.imem.sfence.bits.hg := wb_reg_hfence_g
io.ptw.sfence := io.imem.sfence
ibuf.io.inst(0).ready := !ctrl_stalld
io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken)
io.imem.btb_update.bits.isValid := mem_cfi
io.imem.btb_update.bits.cfiType :=
Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call,
Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret,
Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump,
CFIType.branch)))
io.imem.btb_update.bits.target := io.imem.req.bits.pc
io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc)
io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U)
io.imem.btb_update.bits.prediction := mem_reg_btb_resp
io.imem.btb_update.bits.taken := DontCare
io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb
io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc
io.imem.bht_update.bits.taken := mem_br_taken
io.imem.bht_update.bits.mispredict := mem_wrong_npc
io.imem.bht_update.bits.branch := mem_ctrl.branch
io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht
// Connect RAS in Frontend
io.imem.ras_update := DontCare
io.fpu.valid := !ctrl_killd && id_ctrl.fp
io.fpu.killx := ctrl_killx
io.fpu.killm := killm_common
io.fpu.inst := id_inst(0)
io.fpu.fromint_data := ex_rs(0)
io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu
io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data)
io.fpu.ll_resp_type := io.dmem.resp.bits.size
io.fpu.ll_resp_tag := dmem_resp_waddr
io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate
io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U)
io.vector.map { v =>
when (!(dmem_resp_valid && dmem_resp_fpu)) {
io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp
io.fpu.ll_resp_data := v.resp.bits.data
io.fpu.ll_resp_type := v.resp.bits.size
io.fpu.ll_resp_tag := v.resp.bits.rd
}
}
io.vector.foreach { v =>
v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx
v.ex.inst := ex_reg_inst
v.ex.vconfig := csr.io.vector.get.vconfig
v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart)
v.ex.rs1 := ex_rs(0)
v.ex.rs2 := ex_rs(1)
v.ex.pc := ex_reg_pc
v.mem.frs1 := io.fpu.store_data
v.killm := killm_common
v.status := csr.io.status
}
io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem
val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp)
require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth)
io.dmem.req.bits.tag := ex_dcache_tag
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
io.dmem.req.bits.size := ex_reg_mem_size
io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14))
io.dmem.req.bits.phys := false.B
io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr)
io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv)
io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv
io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U)
io.dmem.req.bits.no_alloc := DontCare
io.dmem.req.bits.no_xcpt := DontCare
io.dmem.req.bits.data := DontCare
io.dmem.req.bits.mask := DontCare
io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2))
io.dmem.s1_data.mask := DontCare
io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem
io.dmem.s2_kill := false.B
// don't let D$ go to sleep if we're probably going to use it soon
io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall
io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
io.rocc.cmd.bits.status := csr.io.status
io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction())
io.rocc.cmd.bits.rs1 := wb_reg_wdata
io.rocc.cmd.bits.rs2 := wb_reg_rs2
// gate the clock
val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc
when (unpause) { id_reg_pause := false.B }
io.cease := csr.io.status.cease && !clock_en_reg
io.wfi := csr.io.status.wfi
if (rocketParams.clockGate) {
long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause
clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid)
clock_en_reg :=
ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight
io.ptw.customCSRs.disableCoreClockGate || // chicken bit
!div.io.req.ready || // mul/div in flight
usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight
io.dmem.replay_next || // long-latency load replaying
(!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending
assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en)
}
// evaluate performance counters
val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid))
csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))
coreMonitorBundle.clock := clock
coreMonitorBundle.reset := reset
coreMonitorBundle.hartid := io.hartid
coreMonitorBundle.timer := csr.io.time(31,0)
coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception
coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen)
coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard
coreMonitorBundle.wrenf := false.B
coreMonitorBundle.wrdst := wb_waddr
coreMonitorBundle.wrdata := rf_wdata
coreMonitorBundle.rd0src := wb_reg_inst(19,15)
coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0)))
coreMonitorBundle.rd1src := wb_reg_inst(24,20)
coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1)))
coreMonitorBundle.inst := csr.io.trace(0).insn
coreMonitorBundle.excpt := csr.io.trace(0).exception
coreMonitorBundle.priv_mode := csr.io.trace(0).priv
if (enableCommitLog) {
val t = csr.io.trace(0)
val rd = wb_waddr
val wfd = wb_ctrl.wfd
val wxd = wb_ctrl.wxd
val has_data = wb_wen && !wb_set_sboard
when (t.valid && !t.exception) {
when (wfd) {
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U)
}
.elsewhen (wxd && rd =/= 0.U && has_data) {
printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata)
}
.elsewhen (wxd && rd =/= 0.U && !has_data) {
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd)
}
.otherwise {
printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn)
}
}
when (ll_wen && rf_waddr =/= 0.U) {
printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
}
}
else {
when (csr.io.trace(0).valid) {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,
coreMonitorBundle.pc,
Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U),
Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U),
coreMonitorBundle.wrenx,
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U),
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U),
coreMonitorBundle.inst, coreMonitorBundle.inst)
}
}
// CoreMonitorBundle for late latency writes
val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen))
xrfWriteBundle.clock := clock
xrfWriteBundle.reset := reset
xrfWriteBundle.hartid := io.hartid
xrfWriteBundle.timer := csr.io.time(31,0)
xrfWriteBundle.valid := false.B
xrfWriteBundle.pc := 0.U
xrfWriteBundle.wrdst := rf_waddr
xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr))
xrfWriteBundle.wrenf := false.B
xrfWriteBundle.wrdata := rf_wdata
xrfWriteBundle.rd0src := 0.U
xrfWriteBundle.rd0val := 0.U
xrfWriteBundle.rd1src := 0.U
xrfWriteBundle.rd1val := 0.U
xrfWriteBundle.inst := 0.U
xrfWriteBundle.excpt := false.B
xrfWriteBundle.priv_mode := csr.io.trace(0).priv
if (rocketParams.haveSimTimeout) PlusArg.timeout(
name = "max_core_cycles",
docstring = "Kill the emulation after INT rdtime cycles. Off if 0."
)(csr.io.time)
} // leaving gated-clock domain
val rocketImpl = withClock (gated_clock) { new RocketImpl }
def checkExceptions(x: Seq[(Bool, UInt)]) =
(WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x)))
def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = {
for ((coverCause, label) <- coverCausesLabels) {
property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}")
}
}
def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
targets.map(h => h._1 && cond(h._2)).reduce(_||_)
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {
// efficient means to compress 64-bit VA into vaddrBits+1 bits
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
val b = vaddrBitsExtended-1
val a = (a0 >> b).asSInt
val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1))
Cat(msb, ea(b-1, 0))
}
class Scoreboard(n: Int, zero: Boolean = false)
{
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
def read(addr: UInt): Bool = r(addr)
def readBypassed(addr: UInt): Bool = _next(addr)
private val _r = RegInit(0.U(n.W))
private val r = if (zero) (_r >> 1 << 1) else _r
private var _next = r
private var ens = false.B
private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U)
private def update(en: Bool, update: UInt) = {
_next = update
ens = ens || en
when (ens) { _r := _next }
}
}
}
class RegFile(n: Int, w: Int, zero: Boolean = false) {
val rf = Mem(n, UInt(w.W))
private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0))
private val reads = ArrayBuffer[(UInt,UInt)]()
private var canRead = true
def read(addr: UInt) = {
require(canRead)
reads += addr -> Wire(UInt())
reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr))
reads.last._2
}
def write(addr: UInt, data: UInt) = {
canRead = false
when (addr =/= 0.U) {
access(addr) := data
for ((raddr, rdata) <- reads)
when (addr === raddr) { rdata := data }
}
}
}
object ImmGen {
def apply(sel: UInt, inst: UInt) = {
val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt)
val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign)
val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt)
val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S,
Mux(sel === IMM_UJ, inst(20).asSInt,
Mux(sel === IMM_SB, inst(7).asSInt, sign)))
val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25))
val b4_1 = Mux(sel === IMM_U, 0.U,
Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
val b0 = Mux(sel === IMM_S, inst(7),
Mux(sel === IMM_I, inst(20),
Mux(sel === IMM_Z, inst(15), 0.U)))
Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt
}
} | module rf_31x64(
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [63:0] R0_data,
input [4:0] R1_addr,
input R1_en,
input R1_clk,
output [63:0] R1_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [63:0] W0_data
);
reg [63:0] Memory[0:30];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 64'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 64'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2017 SiFive, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of SiFive nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*
s = sigWidth
c_i = newBit
Division:
width of a is (s+2)
Normal
------
(qi + ci * 2^(-i))*b <= a
q0 = 0
r0 = a
q(i+1) = qi + ci*2^(-i)
ri = a - qi*b
r(i+1) = a - q(i+1)*b
= a - qi*b - ci*2^(-i)*b
r(i+1) = ri - ci*2^(-i)*b
ci = ri >= 2^(-i)*b
summary_i = ri != 0
i = 0 to s+1
(s+1)th bit plus summary_(i+1) gives enough information for rounding
If (a < b), then we need to calculate (s+2)th bit and summary_(i+1)
because we need s bits ignoring the leading zero. (This is skipCycle2
part of Hauser's code.)
Hauser
------
sig_i = qi
rem_i = 2^(i-2)*ri
cycle_i = s+3-i
sig_0 = 0
rem_0 = a/4
cycle_0 = s+3
bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)
sig(i+1) = sig(i) + ci*bit_i
rem(i+1) = 2rem_i - ci*b/2
ci = 2rem_i >= b/2
bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)
cycle(i+1) = cycle_i-1
summary_1 = a <> b
summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0
Proof:
2^i*r(i+1) = 2^i*ri - ci*b. Qed
ci = 2^i*ri >= b. Qed
summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0
Now, note that all of ck's cannot be 0, since that means
a is 0. So when you traverse through a chain of 0 ck's,
from the end,
eventually, you reach a non-zero cj. That is exactly the
value of ri as the reminder remains the same. When all ck's
are 0 except c0 (which must be 1) then summary_1 is set
correctly according
to r1 = a-b != 0. So summary(i+1) is always set correctly
according to r(i+1)
Square root:
width of a is (s+1)
Normal
------
(xi + ci*2^(-i))^2 <= a
xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a
x0 = 0
x(i+1) = xi + ci*2^(-i)
ri = a - xi^2
r(i+1) = a - x(i+1)^2
= a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))
= ri - ci*2^(-i)*(2xi+ci*2^(-i))
= ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1
ci = ri >= 2^(-i)*(2xi + 2^(-i))
summary_i = ri != 0
i = 0 to s+1
For odd expression, do 2 steps initially.
(s+1)th bit plus summary_(i+1) gives enough information for rounding.
Hauser
------
sig_i = xi
rem_i = ri*2^(i-1)
cycle_i = s+2-i
bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)
sig_0 = 0
rem_0 = a/2
cycle_0 = s+2
bit_0 = 1 (= 2^s in terms of bit representation)
sig(i+1) = sig_i + ci * bit_i
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
ci = 2*sig_i + bit_i <= 2*rem_i
bit_i = 2^(cycle_i-2) (in terms of bit representation)
cycle(i+1) = cycle_i-1
summary_1 = a - (2^s) (in terms of bit representation)
summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0
Proof:
ci = 2*sig_i + bit_i <= 2*rem_i
ci = 2xi + 2^(-i) <= ri*2^i. Qed
sig(i+1) = sig_i + ci * bit_i
x(i+1) = xi + ci*2^(-i). Qed
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))
r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed
Same argument as before for summary.
------------------------------
Note that all registers are updated normally until cycle == 2.
At cycle == 2, rem is not updated, but all other registers are updated normally.
But, cycle == 1 does not read rem to calculate anything (note that final summary
is calculated using the values at cycle = 2).
*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))
val inReady = RegInit(true.B) // <-> (cycleNum <= 1)
val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)
val sqrtOp_Z = Reg(Bool())
val majorExc_Z = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_Z = Reg(Bool())
val isInf_Z = Reg(Bool())
val isZero_Z = Reg(Bool())
val sign_Z = Reg(Bool())
val sExp_Z = Reg(SInt((expWidth + 2).W))
val fractB_Z = Reg(UInt(sigWidth.W))
val roundingMode_Z = Reg(UInt(3.W))
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
val rem_Z = Reg(UInt((sigWidth + 2).W))
val notZeroRem_Z = Reg(Bool())
val sigX_Z = Reg(UInt((sigWidth + 2).W))
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rawA_S = io.a
val rawB_S = io.b
//*** IMPROVE THESE:
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +&
Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(expWidth + 1, expWidth - 2)
),
sExpQuot_S_div(expWidth - 3, 0)
).asSInt
val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)
val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val idle = cycleNum === 0.U
val entering = inReady && io.inValid
val entering_normalCase = entering && normalCase_S
val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B
val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B
when (! idle || entering) {
def computeCycleNum(f: UInt => UInt): UInt = {
Mux(entering & ! normalCase_S, f(1.U), 0.U) |
Mux(entering_normalCase,
Mux(io.sqrtOp,
Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),
f((sigWidth + 2).U)
),
0.U
) |
Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |
Mux(skipCycle2, f(1.U), 0.U)
}
inReady := computeCycleNum(_ <= 1.U).asBool
rawOutValid := computeCycleNum(_ === 1.U).asBool
cycleNum := computeCycleNum(x => x)
}
io.inReady := inReady
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering) {
sqrtOp_Z := io.sqrtOp
majorExc_Z := majorExc_S
isNaN_Z := isNaN_S
isInf_Z := isInf_S
isZero_Z := isZero_S
sign_Z := sign_S
sExp_Z :=
Mux(io.sqrtOp,
(rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,
sSatExpQuot_S_div
)
roundingMode_Z := io.roundingMode
}
when (entering || ! inReady && sqrtOp_Z) {
fractB_Z :=
Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |
Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |
Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rem =
Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |
Mux(inReady && oddSqrt_S,
Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,
rawA_S.sig(sigWidth - 3, 0)<<3
),
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady, fractB_Z, 0.U) |
Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) |
Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U)
val trialRem = rem.zext -& trialTerm.zext
val newBit = (0.S <= trialRem)
val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0)
val rem2 = nextRem_Z<<1
val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))
val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)
val trialRem2 =
Mux(newBit,
(trialRem<<1) - trialTerm2_newBit1.zext,
(rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)
val newBit2 = (0.S <= trialRem2)
val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)
val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)
processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||
processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||
!(processTwoBits && newBit2) && nextNotZeroRem_Z
val nextRem_Z_2 =
Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |
Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |
Mux(!processTwoBits, nextRem_Z, 0.U)
when (entering || ! inReady) {
notZeroRem_Z := nextNotZeroRem_Z_2
rem_Z := nextRem_Z_2
sigX_Z :=
Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |
Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) |
Mux(! inReady, sigX_Z, 0.U) |
Mux(! inReady && newBit, bitMask, 0.U) |
Mux(processTwoBits && newBit2, bitMask>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := rawOutValid && ! sqrtOp_Z
io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z
io.roundingModeOut := roundingMode_Z
io.invalidExc := majorExc_Z && isNaN_Z
io.infiniteExc := majorExc_Z && ! isNaN_Z
io.rawOut.isNaN := isNaN_Z
io.rawOut.isInf := isInf_Z
io.rawOut.isZero := isZero_Z
io.rawOut.sign := sign_Z
io.rawOut.sExp := sExp_Z
io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val divSqrtRawFN =
Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))
io.inReady := divSqrtRawFN.io.inReady
divSqrtRawFN.io.inValid := io.inValid
divSqrtRawFN.io.sqrtOp := io.sqrtOp
divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
divSqrtRawFN.io.roundingMode := io.roundingMode
io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div
io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt
io.roundingModeOut := divSqrtRawFN.io.roundingModeOut
io.invalidExc := divSqrtRawFN.io.invalidExc
io.infiniteExc := divSqrtRawFN.io.infiniteExc
io.rawOut := divSqrtRawFN.io.rawOut
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecFNToRaw =
Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))
io.inReady := divSqrtRecFNToRaw.io.inReady
divSqrtRecFNToRaw.io.inValid := io.inValid
divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecFNToRaw.io.a := io.a
divSqrtRecFNToRaw.io.b := io.b
divSqrtRecFNToRaw.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module DivSqrtRecFM_small_e11_s53(
input clock,
input reset,
output io_inReady,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [2:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;
wire _divSqrtRecFNToRaw_io_invalidExc;
wire _divSqrtRecFNToRaw_io_infiniteExc;
wire _divSqrtRecFNToRaw_io_rawOut_isNaN;
wire _divSqrtRecFNToRaw_io_rawOut_isInf;
wire _divSqrtRecFNToRaw_io_rawOut_isZero;
wire _divSqrtRecFNToRaw_io_rawOut_sign;
wire [12:0] _divSqrtRecFNToRaw_io_rawOut_sExp;
wire [55:0] _divSqrtRecFNToRaw_io_rawOut_sig;
DivSqrtRecFMToRaw_small_e11_s53 divSqrtRecFNToRaw (
.clock (clock),
.reset (reset),
.io_inReady (io_inReady),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a (io_a),
.io_b (io_b),
.io_roundingMode (io_roundingMode),
.io_rawOutValid_div (io_outValid_div),
.io_rawOutValid_sqrt (io_outValid_sqrt),
.io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)
);
RoundRawFNToRecFN_e11_s53 roundRawFNToRecFN (
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),
.io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module hi_us(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericDeserializer_TLBeatw10_f32_TestHarness_UNIQUIFIED(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output io_out_bits_head,
output io_out_bits_tail
);
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign io_out_bits_head = io_in_bits_flit[1];
assign io_out_bits_tail = io_in_bits_flit[0];
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3.{dontTouch, _}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.AMBAProtField
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType}
import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters}
import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata}
import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle}
import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt}
import scala.collection.mutable.ListBuffer
case class DCacheParams(
nSets: Int = 64,
nWays: Int = 4,
rowBits: Int = 64,
subWordBits: Option[Int] = None,
replacementPolicy: String = "random",
nTLBSets: Int = 1,
nTLBWays: Int = 32,
nTLBBasePageSectors: Int = 4,
nTLBSuperpages: Int = 4,
tagECC: Option[String] = None,
dataECC: Option[String] = None,
dataECCBytes: Int = 1,
nMSHRs: Int = 1,
nSDQ: Int = 17,
nRPQ: Int = 16,
nMMIOs: Int = 1,
blockBytes: Int = 64,
separateUncachedResp: Boolean = false,
acquireBeforeRelease: Boolean = false,
pipelineWayMux: Boolean = false,
clockGate: Boolean = false,
scratch: Option[BigInt] = None) extends L1CacheParams {
def tagCode: Code = Code.fromString(tagECC)
def dataCode: Code = Code.fromString(dataECC)
def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)
def replacement = new RandomReplacement(nWays)
def silentDrop: Boolean = !acquireBeforeRelease
require((!scratch.isDefined || nWays == 1),
"Scratchpad only allowed in direct-mapped cache.")
require((!scratch.isDefined || nMSHRs == 0),
"Scratchpad only allowed in blocking cache.")
if (scratch.isEmpty)
require(isPow2(nSets), s"nSets($nSets) must be pow2")
}
trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters {
val cacheParams = tileParams.dcache.get
val cfg = cacheParams
def wordBits = coreDataBits
def wordBytes = coreDataBytes
def subWordBits = cacheParams.subWordBits.getOrElse(wordBits)
def subWordBytes = subWordBits / 8
def wordOffBits = log2Up(wordBytes)
def beatBytes = cacheBlockBytes / cacheDataBeats
def beatWords = beatBytes / wordBytes
def beatOffBits = log2Up(beatBytes)
def idxMSB = untagBits-1
def idxLSB = blockOffBits
def offsetmsb = idxLSB-1
def offsetlsb = wordOffBits
def rowWords = rowBits/wordBits
def doNarrowRead = coreDataBits * nWays % rowBits == 0
def eccBytes = cacheParams.dataECCBytes
val eccBits = cacheParams.dataECCBytes * 8
val encBits = cacheParams.dataCode.width(eccBits)
val encWordBits = encBits * (wordBits / eccBits)
def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only
def encRowBits = encDataBits*rowWords
def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed
def lrscBackoff = 3 // disallow LRSC reacquisition briefly
def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant
def nIOMSHRs = cacheParams.nMMIOs
def maxUncachedInFlight = cacheParams.nMMIOs
def dataScratchpadSize = cacheParams.dataScratchpadBytes
require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)")
if (!usingDataScratchpad)
require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)")
// would need offset addr for puts if data width < xlen
require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)")
}
abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
with HasL1HellaCacheParameters
abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasL1HellaCacheParameters
/** Bundle definitions for HellaCache interfaces */
trait HasCoreMemOp extends HasL1HellaCacheParameters {
val addr = UInt(coreMaxAddrBits.W)
val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W))
val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W)
val cmd = UInt(M_SZ.W)
val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W)
val signed = Bool()
val dprv = UInt(PRV.SZ.W)
val dv = Bool()
}
trait HasCoreData extends HasCoreParameters {
val data = UInt(coreDataBits.W)
val mask = UInt(coreDataBytes.W)
}
class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp {
val phys = Bool()
val no_resp = Bool() // The dcache may omit generating a response for this request
val no_alloc = Bool()
val no_xcpt = Bool()
}
class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp
with HasCoreData {
val replay = Bool()
val has_data = Bool()
val data_word_bypass = UInt(coreDataBits.W)
val data_raw = UInt(coreDataBits.W)
val store_data = UInt(coreDataBits.W)
}
class AlignmentExceptions extends Bundle {
val ld = Bool()
val st = Bool()
}
class HellaCacheExceptions extends Bundle {
val ma = new AlignmentExceptions
val pf = new AlignmentExceptions
val gf = new AlignmentExceptions
val ae = new AlignmentExceptions
}
class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData
class HellaCachePerfEvents extends Bundle {
val acquire = Bool()
val release = Bool()
val grant = Bool()
val tlbMiss = Bool()
val blocked = Bool()
val canAcceptStoreThenLoad = Bool()
val canAcceptStoreThenRMW = Bool()
val canAcceptLoadThenLoad = Bool()
val storeBufferEmptyAfterLoad = Bool()
val storeBufferEmptyAfterStore = Bool()
}
// interface between D$ and processor/DTLB
class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
val req = Decoupled(new HellaCacheReq)
val s1_kill = Output(Bool()) // kill previous cycle's req
val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req
val s2_nack = Input(Bool()) // req from two cycles ago is rejected
val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint)
val s2_kill = Output(Bool()) // kill req from two cycles ago
val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO
val s2_paddr = Input(UInt(paddrBits.W)) // translated address
val resp = Flipped(Valid(new HellaCacheResp))
val replay_next = Input(Bool())
val s2_xcpt = Input(new HellaCacheExceptions)
val s2_gpa = Input(UInt(vaddrBitsExtended.W))
val s2_gpa_is_pte = Input(Bool())
val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp)))
val ordered = Input(Bool())
val store_pending = Input(Bool()) // there is a store in a store buffer somewhere
val perf = Input(new HellaCachePerfEvents())
val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself?
val clock_enabled = Input(Bool()) // is D$ currently being clocked?
}
/** Base classes for Diplomatic TL2 HellaCaches */
abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule
with HasNonDiplomaticTileParameters {
protected val cfg = tileParams.dcache.get
protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(
name = s"Core ${tileId} DCache",
sourceId = IdRange(0, 1 max cfg.nMSHRs),
supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))
protected def mmioClientParameters = Seq(TLMasterParameters.v1(
name = s"Core ${tileId} DCache MMIO",
sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs),
requestFifo = true))
def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = cacheClientParameters ++ mmioClientParameters,
minLatency = 1,
requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField())))))
val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())
val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())
val module: HellaCacheModule
def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)
def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits)
require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$")
}
class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) {
val cpu = Flipped(new HellaCacheIO)
val ptw = new TLBPTWIO()
val errors = new DCacheErrors
val tlb_port = new DCacheTLBPort
}
class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters {
implicit val edge: TLEdgeOut = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new HellaCacheBundle)
val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle)
val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle)
dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals
dontTouch(io.cpu.s1_data)
require(rowBits == edge.bundle.dataBits)
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)
fifoManagers.foreach { m =>
require (m.fifoId == fifoManagers.head.fifoId,
s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+
s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}")
}
}
/** Support overriding which HellaCache is instantiated */
case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply)
object HellaCacheFactory {
def apply(tile: BaseTile)(p: Parameters): HellaCache = {
if (tile.tileParams.dcache.get.nMSHRs == 0)
new DCache(tile.tileId, tile.crossing)(p)
else
new NonBlockingDCache(tile.tileId)(p)
}
}
/** Mix-ins for constructing tiles that have a HellaCache */
trait HasHellaCache { this: BaseTile =>
val module: HasHellaCacheModule
implicit val p: Parameters
var nDCachePorts = 0
lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p))
tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node
dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode }
dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode }
InModuleBody {
dcache.module.io.tlb_port := DontCare
}
}
trait HasHellaCacheModule {
val outer: HasHellaCache with HasTileParameters
implicit val p: Parameters
val dcachePorts = ListBuffer[HellaCacheIO]()
val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p))
outer.dcache.module.io.cpu <> dcacheArb.io.mem
}
/** Metadata array used for all HellaCaches */
class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val coh = new ClientMetadata
val tag = UInt(tagBits.W)
}
object L1Metadata {
def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = {
val meta = Wire(new L1Metadata)
meta.tag := tag
meta.coh := coh
meta
}
}
class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val idx = UInt(idxBits.W)
val way_en = UInt(nWays.W)
val tag = UInt(tagBits.W)
}
class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) {
val data = new L1Metadata
}
class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val rstVal = onReset()
val io = IO(new Bundle {
val read = Flipped(Decoupled(new L1MetaReadReq))
val write = Flipped(Decoupled(new L1MetaWriteReq))
val resp = Output(Vec(nWays, rstVal.cloneType))
})
val rst_cnt = RegInit(0.U(log2Up(nSets+1).W))
val rst = rst_cnt < nSets.U
val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools
val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools
when (rst) { rst_cnt := rst_cnt+1.U }
val metabits = rstVal.getWidth
val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W)))
val wen = rst || io.write.valid
when (wen) {
tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask)
}
io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal)))
io.read.ready := !wen // so really this could be a 6T RAM
io.write.ready := !rst
} | module L1MetadataArray(
input clock,
input reset,
output io_read_ready,
input io_read_valid,
input [5:0] io_read_bits_idx,
output io_write_ready,
input io_write_valid,
input [5:0] io_write_bits_idx,
input [3:0] io_write_bits_way_en,
input [1:0] io_write_bits_data_coh_state,
input [19:0] io_write_bits_data_tag,
output [1:0] io_resp_0_coh_state,
output [19:0] io_resp_0_tag,
output [1:0] io_resp_1_coh_state,
output [19:0] io_resp_1_tag,
output [1:0] io_resp_2_coh_state,
output [19:0] io_resp_2_tag,
output [1:0] io_resp_3_coh_state,
output [19:0] io_resp_3_tag
);
wire tag_array_MPORT_1_en;
wire wen;
wire [87:0] _tag_array_RW0_rdata;
reg [6:0] rst_cnt;
wire [1:0] _wdata_T_coh_state = rst_cnt[6] ? io_write_bits_data_coh_state : 2'h0;
wire [19:0] _wdata_T_tag = rst_cnt[6] ? io_write_bits_data_tag : 20'h0;
assign wen = ~(rst_cnt[6]) | io_write_valid;
assign tag_array_MPORT_1_en = ~wen & io_read_valid;
always @(posedge clock) begin
if (reset)
rst_cnt <= 7'h0;
else if (rst_cnt[6]) begin
end
else
rst_cnt <= rst_cnt + 7'h1;
end
tag_array tag_array (
.RW0_addr (wen ? (rst_cnt[6] ? io_write_bits_idx : rst_cnt[5:0]) : io_read_bits_idx),
.RW0_en (tag_array_MPORT_1_en | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata ({_wdata_T_coh_state, _wdata_T_tag, _wdata_T_coh_state, _wdata_T_tag, _wdata_T_coh_state, _wdata_T_tag, _wdata_T_coh_state, _wdata_T_tag}),
.RW0_rdata (_tag_array_RW0_rdata),
.RW0_wmask (rst_cnt[6] ? io_write_bits_way_en : 4'hF)
);
assign io_read_ready = ~wen;
assign io_write_ready = rst_cnt[6];
assign io_resp_0_coh_state = _tag_array_RW0_rdata[21:20];
assign io_resp_0_tag = _tag_array_RW0_rdata[19:0];
assign io_resp_1_coh_state = _tag_array_RW0_rdata[43:42];
assign io_resp_1_tag = _tag_array_RW0_rdata[41:22];
assign io_resp_2_coh_state = _tag_array_RW0_rdata[65:64];
assign io_resp_2_tag = _tag_array_RW0_rdata[63:44];
assign io_resp_3_coh_state = _tag_array_RW0_rdata[87:86];
assign io_resp_3_tag = _tag_array_RW0_rdata[85:66];
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
import freechips.rocketchip.util._
import ALU._
class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
val fn = Bits(SZ_ALU_FN.W)
val dw = Bits(SZ_DW.W)
val in1 = Bits(dataBits.W)
val in2 = Bits(dataBits.W)
val tag = UInt(tagBits.W)
}
class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {
val data = Bits(dataBits.W)
val full_data = Bits((2*dataBits).W)
val tag = UInt(tagBits.W)
}
class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {
val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))
val kill = Input(Bool())
val resp = Decoupled(new MultiplierResp(dataBits, tagBits))
}
case class MulDivParams(
mulUnroll: Int = 1,
divUnroll: Int = 1,
mulEarlyOut: Boolean = false,
divEarlyOut: Boolean = false,
divEarlyOutGranularity: Int = 1
)
class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)
private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)
def minLatency: Int = (minDivLatency ++ minMulLatency).min
val io = IO(new MultiplierIO(width, log2Up(nXpr)))
val w = io.req.bits.in1.getWidth
val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll
val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0
val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8)
val state = RegInit(s_ready)
val req = Reg(chiselTypeOf(io.req.bits))
val count = Reg(UInt(log2Ceil(
((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++
(cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W))
val neg_out = Reg(Bool())
val isHi = Reg(Bool())
val resHi = Reg(Bool())
val divisor = Reg(Bits((w+1).W)) // div only needs w bits
val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits
val mulDecode = List(
FN_MUL -> List(Y, N, X, X),
FN_MULH -> List(Y, Y, Y, Y),
FN_MULHU -> List(Y, Y, N, N),
FN_MULHSU -> List(Y, Y, Y, N))
val divDecode = List(
FN_DIV -> List(N, N, Y, Y),
FN_REM -> List(N, Y, Y, Y),
FN_DIVU -> List(N, N, N, N),
FN_REMU -> List(N, Y, N, N))
val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(io.req.bits.fn, List(X, X, X, X),
(if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)
require(w == 32 || w == 64)
def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32
def sext(x: Bits, halfW: Bool, signed: Bool) = {
val sign = signed && Mux(halfW, x(w/2-1), x(w-1))
val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))
(Cat(hi, x(w/2-1,0)), sign)
}
val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)
val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)
val subtractor = remainder(2*w,w) - divisor
val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0))
val negated_remainder = -result
if (cfg.divUnroll != 0) when (state === s_neg_inputs) {
when (remainder(w-1)) {
remainder := negated_remainder
}
when (divisor(w-1)) {
divisor := subtractor
}
state := s_div
}
if (cfg.divUnroll != 0) when (state === s_neg_output) {
remainder := negated_remainder
state := s_done_div
resHi := false.B
}
if (cfg.mulUnroll != 0) when (state === s_mul) {
val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
val mplierSign = remainder(w)
val mplier = mulReg(mulw-1,0)
val accum = mulReg(2*mulw,mulw).asSInt
val mpcand = divisor.asSInt
val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum
val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll))
val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out
val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0)
val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U &&
!isHi && (mplier & ~eOutMask) === 0.U
val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))
val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0))
count := count + 1.U
when (eOut || count === (mulw/cfg.mulUnroll-1).U) {
state := s_done_mul
resHi := isHi
}
}
if (cfg.divUnroll != 0) when (state === s_div) {
val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) =>
// the special case for iteration 0 is to save HW, not for correctness
val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0)
val less = difference(w)
Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less)
}.tail
remainder := unrolls.last
when (count === (w/cfg.divUnroll).U) {
state := Mux(neg_out, s_neg_output, s_done_div)
resHi := isHi
if (w % cfg.divUnroll < cfg.divUnroll - 1)
remainder := unrolls(w % cfg.divUnroll)
}
count := count + 1.U
val divby0 = count === 0.U && !subtractor(w)
if (cfg.divEarlyOut) {
val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity)
val alignMask = ~((align-1).U(log2Ceil(w).W))
val divisorMSB = Log2(divisor(w-1,0), w) & alignMask
val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask
val eOutPos = ~(dividendMSB - divisorMSB)
val eOut = count === 0.U && !divby0 && eOutPos >= align.U
when (eOut) {
remainder := remainder(w-1,0) << eOutPos
count := eOutPos >> log2Floor(cfg.divUnroll)
}
}
when (divby0 && !isHi) { neg_out := false.B }
}
when (io.resp.fire || io.kill) {
state := s_ready
}
when (io.req.fire) {
state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))
isHi := cmdHi
resHi := false.B
count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U)
neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)
divisor := Cat(rhs_sign, rhs_in)
remainder := lhs_in
req := io.req.bits
}
val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div)
val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0))
val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2))
io.resp.bits.tag := req.tag
io.resp.bits.data := Cat(hiOut, loOut)
io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0))
io.resp.valid := (state === s_done_mul || state === s_done_div)
io.req.ready := state === s_ready
}
class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {
val io = IO(new Bundle {
val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))
val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))
})
val in = Pipe(io.req)
val decode = List(
FN_MUL -> List(N, X, X),
FN_MULH -> List(Y, Y, Y),
FN_MULHU -> List(Y, N, N),
FN_MULHSU -> List(Y, Y, N))
val cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)
val cmdHalf = (width > 32).B && in.bits.dw === DW_32
val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt
val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt
val prod = lhs * rhs
val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0)))
val resp = Pipe(in, latency-1)
io.resp.valid := resp.valid
io.resp.bits.tag := resp.bits.tag
io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits
io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt
} | module MulDiv(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [4:0] io_req_bits_fn,
input io_req_bits_dw,
input [63:0] io_req_bits_in1,
input [63:0] io_req_bits_in2,
input io_kill,
input io_resp_ready,
output io_resp_valid,
output [63:0] io_resp_bits_data
);
reg [2:0] state;
reg req_dw;
reg [6:0] count;
reg neg_out;
reg isHi;
reg resHi;
reg [64:0] divisor;
reg [129:0] remainder;
wire [63:0] result = resHi ? remainder[128:65] : remainder[63:0];
wire [31:0] loOut = req_dw | state[0] ? result[31:0] : result[63:32];
wire io_resp_valid_0 = state == 3'h6 | (&state);
wire io_req_ready_0 = state == 3'h0;
wire [5:0] _eOutPos_T =
{|(remainder[63:32]), (|(remainder[63:32])) ? {|(remainder[63:48]), (|(remainder[63:48])) ? {|(remainder[63:56]), (|(remainder[63:56])) ? {|(remainder[63:60]), (|(remainder[63:60])) ? (remainder[63] ? 2'h3 : remainder[62] ? 2'h2 : {1'h0, remainder[61]}) : remainder[59] ? 2'h3 : remainder[58] ? 2'h2 : {1'h0, remainder[57]}} : {|(remainder[55:52]), (|(remainder[55:52])) ? (remainder[55] ? 2'h3 : remainder[54] ? 2'h2 : {1'h0, remainder[53]}) : remainder[51] ? 2'h3 : remainder[50] ? 2'h2 : {1'h0, remainder[49]}}} : {|(remainder[47:40]), (|(remainder[47:40])) ? {|(remainder[47:44]), (|(remainder[47:44])) ? (remainder[47] ? 2'h3 : remainder[46] ? 2'h2 : {1'h0, remainder[45]}) : remainder[43] ? 2'h3 : remainder[42] ? 2'h2 : {1'h0, remainder[41]}} : {|(remainder[39:36]), (|(remainder[39:36])) ? (remainder[39] ? 2'h3 : remainder[38] ? 2'h2 : {1'h0, remainder[37]}) : remainder[35] ? 2'h3 : remainder[34] ? 2'h2 : {1'h0, remainder[33]}}}} : {|(remainder[31:16]), (|(remainder[31:16])) ? {|(remainder[31:24]), (|(remainder[31:24])) ? {|(remainder[31:28]), (|(remainder[31:28])) ? (remainder[31] ? 2'h3 : remainder[30] ? 2'h2 : {1'h0, remainder[29]}) : remainder[27] ? 2'h3 : remainder[26] ? 2'h2 : {1'h0, remainder[25]}} : {|(remainder[23:20]), (|(remainder[23:20])) ? (remainder[23] ? 2'h3 : remainder[22] ? 2'h2 : {1'h0, remainder[21]}) : remainder[19] ? 2'h3 : remainder[18] ? 2'h2 : {1'h0, remainder[17]}}} : {|(remainder[15:8]), (|(remainder[15:8])) ? {|(remainder[15:12]), (|(remainder[15:12])) ? (remainder[15] ? 2'h3 : remainder[14] ? 2'h2 : {1'h0, remainder[13]}) : remainder[11] ? 2'h3 : remainder[10] ? 2'h2 : {1'h0, remainder[9]}} : {|(remainder[7:4]), (|(remainder[7:4])) ? (remainder[7] ? 2'h3 : remainder[6] ? 2'h2 : {1'h0, remainder[5]}) : remainder[3] ? 2'h3 : remainder[2] ? 2'h2 : {1'h0, remainder[1]}}}}}
- {|(divisor[63:32]), (|(divisor[63:32])) ? {|(divisor[63:48]), (|(divisor[63:48])) ? {|(divisor[63:56]), (|(divisor[63:56])) ? {|(divisor[63:60]), (|(divisor[63:60])) ? (divisor[63] ? 2'h3 : divisor[62] ? 2'h2 : {1'h0, divisor[61]}) : divisor[59] ? 2'h3 : divisor[58] ? 2'h2 : {1'h0, divisor[57]}} : {|(divisor[55:52]), (|(divisor[55:52])) ? (divisor[55] ? 2'h3 : divisor[54] ? 2'h2 : {1'h0, divisor[53]}) : divisor[51] ? 2'h3 : divisor[50] ? 2'h2 : {1'h0, divisor[49]}}} : {|(divisor[47:40]), (|(divisor[47:40])) ? {|(divisor[47:44]), (|(divisor[47:44])) ? (divisor[47] ? 2'h3 : divisor[46] ? 2'h2 : {1'h0, divisor[45]}) : divisor[43] ? 2'h3 : divisor[42] ? 2'h2 : {1'h0, divisor[41]}} : {|(divisor[39:36]), (|(divisor[39:36])) ? (divisor[39] ? 2'h3 : divisor[38] ? 2'h2 : {1'h0, divisor[37]}) : divisor[35] ? 2'h3 : divisor[34] ? 2'h2 : {1'h0, divisor[33]}}}} : {|(divisor[31:16]), (|(divisor[31:16])) ? {|(divisor[31:24]), (|(divisor[31:24])) ? {|(divisor[31:28]), (|(divisor[31:28])) ? (divisor[31] ? 2'h3 : divisor[30] ? 2'h2 : {1'h0, divisor[29]}) : divisor[27] ? 2'h3 : divisor[26] ? 2'h2 : {1'h0, divisor[25]}} : {|(divisor[23:20]), (|(divisor[23:20])) ? (divisor[23] ? 2'h3 : divisor[22] ? 2'h2 : {1'h0, divisor[21]}) : divisor[19] ? 2'h3 : divisor[18] ? 2'h2 : {1'h0, divisor[17]}}} : {|(divisor[15:8]), (|(divisor[15:8])) ? {|(divisor[15:12]), (|(divisor[15:12])) ? (divisor[15] ? 2'h3 : divisor[14] ? 2'h2 : {1'h0, divisor[13]}) : divisor[11] ? 2'h3 : divisor[10] ? 2'h2 : {1'h0, divisor[9]}} : {|(divisor[7:4]), (|(divisor[7:4])) ? (divisor[7] ? 2'h3 : divisor[6] ? 2'h2 : {1'h0, divisor[5]}) : divisor[3] ? 2'h3 : divisor[2] ? 2'h2 : {1'h0, divisor[1]}}}}};
wire [65:0] _prod_T_4 = {{65{remainder[64]}}, remainder[0]} * {divisor[64], divisor} + {remainder[129], remainder[129:65]};
wire [2:0] decoded_invInputs = ~(io_req_bits_fn[2:0]);
wire [1:0] _decoded_andMatrixOutputs_T = {decoded_invInputs[1], decoded_invInputs[2]};
wire [1:0] _decoded_orMatrixOutputs_T_4 = {&{io_req_bits_fn[0], decoded_invInputs[2]}, io_req_bits_fn[1]};
wire lhs_sign = (|{decoded_invInputs[0], &_decoded_andMatrixOutputs_T}) & (io_req_bits_dw ? io_req_bits_in1[63] : io_req_bits_in1[31]);
wire rhs_sign = (|{&_decoded_andMatrixOutputs_T, &{decoded_invInputs[0], io_req_bits_fn[2]}}) & (io_req_bits_dw ? io_req_bits_in2[63] : io_req_bits_in2[31]);
wire [64:0] _subtractor_T_1 = remainder[128:64] - divisor;
wire _GEN = state == 3'h1;
wire _GEN_0 = state == 3'h5;
wire _GEN_1 = state == 3'h2;
wire _GEN_2 = _GEN_1 & count == 7'h3F;
wire _GEN_3 = state == 3'h3;
wire _GEN_4 = count == 7'h40;
wire _eOut_T_9 = count == 7'h0;
wire divby0 = _eOut_T_9 & ~(_subtractor_T_1[64]);
wire _GEN_5 = io_req_ready_0 & io_req_valid;
wire eOut_1 = _eOut_T_9 & ~divby0 & _eOutPos_T != 6'h3F;
always @(posedge clock) begin
if (reset)
state <= 3'h0;
else if (_GEN_5)
state <= decoded_invInputs[2] ? 3'h2 : {1'h0, ~(lhs_sign | rhs_sign), 1'h1};
else if (io_resp_ready & io_resp_valid_0 | io_kill)
state <= 3'h0;
else if (_GEN_3 & _GEN_4)
state <= {1'h1, ~neg_out, 1'h1};
else if (_GEN_2)
state <= 3'h6;
else if (_GEN_0)
state <= 3'h7;
else if (_GEN)
state <= 3'h3;
if (_GEN_5) begin
req_dw <= io_req_bits_dw;
count <= {1'h0, decoded_invInputs[2] & ~io_req_bits_dw, 5'h0};
isHi <= |_decoded_orMatrixOutputs_T_4;
divisor <= {rhs_sign, io_req_bits_dw ? io_req_bits_in2[63:32] : {32{rhs_sign}}, io_req_bits_in2[31:0]};
remainder <= {66'h0, io_req_bits_dw ? io_req_bits_in1[63:32] : {32{lhs_sign}}, io_req_bits_in1[31:0]};
end
else begin
if (_GEN_3) begin
count <= eOut_1 ? {1'h0, ~_eOutPos_T} : count + 7'h1;
remainder <= eOut_1 ? {3'h0, {63'h0, remainder[63:0]} << ~_eOutPos_T} : {1'h0, _subtractor_T_1[64] ? remainder[127:64] : _subtractor_T_1[63:0], remainder[63:0], ~(_subtractor_T_1[64])};
end
else if (_GEN_1) begin
count <= count + 7'h1;
remainder <= {_prod_T_4[65:1], count == 7'h3E & neg_out, _prod_T_4[0], remainder[63:1]};
end
else if (_GEN_0 | _GEN & remainder[63])
remainder <= {66'h0, 64'h0 - result};
if (_GEN & divisor[63])
divisor <= _subtractor_T_1;
end
neg_out <= _GEN_5 ? ((|_decoded_orMatrixOutputs_T_4) ? lhs_sign : lhs_sign != rhs_sign) : ~(_GEN_3 & divby0 & ~isHi) & neg_out;
resHi <= ~_GEN_5 & (_GEN_3 & _GEN_4 | _GEN_2 ? isHi : ~_GEN_0 & resHi);
end
assign io_req_ready = io_req_ready_0;
assign io_resp_valid = io_resp_valid_0;
assign io_resp_bits_data = {req_dw ? result[63:32] : {32{loOut[31]}}, loOut};
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3.{dontTouch, _}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.AMBAProtField
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType}
import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters}
import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata}
import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle}
import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt}
import scala.collection.mutable.ListBuffer
case class DCacheParams(
nSets: Int = 64,
nWays: Int = 4,
rowBits: Int = 64,
subWordBits: Option[Int] = None,
replacementPolicy: String = "random",
nTLBSets: Int = 1,
nTLBWays: Int = 32,
nTLBBasePageSectors: Int = 4,
nTLBSuperpages: Int = 4,
tagECC: Option[String] = None,
dataECC: Option[String] = None,
dataECCBytes: Int = 1,
nMSHRs: Int = 1,
nSDQ: Int = 17,
nRPQ: Int = 16,
nMMIOs: Int = 1,
blockBytes: Int = 64,
separateUncachedResp: Boolean = false,
acquireBeforeRelease: Boolean = false,
pipelineWayMux: Boolean = false,
clockGate: Boolean = false,
scratch: Option[BigInt] = None) extends L1CacheParams {
def tagCode: Code = Code.fromString(tagECC)
def dataCode: Code = Code.fromString(dataECC)
def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)
def replacement = new RandomReplacement(nWays)
def silentDrop: Boolean = !acquireBeforeRelease
require((!scratch.isDefined || nWays == 1),
"Scratchpad only allowed in direct-mapped cache.")
require((!scratch.isDefined || nMSHRs == 0),
"Scratchpad only allowed in blocking cache.")
if (scratch.isEmpty)
require(isPow2(nSets), s"nSets($nSets) must be pow2")
}
trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters {
val cacheParams = tileParams.dcache.get
val cfg = cacheParams
def wordBits = coreDataBits
def wordBytes = coreDataBytes
def subWordBits = cacheParams.subWordBits.getOrElse(wordBits)
def subWordBytes = subWordBits / 8
def wordOffBits = log2Up(wordBytes)
def beatBytes = cacheBlockBytes / cacheDataBeats
def beatWords = beatBytes / wordBytes
def beatOffBits = log2Up(beatBytes)
def idxMSB = untagBits-1
def idxLSB = blockOffBits
def offsetmsb = idxLSB-1
def offsetlsb = wordOffBits
def rowWords = rowBits/wordBits
def doNarrowRead = coreDataBits * nWays % rowBits == 0
def eccBytes = cacheParams.dataECCBytes
val eccBits = cacheParams.dataECCBytes * 8
val encBits = cacheParams.dataCode.width(eccBits)
val encWordBits = encBits * (wordBits / eccBits)
def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only
def encRowBits = encDataBits*rowWords
def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed
def lrscBackoff = 3 // disallow LRSC reacquisition briefly
def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant
def nIOMSHRs = cacheParams.nMMIOs
def maxUncachedInFlight = cacheParams.nMMIOs
def dataScratchpadSize = cacheParams.dataScratchpadBytes
require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)")
if (!usingDataScratchpad)
require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)")
// would need offset addr for puts if data width < xlen
require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)")
}
abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
with HasL1HellaCacheParameters
abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasL1HellaCacheParameters
/** Bundle definitions for HellaCache interfaces */
trait HasCoreMemOp extends HasL1HellaCacheParameters {
val addr = UInt(coreMaxAddrBits.W)
val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W))
val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W)
val cmd = UInt(M_SZ.W)
val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W)
val signed = Bool()
val dprv = UInt(PRV.SZ.W)
val dv = Bool()
}
trait HasCoreData extends HasCoreParameters {
val data = UInt(coreDataBits.W)
val mask = UInt(coreDataBytes.W)
}
class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp {
val phys = Bool()
val no_resp = Bool() // The dcache may omit generating a response for this request
val no_alloc = Bool()
val no_xcpt = Bool()
}
class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp
with HasCoreData {
val replay = Bool()
val has_data = Bool()
val data_word_bypass = UInt(coreDataBits.W)
val data_raw = UInt(coreDataBits.W)
val store_data = UInt(coreDataBits.W)
}
class AlignmentExceptions extends Bundle {
val ld = Bool()
val st = Bool()
}
class HellaCacheExceptions extends Bundle {
val ma = new AlignmentExceptions
val pf = new AlignmentExceptions
val gf = new AlignmentExceptions
val ae = new AlignmentExceptions
}
class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData
class HellaCachePerfEvents extends Bundle {
val acquire = Bool()
val release = Bool()
val grant = Bool()
val tlbMiss = Bool()
val blocked = Bool()
val canAcceptStoreThenLoad = Bool()
val canAcceptStoreThenRMW = Bool()
val canAcceptLoadThenLoad = Bool()
val storeBufferEmptyAfterLoad = Bool()
val storeBufferEmptyAfterStore = Bool()
}
// interface between D$ and processor/DTLB
class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
val req = Decoupled(new HellaCacheReq)
val s1_kill = Output(Bool()) // kill previous cycle's req
val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req
val s2_nack = Input(Bool()) // req from two cycles ago is rejected
val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint)
val s2_kill = Output(Bool()) // kill req from two cycles ago
val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO
val s2_paddr = Input(UInt(paddrBits.W)) // translated address
val resp = Flipped(Valid(new HellaCacheResp))
val replay_next = Input(Bool())
val s2_xcpt = Input(new HellaCacheExceptions)
val s2_gpa = Input(UInt(vaddrBitsExtended.W))
val s2_gpa_is_pte = Input(Bool())
val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp)))
val ordered = Input(Bool())
val store_pending = Input(Bool()) // there is a store in a store buffer somewhere
val perf = Input(new HellaCachePerfEvents())
val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself?
val clock_enabled = Input(Bool()) // is D$ currently being clocked?
}
/** Base classes for Diplomatic TL2 HellaCaches */
abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule
with HasNonDiplomaticTileParameters {
protected val cfg = tileParams.dcache.get
protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(
name = s"Core ${tileId} DCache",
sourceId = IdRange(0, 1 max cfg.nMSHRs),
supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))
protected def mmioClientParameters = Seq(TLMasterParameters.v1(
name = s"Core ${tileId} DCache MMIO",
sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs),
requestFifo = true))
def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = cacheClientParameters ++ mmioClientParameters,
minLatency = 1,
requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField())))))
val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())
val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())
val module: HellaCacheModule
def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)
def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits)
require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$")
}
class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) {
val cpu = Flipped(new HellaCacheIO)
val ptw = new TLBPTWIO()
val errors = new DCacheErrors
val tlb_port = new DCacheTLBPort
}
class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters {
implicit val edge: TLEdgeOut = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new HellaCacheBundle)
val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle)
val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle)
dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals
dontTouch(io.cpu.s1_data)
require(rowBits == edge.bundle.dataBits)
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)
fifoManagers.foreach { m =>
require (m.fifoId == fifoManagers.head.fifoId,
s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+
s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}")
}
}
/** Support overriding which HellaCache is instantiated */
case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply)
object HellaCacheFactory {
def apply(tile: BaseTile)(p: Parameters): HellaCache = {
if (tile.tileParams.dcache.get.nMSHRs == 0)
new DCache(tile.tileId, tile.crossing)(p)
else
new NonBlockingDCache(tile.tileId)(p)
}
}
/** Mix-ins for constructing tiles that have a HellaCache */
trait HasHellaCache { this: BaseTile =>
val module: HasHellaCacheModule
implicit val p: Parameters
var nDCachePorts = 0
lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p))
tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node
dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode }
dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode }
InModuleBody {
dcache.module.io.tlb_port := DontCare
}
}
trait HasHellaCacheModule {
val outer: HasHellaCache with HasTileParameters
implicit val p: Parameters
val dcachePorts = ListBuffer[HellaCacheIO]()
val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p))
outer.dcache.module.io.cpu <> dcacheArb.io.mem
}
/** Metadata array used for all HellaCaches */
class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val coh = new ClientMetadata
val tag = UInt(tagBits.W)
}
object L1Metadata {
def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = {
val meta = Wire(new L1Metadata)
meta.tag := tag
meta.coh := coh
meta
}
}
class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val idx = UInt(idxBits.W)
val way_en = UInt(nWays.W)
val tag = UInt(tagBits.W)
}
class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) {
val data = new L1Metadata
}
class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val rstVal = onReset()
val io = IO(new Bundle {
val read = Flipped(Decoupled(new L1MetaReadReq))
val write = Flipped(Decoupled(new L1MetaWriteReq))
val resp = Output(Vec(nWays, rstVal.cloneType))
})
val rst_cnt = RegInit(0.U(log2Up(nSets+1).W))
val rst = rst_cnt < nSets.U
val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools
val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools
when (rst) { rst_cnt := rst_cnt+1.U }
val metabits = rstVal.getWidth
val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W)))
val wen = rst || io.write.valid
when (wen) {
tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask)
}
io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal)))
io.read.ready := !wen // so really this could be a 6T RAM
io.write.ready := !rst
} | module tag_array(
input [5:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [87:0] RW0_wdata,
output [87:0] RW0_rdata,
input [3:0] RW0_wmask
);
tag_array_ext tag_array_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module dataArrayWay_0(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
dataArrayWay_0_ext dataArrayWay_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module table_4(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [51:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [51:0] W0_data,
input [3:0] W0_mask
);
table_1_ext table_1_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2012 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Datapath: Rename Logic
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Supports 1-cycle and 2-cycle latencies. (aka, passthrough versus registers between ren1 and ren2).
// - ren1: read the map tables and allocate a new physical register from the freelist.
// - ren2: read the busy table for the physical operands.
//
// Ren1 data is provided as an output to be fed directly into the ROB.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
/**
* IO bundle to interface with the Register Rename logic
*
* @param plWidth pipeline width
* @param numIntPregs number of int physical registers
* @param numFpPregs number of FP physical registers
* @param numWbPorts number of int writeback ports
* @param numWbPorts number of FP writeback ports
*/
class RenameStageIO(
val plWidth: Int,
val numPhysRegs: Int,
val numWbPorts: Int)
(implicit p: Parameters) extends BoomBundle
/**
* IO bundle to debug the rename stage
*/
class DebugRenameStageIO(val numPhysRegs: Int)(implicit p: Parameters) extends BoomBundle
{
val freelist = Bits(numPhysRegs.W)
val isprlist = Bits(numPhysRegs.W)
val busytable = UInt(numPhysRegs.W)
}
abstract class AbstractRenameStage(
plWidth: Int,
numPhysRegs: Int,
numWbPorts: Int)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val ren_stalls = Output(Vec(plWidth, Bool()))
val kill = Input(Bool())
val dec_fire = Input(Vec(plWidth, Bool())) // will commit state updates
val dec_uops = Input(Vec(plWidth, new MicroOp()))
// physical specifiers available AND busy/ready status available.
val ren2_mask = Vec(plWidth, Output(Bool())) // mask of valid instructions
val ren2_uops = Vec(plWidth, Output(new MicroOp()))
// branch resolution (execute)
val brupdate = Input(new BrUpdateInfo())
val dis_fire = Input(Vec(coreWidth, Bool()))
val dis_ready = Input(Bool())
// wakeup ports
val wakeups = Flipped(Vec(numWbPorts, Valid(new ExeUnitResp(xLen))))
// commit stage
val com_valids = Input(Vec(plWidth, Bool()))
val com_uops = Input(Vec(plWidth, new MicroOp()))
val rbk_valids = Input(Vec(plWidth, Bool()))
val rollback = Input(Bool())
val debug_rob_empty = Input(Bool())
val debug = Output(new DebugRenameStageIO(numPhysRegs))
})
io.ren_stalls.foreach(_ := false.B)
io.debug := DontCare
def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp
//-------------------------------------------------------------
// Pipeline State & Wires
// Stage 1
val ren1_fire = Wire(Vec(plWidth, Bool()))
val ren1_uops = Wire(Vec(plWidth, new MicroOp))
// Stage 2
val ren2_fire = io.dis_fire
val ren2_ready = io.dis_ready
val ren2_valids = Wire(Vec(plWidth, Bool()))
val ren2_uops = Wire(Vec(plWidth, new MicroOp))
val ren2_alloc_reqs = Wire(Vec(plWidth, Bool()))
//-------------------------------------------------------------
// pipeline registers
for (w <- 0 until plWidth) {
ren1_fire(w) := io.dec_fire(w)
ren1_uops(w) := io.dec_uops(w)
}
for (w <- 0 until plWidth) {
val r_valid = RegInit(false.B)
val r_uop = Reg(new MicroOp)
val next_uop = Wire(new MicroOp)
next_uop := r_uop
when (io.kill) {
r_valid := false.B
} .elsewhen (ren2_ready) {
r_valid := ren1_fire(w)
next_uop := ren1_uops(w)
} .otherwise {
r_valid := r_valid && !ren2_fire(w) // clear bit if uop gets dispatched
next_uop := r_uop
}
r_uop := GetNewUopAndBrMask(BypassAllocations(next_uop, ren2_uops, ren2_alloc_reqs), io.brupdate)
ren2_valids(w) := r_valid
ren2_uops(w) := r_uop
}
//-------------------------------------------------------------
// Outputs
io.ren2_mask := ren2_valids
}
/**
* Rename stage that connets the map table, free list, and busy table.
* Can be used in both the FP pipeline and the normal execute pipeline.
*
* @param plWidth pipeline width
* @param numWbPorts number of int writeback ports
* @param numWbPorts number of FP writeback ports
*/
class RenameStage(
plWidth: Int,
numPhysRegs: Int,
numWbPorts: Int,
float: Boolean)
(implicit p: Parameters) extends AbstractRenameStage(plWidth, numPhysRegs, numWbPorts)(p)
{
val pregSz = log2Ceil(numPhysRegs)
val rtype = if (float) RT_FLT else RT_FIX
//-------------------------------------------------------------
// Helper Functions
def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = {
val bypassed_uop = Wire(new MicroOp)
bypassed_uop := uop
val bypass_hits_rs1 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs1 }
val bypass_hits_rs2 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs2 }
val bypass_hits_rs3 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs3 }
val bypass_hits_dst = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.ldst }
val bypass_sel_rs1 = PriorityEncoderOH(bypass_hits_rs1.reverse).reverse
val bypass_sel_rs2 = PriorityEncoderOH(bypass_hits_rs2.reverse).reverse
val bypass_sel_rs3 = PriorityEncoderOH(bypass_hits_rs3.reverse).reverse
val bypass_sel_dst = PriorityEncoderOH(bypass_hits_dst.reverse).reverse
val do_bypass_rs1 = bypass_hits_rs1.reduce(_||_)
val do_bypass_rs2 = bypass_hits_rs2.reduce(_||_)
val do_bypass_rs3 = bypass_hits_rs3.reduce(_||_)
val do_bypass_dst = bypass_hits_dst.reduce(_||_)
val bypass_pdsts = older_uops.map(_.pdst)
when (do_bypass_rs1) { bypassed_uop.prs1 := Mux1H(bypass_sel_rs1, bypass_pdsts) }
when (do_bypass_rs2) { bypassed_uop.prs2 := Mux1H(bypass_sel_rs2, bypass_pdsts) }
when (do_bypass_rs3) { bypassed_uop.prs3 := Mux1H(bypass_sel_rs3, bypass_pdsts) }
when (do_bypass_dst) { bypassed_uop.stale_pdst := Mux1H(bypass_sel_dst, bypass_pdsts) }
bypassed_uop.prs1_busy := uop.prs1_busy || do_bypass_rs1
bypassed_uop.prs2_busy := uop.prs2_busy || do_bypass_rs2
bypassed_uop.prs3_busy := uop.prs3_busy || do_bypass_rs3
if (!float) {
bypassed_uop.prs3 := DontCare
bypassed_uop.prs3_busy := false.B
}
bypassed_uop
}
//-------------------------------------------------------------
// Rename Structures
val maptable = Module(new RenameMapTable(
plWidth,
32,
numPhysRegs,
false,
float))
val freelist = Module(new RenameFreeList(
plWidth,
numPhysRegs,
if (float) 32 else 31))
val busytable = Module(new RenameBusyTable(
plWidth,
numPhysRegs,
numWbPorts,
false,
float))
val ren2_br_tags = Wire(Vec(plWidth, Valid(UInt(brTagSz.W))))
// Commit/Rollback
val com_valids = Wire(Vec(plWidth, Bool()))
val rbk_valids = Wire(Vec(plWidth, Bool()))
for (w <- 0 until plWidth) {
ren2_alloc_reqs(w) := ren2_uops(w).ldst_val && ren2_uops(w).dst_rtype === rtype && ren2_fire(w)
ren2_br_tags(w).valid := ren2_fire(w) && ren2_uops(w).allocate_brtag
com_valids(w) := io.com_uops(w).ldst_val && io.com_uops(w).dst_rtype === rtype && io.com_valids(w)
rbk_valids(w) := io.com_uops(w).ldst_val && io.com_uops(w).dst_rtype === rtype && io.rbk_valids(w)
ren2_br_tags(w).bits := ren2_uops(w).br_tag
}
//-------------------------------------------------------------
// Rename Table
// Maptable inputs.
val map_reqs = Wire(Vec(plWidth, new MapReq(lregSz)))
val remap_reqs = Wire(Vec(plWidth, new RemapReq(lregSz, pregSz)))
// Generate maptable requests.
for ((((ren1,ren2),com),w) <- (ren1_uops zip ren2_uops zip io.com_uops.reverse).zipWithIndex) {
map_reqs(w).lrs1 := ren1.lrs1
map_reqs(w).lrs2 := ren1.lrs2
map_reqs(w).lrs3 := ren1.lrs3
map_reqs(w).ldst := ren1.ldst
remap_reqs(w).ldst := Mux(io.rollback, com.ldst , ren2.ldst)
remap_reqs(w).pdst := Mux(io.rollback, com.stale_pdst, ren2.pdst)
}
ren2_alloc_reqs zip rbk_valids.reverse zip remap_reqs map {
case ((a,r),rr) => rr.valid := a || r}
// Hook up inputs.
maptable.io.map_reqs := map_reqs
maptable.io.remap_reqs := remap_reqs
maptable.io.ren_br_tags := ren2_br_tags
maptable.io.brupdate := io.brupdate
maptable.io.rollback := io.rollback
// Maptable outputs.
for ((uop, w) <- ren1_uops.zipWithIndex) {
val mappings = maptable.io.map_resps(w)
uop.prs1 := mappings.prs1
uop.prs2 := mappings.prs2
uop.prs3 := mappings.prs3 // only FP has 3rd operand
uop.stale_pdst := mappings.stale_pdst
}
//-------------------------------------------------------------
// Free List
// Freelist inputs.
freelist.io.reqs := ren2_alloc_reqs
freelist.io.dealloc_pregs zip com_valids zip rbk_valids map
{case ((d,c),r) => d.valid := c || r}
freelist.io.dealloc_pregs zip io.com_uops map
{case (d,c) => d.bits := Mux(io.rollback, c.pdst, c.stale_pdst)}
freelist.io.ren_br_tags := ren2_br_tags
freelist.io.brupdate := io.brupdate
freelist.io.debug.pipeline_empty := io.debug_rob_empty
assert (ren2_alloc_reqs zip freelist.io.alloc_pregs map {case (r,p) => !r || p.bits =/= 0.U} reduce (_&&_),
"[rename-stage] A uop is trying to allocate the zero physical register.")
// Freelist outputs.
for ((uop, w) <- ren2_uops.zipWithIndex) {
val preg = freelist.io.alloc_pregs(w).bits
uop.pdst := Mux(uop.ldst =/= 0.U || float.B, preg, 0.U)
}
//-------------------------------------------------------------
// Busy Table
busytable.io.ren_uops := ren2_uops // expects pdst to be set up.
busytable.io.rebusy_reqs := ren2_alloc_reqs
busytable.io.wb_valids := io.wakeups.map(_.valid)
busytable.io.wb_pdsts := io.wakeups.map(_.bits.uop.pdst)
assert (!(io.wakeups.map(x => x.valid && x.bits.uop.dst_rtype =/= rtype).reduce(_||_)),
"[rename] Wakeup has wrong rtype.")
for ((uop, w) <- ren2_uops.zipWithIndex) {
val busy = busytable.io.busy_resps(w)
uop.prs1_busy := uop.lrs1_rtype === rtype && busy.prs1_busy
uop.prs2_busy := uop.lrs2_rtype === rtype && busy.prs2_busy
uop.prs3_busy := uop.frs3_en && busy.prs3_busy
val valid = ren2_valids(w)
assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), "[rename] x0 is busy??")
assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), "[rename] x0 is busy??")
}
//-------------------------------------------------------------
// Outputs
for (w <- 0 until plWidth) {
val can_allocate = freelist.io.alloc_pregs(w).valid
// Push back against Decode stage if Rename1 can't proceed.
io.ren_stalls(w) := (ren2_uops(w).dst_rtype === rtype) && !can_allocate
val bypassed_uop = Wire(new MicroOp)
if (w > 0) bypassed_uop := BypassAllocations(ren2_uops(w), ren2_uops.slice(0,w), ren2_alloc_reqs.slice(0,w))
else bypassed_uop := ren2_uops(w)
io.ren2_uops(w) := GetNewUopAndBrMask(bypassed_uop, io.brupdate)
}
//-------------------------------------------------------------
// Debug signals
io.debug.freelist := freelist.io.debug.freelist
io.debug.isprlist := freelist.io.debug.isprlist
io.debug.busytable := busytable.io.debug.busytable
}
class PredRenameStage(
plWidth: Int,
numPhysRegs: Int,
numWbPorts: Int)
(implicit p: Parameters) extends AbstractRenameStage(plWidth, numPhysRegs, numWbPorts)(p)
{
def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = {
uop
}
ren2_alloc_reqs := DontCare
val busy_table = RegInit(VecInit(0.U(ftqSz.W).asBools))
val to_busy = WireInit(VecInit(0.U(ftqSz.W).asBools))
val unbusy = WireInit(VecInit(0.U(ftqSz.W).asBools))
val current_ftq_idx = Reg(UInt(log2Ceil(ftqSz).W))
var next_ftq_idx = current_ftq_idx
for (w <- 0 until plWidth) {
io.ren2_uops(w) := ren2_uops(w)
val is_sfb_br = ren2_uops(w).is_sfb_br && ren2_fire(w)
val is_sfb_shadow = ren2_uops(w).is_sfb_shadow && ren2_fire(w)
val ftq_idx = ren2_uops(w).ftq_idx
when (is_sfb_br) {
io.ren2_uops(w).pdst := ftq_idx
to_busy(ftq_idx) := true.B
}
next_ftq_idx = Mux(is_sfb_br, ftq_idx, next_ftq_idx)
when (is_sfb_shadow) {
io.ren2_uops(w).ppred := next_ftq_idx
io.ren2_uops(w).ppred_busy := (busy_table(next_ftq_idx) || to_busy(next_ftq_idx)) && !unbusy(next_ftq_idx)
}
}
for (w <- 0 until numWbPorts) {
when (io.wakeups(w).valid) {
unbusy(io.wakeups(w).bits.uop.pdst) := true.B
}
}
current_ftq_idx := next_ftq_idx
busy_table := ((busy_table.asUInt | to_busy.asUInt) & ~unbusy.asUInt).asBools
} | module RenameStage_1(
input clock,
input reset,
output io_ren_stalls_0,
input io_kill,
input io_dec_uops_0_is_br,
input io_dec_uops_0_is_jalr,
input io_dec_uops_0_is_sfb,
input [2:0] io_dec_uops_0_br_tag,
input [5:0] io_dec_uops_0_ldst,
input [5:0] io_dec_uops_0_lrs1,
input [5:0] io_dec_uops_0_lrs2,
input [5:0] io_dec_uops_0_lrs3,
input io_dec_uops_0_ldst_val,
input [1:0] io_dec_uops_0_dst_rtype,
input [1:0] io_dec_uops_0_lrs1_rtype,
input [1:0] io_dec_uops_0_lrs2_rtype,
input io_dec_uops_0_frs3_en,
output [5:0] io_ren2_uops_0_pdst,
output [5:0] io_ren2_uops_0_prs1,
output [5:0] io_ren2_uops_0_prs2,
output [5:0] io_ren2_uops_0_prs3,
output io_ren2_uops_0_prs1_busy,
output io_ren2_uops_0_prs2_busy,
output io_ren2_uops_0_prs3_busy,
output [5:0] io_ren2_uops_0_stale_pdst,
input [2:0] io_brupdate_b2_uop_br_tag,
input io_brupdate_b2_mispredict,
input io_dis_fire_0,
input io_dis_ready,
input io_wakeups_0_valid,
input [5:0] io_wakeups_0_bits_uop_pdst,
input [1:0] io_wakeups_0_bits_uop_dst_rtype,
input io_wakeups_1_valid,
input [5:0] io_wakeups_1_bits_uop_pdst,
input [1:0] io_wakeups_1_bits_uop_dst_rtype,
input io_com_valids_0,
input [5:0] io_com_uops_0_pdst,
input [5:0] io_com_uops_0_stale_pdst,
input [5:0] io_com_uops_0_ldst,
input io_com_uops_0_ldst_val,
input [1:0] io_com_uops_0_dst_rtype,
input io_rbk_valids_0,
input io_rollback,
input io_debug_rob_empty
);
wire _busytable_io_busy_resps_0_prs1_busy;
wire _busytable_io_busy_resps_0_prs2_busy;
wire _busytable_io_busy_resps_0_prs3_busy;
wire _freelist_io_alloc_pregs_0_valid;
wire [5:0] _freelist_io_alloc_pregs_0_bits;
wire [5:0] _maptable_io_map_resps_0_prs1;
wire [5:0] _maptable_io_map_resps_0_prs2;
wire [5:0] _maptable_io_map_resps_0_prs3;
wire [5:0] _maptable_io_map_resps_0_stale_pdst;
reg r_uop_is_br;
reg r_uop_is_jalr;
reg r_uop_is_sfb;
reg [2:0] r_uop_br_tag;
reg [5:0] r_uop_prs1;
reg [5:0] r_uop_prs2;
reg [5:0] r_uop_prs3;
reg [5:0] r_uop_stale_pdst;
reg [5:0] r_uop_ldst;
reg [5:0] r_uop_lrs1;
reg [5:0] r_uop_lrs2;
reg [5:0] r_uop_lrs3;
reg r_uop_ldst_val;
reg [1:0] r_uop_dst_rtype;
reg [1:0] r_uop_lrs1_rtype;
reg [1:0] r_uop_lrs2_rtype;
reg r_uop_frs3_en;
wire _io_ren_stalls_0_T = r_uop_dst_rtype == 2'h1;
wire freelist_io_reqs_0 = r_uop_ldst_val & _io_ren_stalls_0_T & io_dis_fire_0;
wire ren2_br_tags_0_valid = io_dis_fire_0 & (r_uop_is_br & ~r_uop_is_sfb | r_uop_is_jalr);
wire _rbk_valids_0_T = io_com_uops_0_dst_rtype == 2'h1;
wire rbk_valids_0 = io_com_uops_0_ldst_val & _rbk_valids_0_T & io_rbk_valids_0;
wire _GEN = io_kill | ~io_dis_ready;
always @(posedge clock) begin
if (_GEN) begin
end
else begin
r_uop_is_br <= io_dec_uops_0_is_br;
r_uop_is_jalr <= io_dec_uops_0_is_jalr;
r_uop_is_sfb <= io_dec_uops_0_is_sfb;
r_uop_br_tag <= io_dec_uops_0_br_tag;
end
if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_lrs1 : io_dec_uops_0_lrs1))
r_uop_prs1 <= _freelist_io_alloc_pregs_0_bits;
else if (_GEN) begin
end
else
r_uop_prs1 <= _maptable_io_map_resps_0_prs1;
if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_lrs2 : io_dec_uops_0_lrs2))
r_uop_prs2 <= _freelist_io_alloc_pregs_0_bits;
else if (_GEN) begin
end
else
r_uop_prs2 <= _maptable_io_map_resps_0_prs2;
if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_lrs3 : io_dec_uops_0_lrs3))
r_uop_prs3 <= _freelist_io_alloc_pregs_0_bits;
else if (_GEN) begin
end
else
r_uop_prs3 <= _maptable_io_map_resps_0_prs3;
if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_ldst : io_dec_uops_0_ldst))
r_uop_stale_pdst <= _freelist_io_alloc_pregs_0_bits;
else if (_GEN) begin
end
else
r_uop_stale_pdst <= _maptable_io_map_resps_0_stale_pdst;
if (_GEN) begin
end
else begin
r_uop_ldst <= io_dec_uops_0_ldst;
r_uop_lrs1 <= io_dec_uops_0_lrs1;
r_uop_lrs2 <= io_dec_uops_0_lrs2;
r_uop_lrs3 <= io_dec_uops_0_lrs3;
r_uop_ldst_val <= io_dec_uops_0_ldst_val;
r_uop_dst_rtype <= io_dec_uops_0_dst_rtype;
r_uop_lrs1_rtype <= io_dec_uops_0_lrs1_rtype;
r_uop_lrs2_rtype <= io_dec_uops_0_lrs2_rtype;
r_uop_frs3_en <= io_dec_uops_0_frs3_en;
end
end
RenameMapTable_1 maptable (
.clock (clock),
.reset (reset),
.io_map_reqs_0_lrs1 (io_dec_uops_0_lrs1),
.io_map_reqs_0_lrs2 (io_dec_uops_0_lrs2),
.io_map_reqs_0_lrs3 (io_dec_uops_0_lrs3),
.io_map_reqs_0_ldst (io_dec_uops_0_ldst),
.io_map_resps_0_prs1 (_maptable_io_map_resps_0_prs1),
.io_map_resps_0_prs2 (_maptable_io_map_resps_0_prs2),
.io_map_resps_0_prs3 (_maptable_io_map_resps_0_prs3),
.io_map_resps_0_stale_pdst (_maptable_io_map_resps_0_stale_pdst),
.io_remap_reqs_0_ldst (io_rollback ? io_com_uops_0_ldst : r_uop_ldst),
.io_remap_reqs_0_pdst (io_rollback ? io_com_uops_0_stale_pdst : _freelist_io_alloc_pregs_0_bits),
.io_remap_reqs_0_valid (freelist_io_reqs_0 | rbk_valids_0),
.io_ren_br_tags_0_valid (ren2_br_tags_0_valid),
.io_ren_br_tags_0_bits (r_uop_br_tag),
.io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag),
.io_brupdate_b2_mispredict (io_brupdate_b2_mispredict),
.io_rollback (io_rollback)
);
RenameFreeList_1 freelist (
.clock (clock),
.reset (reset),
.io_reqs_0 (freelist_io_reqs_0),
.io_alloc_pregs_0_valid (_freelist_io_alloc_pregs_0_valid),
.io_alloc_pregs_0_bits (_freelist_io_alloc_pregs_0_bits),
.io_dealloc_pregs_0_valid (io_com_uops_0_ldst_val & _rbk_valids_0_T & io_com_valids_0 | rbk_valids_0),
.io_dealloc_pregs_0_bits (io_rollback ? io_com_uops_0_pdst : io_com_uops_0_stale_pdst),
.io_ren_br_tags_0_valid (ren2_br_tags_0_valid),
.io_ren_br_tags_0_bits (r_uop_br_tag),
.io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag),
.io_brupdate_b2_mispredict (io_brupdate_b2_mispredict),
.io_debug_pipeline_empty (io_debug_rob_empty)
);
RenameBusyTable_1 busytable (
.clock (clock),
.reset (reset),
.io_ren_uops_0_pdst (_freelist_io_alloc_pregs_0_bits),
.io_ren_uops_0_prs1 (r_uop_prs1),
.io_ren_uops_0_prs2 (r_uop_prs2),
.io_ren_uops_0_prs3 (r_uop_prs3),
.io_busy_resps_0_prs1_busy (_busytable_io_busy_resps_0_prs1_busy),
.io_busy_resps_0_prs2_busy (_busytable_io_busy_resps_0_prs2_busy),
.io_busy_resps_0_prs3_busy (_busytable_io_busy_resps_0_prs3_busy),
.io_rebusy_reqs_0 (freelist_io_reqs_0),
.io_wb_pdsts_0 (io_wakeups_0_bits_uop_pdst),
.io_wb_pdsts_1 (io_wakeups_1_bits_uop_pdst),
.io_wb_valids_0 (io_wakeups_0_valid),
.io_wb_valids_1 (io_wakeups_1_valid)
);
assign io_ren_stalls_0 = _io_ren_stalls_0_T & ~_freelist_io_alloc_pregs_0_valid;
assign io_ren2_uops_0_pdst = _freelist_io_alloc_pregs_0_bits;
assign io_ren2_uops_0_prs1 = r_uop_prs1;
assign io_ren2_uops_0_prs2 = r_uop_prs2;
assign io_ren2_uops_0_prs3 = r_uop_prs3;
assign io_ren2_uops_0_prs1_busy = r_uop_lrs1_rtype == 2'h1 & _busytable_io_busy_resps_0_prs1_busy;
assign io_ren2_uops_0_prs2_busy = r_uop_lrs2_rtype == 2'h1 & _busytable_io_busy_resps_0_prs2_busy;
assign io_ren2_uops_0_prs3_busy = r_uop_frs3_en & _busytable_io_busy_resps_0_prs3_busy;
assign io_ren2_uops_0_stale_pdst = r_uop_stale_pdst;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLBFromBeat_SerialRAM_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(posedge clock) begin
if (reset)
is_const <= 1'h1;
else
is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;
end
assign io_beat_ready = io_beat_ready_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module cc_banks_7(
input [13:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
} | module BranchKillableQueue_3(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [6:0] io_enq_bits_uop_uopc,
input [31:0] io_enq_bits_uop_inst,
input [31:0] io_enq_bits_uop_debug_inst,
input io_enq_bits_uop_is_rvc,
input [39:0] io_enq_bits_uop_debug_pc,
input [2:0] io_enq_bits_uop_iq_type,
input [9:0] io_enq_bits_uop_fu_code,
input [3:0] io_enq_bits_uop_ctrl_br_type,
input [1:0] io_enq_bits_uop_ctrl_op1_sel,
input [2:0] io_enq_bits_uop_ctrl_op2_sel,
input [2:0] io_enq_bits_uop_ctrl_imm_sel,
input [4:0] io_enq_bits_uop_ctrl_op_fcn,
input io_enq_bits_uop_ctrl_fcn_dw,
input [2:0] io_enq_bits_uop_ctrl_csr_cmd,
input io_enq_bits_uop_ctrl_is_load,
input io_enq_bits_uop_ctrl_is_sta,
input io_enq_bits_uop_ctrl_is_std,
input [1:0] io_enq_bits_uop_iw_state,
input io_enq_bits_uop_iw_p1_poisoned,
input io_enq_bits_uop_iw_p2_poisoned,
input io_enq_bits_uop_is_br,
input io_enq_bits_uop_is_jalr,
input io_enq_bits_uop_is_jal,
input io_enq_bits_uop_is_sfb,
input [7:0] io_enq_bits_uop_br_mask,
input [2:0] io_enq_bits_uop_br_tag,
input [3:0] io_enq_bits_uop_ftq_idx,
input io_enq_bits_uop_edge_inst,
input [5:0] io_enq_bits_uop_pc_lob,
input io_enq_bits_uop_taken,
input [19:0] io_enq_bits_uop_imm_packed,
input [11:0] io_enq_bits_uop_csr_addr,
input [4:0] io_enq_bits_uop_rob_idx,
input [2:0] io_enq_bits_uop_ldq_idx,
input [2:0] io_enq_bits_uop_stq_idx,
input [1:0] io_enq_bits_uop_rxq_idx,
input [5:0] io_enq_bits_uop_pdst,
input [5:0] io_enq_bits_uop_prs1,
input [5:0] io_enq_bits_uop_prs2,
input [5:0] io_enq_bits_uop_prs3,
input [3:0] io_enq_bits_uop_ppred,
input io_enq_bits_uop_prs1_busy,
input io_enq_bits_uop_prs2_busy,
input io_enq_bits_uop_prs3_busy,
input io_enq_bits_uop_ppred_busy,
input [5:0] io_enq_bits_uop_stale_pdst,
input io_enq_bits_uop_exception,
input [63:0] io_enq_bits_uop_exc_cause,
input io_enq_bits_uop_bypassable,
input [4:0] io_enq_bits_uop_mem_cmd,
input [1:0] io_enq_bits_uop_mem_size,
input io_enq_bits_uop_mem_signed,
input io_enq_bits_uop_is_fence,
input io_enq_bits_uop_is_fencei,
input io_enq_bits_uop_is_amo,
input io_enq_bits_uop_uses_ldq,
input io_enq_bits_uop_uses_stq,
input io_enq_bits_uop_is_sys_pc2epc,
input io_enq_bits_uop_is_unique,
input io_enq_bits_uop_flush_on_commit,
input io_enq_bits_uop_ldst_is_rs1,
input [5:0] io_enq_bits_uop_ldst,
input [5:0] io_enq_bits_uop_lrs1,
input [5:0] io_enq_bits_uop_lrs2,
input [5:0] io_enq_bits_uop_lrs3,
input io_enq_bits_uop_ldst_val,
input [1:0] io_enq_bits_uop_dst_rtype,
input [1:0] io_enq_bits_uop_lrs1_rtype,
input [1:0] io_enq_bits_uop_lrs2_rtype,
input io_enq_bits_uop_frs3_en,
input io_enq_bits_uop_fp_val,
input io_enq_bits_uop_fp_single,
input io_enq_bits_uop_xcpt_pf_if,
input io_enq_bits_uop_xcpt_ae_if,
input io_enq_bits_uop_xcpt_ma_if,
input io_enq_bits_uop_bp_debug_if,
input io_enq_bits_uop_bp_xcpt_if,
input [1:0] io_enq_bits_uop_debug_fsrc,
input [1:0] io_enq_bits_uop_debug_tsrc,
input [64:0] io_enq_bits_data,
input io_enq_bits_fflags_valid,
input [6:0] io_enq_bits_fflags_bits_uop_uopc,
input [31:0] io_enq_bits_fflags_bits_uop_inst,
input [31:0] io_enq_bits_fflags_bits_uop_debug_inst,
input io_enq_bits_fflags_bits_uop_is_rvc,
input [39:0] io_enq_bits_fflags_bits_uop_debug_pc,
input [2:0] io_enq_bits_fflags_bits_uop_iq_type,
input [9:0] io_enq_bits_fflags_bits_uop_fu_code,
input [3:0] io_enq_bits_fflags_bits_uop_ctrl_br_type,
input [1:0] io_enq_bits_fflags_bits_uop_ctrl_op1_sel,
input [2:0] io_enq_bits_fflags_bits_uop_ctrl_op2_sel,
input [2:0] io_enq_bits_fflags_bits_uop_ctrl_imm_sel,
input [4:0] io_enq_bits_fflags_bits_uop_ctrl_op_fcn,
input io_enq_bits_fflags_bits_uop_ctrl_fcn_dw,
input [2:0] io_enq_bits_fflags_bits_uop_ctrl_csr_cmd,
input io_enq_bits_fflags_bits_uop_ctrl_is_load,
input io_enq_bits_fflags_bits_uop_ctrl_is_sta,
input io_enq_bits_fflags_bits_uop_ctrl_is_std,
input [1:0] io_enq_bits_fflags_bits_uop_iw_state,
input io_enq_bits_fflags_bits_uop_iw_p1_poisoned,
input io_enq_bits_fflags_bits_uop_iw_p2_poisoned,
input io_enq_bits_fflags_bits_uop_is_br,
input io_enq_bits_fflags_bits_uop_is_jalr,
input io_enq_bits_fflags_bits_uop_is_jal,
input io_enq_bits_fflags_bits_uop_is_sfb,
input [7:0] io_enq_bits_fflags_bits_uop_br_mask,
input [2:0] io_enq_bits_fflags_bits_uop_br_tag,
input [3:0] io_enq_bits_fflags_bits_uop_ftq_idx,
input io_enq_bits_fflags_bits_uop_edge_inst,
input [5:0] io_enq_bits_fflags_bits_uop_pc_lob,
input io_enq_bits_fflags_bits_uop_taken,
input [19:0] io_enq_bits_fflags_bits_uop_imm_packed,
input [11:0] io_enq_bits_fflags_bits_uop_csr_addr,
input [4:0] io_enq_bits_fflags_bits_uop_rob_idx,
input [2:0] io_enq_bits_fflags_bits_uop_ldq_idx,
input [2:0] io_enq_bits_fflags_bits_uop_stq_idx,
input [1:0] io_enq_bits_fflags_bits_uop_rxq_idx,
input [5:0] io_enq_bits_fflags_bits_uop_pdst,
input [5:0] io_enq_bits_fflags_bits_uop_prs1,
input [5:0] io_enq_bits_fflags_bits_uop_prs2,
input [5:0] io_enq_bits_fflags_bits_uop_prs3,
input [3:0] io_enq_bits_fflags_bits_uop_ppred,
input io_enq_bits_fflags_bits_uop_prs1_busy,
input io_enq_bits_fflags_bits_uop_prs2_busy,
input io_enq_bits_fflags_bits_uop_prs3_busy,
input io_enq_bits_fflags_bits_uop_ppred_busy,
input [5:0] io_enq_bits_fflags_bits_uop_stale_pdst,
input io_enq_bits_fflags_bits_uop_exception,
input [63:0] io_enq_bits_fflags_bits_uop_exc_cause,
input io_enq_bits_fflags_bits_uop_bypassable,
input [4:0] io_enq_bits_fflags_bits_uop_mem_cmd,
input [1:0] io_enq_bits_fflags_bits_uop_mem_size,
input io_enq_bits_fflags_bits_uop_mem_signed,
input io_enq_bits_fflags_bits_uop_is_fence,
input io_enq_bits_fflags_bits_uop_is_fencei,
input io_enq_bits_fflags_bits_uop_is_amo,
input io_enq_bits_fflags_bits_uop_uses_ldq,
input io_enq_bits_fflags_bits_uop_uses_stq,
input io_enq_bits_fflags_bits_uop_is_sys_pc2epc,
input io_enq_bits_fflags_bits_uop_is_unique,
input io_enq_bits_fflags_bits_uop_flush_on_commit,
input io_enq_bits_fflags_bits_uop_ldst_is_rs1,
input [5:0] io_enq_bits_fflags_bits_uop_ldst,
input [5:0] io_enq_bits_fflags_bits_uop_lrs1,
input [5:0] io_enq_bits_fflags_bits_uop_lrs2,
input [5:0] io_enq_bits_fflags_bits_uop_lrs3,
input io_enq_bits_fflags_bits_uop_ldst_val,
input [1:0] io_enq_bits_fflags_bits_uop_dst_rtype,
input [1:0] io_enq_bits_fflags_bits_uop_lrs1_rtype,
input [1:0] io_enq_bits_fflags_bits_uop_lrs2_rtype,
input io_enq_bits_fflags_bits_uop_frs3_en,
input io_enq_bits_fflags_bits_uop_fp_val,
input io_enq_bits_fflags_bits_uop_fp_single,
input io_enq_bits_fflags_bits_uop_xcpt_pf_if,
input io_enq_bits_fflags_bits_uop_xcpt_ae_if,
input io_enq_bits_fflags_bits_uop_xcpt_ma_if,
input io_enq_bits_fflags_bits_uop_bp_debug_if,
input io_enq_bits_fflags_bits_uop_bp_xcpt_if,
input [1:0] io_enq_bits_fflags_bits_uop_debug_fsrc,
input [1:0] io_enq_bits_fflags_bits_uop_debug_tsrc,
input [4:0] io_enq_bits_fflags_bits_flags,
input io_deq_ready,
output io_deq_valid,
output [6:0] io_deq_bits_uop_uopc,
output [7:0] io_deq_bits_uop_br_mask,
output [4:0] io_deq_bits_uop_rob_idx,
output [2:0] io_deq_bits_uop_stq_idx,
output [5:0] io_deq_bits_uop_pdst,
output io_deq_bits_uop_is_amo,
output io_deq_bits_uop_uses_stq,
output [1:0] io_deq_bits_uop_dst_rtype,
output io_deq_bits_uop_fp_val,
output [64:0] io_deq_bits_data,
output io_deq_bits_predicated,
output io_deq_bits_fflags_valid,
output [4:0] io_deq_bits_fflags_bits_uop_rob_idx,
output [4:0] io_deq_bits_fflags_bits_flags,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask,
input io_flush,
output io_empty
);
wire [76:0] _ram_ext_R0_data;
reg valids_0;
reg valids_1;
reg valids_2;
reg valids_3;
reg valids_4;
reg [6:0] uops_0_uopc;
reg [7:0] uops_0_br_mask;
reg [4:0] uops_0_rob_idx;
reg [2:0] uops_0_stq_idx;
reg [5:0] uops_0_pdst;
reg uops_0_is_amo;
reg uops_0_uses_stq;
reg [1:0] uops_0_dst_rtype;
reg uops_0_fp_val;
reg [6:0] uops_1_uopc;
reg [7:0] uops_1_br_mask;
reg [4:0] uops_1_rob_idx;
reg [2:0] uops_1_stq_idx;
reg [5:0] uops_1_pdst;
reg uops_1_is_amo;
reg uops_1_uses_stq;
reg [1:0] uops_1_dst_rtype;
reg uops_1_fp_val;
reg [6:0] uops_2_uopc;
reg [7:0] uops_2_br_mask;
reg [4:0] uops_2_rob_idx;
reg [2:0] uops_2_stq_idx;
reg [5:0] uops_2_pdst;
reg uops_2_is_amo;
reg uops_2_uses_stq;
reg [1:0] uops_2_dst_rtype;
reg uops_2_fp_val;
reg [6:0] uops_3_uopc;
reg [7:0] uops_3_br_mask;
reg [4:0] uops_3_rob_idx;
reg [2:0] uops_3_stq_idx;
reg [5:0] uops_3_pdst;
reg uops_3_is_amo;
reg uops_3_uses_stq;
reg [1:0] uops_3_dst_rtype;
reg uops_3_fp_val;
reg [6:0] uops_4_uopc;
reg [7:0] uops_4_br_mask;
reg [4:0] uops_4_rob_idx;
reg [2:0] uops_4_stq_idx;
reg [5:0] uops_4_pdst;
reg uops_4_is_amo;
reg uops_4_uses_stq;
reg [1:0] uops_4_dst_rtype;
reg uops_4_fp_val;
reg [2:0] enq_ptr_value;
reg [2:0] deq_ptr_value;
reg maybe_full;
wire ptr_match = enq_ptr_value == deq_ptr_value;
wire io_empty_0 = ptr_match & ~maybe_full;
wire full = ptr_match & maybe_full;
wire [7:0] _GEN = {{valids_0}, {valids_0}, {valids_0}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}};
wire _GEN_0 = _GEN[deq_ptr_value];
wire [7:0][6:0] _GEN_1 = {{uops_0_uopc}, {uops_0_uopc}, {uops_0_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}};
wire [7:0][7:0] _GEN_2 = {{uops_0_br_mask}, {uops_0_br_mask}, {uops_0_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}};
wire [7:0] out_uop_br_mask = _GEN_2[deq_ptr_value];
wire [7:0][4:0] _GEN_3 = {{uops_0_rob_idx}, {uops_0_rob_idx}, {uops_0_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}};
wire [7:0][2:0] _GEN_4 = {{uops_0_stq_idx}, {uops_0_stq_idx}, {uops_0_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}};
wire [7:0][5:0] _GEN_5 = {{uops_0_pdst}, {uops_0_pdst}, {uops_0_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}};
wire [7:0] _GEN_6 = {{uops_0_is_amo}, {uops_0_is_amo}, {uops_0_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}};
wire [7:0] _GEN_7 = {{uops_0_uses_stq}, {uops_0_uses_stq}, {uops_0_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}};
wire [7:0][1:0] _GEN_8 = {{uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}};
wire [7:0] _GEN_9 = {{uops_0_fp_val}, {uops_0_fp_val}, {uops_0_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}};
wire do_deq = ~io_empty_0 & (io_deq_ready | ~_GEN_0) & ~io_empty_0;
wire do_enq = ~(io_empty_0 & io_deq_ready) & ~full & io_enq_valid;
wire _GEN_10 = enq_ptr_value == 3'h0;
wire _GEN_11 = do_enq & _GEN_10;
wire _GEN_12 = enq_ptr_value == 3'h1;
wire _GEN_13 = do_enq & _GEN_12;
wire _GEN_14 = enq_ptr_value == 3'h2;
wire _GEN_15 = do_enq & _GEN_14;
wire _GEN_16 = enq_ptr_value == 3'h3;
wire _GEN_17 = do_enq & _GEN_16;
wire _GEN_18 = enq_ptr_value == 3'h4;
wire _GEN_19 = do_enq & _GEN_18;
wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;
always @(posedge clock) begin
if (reset) begin
valids_0 <= 1'h0;
valids_1 <= 1'h0;
valids_2 <= 1'h0;
valids_3 <= 1'h0;
valids_4 <= 1'h0;
enq_ptr_value <= 3'h0;
deq_ptr_value <= 3'h0;
maybe_full <= 1'h0;
end
else begin
valids_0 <= ~(do_deq & deq_ptr_value == 3'h0) & (_GEN_11 | valids_0 & (io_brupdate_b1_mispredict_mask & uops_0_br_mask) == 8'h0 & ~io_flush);
valids_1 <= ~(do_deq & deq_ptr_value == 3'h1) & (_GEN_13 | valids_1 & (io_brupdate_b1_mispredict_mask & uops_1_br_mask) == 8'h0 & ~io_flush);
valids_2 <= ~(do_deq & deq_ptr_value == 3'h2) & (_GEN_15 | valids_2 & (io_brupdate_b1_mispredict_mask & uops_2_br_mask) == 8'h0 & ~io_flush);
valids_3 <= ~(do_deq & deq_ptr_value == 3'h3) & (_GEN_17 | valids_3 & (io_brupdate_b1_mispredict_mask & uops_3_br_mask) == 8'h0 & ~io_flush);
valids_4 <= ~(do_deq & deq_ptr_value == 3'h4) & (_GEN_19 | valids_4 & (io_brupdate_b1_mispredict_mask & uops_4_br_mask) == 8'h0 & ~io_flush);
if (do_enq)
enq_ptr_value <= enq_ptr_value == 3'h4 ? 3'h0 : enq_ptr_value + 3'h1;
if (do_deq)
deq_ptr_value <= deq_ptr_value == 3'h4 ? 3'h0 : deq_ptr_value + 3'h1;
if (~(do_enq == do_deq))
maybe_full <= do_enq;
end
if (_GEN_11) begin
uops_0_uopc <= io_enq_bits_uop_uopc;
uops_0_rob_idx <= io_enq_bits_uop_rob_idx;
uops_0_stq_idx <= io_enq_bits_uop_stq_idx;
uops_0_pdst <= io_enq_bits_uop_pdst;
uops_0_is_amo <= io_enq_bits_uop_is_amo;
uops_0_uses_stq <= io_enq_bits_uop_uses_stq;
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_0_fp_val <= io_enq_bits_uop_fp_val;
end
uops_0_br_mask <= do_enq & _GEN_10 ? _uops_br_mask_T_1 : ({8{~valids_0}} | ~io_brupdate_b1_resolve_mask) & uops_0_br_mask;
if (_GEN_13) begin
uops_1_uopc <= io_enq_bits_uop_uopc;
uops_1_rob_idx <= io_enq_bits_uop_rob_idx;
uops_1_stq_idx <= io_enq_bits_uop_stq_idx;
uops_1_pdst <= io_enq_bits_uop_pdst;
uops_1_is_amo <= io_enq_bits_uop_is_amo;
uops_1_uses_stq <= io_enq_bits_uop_uses_stq;
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_1_fp_val <= io_enq_bits_uop_fp_val;
end
uops_1_br_mask <= do_enq & _GEN_12 ? _uops_br_mask_T_1 : ({8{~valids_1}} | ~io_brupdate_b1_resolve_mask) & uops_1_br_mask;
if (_GEN_15) begin
uops_2_uopc <= io_enq_bits_uop_uopc;
uops_2_rob_idx <= io_enq_bits_uop_rob_idx;
uops_2_stq_idx <= io_enq_bits_uop_stq_idx;
uops_2_pdst <= io_enq_bits_uop_pdst;
uops_2_is_amo <= io_enq_bits_uop_is_amo;
uops_2_uses_stq <= io_enq_bits_uop_uses_stq;
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_2_fp_val <= io_enq_bits_uop_fp_val;
end
uops_2_br_mask <= do_enq & _GEN_14 ? _uops_br_mask_T_1 : ({8{~valids_2}} | ~io_brupdate_b1_resolve_mask) & uops_2_br_mask;
if (_GEN_17) begin
uops_3_uopc <= io_enq_bits_uop_uopc;
uops_3_rob_idx <= io_enq_bits_uop_rob_idx;
uops_3_stq_idx <= io_enq_bits_uop_stq_idx;
uops_3_pdst <= io_enq_bits_uop_pdst;
uops_3_is_amo <= io_enq_bits_uop_is_amo;
uops_3_uses_stq <= io_enq_bits_uop_uses_stq;
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_3_fp_val <= io_enq_bits_uop_fp_val;
end
uops_3_br_mask <= do_enq & _GEN_16 ? _uops_br_mask_T_1 : ({8{~valids_3}} | ~io_brupdate_b1_resolve_mask) & uops_3_br_mask;
if (_GEN_19) begin
uops_4_uopc <= io_enq_bits_uop_uopc;
uops_4_rob_idx <= io_enq_bits_uop_rob_idx;
uops_4_stq_idx <= io_enq_bits_uop_stq_idx;
uops_4_pdst <= io_enq_bits_uop_pdst;
uops_4_is_amo <= io_enq_bits_uop_is_amo;
uops_4_uses_stq <= io_enq_bits_uop_uses_stq;
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_4_fp_val <= io_enq_bits_uop_fp_val;
end
uops_4_br_mask <= do_enq & _GEN_18 ? _uops_br_mask_T_1 : ({8{~valids_4}} | ~io_brupdate_b1_resolve_mask) & uops_4_br_mask;
end
ram_5x77 ram_ext (
.R0_addr (deq_ptr_value),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value),
.W0_en (do_enq),
.W0_clk (clock),
.W0_data ({io_enq_bits_fflags_bits_flags, io_enq_bits_fflags_bits_uop_rob_idx, io_enq_bits_fflags_valid, 1'h0, io_enq_bits_data})
);
assign io_enq_ready = ~full;
assign io_deq_valid = io_empty_0 ? io_enq_valid : ~io_empty_0 & _GEN_0 & (io_brupdate_b1_mispredict_mask & out_uop_br_mask) == 8'h0 & ~io_flush;
assign io_deq_bits_uop_uopc = io_empty_0 ? io_enq_bits_uop_uopc : _GEN_1[deq_ptr_value];
assign io_deq_bits_uop_br_mask = io_empty_0 ? io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask : out_uop_br_mask & ~io_brupdate_b1_resolve_mask;
assign io_deq_bits_uop_rob_idx = io_empty_0 ? io_enq_bits_uop_rob_idx : _GEN_3[deq_ptr_value];
assign io_deq_bits_uop_stq_idx = io_empty_0 ? io_enq_bits_uop_stq_idx : _GEN_4[deq_ptr_value];
assign io_deq_bits_uop_pdst = io_empty_0 ? io_enq_bits_uop_pdst : _GEN_5[deq_ptr_value];
assign io_deq_bits_uop_is_amo = io_empty_0 ? io_enq_bits_uop_is_amo : _GEN_6[deq_ptr_value];
assign io_deq_bits_uop_uses_stq = io_empty_0 ? io_enq_bits_uop_uses_stq : _GEN_7[deq_ptr_value];
assign io_deq_bits_uop_dst_rtype = io_empty_0 ? io_enq_bits_uop_dst_rtype : _GEN_8[deq_ptr_value];
assign io_deq_bits_uop_fp_val = io_empty_0 ? io_enq_bits_uop_fp_val : _GEN_9[deq_ptr_value];
assign io_deq_bits_data = io_empty_0 ? io_enq_bits_data : _ram_ext_R0_data[64:0];
assign io_deq_bits_predicated = ~io_empty_0 & _ram_ext_R0_data[65];
assign io_deq_bits_fflags_valid = io_empty_0 ? io_enq_bits_fflags_valid : _ram_ext_R0_data[66];
assign io_deq_bits_fflags_bits_uop_rob_idx = io_empty_0 ? io_enq_bits_fflags_bits_uop_rob_idx : _ram_ext_R0_data[71:67];
assign io_deq_bits_fflags_bits_flags = io_empty_0 ? io_enq_bits_fflags_bits_flags : _ram_ext_R0_data[76:72];
assign io_empty = io_empty_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
} | module AsyncQueue_TestHarness_UNIQUIFIED(
input io_enq_clock,
input io_enq_reset,
output io_enq_ready,
input io_enq_valid,
input [31:0] io_enq_bits_phit,
input io_deq_clock,
input io_deq_reset,
input io_deq_ready,
output io_deq_valid,
output [31:0] io_deq_bits_phit
);
wire [3:0] _sink_io_async_ridx;
wire _sink_io_async_safe_ridx_valid;
wire _sink_io_async_safe_sink_reset_n;
wire [31:0] _source_io_async_mem_0_phit;
wire [31:0] _source_io_async_mem_1_phit;
wire [31:0] _source_io_async_mem_2_phit;
wire [31:0] _source_io_async_mem_3_phit;
wire [31:0] _source_io_async_mem_4_phit;
wire [31:0] _source_io_async_mem_5_phit;
wire [31:0] _source_io_async_mem_6_phit;
wire [31:0] _source_io_async_mem_7_phit;
wire [3:0] _source_io_async_widx;
wire _source_io_async_safe_widx_valid;
wire _source_io_async_safe_source_reset_n;
AsyncQueueSource_Phit source (
.clock (io_enq_clock),
.reset (io_enq_reset),
.io_enq_ready (io_enq_ready),
.io_enq_valid (io_enq_valid),
.io_enq_bits_phit (io_enq_bits_phit),
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
);
AsyncQueueSink_Phit sink (
.clock (io_deq_clock),
.reset (io_deq_reset),
.io_deq_ready (io_deq_ready),
.io_deq_valid (io_deq_valid),
.io_deq_bits_phit (io_deq_bits_phit),
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.FPConstants._
import freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters}
import freechips.rocketchip.tile
import freechips.rocketchip.rocket
import freechips.rocketchip.util.uintToBitPat
import boom.v3.common._
import boom.v3.util.{ImmGenRm, ImmGenTyp}
/**
* FP Decoder for the FPU
*
* TODO get rid of this decoder and move into the Decode stage? Or the RRd stage?
* most of these signals are already created, just need to be translated
* to the Rocket FPU-speak
*/
class UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters
{
val io = IO(new Bundle {
val uopc = Input(Bits(UOPC_SZ.W))
val sigs = Output(new FPUCtrlSigs())
})
// TODO change N,Y,X to BitPat("b1"), BitPat("b0"), and BitPat("b?")
val N = false.B
val Y = true.B
val X = false.B
val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X)
val f_table: Array[(BitPat, List[BitPat])] =
// Note: not all of these signals are used or necessary, but we're
// constrained by the need to fit the rocket.FPU units' ctrl signals.
// swap12 fma
// | swap32 | div
// | | typeTagIn | | sqrt
// ldst | | | typeTagOut | | wflags
// | wen | | | | from_int | | |
// | | ren1 | | | | | to_int | | |
// | | | ren2 | | | | | | fastpipe |
// | | | | ren3 | | | | | | | | | |
// | | | | | | | | | | | | | | | |
Array(
BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N),
BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N),
BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N),
BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y),
BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y),
BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y),
BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N),
BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y),
BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y)
)
val d_table: Array[(BitPat, List[BitPat])] =
Array(
BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),
BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N),
BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),
BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y),
BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y),
BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y),
BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y),
BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y),
BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N),
BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y),
BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y)
)
// val insns = fLen match {
// case 32 => f_table
// case 64 => f_table ++ d_table
// }
val insns = f_table ++ d_table
val decoder = rocket.DecodeLogic(io.uopc, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,
s.div, s.sqrt, s.wflags)
sigs zip decoder map {case(s,d) => s := d}
s.vec := false.B
}
/**
* FP fused multiple add decoder for the FPU
*/
class FMADecoder extends Module
{
val io = IO(new Bundle {
val uopc = Input(UInt(UOPC_SZ.W))
val cmd = Output(UInt(2.W))
})
val default: List[BitPat] = List(BitPat("b??"))
val table: Array[(BitPat, List[BitPat])] =
Array(
BitPat(uopFADD_S) -> List(BitPat("b00")),
BitPat(uopFSUB_S) -> List(BitPat("b01")),
BitPat(uopFMUL_S) -> List(BitPat("b00")),
BitPat(uopFMADD_S) -> List(BitPat("b00")),
BitPat(uopFMSUB_S) -> List(BitPat("b01")),
BitPat(uopFNMADD_S) -> List(BitPat("b11")),
BitPat(uopFNMSUB_S) -> List(BitPat("b10")),
BitPat(uopFADD_D) -> List(BitPat("b00")),
BitPat(uopFSUB_D) -> List(BitPat("b01")),
BitPat(uopFMUL_D) -> List(BitPat("b00")),
BitPat(uopFMADD_D) -> List(BitPat("b00")),
BitPat(uopFMSUB_D) -> List(BitPat("b01")),
BitPat(uopFNMADD_D) -> List(BitPat("b11")),
BitPat(uopFNMSUB_D) -> List(BitPat("b10"))
)
val decoder = rocket.DecodeLogic(io.uopc, default, table)
val (cmd: UInt) :: Nil = decoder
io.cmd := cmd
}
/**
* Bundle representing data to be sent to the FPU
*/
class FpuReq()(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val rs1_data = Bits(65.W)
val rs2_data = Bits(65.W)
val rs3_data = Bits(65.W)
val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W)
}
/**
* FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat)
*/
class FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters
{
val io = IO(new Bundle {
val req = Flipped(new ValidIO(new FpuReq))
val resp = new ValidIO(new ExeUnitResp(65))
})
io.resp.bits := DontCare
// all FP units are padded out to the same latency for easy scheduling of the write port
val fpu_latency = dfmaLatency
val io_req = io.req.bits
val fp_decoder = Module(new UOPCodeFPUDecoder)
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
def fuInput(minT: Option[tile.FType]): tile.FPInput = {
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, minT)
req.in2 := unbox(io_req.rs2_data, tag, minT)
req.in3 := unbox(io_req.rs3_data, tag, minT)
when (fp_ctrl.swap23) { req.in3 := req.in2 }
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below
when (io_req.uop.uopc === uopFMV_X_W) {
req.fmt := 0.U
}
val fma_decoder = Module(new FMADecoder)
fma_decoder.io.uopc := io_req.uop.uopc
req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) | (!fp_ctrl.ren3 && ex_reg_inst(27))
req
}
val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D))
dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D)
dfma.io.in.bits := fuInput(Some(dfma.t))
val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S))
sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S)
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new tile.FPToInt)
fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint || (fp_ctrl.fastpipe && fp_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe),
fpiu.io.out.bits, fpu_latency-1)
val fpiu_result = Wire(new tile.FPResult)
fpiu_result.data := fpiu_out.bits.toint
fpiu_result.exc := fpiu_out.bits.exc
val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket
fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits
// Response (all FP units have been padded out to the same latency)
io.resp.valid := fpiu_out.valid ||
fpmu.io.out.valid ||
sfma.io.out.valid ||
dfma.io.out.valid
val fpu_out_data =
Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B),
Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B),
Mux(fpiu_out.valid, fpiu_result.data,
box(fpmu.io.out.bits.data, fpmu_double))))
val fpu_out_exc =
Mux(dfma.io.out.valid, dfma.io.out.bits.exc,
Mux(sfma.io.out.valid, sfma.io.out.bits.exc,
Mux(fpiu_out.valid, fpiu_result.exc,
fpmu.io.out.bits.exc)))
io.resp.bits.data := fpu_out_data
io.resp.bits.fflags.valid := io.resp.valid
io.resp.bits.fflags.bits.flags := fpu_out_exc
} | module UOPCodeFPUDecoder(
input [6:0] io_uopc,
output io_sigs_ren2,
output io_sigs_ren3,
output io_sigs_swap23,
output [1:0] io_sigs_typeTagIn,
output [1:0] io_sigs_typeTagOut,
output io_sigs_fromint,
output io_sigs_toint,
output io_sigs_fastpipe,
output io_sigs_fma,
output io_sigs_wflags
);
wire [5:0] decoder_decoded_invInputs = ~(io_uopc[5:0]);
wire [4:0] _decoder_decoded_andMatrixOutputs_T_3 = {io_uopc[0], io_uopc[2], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]};
wire [3:0] _decoder_decoded_andMatrixOutputs_T_14 = {decoder_decoded_invInputs[1], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};
wire [4:0] _decoder_decoded_andMatrixOutputs_T_22 = {io_uopc[0], io_uopc[2], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};
wire [3:0] _decoder_decoded_andMatrixOutputs_T_25 = {io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};
wire [5:0] _decoder_decoded_andMatrixOutputs_T_27 = {io_uopc[1], decoder_decoded_invInputs[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};
wire [6:0] _decoder_decoded_andMatrixOutputs_T_28 = {decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};
wire [5:0] _decoder_decoded_andMatrixOutputs_T_31 = {decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};
wire [4:0] _decoder_decoded_andMatrixOutputs_T_32 = {decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};
wire [5:0] _decoder_decoded_andMatrixOutputs_T_33 = {io_uopc[0], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};
wire [5:0] _decoder_decoded_andMatrixOutputs_T_34 = {io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};
assign io_sigs_ren2 = |{&{decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_uopc[3], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_22, &_decoder_decoded_andMatrixOutputs_T_25, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_32};
assign io_sigs_ren3 = |{&{io_uopc[0], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_32};
assign io_sigs_swap23 = |{&{io_uopc[0], io_uopc[1], io_uopc[2], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_27};
assign io_sigs_typeTagIn = {1'h0, |{&_decoder_decoded_andMatrixOutputs_T_3, &{io_uopc[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], decoder_decoded_invInputs[1], io_uopc[3], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], io_uopc[1], decoder_decoded_invInputs[2], io_uopc[3], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], decoder_decoded_invInputs[2], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_33, &_decoder_decoded_andMatrixOutputs_T_34, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}};
assign io_sigs_typeTagOut = {1'h0, |{&{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[6]}, &{io_uopc[0], decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_3, &{io_uopc[0], io_uopc[3], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_33, &_decoder_decoded_andMatrixOutputs_T_34}};
assign io_sigs_fromint = &{decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]};
assign io_sigs_toint = |{&{io_uopc[1], io_uopc[2], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}};
assign io_sigs_fastpipe = |{&{decoder_decoded_invInputs[2], io_uopc[3], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}};
assign io_sigs_fma = |{&{io_uopc[0], io_uopc[1], io_uopc[2], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_25, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_32};
assign io_sigs_wflags = |{&{io_uopc[1], io_uopc[3], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[2], io_uopc[3], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_22, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_32};
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
class DivSqrtRecF64 extends Module
{
val io = IO(new Bundle {
val inReady_div = Output(Bool())
val inReady_sqrt = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(Bits(65.W))
val b = Input(Bits(65.W))
val roundingMode = Input(Bits(3.W))
val detectTininess = Input(UInt(1.W))
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(Bits(65.W))
val exceptionFlags = Output(Bits(5.W))
})
val ds = Module(new DivSqrtRecF64_mulAddZ31(0))
io.inReady_div := ds.io.inReady_div
io.inReady_sqrt := ds.io.inReady_sqrt
ds.io.inValid := io.inValid
ds.io.sqrtOp := io.sqrtOp
ds.io.a := io.a
ds.io.b := io.b
ds.io.roundingMode := io.roundingMode
ds.io.detectTininess := io.detectTininess
io.outValid_div := ds.io.outValid_div
io.outValid_sqrt := ds.io.outValid_sqrt
io.out := ds.io.out
io.exceptionFlags := ds.io.exceptionFlags
val mul = Module(new Mul54)
mul.io.val_s0 := ds.io.usingMulAdd(0)
mul.io.latch_a_s0 := ds.io.latchMulAddA_0
mul.io.a_s0 := ds.io.mulAddA_0
mul.io.latch_b_s0 := ds.io.latchMulAddB_0
mul.io.b_s0 := ds.io.mulAddB_0
mul.io.c_s2 := ds.io.mulAddC_2
ds.io.mulAddResult_3 := mul.io.result_s3
}
class Mul54 extends Module
{
val io = IO(new Bundle {
val val_s0 = Input(Bool())
val latch_a_s0 = Input(Bool())
val a_s0 = Input(UInt(54.W))
val latch_b_s0 = Input(Bool())
val b_s0 = Input(UInt(54.W))
val c_s2 = Input(UInt(105.W))
val result_s3 = Output(UInt(105.W))
})
val val_s1 = Reg(Bool())
val val_s2 = Reg(Bool())
val reg_a_s1 = Reg(UInt(54.W))
val reg_b_s1 = Reg(UInt(54.W))
val reg_a_s2 = Reg(UInt(54.W))
val reg_b_s2 = Reg(UInt(54.W))
val reg_result_s3 = Reg(UInt(105.W))
val_s1 := io.val_s0
val_s2 := val_s1
when (io.val_s0) {
when (io.latch_a_s0) {
reg_a_s1 := io.a_s0
}
when (io.latch_b_s0) {
reg_b_s1 := io.b_s0
}
}
when (val_s1) {
reg_a_s2 := reg_a_s1
reg_b_s2 := reg_b_s1
}
when (val_s2) {
reg_result_s3 := (reg_a_s2 * reg_b_s2)(104,0) + io.c_s2
}
io.result_s3 := reg_result_s3
} | module Mul54(
input clock,
input io_val_s0,
input io_latch_a_s0,
input [53:0] io_a_s0,
input io_latch_b_s0,
input [53:0] io_b_s0,
input [104:0] io_c_s2,
output [104:0] io_result_s3
);
reg val_s1;
reg val_s2;
reg [53:0] reg_a_s1;
reg [53:0] reg_b_s1;
reg [53:0] reg_a_s2;
reg [53:0] reg_b_s2;
reg [104:0] reg_result_s3;
always @(posedge clock) begin
val_s1 <= io_val_s0;
val_s2 <= val_s1;
if (io_val_s0 & io_latch_a_s0)
reg_a_s1 <= io_a_s0;
if (io_val_s0 & io_latch_b_s0)
reg_b_s1 <= io_b_s0;
if (val_s1) begin
reg_a_s2 <= reg_a_s1;
reg_b_s2 <= reg_b_s1;
end
if (val_s2)
reg_result_s3 <= {51'h0, reg_a_s2} * {51'h0, reg_b_s2} + io_c_s2;
end
assign io_result_s3 = reg_result_s3;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
} | module ClockCrossingReg_w15(
input clock,
input [14:0] io_d,
output [14:0] io_q,
input io_en
);
reg [14:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module data_16x65(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [64:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [64:0] W0_data
);
reg [64:0] Memory[0:15];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2018 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Fetch Buffer
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Takes a FetchBundle and converts into a vector of MicroOps.
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.rocket.{MStatus, BP, BreakpointUnit}
import boom.v3.common._
import boom.v3.util.{BoolToChar, MaskUpper}
/**
* Bundle that is made up of converted MicroOps from the Fetch Bundle
* input to the Fetch Buffer. This is handed to the Decode stage.
*/
class FetchBufferResp(implicit p: Parameters) extends BoomBundle
{
val uops = Vec(coreWidth, Valid(new MicroOp()))
}
/**
* Buffer to hold fetched packets and convert them into a vector of MicroOps
* to give the Decode stage
*
* @param num_entries effectively the number of full-sized fetch packets we can hold.
*/
class FetchBuffer(implicit p: Parameters) extends BoomModule
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val numEntries = numFetchBufferEntries
val io = IO(new BoomBundle {
val enq = Flipped(Decoupled(new FetchBundle()))
val deq = new DecoupledIO(new FetchBufferResp())
// Was the pipeline redirected? Clear/reset the fetchbuffer.
val clear = Input(Bool())
})
require (numEntries > fetchWidth)
require (numEntries % coreWidth == 0)
val numRows = numEntries / coreWidth
val ram = Reg(Vec(numEntries, new MicroOp))
ram.suggestName("fb_uop_ram")
val deq_vec = Wire(Vec(numRows, Vec(coreWidth, new MicroOp)))
val head = RegInit(1.U(numRows.W))
val tail = RegInit(1.U(numEntries.W))
val maybe_full = RegInit(false.B)
//-------------------------------------------------------------
// **** Enqueue Uops ****
//-------------------------------------------------------------
// Step 1: Convert FetchPacket into a vector of MicroOps.
// Step 2: Generate one-hot write indices.
// Step 3: Write MicroOps into the RAM.
def rotateLeft(in: UInt, k: Int) = {
val n = in.getWidth
Cat(in(n-k-1,0), in(n-1, n-k))
}
val might_hit_head = (1 until fetchWidth).map(k => VecInit(rotateLeft(tail, k).asBools.zipWithIndex.filter
{case (e,i) => i % coreWidth == 0}.map {case (e,i) => e}).asUInt).map(tail => head & tail).reduce(_|_).orR
val at_head = (VecInit(tail.asBools.zipWithIndex.filter {case (e,i) => i % coreWidth == 0}
.map {case (e,i) => e}).asUInt & head).orR
val do_enq = !(at_head && maybe_full || might_hit_head)
io.enq.ready := do_enq
// Input microops.
val in_mask = Wire(Vec(fetchWidth, Bool()))
val in_uops = Wire(Vec(fetchWidth, new MicroOp()))
// Step 1: Convert FetchPacket into a vector of MicroOps.
for (b <- 0 until nBanks) {
for (w <- 0 until bankWidth) {
val i = (b * bankWidth) + w
val pc = (bankAlign(io.enq.bits.pc) + (i << 1).U)
in_uops(i) := DontCare
in_mask(i) := io.enq.valid && io.enq.bits.mask(i)
in_uops(i).edge_inst := false.B
in_uops(i).debug_pc := pc
in_uops(i).pc_lob := pc
in_uops(i).is_sfb := io.enq.bits.sfbs(i) || io.enq.bits.shadowed_mask(i)
if (w == 0) {
when (io.enq.bits.edge_inst(b)) {
in_uops(i).debug_pc := bankAlign(io.enq.bits.pc) + (b * bankBytes).U - 2.U
in_uops(i).pc_lob := bankAlign(io.enq.bits.pc) + (b * bankBytes).U
in_uops(i).edge_inst := true.B
}
}
in_uops(i).ftq_idx := io.enq.bits.ftq_idx
in_uops(i).inst := io.enq.bits.exp_insts(i)
in_uops(i).debug_inst := io.enq.bits.insts(i)
in_uops(i).is_rvc := io.enq.bits.insts(i)(1,0) =/= 3.U
in_uops(i).taken := io.enq.bits.cfi_idx.bits === i.U && io.enq.bits.cfi_idx.valid
in_uops(i).xcpt_pf_if := io.enq.bits.xcpt_pf_if
in_uops(i).xcpt_ae_if := io.enq.bits.xcpt_ae_if
in_uops(i).bp_debug_if := io.enq.bits.bp_debug_if_oh(i)
in_uops(i).bp_xcpt_if := io.enq.bits.bp_xcpt_if_oh(i)
in_uops(i).debug_fsrc := io.enq.bits.fsrc
}
}
// Step 2. Generate one-hot write indices.
val enq_idxs = Wire(Vec(fetchWidth, UInt(numEntries.W)))
def inc(ptr: UInt) = {
val n = ptr.getWidth
Cat(ptr(n-2,0), ptr(n-1))
}
var enq_idx = tail
for (i <- 0 until fetchWidth) {
enq_idxs(i) := enq_idx
enq_idx = Mux(in_mask(i), inc(enq_idx), enq_idx)
}
// Step 3: Write MicroOps into the RAM.
for (i <- 0 until fetchWidth) {
for (j <- 0 until numEntries) {
when (do_enq && in_mask(i) && enq_idxs(i)(j)) {
ram(j) := in_uops(i)
}
}
}
//-------------------------------------------------------------
// **** Dequeue Uops ****
//-------------------------------------------------------------
val tail_collisions = VecInit((0 until numEntries).map(i =>
head(i/coreWidth) && (!maybe_full || (i % coreWidth != 0).B))).asUInt & tail
val slot_will_hit_tail = (0 until numRows).map(i => tail_collisions((i+1)*coreWidth-1, i*coreWidth)).reduce(_|_)
val will_hit_tail = slot_will_hit_tail.orR
val do_deq = io.deq.ready && !will_hit_tail
val deq_valids = (~MaskUpper(slot_will_hit_tail)).asBools
// Generate vec for dequeue read port.
for (i <- 0 until numEntries) {
deq_vec(i/coreWidth)(i%coreWidth) := ram(i)
}
io.deq.bits.uops zip deq_valids map {case (d,v) => d.valid := v}
io.deq.bits.uops zip Mux1H(head, deq_vec) map {case (d,q) => d.bits := q}
io.deq.valid := deq_valids.reduce(_||_)
//-------------------------------------------------------------
// **** Update State ****
//-------------------------------------------------------------
when (do_enq) {
tail := enq_idx
when (in_mask.reduce(_||_)) {
maybe_full := true.B
}
}
when (do_deq) {
head := inc(head)
maybe_full := false.B
}
when (io.clear) {
head := 1.U
tail := 1.U
maybe_full := false.B
}
// TODO Is this necessary?
when (reset.asBool) {
io.deq.bits.uops map { u => u.valid := false.B }
}
} | module FetchBuffer(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [39:0] io_enq_bits_pc,
input io_enq_bits_edge_inst_0,
input [31:0] io_enq_bits_insts_0,
input [31:0] io_enq_bits_insts_1,
input [31:0] io_enq_bits_insts_2,
input [31:0] io_enq_bits_insts_3,
input [31:0] io_enq_bits_exp_insts_0,
input [31:0] io_enq_bits_exp_insts_1,
input [31:0] io_enq_bits_exp_insts_2,
input [31:0] io_enq_bits_exp_insts_3,
input io_enq_bits_shadowed_mask_0,
input io_enq_bits_shadowed_mask_1,
input io_enq_bits_shadowed_mask_2,
input io_enq_bits_shadowed_mask_3,
input io_enq_bits_cfi_idx_valid,
input [1:0] io_enq_bits_cfi_idx_bits,
input [3:0] io_enq_bits_ftq_idx,
input [3:0] io_enq_bits_mask,
input io_enq_bits_xcpt_pf_if,
input io_enq_bits_xcpt_ae_if,
input io_enq_bits_bp_debug_if_oh_0,
input io_enq_bits_bp_debug_if_oh_1,
input io_enq_bits_bp_debug_if_oh_2,
input io_enq_bits_bp_debug_if_oh_3,
input io_enq_bits_bp_xcpt_if_oh_0,
input io_enq_bits_bp_xcpt_if_oh_1,
input io_enq_bits_bp_xcpt_if_oh_2,
input io_enq_bits_bp_xcpt_if_oh_3,
input [1:0] io_enq_bits_fsrc,
input io_deq_ready,
output io_deq_valid,
output io_deq_bits_uops_0_valid,
output [31:0] io_deq_bits_uops_0_bits_inst,
output [31:0] io_deq_bits_uops_0_bits_debug_inst,
output io_deq_bits_uops_0_bits_is_rvc,
output [39:0] io_deq_bits_uops_0_bits_debug_pc,
output io_deq_bits_uops_0_bits_is_sfb,
output [3:0] io_deq_bits_uops_0_bits_ftq_idx,
output io_deq_bits_uops_0_bits_edge_inst,
output [5:0] io_deq_bits_uops_0_bits_pc_lob,
output io_deq_bits_uops_0_bits_taken,
output io_deq_bits_uops_0_bits_xcpt_pf_if,
output io_deq_bits_uops_0_bits_xcpt_ae_if,
output io_deq_bits_uops_0_bits_bp_debug_if,
output io_deq_bits_uops_0_bits_bp_xcpt_if,
output [1:0] io_deq_bits_uops_0_bits_debug_fsrc,
input io_clear
);
reg [31:0] fb_uop_ram_0_inst;
reg [31:0] fb_uop_ram_0_debug_inst;
reg fb_uop_ram_0_is_rvc;
reg [39:0] fb_uop_ram_0_debug_pc;
reg fb_uop_ram_0_is_sfb;
reg [3:0] fb_uop_ram_0_ftq_idx;
reg fb_uop_ram_0_edge_inst;
reg [5:0] fb_uop_ram_0_pc_lob;
reg fb_uop_ram_0_taken;
reg fb_uop_ram_0_xcpt_pf_if;
reg fb_uop_ram_0_xcpt_ae_if;
reg fb_uop_ram_0_bp_debug_if;
reg fb_uop_ram_0_bp_xcpt_if;
reg [1:0] fb_uop_ram_0_debug_fsrc;
reg [31:0] fb_uop_ram_1_inst;
reg [31:0] fb_uop_ram_1_debug_inst;
reg fb_uop_ram_1_is_rvc;
reg [39:0] fb_uop_ram_1_debug_pc;
reg fb_uop_ram_1_is_sfb;
reg [3:0] fb_uop_ram_1_ftq_idx;
reg fb_uop_ram_1_edge_inst;
reg [5:0] fb_uop_ram_1_pc_lob;
reg fb_uop_ram_1_taken;
reg fb_uop_ram_1_xcpt_pf_if;
reg fb_uop_ram_1_xcpt_ae_if;
reg fb_uop_ram_1_bp_debug_if;
reg fb_uop_ram_1_bp_xcpt_if;
reg [1:0] fb_uop_ram_1_debug_fsrc;
reg [31:0] fb_uop_ram_2_inst;
reg [31:0] fb_uop_ram_2_debug_inst;
reg fb_uop_ram_2_is_rvc;
reg [39:0] fb_uop_ram_2_debug_pc;
reg fb_uop_ram_2_is_sfb;
reg [3:0] fb_uop_ram_2_ftq_idx;
reg fb_uop_ram_2_edge_inst;
reg [5:0] fb_uop_ram_2_pc_lob;
reg fb_uop_ram_2_taken;
reg fb_uop_ram_2_xcpt_pf_if;
reg fb_uop_ram_2_xcpt_ae_if;
reg fb_uop_ram_2_bp_debug_if;
reg fb_uop_ram_2_bp_xcpt_if;
reg [1:0] fb_uop_ram_2_debug_fsrc;
reg [31:0] fb_uop_ram_3_inst;
reg [31:0] fb_uop_ram_3_debug_inst;
reg fb_uop_ram_3_is_rvc;
reg [39:0] fb_uop_ram_3_debug_pc;
reg fb_uop_ram_3_is_sfb;
reg [3:0] fb_uop_ram_3_ftq_idx;
reg fb_uop_ram_3_edge_inst;
reg [5:0] fb_uop_ram_3_pc_lob;
reg fb_uop_ram_3_taken;
reg fb_uop_ram_3_xcpt_pf_if;
reg fb_uop_ram_3_xcpt_ae_if;
reg fb_uop_ram_3_bp_debug_if;
reg fb_uop_ram_3_bp_xcpt_if;
reg [1:0] fb_uop_ram_3_debug_fsrc;
reg [31:0] fb_uop_ram_4_inst;
reg [31:0] fb_uop_ram_4_debug_inst;
reg fb_uop_ram_4_is_rvc;
reg [39:0] fb_uop_ram_4_debug_pc;
reg fb_uop_ram_4_is_sfb;
reg [3:0] fb_uop_ram_4_ftq_idx;
reg fb_uop_ram_4_edge_inst;
reg [5:0] fb_uop_ram_4_pc_lob;
reg fb_uop_ram_4_taken;
reg fb_uop_ram_4_xcpt_pf_if;
reg fb_uop_ram_4_xcpt_ae_if;
reg fb_uop_ram_4_bp_debug_if;
reg fb_uop_ram_4_bp_xcpt_if;
reg [1:0] fb_uop_ram_4_debug_fsrc;
reg [31:0] fb_uop_ram_5_inst;
reg [31:0] fb_uop_ram_5_debug_inst;
reg fb_uop_ram_5_is_rvc;
reg [39:0] fb_uop_ram_5_debug_pc;
reg fb_uop_ram_5_is_sfb;
reg [3:0] fb_uop_ram_5_ftq_idx;
reg fb_uop_ram_5_edge_inst;
reg [5:0] fb_uop_ram_5_pc_lob;
reg fb_uop_ram_5_taken;
reg fb_uop_ram_5_xcpt_pf_if;
reg fb_uop_ram_5_xcpt_ae_if;
reg fb_uop_ram_5_bp_debug_if;
reg fb_uop_ram_5_bp_xcpt_if;
reg [1:0] fb_uop_ram_5_debug_fsrc;
reg [31:0] fb_uop_ram_6_inst;
reg [31:0] fb_uop_ram_6_debug_inst;
reg fb_uop_ram_6_is_rvc;
reg [39:0] fb_uop_ram_6_debug_pc;
reg fb_uop_ram_6_is_sfb;
reg [3:0] fb_uop_ram_6_ftq_idx;
reg fb_uop_ram_6_edge_inst;
reg [5:0] fb_uop_ram_6_pc_lob;
reg fb_uop_ram_6_taken;
reg fb_uop_ram_6_xcpt_pf_if;
reg fb_uop_ram_6_xcpt_ae_if;
reg fb_uop_ram_6_bp_debug_if;
reg fb_uop_ram_6_bp_xcpt_if;
reg [1:0] fb_uop_ram_6_debug_fsrc;
reg [31:0] fb_uop_ram_7_inst;
reg [31:0] fb_uop_ram_7_debug_inst;
reg fb_uop_ram_7_is_rvc;
reg [39:0] fb_uop_ram_7_debug_pc;
reg fb_uop_ram_7_is_sfb;
reg [3:0] fb_uop_ram_7_ftq_idx;
reg fb_uop_ram_7_edge_inst;
reg [5:0] fb_uop_ram_7_pc_lob;
reg fb_uop_ram_7_taken;
reg fb_uop_ram_7_xcpt_pf_if;
reg fb_uop_ram_7_xcpt_ae_if;
reg fb_uop_ram_7_bp_debug_if;
reg fb_uop_ram_7_bp_xcpt_if;
reg [1:0] fb_uop_ram_7_debug_fsrc;
reg [7:0] head;
reg [7:0] tail;
reg maybe_full;
wire do_enq = {(|(tail & head)) & maybe_full, head & {tail[6:0], tail[7]} | head & {tail[5:0], tail[7:6]} | head & {tail[4:0], tail[7:5]}} == 9'h0;
wire will_hit_tail = head[0] & ~maybe_full & tail[0] | head[1] & ~maybe_full & tail[1] | head[2] & ~maybe_full & tail[2] | head[3] & ~maybe_full & tail[3] | head[4] & ~maybe_full & tail[4] | head[5] & ~maybe_full & tail[5] | head[6] & ~maybe_full & tail[6] | head[7] & ~maybe_full & tail[7];
wire do_deq = io_deq_ready & ~will_hit_tail;
wire in_mask_0 = io_enq_valid & io_enq_bits_mask[0];
wire [39:0] _GEN = {io_enq_bits_pc[39:3], 3'h0};
wire [39:0] in_uops_0_debug_pc = io_enq_bits_edge_inst_0 ? _GEN - 40'h2 : {io_enq_bits_pc[39:3], 3'h0};
wire [5:0] in_uops_0_pc_lob = {io_enq_bits_pc[5:3], 3'h0};
wire in_uops_0_is_rvc = io_enq_bits_insts_0[1:0] != 2'h3;
wire in_uops_0_taken = io_enq_bits_cfi_idx_bits == 2'h0 & io_enq_bits_cfi_idx_valid;
wire [39:0] _pc_T_7 = _GEN + 40'h2;
wire in_mask_1 = io_enq_valid & io_enq_bits_mask[1];
wire in_uops_1_is_rvc = io_enq_bits_insts_1[1:0] != 2'h3;
wire in_uops_1_taken = io_enq_bits_cfi_idx_bits == 2'h1 & io_enq_bits_cfi_idx_valid;
wire [39:0] _pc_T_11 = _GEN + 40'h4;
wire in_mask_2 = io_enq_valid & io_enq_bits_mask[2];
wire in_uops_2_is_rvc = io_enq_bits_insts_2[1:0] != 2'h3;
wire in_uops_2_taken = io_enq_bits_cfi_idx_bits == 2'h2 & io_enq_bits_cfi_idx_valid;
wire [39:0] _pc_T_15 = _GEN + 40'h6;
wire in_mask_3 = io_enq_valid & io_enq_bits_mask[3];
wire in_uops_3_is_rvc = io_enq_bits_insts_3[1:0] != 2'h3;
wire in_uops_3_taken = (&io_enq_bits_cfi_idx_bits) & io_enq_bits_cfi_idx_valid;
wire [7:0] _GEN_0 = {tail[6:0], tail[7]};
wire [7:0] enq_idxs_1 = in_mask_0 ? _GEN_0 : tail;
wire [7:0] _GEN_1 = {enq_idxs_1[6:0], enq_idxs_1[7]};
wire [7:0] enq_idxs_2 = in_mask_1 ? _GEN_1 : enq_idxs_1;
wire [7:0] _GEN_2 = {enq_idxs_2[6:0], enq_idxs_2[7]};
wire [7:0] enq_idxs_3 = in_mask_2 ? _GEN_2 : enq_idxs_2;
wire _GEN_3 = do_enq & in_mask_0;
wire _GEN_4 = _GEN_3 & tail[0];
wire _GEN_5 = _GEN_3 & tail[1];
wire _GEN_6 = _GEN_3 & tail[2];
wire _GEN_7 = _GEN_3 & tail[3];
wire _GEN_8 = _GEN_3 & tail[4];
wire _GEN_9 = _GEN_3 & tail[5];
wire _GEN_10 = _GEN_3 & tail[6];
wire _GEN_11 = _GEN_3 & tail[7];
wire _GEN_12 = do_enq & in_mask_1;
wire _GEN_13 = _GEN_12 & enq_idxs_1[0];
wire _GEN_14 = _GEN_12 & enq_idxs_1[1];
wire _GEN_15 = _GEN_12 & enq_idxs_1[2];
wire _GEN_16 = _GEN_12 & enq_idxs_1[3];
wire _GEN_17 = _GEN_12 & enq_idxs_1[4];
wire _GEN_18 = _GEN_12 & enq_idxs_1[5];
wire _GEN_19 = _GEN_12 & enq_idxs_1[6];
wire _GEN_20 = _GEN_12 & enq_idxs_1[7];
wire _GEN_21 = do_enq & in_mask_2;
wire _GEN_22 = _GEN_21 & enq_idxs_2[0];
wire _GEN_23 = _GEN_21 & enq_idxs_2[1];
wire _GEN_24 = _GEN_21 & enq_idxs_2[2];
wire _GEN_25 = _GEN_21 & enq_idxs_2[3];
wire _GEN_26 = _GEN_21 & enq_idxs_2[4];
wire _GEN_27 = _GEN_21 & enq_idxs_2[5];
wire _GEN_28 = _GEN_21 & enq_idxs_2[6];
wire _GEN_29 = _GEN_21 & enq_idxs_2[7];
wire _GEN_30 = do_enq & in_mask_3;
wire _GEN_31 = _GEN_30 & enq_idxs_3[0];
wire _GEN_32 = _GEN_30 & enq_idxs_3[1];
wire _GEN_33 = _GEN_30 & enq_idxs_3[2];
wire _GEN_34 = _GEN_30 & enq_idxs_3[3];
wire _GEN_35 = _GEN_30 & enq_idxs_3[4];
wire _GEN_36 = _GEN_30 & enq_idxs_3[5];
wire _GEN_37 = _GEN_30 & enq_idxs_3[6];
wire _GEN_38 = _GEN_30 & enq_idxs_3[7];
always @(posedge clock) begin
if (_GEN_31) begin
fb_uop_ram_0_inst <= io_enq_bits_exp_insts_3;
fb_uop_ram_0_debug_inst <= io_enq_bits_insts_3;
fb_uop_ram_0_is_rvc <= in_uops_3_is_rvc;
fb_uop_ram_0_debug_pc <= _pc_T_15;
fb_uop_ram_0_is_sfb <= io_enq_bits_shadowed_mask_3;
fb_uop_ram_0_pc_lob <= _pc_T_15[5:0];
fb_uop_ram_0_taken <= in_uops_3_taken;
fb_uop_ram_0_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;
fb_uop_ram_0_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;
end
else if (_GEN_22) begin
fb_uop_ram_0_inst <= io_enq_bits_exp_insts_2;
fb_uop_ram_0_debug_inst <= io_enq_bits_insts_2;
fb_uop_ram_0_is_rvc <= in_uops_2_is_rvc;
fb_uop_ram_0_debug_pc <= _pc_T_11;
fb_uop_ram_0_is_sfb <= io_enq_bits_shadowed_mask_2;
fb_uop_ram_0_pc_lob <= _pc_T_11[5:0];
fb_uop_ram_0_taken <= in_uops_2_taken;
fb_uop_ram_0_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;
fb_uop_ram_0_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;
end
else if (_GEN_13) begin
fb_uop_ram_0_inst <= io_enq_bits_exp_insts_1;
fb_uop_ram_0_debug_inst <= io_enq_bits_insts_1;
fb_uop_ram_0_is_rvc <= in_uops_1_is_rvc;
fb_uop_ram_0_debug_pc <= _pc_T_7;
fb_uop_ram_0_is_sfb <= io_enq_bits_shadowed_mask_1;
fb_uop_ram_0_pc_lob <= _pc_T_7[5:0];
fb_uop_ram_0_taken <= in_uops_1_taken;
fb_uop_ram_0_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;
fb_uop_ram_0_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;
end
else if (_GEN_4) begin
fb_uop_ram_0_inst <= io_enq_bits_exp_insts_0;
fb_uop_ram_0_debug_inst <= io_enq_bits_insts_0;
fb_uop_ram_0_is_rvc <= in_uops_0_is_rvc;
fb_uop_ram_0_debug_pc <= in_uops_0_debug_pc;
fb_uop_ram_0_is_sfb <= io_enq_bits_shadowed_mask_0;
fb_uop_ram_0_pc_lob <= in_uops_0_pc_lob;
fb_uop_ram_0_taken <= in_uops_0_taken;
fb_uop_ram_0_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;
fb_uop_ram_0_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;
end
if (_GEN_31 | _GEN_22 | _GEN_13 | _GEN_4) begin
fb_uop_ram_0_ftq_idx <= io_enq_bits_ftq_idx;
fb_uop_ram_0_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;
fb_uop_ram_0_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;
fb_uop_ram_0_debug_fsrc <= io_enq_bits_fsrc;
end
fb_uop_ram_0_edge_inst <= ~(_GEN_31 | _GEN_22 | _GEN_13) & (_GEN_4 ? io_enq_bits_edge_inst_0 : fb_uop_ram_0_edge_inst);
if (_GEN_32) begin
fb_uop_ram_1_inst <= io_enq_bits_exp_insts_3;
fb_uop_ram_1_debug_inst <= io_enq_bits_insts_3;
fb_uop_ram_1_is_rvc <= in_uops_3_is_rvc;
fb_uop_ram_1_debug_pc <= _pc_T_15;
fb_uop_ram_1_is_sfb <= io_enq_bits_shadowed_mask_3;
fb_uop_ram_1_pc_lob <= _pc_T_15[5:0];
fb_uop_ram_1_taken <= in_uops_3_taken;
fb_uop_ram_1_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;
fb_uop_ram_1_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;
end
else if (_GEN_23) begin
fb_uop_ram_1_inst <= io_enq_bits_exp_insts_2;
fb_uop_ram_1_debug_inst <= io_enq_bits_insts_2;
fb_uop_ram_1_is_rvc <= in_uops_2_is_rvc;
fb_uop_ram_1_debug_pc <= _pc_T_11;
fb_uop_ram_1_is_sfb <= io_enq_bits_shadowed_mask_2;
fb_uop_ram_1_pc_lob <= _pc_T_11[5:0];
fb_uop_ram_1_taken <= in_uops_2_taken;
fb_uop_ram_1_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;
fb_uop_ram_1_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;
end
else if (_GEN_14) begin
fb_uop_ram_1_inst <= io_enq_bits_exp_insts_1;
fb_uop_ram_1_debug_inst <= io_enq_bits_insts_1;
fb_uop_ram_1_is_rvc <= in_uops_1_is_rvc;
fb_uop_ram_1_debug_pc <= _pc_T_7;
fb_uop_ram_1_is_sfb <= io_enq_bits_shadowed_mask_1;
fb_uop_ram_1_pc_lob <= _pc_T_7[5:0];
fb_uop_ram_1_taken <= in_uops_1_taken;
fb_uop_ram_1_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;
fb_uop_ram_1_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;
end
else if (_GEN_5) begin
fb_uop_ram_1_inst <= io_enq_bits_exp_insts_0;
fb_uop_ram_1_debug_inst <= io_enq_bits_insts_0;
fb_uop_ram_1_is_rvc <= in_uops_0_is_rvc;
fb_uop_ram_1_debug_pc <= in_uops_0_debug_pc;
fb_uop_ram_1_is_sfb <= io_enq_bits_shadowed_mask_0;
fb_uop_ram_1_pc_lob <= in_uops_0_pc_lob;
fb_uop_ram_1_taken <= in_uops_0_taken;
fb_uop_ram_1_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;
fb_uop_ram_1_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;
end
if (_GEN_32 | _GEN_23 | _GEN_14 | _GEN_5) begin
fb_uop_ram_1_ftq_idx <= io_enq_bits_ftq_idx;
fb_uop_ram_1_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;
fb_uop_ram_1_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;
fb_uop_ram_1_debug_fsrc <= io_enq_bits_fsrc;
end
fb_uop_ram_1_edge_inst <= ~(_GEN_32 | _GEN_23 | _GEN_14) & (_GEN_5 ? io_enq_bits_edge_inst_0 : fb_uop_ram_1_edge_inst);
if (_GEN_33) begin
fb_uop_ram_2_inst <= io_enq_bits_exp_insts_3;
fb_uop_ram_2_debug_inst <= io_enq_bits_insts_3;
fb_uop_ram_2_is_rvc <= in_uops_3_is_rvc;
fb_uop_ram_2_debug_pc <= _pc_T_15;
fb_uop_ram_2_is_sfb <= io_enq_bits_shadowed_mask_3;
fb_uop_ram_2_pc_lob <= _pc_T_15[5:0];
fb_uop_ram_2_taken <= in_uops_3_taken;
fb_uop_ram_2_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;
fb_uop_ram_2_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;
end
else if (_GEN_24) begin
fb_uop_ram_2_inst <= io_enq_bits_exp_insts_2;
fb_uop_ram_2_debug_inst <= io_enq_bits_insts_2;
fb_uop_ram_2_is_rvc <= in_uops_2_is_rvc;
fb_uop_ram_2_debug_pc <= _pc_T_11;
fb_uop_ram_2_is_sfb <= io_enq_bits_shadowed_mask_2;
fb_uop_ram_2_pc_lob <= _pc_T_11[5:0];
fb_uop_ram_2_taken <= in_uops_2_taken;
fb_uop_ram_2_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;
fb_uop_ram_2_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;
end
else if (_GEN_15) begin
fb_uop_ram_2_inst <= io_enq_bits_exp_insts_1;
fb_uop_ram_2_debug_inst <= io_enq_bits_insts_1;
fb_uop_ram_2_is_rvc <= in_uops_1_is_rvc;
fb_uop_ram_2_debug_pc <= _pc_T_7;
fb_uop_ram_2_is_sfb <= io_enq_bits_shadowed_mask_1;
fb_uop_ram_2_pc_lob <= _pc_T_7[5:0];
fb_uop_ram_2_taken <= in_uops_1_taken;
fb_uop_ram_2_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;
fb_uop_ram_2_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;
end
else if (_GEN_6) begin
fb_uop_ram_2_inst <= io_enq_bits_exp_insts_0;
fb_uop_ram_2_debug_inst <= io_enq_bits_insts_0;
fb_uop_ram_2_is_rvc <= in_uops_0_is_rvc;
fb_uop_ram_2_debug_pc <= in_uops_0_debug_pc;
fb_uop_ram_2_is_sfb <= io_enq_bits_shadowed_mask_0;
fb_uop_ram_2_pc_lob <= in_uops_0_pc_lob;
fb_uop_ram_2_taken <= in_uops_0_taken;
fb_uop_ram_2_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;
fb_uop_ram_2_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;
end
if (_GEN_33 | _GEN_24 | _GEN_15 | _GEN_6) begin
fb_uop_ram_2_ftq_idx <= io_enq_bits_ftq_idx;
fb_uop_ram_2_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;
fb_uop_ram_2_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;
fb_uop_ram_2_debug_fsrc <= io_enq_bits_fsrc;
end
fb_uop_ram_2_edge_inst <= ~(_GEN_33 | _GEN_24 | _GEN_15) & (_GEN_6 ? io_enq_bits_edge_inst_0 : fb_uop_ram_2_edge_inst);
if (_GEN_34) begin
fb_uop_ram_3_inst <= io_enq_bits_exp_insts_3;
fb_uop_ram_3_debug_inst <= io_enq_bits_insts_3;
fb_uop_ram_3_is_rvc <= in_uops_3_is_rvc;
fb_uop_ram_3_debug_pc <= _pc_T_15;
fb_uop_ram_3_is_sfb <= io_enq_bits_shadowed_mask_3;
fb_uop_ram_3_pc_lob <= _pc_T_15[5:0];
fb_uop_ram_3_taken <= in_uops_3_taken;
fb_uop_ram_3_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;
fb_uop_ram_3_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;
end
else if (_GEN_25) begin
fb_uop_ram_3_inst <= io_enq_bits_exp_insts_2;
fb_uop_ram_3_debug_inst <= io_enq_bits_insts_2;
fb_uop_ram_3_is_rvc <= in_uops_2_is_rvc;
fb_uop_ram_3_debug_pc <= _pc_T_11;
fb_uop_ram_3_is_sfb <= io_enq_bits_shadowed_mask_2;
fb_uop_ram_3_pc_lob <= _pc_T_11[5:0];
fb_uop_ram_3_taken <= in_uops_2_taken;
fb_uop_ram_3_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;
fb_uop_ram_3_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;
end
else if (_GEN_16) begin
fb_uop_ram_3_inst <= io_enq_bits_exp_insts_1;
fb_uop_ram_3_debug_inst <= io_enq_bits_insts_1;
fb_uop_ram_3_is_rvc <= in_uops_1_is_rvc;
fb_uop_ram_3_debug_pc <= _pc_T_7;
fb_uop_ram_3_is_sfb <= io_enq_bits_shadowed_mask_1;
fb_uop_ram_3_pc_lob <= _pc_T_7[5:0];
fb_uop_ram_3_taken <= in_uops_1_taken;
fb_uop_ram_3_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;
fb_uop_ram_3_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;
end
else if (_GEN_7) begin
fb_uop_ram_3_inst <= io_enq_bits_exp_insts_0;
fb_uop_ram_3_debug_inst <= io_enq_bits_insts_0;
fb_uop_ram_3_is_rvc <= in_uops_0_is_rvc;
fb_uop_ram_3_debug_pc <= in_uops_0_debug_pc;
fb_uop_ram_3_is_sfb <= io_enq_bits_shadowed_mask_0;
fb_uop_ram_3_pc_lob <= in_uops_0_pc_lob;
fb_uop_ram_3_taken <= in_uops_0_taken;
fb_uop_ram_3_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;
fb_uop_ram_3_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;
end
if (_GEN_34 | _GEN_25 | _GEN_16 | _GEN_7) begin
fb_uop_ram_3_ftq_idx <= io_enq_bits_ftq_idx;
fb_uop_ram_3_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;
fb_uop_ram_3_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;
fb_uop_ram_3_debug_fsrc <= io_enq_bits_fsrc;
end
fb_uop_ram_3_edge_inst <= ~(_GEN_34 | _GEN_25 | _GEN_16) & (_GEN_7 ? io_enq_bits_edge_inst_0 : fb_uop_ram_3_edge_inst);
if (_GEN_35) begin
fb_uop_ram_4_inst <= io_enq_bits_exp_insts_3;
fb_uop_ram_4_debug_inst <= io_enq_bits_insts_3;
fb_uop_ram_4_is_rvc <= in_uops_3_is_rvc;
fb_uop_ram_4_debug_pc <= _pc_T_15;
fb_uop_ram_4_is_sfb <= io_enq_bits_shadowed_mask_3;
fb_uop_ram_4_pc_lob <= _pc_T_15[5:0];
fb_uop_ram_4_taken <= in_uops_3_taken;
fb_uop_ram_4_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;
fb_uop_ram_4_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;
end
else if (_GEN_26) begin
fb_uop_ram_4_inst <= io_enq_bits_exp_insts_2;
fb_uop_ram_4_debug_inst <= io_enq_bits_insts_2;
fb_uop_ram_4_is_rvc <= in_uops_2_is_rvc;
fb_uop_ram_4_debug_pc <= _pc_T_11;
fb_uop_ram_4_is_sfb <= io_enq_bits_shadowed_mask_2;
fb_uop_ram_4_pc_lob <= _pc_T_11[5:0];
fb_uop_ram_4_taken <= in_uops_2_taken;
fb_uop_ram_4_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;
fb_uop_ram_4_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;
end
else if (_GEN_17) begin
fb_uop_ram_4_inst <= io_enq_bits_exp_insts_1;
fb_uop_ram_4_debug_inst <= io_enq_bits_insts_1;
fb_uop_ram_4_is_rvc <= in_uops_1_is_rvc;
fb_uop_ram_4_debug_pc <= _pc_T_7;
fb_uop_ram_4_is_sfb <= io_enq_bits_shadowed_mask_1;
fb_uop_ram_4_pc_lob <= _pc_T_7[5:0];
fb_uop_ram_4_taken <= in_uops_1_taken;
fb_uop_ram_4_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;
fb_uop_ram_4_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;
end
else if (_GEN_8) begin
fb_uop_ram_4_inst <= io_enq_bits_exp_insts_0;
fb_uop_ram_4_debug_inst <= io_enq_bits_insts_0;
fb_uop_ram_4_is_rvc <= in_uops_0_is_rvc;
fb_uop_ram_4_debug_pc <= in_uops_0_debug_pc;
fb_uop_ram_4_is_sfb <= io_enq_bits_shadowed_mask_0;
fb_uop_ram_4_pc_lob <= in_uops_0_pc_lob;
fb_uop_ram_4_taken <= in_uops_0_taken;
fb_uop_ram_4_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;
fb_uop_ram_4_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;
end
if (_GEN_35 | _GEN_26 | _GEN_17 | _GEN_8) begin
fb_uop_ram_4_ftq_idx <= io_enq_bits_ftq_idx;
fb_uop_ram_4_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;
fb_uop_ram_4_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;
fb_uop_ram_4_debug_fsrc <= io_enq_bits_fsrc;
end
fb_uop_ram_4_edge_inst <= ~(_GEN_35 | _GEN_26 | _GEN_17) & (_GEN_8 ? io_enq_bits_edge_inst_0 : fb_uop_ram_4_edge_inst);
if (_GEN_36) begin
fb_uop_ram_5_inst <= io_enq_bits_exp_insts_3;
fb_uop_ram_5_debug_inst <= io_enq_bits_insts_3;
fb_uop_ram_5_is_rvc <= in_uops_3_is_rvc;
fb_uop_ram_5_debug_pc <= _pc_T_15;
fb_uop_ram_5_is_sfb <= io_enq_bits_shadowed_mask_3;
fb_uop_ram_5_pc_lob <= _pc_T_15[5:0];
fb_uop_ram_5_taken <= in_uops_3_taken;
fb_uop_ram_5_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;
fb_uop_ram_5_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;
end
else if (_GEN_27) begin
fb_uop_ram_5_inst <= io_enq_bits_exp_insts_2;
fb_uop_ram_5_debug_inst <= io_enq_bits_insts_2;
fb_uop_ram_5_is_rvc <= in_uops_2_is_rvc;
fb_uop_ram_5_debug_pc <= _pc_T_11;
fb_uop_ram_5_is_sfb <= io_enq_bits_shadowed_mask_2;
fb_uop_ram_5_pc_lob <= _pc_T_11[5:0];
fb_uop_ram_5_taken <= in_uops_2_taken;
fb_uop_ram_5_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;
fb_uop_ram_5_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;
end
else if (_GEN_18) begin
fb_uop_ram_5_inst <= io_enq_bits_exp_insts_1;
fb_uop_ram_5_debug_inst <= io_enq_bits_insts_1;
fb_uop_ram_5_is_rvc <= in_uops_1_is_rvc;
fb_uop_ram_5_debug_pc <= _pc_T_7;
fb_uop_ram_5_is_sfb <= io_enq_bits_shadowed_mask_1;
fb_uop_ram_5_pc_lob <= _pc_T_7[5:0];
fb_uop_ram_5_taken <= in_uops_1_taken;
fb_uop_ram_5_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;
fb_uop_ram_5_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;
end
else if (_GEN_9) begin
fb_uop_ram_5_inst <= io_enq_bits_exp_insts_0;
fb_uop_ram_5_debug_inst <= io_enq_bits_insts_0;
fb_uop_ram_5_is_rvc <= in_uops_0_is_rvc;
fb_uop_ram_5_debug_pc <= in_uops_0_debug_pc;
fb_uop_ram_5_is_sfb <= io_enq_bits_shadowed_mask_0;
fb_uop_ram_5_pc_lob <= in_uops_0_pc_lob;
fb_uop_ram_5_taken <= in_uops_0_taken;
fb_uop_ram_5_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;
fb_uop_ram_5_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;
end
if (_GEN_36 | _GEN_27 | _GEN_18 | _GEN_9) begin
fb_uop_ram_5_ftq_idx <= io_enq_bits_ftq_idx;
fb_uop_ram_5_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;
fb_uop_ram_5_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;
fb_uop_ram_5_debug_fsrc <= io_enq_bits_fsrc;
end
fb_uop_ram_5_edge_inst <= ~(_GEN_36 | _GEN_27 | _GEN_18) & (_GEN_9 ? io_enq_bits_edge_inst_0 : fb_uop_ram_5_edge_inst);
if (_GEN_37) begin
fb_uop_ram_6_inst <= io_enq_bits_exp_insts_3;
fb_uop_ram_6_debug_inst <= io_enq_bits_insts_3;
fb_uop_ram_6_is_rvc <= in_uops_3_is_rvc;
fb_uop_ram_6_debug_pc <= _pc_T_15;
fb_uop_ram_6_is_sfb <= io_enq_bits_shadowed_mask_3;
fb_uop_ram_6_pc_lob <= _pc_T_15[5:0];
fb_uop_ram_6_taken <= in_uops_3_taken;
fb_uop_ram_6_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;
fb_uop_ram_6_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;
end
else if (_GEN_28) begin
fb_uop_ram_6_inst <= io_enq_bits_exp_insts_2;
fb_uop_ram_6_debug_inst <= io_enq_bits_insts_2;
fb_uop_ram_6_is_rvc <= in_uops_2_is_rvc;
fb_uop_ram_6_debug_pc <= _pc_T_11;
fb_uop_ram_6_is_sfb <= io_enq_bits_shadowed_mask_2;
fb_uop_ram_6_pc_lob <= _pc_T_11[5:0];
fb_uop_ram_6_taken <= in_uops_2_taken;
fb_uop_ram_6_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;
fb_uop_ram_6_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;
end
else if (_GEN_19) begin
fb_uop_ram_6_inst <= io_enq_bits_exp_insts_1;
fb_uop_ram_6_debug_inst <= io_enq_bits_insts_1;
fb_uop_ram_6_is_rvc <= in_uops_1_is_rvc;
fb_uop_ram_6_debug_pc <= _pc_T_7;
fb_uop_ram_6_is_sfb <= io_enq_bits_shadowed_mask_1;
fb_uop_ram_6_pc_lob <= _pc_T_7[5:0];
fb_uop_ram_6_taken <= in_uops_1_taken;
fb_uop_ram_6_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;
fb_uop_ram_6_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;
end
else if (_GEN_10) begin
fb_uop_ram_6_inst <= io_enq_bits_exp_insts_0;
fb_uop_ram_6_debug_inst <= io_enq_bits_insts_0;
fb_uop_ram_6_is_rvc <= in_uops_0_is_rvc;
fb_uop_ram_6_debug_pc <= in_uops_0_debug_pc;
fb_uop_ram_6_is_sfb <= io_enq_bits_shadowed_mask_0;
fb_uop_ram_6_pc_lob <= in_uops_0_pc_lob;
fb_uop_ram_6_taken <= in_uops_0_taken;
fb_uop_ram_6_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;
fb_uop_ram_6_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;
end
if (_GEN_37 | _GEN_28 | _GEN_19 | _GEN_10) begin
fb_uop_ram_6_ftq_idx <= io_enq_bits_ftq_idx;
fb_uop_ram_6_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;
fb_uop_ram_6_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;
fb_uop_ram_6_debug_fsrc <= io_enq_bits_fsrc;
end
fb_uop_ram_6_edge_inst <= ~(_GEN_37 | _GEN_28 | _GEN_19) & (_GEN_10 ? io_enq_bits_edge_inst_0 : fb_uop_ram_6_edge_inst);
if (_GEN_38) begin
fb_uop_ram_7_inst <= io_enq_bits_exp_insts_3;
fb_uop_ram_7_debug_inst <= io_enq_bits_insts_3;
fb_uop_ram_7_is_rvc <= in_uops_3_is_rvc;
fb_uop_ram_7_debug_pc <= _pc_T_15;
fb_uop_ram_7_is_sfb <= io_enq_bits_shadowed_mask_3;
fb_uop_ram_7_pc_lob <= _pc_T_15[5:0];
fb_uop_ram_7_taken <= in_uops_3_taken;
fb_uop_ram_7_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;
fb_uop_ram_7_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;
end
else if (_GEN_29) begin
fb_uop_ram_7_inst <= io_enq_bits_exp_insts_2;
fb_uop_ram_7_debug_inst <= io_enq_bits_insts_2;
fb_uop_ram_7_is_rvc <= in_uops_2_is_rvc;
fb_uop_ram_7_debug_pc <= _pc_T_11;
fb_uop_ram_7_is_sfb <= io_enq_bits_shadowed_mask_2;
fb_uop_ram_7_pc_lob <= _pc_T_11[5:0];
fb_uop_ram_7_taken <= in_uops_2_taken;
fb_uop_ram_7_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;
fb_uop_ram_7_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;
end
else if (_GEN_20) begin
fb_uop_ram_7_inst <= io_enq_bits_exp_insts_1;
fb_uop_ram_7_debug_inst <= io_enq_bits_insts_1;
fb_uop_ram_7_is_rvc <= in_uops_1_is_rvc;
fb_uop_ram_7_debug_pc <= _pc_T_7;
fb_uop_ram_7_is_sfb <= io_enq_bits_shadowed_mask_1;
fb_uop_ram_7_pc_lob <= _pc_T_7[5:0];
fb_uop_ram_7_taken <= in_uops_1_taken;
fb_uop_ram_7_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;
fb_uop_ram_7_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;
end
else if (_GEN_11) begin
fb_uop_ram_7_inst <= io_enq_bits_exp_insts_0;
fb_uop_ram_7_debug_inst <= io_enq_bits_insts_0;
fb_uop_ram_7_is_rvc <= in_uops_0_is_rvc;
fb_uop_ram_7_debug_pc <= in_uops_0_debug_pc;
fb_uop_ram_7_is_sfb <= io_enq_bits_shadowed_mask_0;
fb_uop_ram_7_pc_lob <= in_uops_0_pc_lob;
fb_uop_ram_7_taken <= in_uops_0_taken;
fb_uop_ram_7_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;
fb_uop_ram_7_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;
end
if (_GEN_38 | _GEN_29 | _GEN_20 | _GEN_11) begin
fb_uop_ram_7_ftq_idx <= io_enq_bits_ftq_idx;
fb_uop_ram_7_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;
fb_uop_ram_7_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;
fb_uop_ram_7_debug_fsrc <= io_enq_bits_fsrc;
end
fb_uop_ram_7_edge_inst <= ~(_GEN_38 | _GEN_29 | _GEN_20) & (_GEN_11 ? io_enq_bits_edge_inst_0 : fb_uop_ram_7_edge_inst);
if (reset) begin
head <= 8'h1;
tail <= 8'h1;
maybe_full <= 1'h0;
end
else begin
if (io_clear) begin
head <= 8'h1;
tail <= 8'h1;
end
else begin
if (do_deq)
head <= {head[6:0], head[7]};
if (do_enq) begin
if (in_mask_3)
tail <= {enq_idxs_3[6:0], enq_idxs_3[7]};
else if (in_mask_2)
tail <= _GEN_2;
else if (in_mask_1)
tail <= _GEN_1;
else if (in_mask_0)
tail <= _GEN_0;
end
end
maybe_full <= ~(io_clear | do_deq) & (do_enq & (in_mask_0 | in_mask_1 | in_mask_2 | in_mask_3) | maybe_full);
end
end
assign io_enq_ready = do_enq;
assign io_deq_valid = ~will_hit_tail;
assign io_deq_bits_uops_0_valid = ~reset & ~will_hit_tail;
assign io_deq_bits_uops_0_bits_inst = (head[0] ? fb_uop_ram_0_inst : 32'h0) | (head[1] ? fb_uop_ram_1_inst : 32'h0) | (head[2] ? fb_uop_ram_2_inst : 32'h0) | (head[3] ? fb_uop_ram_3_inst : 32'h0) | (head[4] ? fb_uop_ram_4_inst : 32'h0) | (head[5] ? fb_uop_ram_5_inst : 32'h0) | (head[6] ? fb_uop_ram_6_inst : 32'h0) | (head[7] ? fb_uop_ram_7_inst : 32'h0);
assign io_deq_bits_uops_0_bits_debug_inst = (head[0] ? fb_uop_ram_0_debug_inst : 32'h0) | (head[1] ? fb_uop_ram_1_debug_inst : 32'h0) | (head[2] ? fb_uop_ram_2_debug_inst : 32'h0) | (head[3] ? fb_uop_ram_3_debug_inst : 32'h0) | (head[4] ? fb_uop_ram_4_debug_inst : 32'h0) | (head[5] ? fb_uop_ram_5_debug_inst : 32'h0) | (head[6] ? fb_uop_ram_6_debug_inst : 32'h0) | (head[7] ? fb_uop_ram_7_debug_inst : 32'h0);
assign io_deq_bits_uops_0_bits_is_rvc = head[0] & fb_uop_ram_0_is_rvc | head[1] & fb_uop_ram_1_is_rvc | head[2] & fb_uop_ram_2_is_rvc | head[3] & fb_uop_ram_3_is_rvc | head[4] & fb_uop_ram_4_is_rvc | head[5] & fb_uop_ram_5_is_rvc | head[6] & fb_uop_ram_6_is_rvc | head[7] & fb_uop_ram_7_is_rvc;
assign io_deq_bits_uops_0_bits_debug_pc = (head[0] ? fb_uop_ram_0_debug_pc : 40'h0) | (head[1] ? fb_uop_ram_1_debug_pc : 40'h0) | (head[2] ? fb_uop_ram_2_debug_pc : 40'h0) | (head[3] ? fb_uop_ram_3_debug_pc : 40'h0) | (head[4] ? fb_uop_ram_4_debug_pc : 40'h0) | (head[5] ? fb_uop_ram_5_debug_pc : 40'h0) | (head[6] ? fb_uop_ram_6_debug_pc : 40'h0) | (head[7] ? fb_uop_ram_7_debug_pc : 40'h0);
assign io_deq_bits_uops_0_bits_is_sfb = head[0] & fb_uop_ram_0_is_sfb | head[1] & fb_uop_ram_1_is_sfb | head[2] & fb_uop_ram_2_is_sfb | head[3] & fb_uop_ram_3_is_sfb | head[4] & fb_uop_ram_4_is_sfb | head[5] & fb_uop_ram_5_is_sfb | head[6] & fb_uop_ram_6_is_sfb | head[7] & fb_uop_ram_7_is_sfb;
assign io_deq_bits_uops_0_bits_ftq_idx = (head[0] ? fb_uop_ram_0_ftq_idx : 4'h0) | (head[1] ? fb_uop_ram_1_ftq_idx : 4'h0) | (head[2] ? fb_uop_ram_2_ftq_idx : 4'h0) | (head[3] ? fb_uop_ram_3_ftq_idx : 4'h0) | (head[4] ? fb_uop_ram_4_ftq_idx : 4'h0) | (head[5] ? fb_uop_ram_5_ftq_idx : 4'h0) | (head[6] ? fb_uop_ram_6_ftq_idx : 4'h0) | (head[7] ? fb_uop_ram_7_ftq_idx : 4'h0);
assign io_deq_bits_uops_0_bits_edge_inst = head[0] & fb_uop_ram_0_edge_inst | head[1] & fb_uop_ram_1_edge_inst | head[2] & fb_uop_ram_2_edge_inst | head[3] & fb_uop_ram_3_edge_inst | head[4] & fb_uop_ram_4_edge_inst | head[5] & fb_uop_ram_5_edge_inst | head[6] & fb_uop_ram_6_edge_inst | head[7] & fb_uop_ram_7_edge_inst;
assign io_deq_bits_uops_0_bits_pc_lob = (head[0] ? fb_uop_ram_0_pc_lob : 6'h0) | (head[1] ? fb_uop_ram_1_pc_lob : 6'h0) | (head[2] ? fb_uop_ram_2_pc_lob : 6'h0) | (head[3] ? fb_uop_ram_3_pc_lob : 6'h0) | (head[4] ? fb_uop_ram_4_pc_lob : 6'h0) | (head[5] ? fb_uop_ram_5_pc_lob : 6'h0) | (head[6] ? fb_uop_ram_6_pc_lob : 6'h0) | (head[7] ? fb_uop_ram_7_pc_lob : 6'h0);
assign io_deq_bits_uops_0_bits_taken = head[0] & fb_uop_ram_0_taken | head[1] & fb_uop_ram_1_taken | head[2] & fb_uop_ram_2_taken | head[3] & fb_uop_ram_3_taken | head[4] & fb_uop_ram_4_taken | head[5] & fb_uop_ram_5_taken | head[6] & fb_uop_ram_6_taken | head[7] & fb_uop_ram_7_taken;
assign io_deq_bits_uops_0_bits_xcpt_pf_if = head[0] & fb_uop_ram_0_xcpt_pf_if | head[1] & fb_uop_ram_1_xcpt_pf_if | head[2] & fb_uop_ram_2_xcpt_pf_if | head[3] & fb_uop_ram_3_xcpt_pf_if | head[4] & fb_uop_ram_4_xcpt_pf_if | head[5] & fb_uop_ram_5_xcpt_pf_if | head[6] & fb_uop_ram_6_xcpt_pf_if | head[7] & fb_uop_ram_7_xcpt_pf_if;
assign io_deq_bits_uops_0_bits_xcpt_ae_if = head[0] & fb_uop_ram_0_xcpt_ae_if | head[1] & fb_uop_ram_1_xcpt_ae_if | head[2] & fb_uop_ram_2_xcpt_ae_if | head[3] & fb_uop_ram_3_xcpt_ae_if | head[4] & fb_uop_ram_4_xcpt_ae_if | head[5] & fb_uop_ram_5_xcpt_ae_if | head[6] & fb_uop_ram_6_xcpt_ae_if | head[7] & fb_uop_ram_7_xcpt_ae_if;
assign io_deq_bits_uops_0_bits_bp_debug_if = head[0] & fb_uop_ram_0_bp_debug_if | head[1] & fb_uop_ram_1_bp_debug_if | head[2] & fb_uop_ram_2_bp_debug_if | head[3] & fb_uop_ram_3_bp_debug_if | head[4] & fb_uop_ram_4_bp_debug_if | head[5] & fb_uop_ram_5_bp_debug_if | head[6] & fb_uop_ram_6_bp_debug_if | head[7] & fb_uop_ram_7_bp_debug_if;
assign io_deq_bits_uops_0_bits_bp_xcpt_if = head[0] & fb_uop_ram_0_bp_xcpt_if | head[1] & fb_uop_ram_1_bp_xcpt_if | head[2] & fb_uop_ram_2_bp_xcpt_if | head[3] & fb_uop_ram_3_bp_xcpt_if | head[4] & fb_uop_ram_4_bp_xcpt_if | head[5] & fb_uop_ram_5_bp_xcpt_if | head[6] & fb_uop_ram_6_bp_xcpt_if | head[7] & fb_uop_ram_7_bp_xcpt_if;
assign io_deq_bits_uops_0_bits_debug_fsrc = (head[0] ? fb_uop_ram_0_debug_fsrc : 2'h0) | (head[1] ? fb_uop_ram_1_debug_fsrc : 2'h0) | (head[2] ? fb_uop_ram_2_debug_fsrc : 2'h0) | (head[3] ? fb_uop_ram_3_debug_fsrc : 2'h0) | (head[4] ? fb_uop_ram_4_debug_fsrc : 2'h0) | (head[5] ? fb_uop_ram_5_debug_fsrc : 2'h0) | (head[6] ? fb_uop_ram_6_debug_fsrc : 2'h0) | (head[7] ? fb_uop_ram_7_debug_fsrc : 2'h0);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module TageTable_3(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [2:0] io_f3_resp_1_bits_ctr,
output [1:0] io_f3_resp_1_bits_u,
output io_f3_resp_2_valid,
output [2:0] io_f3_resp_2_bits_ctr,
output [1:0] io_f3_resp_2_bits_u,
output io_f3_resp_3_valid,
output [2:0] io_f3_resp_3_bits_ctr,
output [1:0] io_f3_resp_3_bits_u,
input io_update_mask_0,
input io_update_mask_1,
input io_update_mask_2,
input io_update_mask_3,
input io_update_taken_0,
input io_update_taken_1,
input io_update_taken_2,
input io_update_taken_3,
input io_update_alloc_0,
input io_update_alloc_1,
input io_update_alloc_2,
input io_update_alloc_3,
input [2:0] io_update_old_ctr_0,
input [2:0] io_update_old_ctr_1,
input [2:0] io_update_old_ctr_2,
input [2:0] io_update_old_ctr_3,
input [39:0] io_update_pc,
input [63:0] io_update_hist,
input io_update_u_mask_0,
input io_update_u_mask_1,
input io_update_u_mask_2,
input io_update_u_mask_3,
input [1:0] io_update_u_0,
input [1:0] io_update_u_1,
input [1:0] io_update_u_2,
input [1:0] io_update_u_3
);
wire update_lo_wdata_3;
wire update_hi_wdata_3;
wire [2:0] update_wdata_3_ctr;
wire update_lo_wdata_2;
wire update_hi_wdata_2;
wire [2:0] update_wdata_2_ctr;
wire update_lo_wdata_1;
wire update_hi_wdata_1;
wire [2:0] update_wdata_1_ctr;
wire update_lo_wdata_0;
wire update_hi_wdata_0;
wire [2:0] update_wdata_0_ctr;
wire lo_us_MPORT_2_data_3;
wire lo_us_MPORT_2_data_2;
wire lo_us_MPORT_2_data_1;
wire lo_us_MPORT_2_data_0;
wire hi_us_MPORT_1_data_3;
wire hi_us_MPORT_1_data_2;
wire hi_us_MPORT_1_data_1;
wire hi_us_MPORT_1_data_0;
wire [11:0] table_MPORT_data_3;
wire [11:0] table_MPORT_data_2;
wire [11:0] table_MPORT_data_1;
wire [11:0] table_MPORT_data_0;
wire [47:0] _table_R0_data;
wire [3:0] _lo_us_R0_data;
wire [3:0] _hi_us_R0_data;
reg doing_reset;
reg [7:0] reset_idx;
wire [7:0] s1_hashed_idx = io_f1_req_pc[10:3] ^ io_f1_req_ghist[7:0] ^ io_f1_req_ghist[15:8];
reg [7:0] s2_tag;
reg io_f3_resp_0_valid_REG;
reg [1:0] io_f3_resp_0_bits_u_REG;
reg [2:0] io_f3_resp_0_bits_ctr_REG;
reg io_f3_resp_1_valid_REG;
reg [1:0] io_f3_resp_1_bits_u_REG;
reg [2:0] io_f3_resp_1_bits_ctr_REG;
reg io_f3_resp_2_valid_REG;
reg [1:0] io_f3_resp_2_bits_u_REG;
reg [2:0] io_f3_resp_2_bits_ctr_REG;
reg io_f3_resp_3_valid_REG;
reg [1:0] io_f3_resp_3_bits_u_REG;
reg [2:0] io_f3_resp_3_bits_ctr_REG;
reg [19:0] clear_u_ctr;
wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;
wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[19];
wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[19]);
wire [7:0] update_idx = io_update_pc[10:3] ^ io_update_hist[7:0] ^ io_update_hist[15:8];
wire [7:0] update_tag = io_update_pc[18:11] ^ io_update_hist[7:0] ^ io_update_hist[15:8];
assign table_MPORT_data_0 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_0_ctr};
assign table_MPORT_data_1 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_1_ctr};
assign table_MPORT_data_2 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_2_ctr};
assign table_MPORT_data_3 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_3_ctr};
wire _GEN = doing_reset | doing_clear_u_hi;
assign hi_us_MPORT_1_data_0 = ~_GEN & update_hi_wdata_0;
assign hi_us_MPORT_1_data_1 = ~_GEN & update_hi_wdata_1;
assign hi_us_MPORT_1_data_2 = ~_GEN & update_hi_wdata_2;
assign hi_us_MPORT_1_data_3 = ~_GEN & update_hi_wdata_3;
wire [3:0] _GEN_0 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};
wire _GEN_1 = doing_reset | doing_clear_u_lo;
assign lo_us_MPORT_2_data_0 = ~_GEN_1 & update_lo_wdata_0;
assign lo_us_MPORT_2_data_1 = ~_GEN_1 & update_lo_wdata_1;
assign lo_us_MPORT_2_data_2 = ~_GEN_1 & update_lo_wdata_2;
assign lo_us_MPORT_2_data_3 = ~_GEN_1 & update_lo_wdata_3;
reg [7:0] wrbypass_tags_0;
reg [7:0] wrbypass_tags_1;
reg [7:0] wrbypass_idxs_0;
reg [7:0] wrbypass_idxs_1;
reg [2:0] wrbypass_0_0;
reg [2:0] wrbypass_0_1;
reg [2:0] wrbypass_0_2;
reg [2:0] wrbypass_0_3;
reg [2:0] wrbypass_1_0;
reg [2:0] wrbypass_1_1;
reg [2:0] wrbypass_1_2;
reg [2:0] wrbypass_1_3;
reg wrbypass_enq_idx;
wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;
wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;
wire [2:0] _GEN_2 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;
wire [2:0] _GEN_3 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;
wire [2:0] _GEN_4 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;
wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;
assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_2) ? 3'h7 : _GEN_2 + 3'h1) : _GEN_2 == 3'h0 ? 3'h0 : _GEN_2 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;
assign update_hi_wdata_0 = io_update_u_0[1];
assign update_lo_wdata_0 = io_update_u_0[0];
assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_3) ? 3'h7 : _GEN_3 + 3'h1) : _GEN_3 == 3'h0 ? 3'h0 : _GEN_3 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;
assign update_hi_wdata_1 = io_update_u_1[1];
assign update_lo_wdata_1 = io_update_u_1[0];
assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_4) ? 3'h7 : _GEN_4 + 3'h1) : _GEN_4 == 3'h0 ? 3'h0 : _GEN_4 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;
assign update_hi_wdata_2 = io_update_u_2[1];
assign update_lo_wdata_2 = io_update_u_2[0];
assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;
assign update_hi_wdata_3 = io_update_u_3[1];
assign update_lo_wdata_3 = io_update_u_3[0];
wire _GEN_6 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;
wire _GEN_7 = ~_GEN_6 | wrbypass_hit | wrbypass_enq_idx;
wire _GEN_8 = ~_GEN_6 | wrbypass_hit | ~wrbypass_enq_idx;
always @(posedge clock) begin
if (reset) begin
doing_reset <= 1'h1;
reset_idx <= 8'h0;
clear_u_ctr <= 20'h0;
wrbypass_enq_idx <= 1'h0;
end
else begin
doing_reset <= reset_idx != 8'hFF & doing_reset;
reset_idx <= reset_idx + {7'h0, doing_reset};
clear_u_ctr <= doing_reset ? 20'h1 : clear_u_ctr + 20'h1;
if (~_GEN_6 | wrbypass_hit) begin
end
else
wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;
end
s2_tag <= io_f1_req_pc[18:11] ^ io_f1_req_ghist[7:0] ^ io_f1_req_ghist[15:8];
io_f3_resp_0_valid_REG <= _table_R0_data[11] & _table_R0_data[10:3] == s2_tag & ~doing_reset;
io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};
io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];
io_f3_resp_1_valid_REG <= _table_R0_data[23] & _table_R0_data[22:15] == s2_tag & ~doing_reset;
io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};
io_f3_resp_1_bits_ctr_REG <= _table_R0_data[14:12];
io_f3_resp_2_valid_REG <= _table_R0_data[35] & _table_R0_data[34:27] == s2_tag & ~doing_reset;
io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};
io_f3_resp_2_bits_ctr_REG <= _table_R0_data[26:24];
io_f3_resp_3_valid_REG <= _table_R0_data[47] & _table_R0_data[46:39] == s2_tag & ~doing_reset;
io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};
io_f3_resp_3_bits_ctr_REG <= _table_R0_data[38:36];
if (_GEN_7) begin
end
else
wrbypass_tags_0 <= update_tag;
if (_GEN_8) begin
end
else
wrbypass_tags_1 <= update_tag;
if (_GEN_7) begin
end
else
wrbypass_idxs_0 <= update_idx;
if (_GEN_8) begin
end
else
wrbypass_idxs_1 <= update_idx;
if (_GEN_6) begin
if (wrbypass_hit) begin
if (wrbypass_hits_0) begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
end
else if (wrbypass_enq_idx) begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
end
end
hi_us_2 hi_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[18:11] : update_idx),
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),
.W0_mask (_GEN ? 4'hF : _GEN_0)
);
lo_us_2 lo_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[18:11] : update_idx),
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),
.W0_mask (_GEN_1 ? 4'hF : _GEN_0)
);
table_2 table_0 (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx),
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),
.W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})
);
assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;
assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;
assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;
assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module FlitToPhit_f32_p32_TestHarness_UNIQUIFIED(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_phit
);
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign io_out_bits_phit = io_in_bits_flit;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Register File (Abstract class and Synthesizable RegFile)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import scala.collection.mutable.ArrayBuffer
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* IO bundle for a register read port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
}
/**
* IO bundle for the register write port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = UInt(addrWidth.W)
val data = UInt(dataWidth.W)
}
/**
* Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.
*/
object WritePort
{
def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)
(implicit p: Parameters): Valid[RegisterFileWritePort] = {
val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))
wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype
wport.bits.addr := enq.bits.uop.pdst
wport.bits.data := enq.bits.data
enq.ready := true.B
wport
}
}
/**
* Register file abstract class
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
abstract class RegisterFile(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?
(implicit p: Parameters) extends BoomModule
{
val io = IO(new BoomBundle {
val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))
val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))
})
private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)
private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer"
override def toString: String = BoomCoreStringPrefix(
"==" + type_str + " Regfile==",
"Num RF Read Ports : " + numReadPorts,
"Num RF Write Ports : " + numWritePorts,
"RF Cost (R+W)*(R+2W) : " + rf_cost,
"Bypassable Units : " + bypassableArray)
}
/**
* A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
class RegisterFileSynthesizable(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean])
(implicit p: Parameters)
extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)
{
// --------------------------------------------------------------
val regfile = Mem(numRegisters, UInt(registerWidth.W))
// --------------------------------------------------------------
// Read ports.
val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))
// Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).
val read_addrs = io.read_ports.map(p => RegNext(p.addr))
for (i <- 0 until numReadPorts) {
read_data(i) := regfile(read_addrs(i))
}
// --------------------------------------------------------------
// Bypass out of the ALU's write ports.
// We are assuming we cannot bypass a writer to a reader within the regfile memory
// for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.
// But since these bypasses are expensive, and not all write ports need to bypass their data,
// only perform the w->r bypass on a select number of write ports.
require (bypassableArray.length == io.write_ports.length)
if (bypassableArray.reduce(_||_)) {
val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()
io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }
for (i <- 0 until numReadPorts) {
val bypass_ens = bypassable_wports.map(x => x.valid &&
x.bits.addr === read_addrs(i))
val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))
io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))
}
} else {
for (i <- 0 until numReadPorts) {
io.read_ports(i).data := read_data(i)
}
}
// --------------------------------------------------------------
// Write ports.
for (wport <- io.write_ports) {
when (wport.valid) {
regfile(wport.bits.addr) := wport.bits.data
}
}
// ensure there is only 1 writer per register (unless to preg0)
if (numWritePorts > 1) {
for (i <- 0 until (numWritePorts - 1)) {
for (j <- (i + 1) until numWritePorts) {
assert(!io.write_ports(i).valid ||
!io.write_ports(j).valid ||
(io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||
(io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here
"[regfile] too many writers a register")
}
}
}
} | module RegisterFileSynthesizable_1(
input clock,
input reset,
input [5:0] io_read_ports_0_addr,
output [63:0] io_read_ports_0_data,
input [5:0] io_read_ports_1_addr,
output [63:0] io_read_ports_1_data,
input [5:0] io_read_ports_2_addr,
output [63:0] io_read_ports_2_data,
input [5:0] io_read_ports_3_addr,
output [63:0] io_read_ports_3_data,
input io_write_ports_0_valid,
input [5:0] io_write_ports_0_bits_addr,
input [63:0] io_write_ports_0_bits_data,
input io_write_ports_1_valid,
input [5:0] io_write_ports_1_bits_addr,
input [63:0] io_write_ports_1_bits_data
);
wire [63:0] _regfile_ext_R0_data;
wire [63:0] _regfile_ext_R1_data;
wire [63:0] _regfile_ext_R2_data;
wire [63:0] _regfile_ext_R3_data;
reg [5:0] read_addrs_0;
reg [5:0] read_addrs_1;
reg [5:0] read_addrs_2;
reg [5:0] read_addrs_3;
wire bypass_ens_0 = io_write_ports_0_valid & io_write_ports_0_bits_addr == read_addrs_0;
wire bypass_ens_1 = io_write_ports_1_valid & io_write_ports_1_bits_addr == read_addrs_0;
wire bypass_ens_0_1 = io_write_ports_0_valid & io_write_ports_0_bits_addr == read_addrs_1;
wire bypass_ens_1_1 = io_write_ports_1_valid & io_write_ports_1_bits_addr == read_addrs_1;
wire bypass_ens_0_2 = io_write_ports_0_valid & io_write_ports_0_bits_addr == read_addrs_2;
wire bypass_ens_1_2 = io_write_ports_1_valid & io_write_ports_1_bits_addr == read_addrs_2;
wire bypass_ens_0_3 = io_write_ports_0_valid & io_write_ports_0_bits_addr == read_addrs_3;
wire bypass_ens_1_3 = io_write_ports_1_valid & io_write_ports_1_bits_addr == read_addrs_3;
always @(posedge clock) begin
read_addrs_0 <= io_read_ports_0_addr;
read_addrs_1 <= io_read_ports_1_addr;
read_addrs_2 <= io_read_ports_2_addr;
read_addrs_3 <= io_read_ports_3_addr;
end
regfile_52x64 regfile_ext (
.R0_addr (read_addrs_3),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_regfile_ext_R0_data),
.R1_addr (read_addrs_2),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_regfile_ext_R1_data),
.R2_addr (read_addrs_1),
.R2_en (1'h1),
.R2_clk (clock),
.R2_data (_regfile_ext_R2_data),
.R3_addr (read_addrs_0),
.R3_en (1'h1),
.R3_clk (clock),
.R3_data (_regfile_ext_R3_data),
.W0_addr (io_write_ports_1_bits_addr),
.W0_en (io_write_ports_1_valid),
.W0_clk (clock),
.W0_data (io_write_ports_1_bits_data),
.W1_addr (io_write_ports_0_bits_addr),
.W1_en (io_write_ports_0_valid),
.W1_clk (clock),
.W1_data (io_write_ports_0_bits_data)
);
assign io_read_ports_0_data = bypass_ens_0 | bypass_ens_1 ? (bypass_ens_0 ? io_write_ports_0_bits_data : 64'h0) | (bypass_ens_1 ? io_write_ports_1_bits_data : 64'h0) : _regfile_ext_R3_data;
assign io_read_ports_1_data = bypass_ens_0_1 | bypass_ens_1_1 ? (bypass_ens_0_1 ? io_write_ports_0_bits_data : 64'h0) | (bypass_ens_1_1 ? io_write_ports_1_bits_data : 64'h0) : _regfile_ext_R2_data;
assign io_read_ports_2_data = bypass_ens_0_2 | bypass_ens_1_2 ? (bypass_ens_0_2 ? io_write_ports_0_bits_data : 64'h0) | (bypass_ens_1_2 ? io_write_ports_1_bits_data : 64'h0) : _regfile_ext_R1_data;
assign io_read_ports_3_data = bypass_ens_0_3 | bypass_ens_1_3 ? (bypass_ens_0_3 ? io_write_ports_0_bits_data : 64'h0) | (bypass_ens_1_3 ? io_write_ports_1_bits_data : 64'h0) : _regfile_ext_R0_data;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module lo_us_4(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Rename BusyTable
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import boom.v3.common._
import boom.v3.util._
import org.chipsalliance.cde.config.Parameters
class BusyResp extends Bundle
{
val prs1_busy = Bool()
val prs2_busy = Bool()
val prs3_busy = Bool()
}
class RenameBusyTable(
val plWidth: Int,
val numPregs: Int,
val numWbPorts: Int,
val bypass: Boolean,
val float: Boolean)
(implicit p: Parameters) extends BoomModule
{
val pregSz = log2Ceil(numPregs)
val io = IO(new BoomBundle()(p) {
val ren_uops = Input(Vec(plWidth, new MicroOp))
val busy_resps = Output(Vec(plWidth, new BusyResp))
val rebusy_reqs = Input(Vec(plWidth, Bool()))
val wb_pdsts = Input(Vec(numWbPorts, UInt(pregSz.W)))
val wb_valids = Input(Vec(numWbPorts, Bool()))
val debug = new Bundle { val busytable = Output(Bits(numPregs.W)) }
})
val busy_table = RegInit(0.U(numPregs.W))
// Unbusy written back registers.
val busy_table_wb = busy_table & ~(io.wb_pdsts zip io.wb_valids)
.map {case (pdst, valid) => UIntToOH(pdst) & Fill(numPregs, valid.asUInt)}.reduce(_|_)
// Rebusy newly allocated registers.
val busy_table_next = busy_table_wb | (io.ren_uops zip io.rebusy_reqs)
.map {case (uop, req) => UIntToOH(uop.pdst) & Fill(numPregs, req.asUInt)}.reduce(_|_)
busy_table := busy_table_next
// Read the busy table.
for (i <- 0 until plWidth) {
val prs1_was_bypassed = (0 until i).map(j =>
io.ren_uops(i).lrs1 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)
val prs2_was_bypassed = (0 until i).map(j =>
io.ren_uops(i).lrs2 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)
val prs3_was_bypassed = (0 until i).map(j =>
io.ren_uops(i).lrs3 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)
io.busy_resps(i).prs1_busy := busy_table(io.ren_uops(i).prs1) || prs1_was_bypassed && bypass.B
io.busy_resps(i).prs2_busy := busy_table(io.ren_uops(i).prs2) || prs2_was_bypassed && bypass.B
io.busy_resps(i).prs3_busy := busy_table(io.ren_uops(i).prs3) || prs3_was_bypassed && bypass.B
if (!float) io.busy_resps(i).prs3_busy := false.B
}
io.debug.busytable := busy_table
} | module RenameBusyTable_1(
input clock,
input reset,
input [5:0] io_ren_uops_0_pdst,
input [5:0] io_ren_uops_0_prs1,
input [5:0] io_ren_uops_0_prs2,
input [5:0] io_ren_uops_0_prs3,
output io_busy_resps_0_prs1_busy,
output io_busy_resps_0_prs2_busy,
output io_busy_resps_0_prs3_busy,
input io_rebusy_reqs_0,
input [5:0] io_wb_pdsts_0,
input [5:0] io_wb_pdsts_1,
input io_wb_valids_0,
input io_wb_valids_1
);
reg [47:0] busy_table;
wire [47:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1;
wire [47:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2;
wire [47:0] _io_busy_resps_0_prs3_busy_T = busy_table >> io_ren_uops_0_prs3;
wire [63:0] _busy_table_next_T = 64'h1 << io_ren_uops_0_pdst;
wire [63:0] _busy_table_wb_T_3 = 64'h1 << io_wb_pdsts_1;
wire [63:0] _busy_table_wb_T = 64'h1 << io_wb_pdsts_0;
always @(posedge clock) begin
if (reset)
busy_table <= 48'h0;
else
busy_table <= ~(_busy_table_wb_T[47:0] & {48{io_wb_valids_0}} | _busy_table_wb_T_3[47:0] & {48{io_wb_valids_1}}) & busy_table | _busy_table_next_T[47:0] & {48{io_rebusy_reqs_0}};
end
assign io_busy_resps_0_prs1_busy = _io_busy_resps_0_prs1_busy_T[0];
assign io_busy_resps_0_prs2_busy = _io_busy_resps_0_prs2_busy_T[0];
assign io_busy_resps_0_prs3_busy = _io_busy_resps_0_prs3_busy_T[0];
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
// The control port response source
class SourceXRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val fail = Bool()
}
class SourceX(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new SourceXRequest(params)))
val x = Decoupled(new SourceXRequest(params))
})
val x = Wire(chiselTypeOf(io.x)) // ready must not depend on valid
io.x <> Queue(x, 1)
io.req.ready := x.ready
x.valid := io.req.valid
params.ccover(x.valid && !x.ready, "SOURCEX_STALL", "Backpressure when sending a control message")
x.bits := io.req.bits
} | module SourceX(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
output io_x_valid
);
Queue1_SourceXRequest io_x_q (
.clock (clock),
.reset (reset),
.io_enq_ready (io_req_ready),
.io_enq_valid (io_req_valid),
.io_deq_valid (io_x_valid)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module lo_us_0(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module TageTable_2(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [2:0] io_f3_resp_1_bits_ctr,
output [1:0] io_f3_resp_1_bits_u,
output io_f3_resp_2_valid,
output [2:0] io_f3_resp_2_bits_ctr,
output [1:0] io_f3_resp_2_bits_u,
output io_f3_resp_3_valid,
output [2:0] io_f3_resp_3_bits_ctr,
output [1:0] io_f3_resp_3_bits_u,
input io_update_mask_0,
input io_update_mask_1,
input io_update_mask_2,
input io_update_mask_3,
input io_update_taken_0,
input io_update_taken_1,
input io_update_taken_2,
input io_update_taken_3,
input io_update_alloc_0,
input io_update_alloc_1,
input io_update_alloc_2,
input io_update_alloc_3,
input [2:0] io_update_old_ctr_0,
input [2:0] io_update_old_ctr_1,
input [2:0] io_update_old_ctr_2,
input [2:0] io_update_old_ctr_3,
input [39:0] io_update_pc,
input [63:0] io_update_hist,
input io_update_u_mask_0,
input io_update_u_mask_1,
input io_update_u_mask_2,
input io_update_u_mask_3,
input [1:0] io_update_u_0,
input [1:0] io_update_u_1,
input [1:0] io_update_u_2,
input [1:0] io_update_u_3
);
wire update_lo_wdata_3;
wire update_hi_wdata_3;
wire [2:0] update_wdata_3_ctr;
wire update_lo_wdata_2;
wire update_hi_wdata_2;
wire [2:0] update_wdata_2_ctr;
wire update_lo_wdata_1;
wire update_hi_wdata_1;
wire [2:0] update_wdata_1_ctr;
wire update_lo_wdata_0;
wire update_hi_wdata_0;
wire [2:0] update_wdata_0_ctr;
wire lo_us_MPORT_2_data_3;
wire lo_us_MPORT_2_data_2;
wire lo_us_MPORT_2_data_1;
wire lo_us_MPORT_2_data_0;
wire hi_us_MPORT_1_data_3;
wire hi_us_MPORT_1_data_2;
wire hi_us_MPORT_1_data_1;
wire hi_us_MPORT_1_data_0;
wire [11:0] table_MPORT_data_3;
wire [11:0] table_MPORT_data_2;
wire [11:0] table_MPORT_data_1;
wire [11:0] table_MPORT_data_0;
wire [47:0] _table_R0_data;
wire [3:0] _lo_us_R0_data;
wire [3:0] _hi_us_R0_data;
reg doing_reset;
reg [7:0] reset_idx;
wire [7:0] s1_hashed_idx = io_f1_req_pc[10:3] ^ io_f1_req_ghist[7:0];
reg [7:0] s2_tag;
reg io_f3_resp_0_valid_REG;
reg [1:0] io_f3_resp_0_bits_u_REG;
reg [2:0] io_f3_resp_0_bits_ctr_REG;
reg io_f3_resp_1_valid_REG;
reg [1:0] io_f3_resp_1_bits_u_REG;
reg [2:0] io_f3_resp_1_bits_ctr_REG;
reg io_f3_resp_2_valid_REG;
reg [1:0] io_f3_resp_2_bits_u_REG;
reg [2:0] io_f3_resp_2_bits_ctr_REG;
reg io_f3_resp_3_valid_REG;
reg [1:0] io_f3_resp_3_bits_u_REG;
reg [2:0] io_f3_resp_3_bits_ctr_REG;
reg [19:0] clear_u_ctr;
wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;
wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[19];
wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[19]);
wire [7:0] update_idx = io_update_pc[10:3] ^ io_update_hist[7:0];
wire [7:0] update_tag = io_update_pc[18:11] ^ io_update_hist[7:0];
assign table_MPORT_data_0 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_0_ctr};
assign table_MPORT_data_1 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_1_ctr};
assign table_MPORT_data_2 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_2_ctr};
assign table_MPORT_data_3 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_3_ctr};
wire _GEN = doing_reset | doing_clear_u_hi;
assign hi_us_MPORT_1_data_0 = ~_GEN & update_hi_wdata_0;
assign hi_us_MPORT_1_data_1 = ~_GEN & update_hi_wdata_1;
assign hi_us_MPORT_1_data_2 = ~_GEN & update_hi_wdata_2;
assign hi_us_MPORT_1_data_3 = ~_GEN & update_hi_wdata_3;
wire [3:0] _GEN_0 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};
wire _GEN_1 = doing_reset | doing_clear_u_lo;
assign lo_us_MPORT_2_data_0 = ~_GEN_1 & update_lo_wdata_0;
assign lo_us_MPORT_2_data_1 = ~_GEN_1 & update_lo_wdata_1;
assign lo_us_MPORT_2_data_2 = ~_GEN_1 & update_lo_wdata_2;
assign lo_us_MPORT_2_data_3 = ~_GEN_1 & update_lo_wdata_3;
reg [7:0] wrbypass_tags_0;
reg [7:0] wrbypass_tags_1;
reg [7:0] wrbypass_idxs_0;
reg [7:0] wrbypass_idxs_1;
reg [2:0] wrbypass_0_0;
reg [2:0] wrbypass_0_1;
reg [2:0] wrbypass_0_2;
reg [2:0] wrbypass_0_3;
reg [2:0] wrbypass_1_0;
reg [2:0] wrbypass_1_1;
reg [2:0] wrbypass_1_2;
reg [2:0] wrbypass_1_3;
reg wrbypass_enq_idx;
wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;
wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;
wire [2:0] _GEN_2 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;
wire [2:0] _GEN_3 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;
wire [2:0] _GEN_4 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;
wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;
assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_2) ? 3'h7 : _GEN_2 + 3'h1) : _GEN_2 == 3'h0 ? 3'h0 : _GEN_2 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;
assign update_hi_wdata_0 = io_update_u_0[1];
assign update_lo_wdata_0 = io_update_u_0[0];
assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_3) ? 3'h7 : _GEN_3 + 3'h1) : _GEN_3 == 3'h0 ? 3'h0 : _GEN_3 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;
assign update_hi_wdata_1 = io_update_u_1[1];
assign update_lo_wdata_1 = io_update_u_1[0];
assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_4) ? 3'h7 : _GEN_4 + 3'h1) : _GEN_4 == 3'h0 ? 3'h0 : _GEN_4 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;
assign update_hi_wdata_2 = io_update_u_2[1];
assign update_lo_wdata_2 = io_update_u_2[0];
assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;
assign update_hi_wdata_3 = io_update_u_3[1];
assign update_lo_wdata_3 = io_update_u_3[0];
wire _GEN_6 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;
wire _GEN_7 = ~_GEN_6 | wrbypass_hit | wrbypass_enq_idx;
wire _GEN_8 = ~_GEN_6 | wrbypass_hit | ~wrbypass_enq_idx;
always @(posedge clock) begin
if (reset) begin
doing_reset <= 1'h1;
reset_idx <= 8'h0;
clear_u_ctr <= 20'h0;
wrbypass_enq_idx <= 1'h0;
end
else begin
doing_reset <= reset_idx != 8'hFF & doing_reset;
reset_idx <= reset_idx + {7'h0, doing_reset};
clear_u_ctr <= doing_reset ? 20'h1 : clear_u_ctr + 20'h1;
if (~_GEN_6 | wrbypass_hit) begin
end
else
wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;
end
s2_tag <= io_f1_req_pc[18:11] ^ io_f1_req_ghist[7:0];
io_f3_resp_0_valid_REG <= _table_R0_data[11] & _table_R0_data[10:3] == s2_tag & ~doing_reset;
io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};
io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];
io_f3_resp_1_valid_REG <= _table_R0_data[23] & _table_R0_data[22:15] == s2_tag & ~doing_reset;
io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};
io_f3_resp_1_bits_ctr_REG <= _table_R0_data[14:12];
io_f3_resp_2_valid_REG <= _table_R0_data[35] & _table_R0_data[34:27] == s2_tag & ~doing_reset;
io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};
io_f3_resp_2_bits_ctr_REG <= _table_R0_data[26:24];
io_f3_resp_3_valid_REG <= _table_R0_data[47] & _table_R0_data[46:39] == s2_tag & ~doing_reset;
io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};
io_f3_resp_3_bits_ctr_REG <= _table_R0_data[38:36];
if (_GEN_7) begin
end
else
wrbypass_tags_0 <= update_tag;
if (_GEN_8) begin
end
else
wrbypass_tags_1 <= update_tag;
if (_GEN_7) begin
end
else
wrbypass_idxs_0 <= update_idx;
if (_GEN_8) begin
end
else
wrbypass_idxs_1 <= update_idx;
if (_GEN_6) begin
if (wrbypass_hit) begin
if (wrbypass_hits_0) begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
end
else if (wrbypass_enq_idx) begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
end
end
hi_us_1 hi_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[18:11] : update_idx),
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),
.W0_mask (_GEN ? 4'hF : _GEN_0)
);
lo_us_1 lo_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[18:11] : update_idx),
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),
.W0_mask (_GEN_1 ? 4'hF : _GEN_0)
);
table_1 table_0 (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx),
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),
.W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})
);
assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;
assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;
assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;
assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [53:0] io_in_sig,
input [2:0] io_roundingMode,
output [16:0] io_out,
output [4:0] io_exceptionFlags
);
wire roundingMode_near_even = io_roundingMode == 3'h0;
wire roundingMode_odd = io_roundingMode == 3'h6;
wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;
wire [13:0] sAdjustedExp = {io_in_sExp[12], io_in_sExp} - 14'h7E0;
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> ~(sAdjustedExp[5:0]));
wire [12:0] _GEN = {1'h1, ~(roundMask_shift[7]), ~(roundMask_shift[8]), ~(roundMask_shift[9]), ~(roundMask_shift[10]), ~(roundMask_shift[11]), ~(roundMask_shift[12]), ~(roundMask_shift[13]), ~(roundMask_shift[14]), ~(roundMask_shift[15]), ~(roundMask_shift[16]), ~(roundMask_shift[17]), ~(roundMask_shift[18])};
wire [12:0] _GEN_0 = {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], roundMask_shift[18], 1'h1};
wire [12:0] _roundPosBit_T = io_in_sig[53:41] & _GEN & _GEN_0;
wire [12:0] _anyRoundExtra_T = {io_in_sig[52:41], |(io_in_sig[40:0])} & _GEN_0;
wire [25:0] _GEN_1 = {_roundPosBit_T, _anyRoundExtra_T};
wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;
wire [12:0] roundedSig = _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & (|_GEN_1) ? {1'h0, io_in_sig[53] | roundMask_shift[7], io_in_sig[52] | roundMask_shift[8], io_in_sig[51] | roundMask_shift[9], io_in_sig[50] | roundMask_shift[10], io_in_sig[49] | roundMask_shift[11], io_in_sig[48] | roundMask_shift[12], io_in_sig[47] | roundMask_shift[13], io_in_sig[46] | roundMask_shift[14], io_in_sig[45] | roundMask_shift[15], io_in_sig[44] | roundMask_shift[16], io_in_sig[43] | roundMask_shift[17], io_in_sig[42] | roundMask_shift[18]} + 13'h1 & ~(roundingMode_near_even & (|_roundPosBit_T) & _anyRoundExtra_T == 13'h0 ? {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], roundMask_shift[18], 1'h1} : 13'h0) : {1'h0, io_in_sig[53:42] & {~(roundMask_shift[7]), ~(roundMask_shift[8]), ~(roundMask_shift[9]), ~(roundMask_shift[10]), ~(roundMask_shift[11]), ~(roundMask_shift[12]), ~(roundMask_shift[13]), ~(roundMask_shift[14]), ~(roundMask_shift[15]), ~(roundMask_shift[16]), ~(roundMask_shift[17]), ~(roundMask_shift[18])}} | (roundingMode_odd & (|_GEN_1) ? _GEN & _GEN_0 : 13'h0);
wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {13'h0, roundedSig[12:11]};
wire common_totalUnderflow = $signed(sRoundedExp) < 15'sh8;
wire isNaNOut = io_invalidExc | io_in_isNaN;
wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero;
wire overflow = commonCase & $signed(sRoundedExp[14:4]) > 11'sh2;
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;
wire pegMinNonzeroMagOut = commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);
wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;
wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp;
assign io_out = {~isNaNOut & io_in_sign, sRoundedExp[5:0] & ~(io_in_isZero | common_totalUnderflow ? 6'h38 : 6'h0) & ~(pegMinNonzeroMagOut ? 6'h37 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} & {2'h3, ~notNaN_isInfOut, 3'h7} | {2'h0, pegMinNonzeroMagOut, 3'h0} | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (notNaN_isInfOut ? 6'h30 : 6'h0) | (isNaNOut ? 6'h38 : 6'h0), (isNaNOut | io_in_isZero | common_totalUnderflow ? {isNaNOut, 9'h0} : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}};
assign io_exceptionFlags = {io_invalidExc, 1'h0, overflow, commonCase & (common_totalUnderflow | (|_GEN_1) & $signed(sAdjustedExp[13:5]) < 9'sh1 & roundMask_shift[18] & ~(~(roundMask_shift[17]) & roundedSig[11] & (|_roundPosBit_T) & (_overflow_roundMagUp_T & io_in_sig[41] | roundMagUp & (|{io_in_sig[41], |(io_in_sig[40:0])})))), overflow | commonCase & (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module cc_dir(
input [9:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [135:0] RW0_wdata,
output [135:0] RW0_rdata,
input [7:0] RW0_wmask
);
cc_dir_ext cc_dir_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module cc_banks_4(
input [13:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
} | module OptimizationBarrier_PTE(
input [43:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [43:0] io_y_ppn,
output io_y_d,
output io_y_a,
output io_y_g,
output io_y_u,
output io_y_x,
output io_y_w,
output io_y_r,
output io_y_v
);
assign io_y_ppn = io_x_ppn;
assign io_y_d = io_x_d;
assign io_y_a = io_x_a;
assign io_y_g = io_x_g;
assign io_y_u = io_x_u;
assign io_y_x = io_x_x;
assign io_y_w = io_x_w;
assign io_y_r = io_x_r;
assign io_y_v = io_x_v;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
} | module ram_16x46(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [45:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [45:0] W0_data
);
reg [45:0] Memory[0:15];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 46'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
} | module FPUFMAPipe_l4_f32(
input clock,
input reset,
input io_in_valid,
input io_in_bits_ren3,
input io_in_bits_swap23,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_fmaCmd,
input [64:0] io_in_bits_in1,
input [64:0] io_in_bits_in2,
input [64:0] io_in_bits_in3,
output io_out_valid,
output [64:0] io_out_bits_data,
output [4:0] io_out_bits_exc
);
wire [32:0] _fma_io_out;
wire [4:0] _fma_io_exceptionFlags;
wire _fma_io_validout;
reg valid;
reg [2:0] in_rm;
reg [1:0] in_fmaCmd;
reg [64:0] in_in1;
reg [64:0] in_in2;
reg [64:0] in_in3;
reg io_out_pipe_v;
reg [64:0] io_out_pipe_b_data;
reg [4:0] io_out_pipe_b_exc;
always @(posedge clock) begin
valid <= io_in_valid;
if (io_in_valid) begin
in_rm <= io_in_bits_rm;
in_fmaCmd <= io_in_bits_fmaCmd;
in_in1 <= io_in_bits_in1;
in_in2 <= io_in_bits_swap23 ? 65'h80000000 : io_in_bits_in2;
in_in3 <= io_in_bits_ren3 | io_in_bits_swap23 ? io_in_bits_in3 : {32'h0, (io_in_bits_in1[32:0] ^ io_in_bits_in2[32:0]) & 33'h100000000};
end
if (_fma_io_validout) begin
io_out_pipe_b_data <= {32'h0, _fma_io_out};
io_out_pipe_b_exc <= _fma_io_exceptionFlags;
end
if (reset)
io_out_pipe_v <= 1'h0;
else
io_out_pipe_v <= _fma_io_validout;
end
MulAddRecFNPipe_l2_e8_s24 fma (
.clock (clock),
.reset (reset),
.io_validin (valid),
.io_op (in_fmaCmd),
.io_a (in_in1[32:0]),
.io_b (in_in2[32:0]),
.io_c (in_in3[32:0]),
.io_roundingMode (in_rm),
.io_out (_fma_io_out),
.io_exceptionFlags (_fma_io_exceptionFlags),
.io_validout (_fma_io_validout)
);
assign io_out_valid = io_out_pipe_v;
assign io_out_bits_data = io_out_pipe_b_data;
assign io_out_bits_exc = io_out_pipe_b_exc;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Rename Map Table
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import boom.v3.common._
import boom.v3.util._
import org.chipsalliance.cde.config.Parameters
class MapReq(val lregSz: Int) extends Bundle
{
val lrs1 = UInt(lregSz.W)
val lrs2 = UInt(lregSz.W)
val lrs3 = UInt(lregSz.W)
val ldst = UInt(lregSz.W)
}
class MapResp(val pregSz: Int) extends Bundle
{
val prs1 = UInt(pregSz.W)
val prs2 = UInt(pregSz.W)
val prs3 = UInt(pregSz.W)
val stale_pdst = UInt(pregSz.W)
}
class RemapReq(val lregSz: Int, val pregSz: Int) extends Bundle
{
val ldst = UInt(lregSz.W)
val pdst = UInt(pregSz.W)
val valid = Bool()
}
class RenameMapTable(
val plWidth: Int,
val numLregs: Int,
val numPregs: Int,
val bypass: Boolean,
val float: Boolean)
(implicit p: Parameters) extends BoomModule
{
val pregSz = log2Ceil(numPregs)
val io = IO(new BoomBundle()(p) {
// Logical sources -> physical sources.
val map_reqs = Input(Vec(plWidth, new MapReq(lregSz)))
val map_resps = Output(Vec(plWidth, new MapResp(pregSz)))
// Remapping an ldst to a newly allocated pdst?
val remap_reqs = Input(Vec(plWidth, new RemapReq(lregSz, pregSz)))
// Dispatching branches: need to take snapshots of table state.
val ren_br_tags = Input(Vec(plWidth, Valid(UInt(brTagSz.W))))
// Signals for restoring state following misspeculation.
val brupdate = Input(new BrUpdateInfo)
val rollback = Input(Bool())
})
// The map table register array and its branch snapshots.
val map_table = RegInit(VecInit(Seq.fill(numLregs){0.U(pregSz.W)}))
val br_snapshots = Reg(Vec(maxBrCount, Vec(numLregs, UInt(pregSz.W))))
// The intermediate states of the map table following modification by each pipeline slot.
val remap_table = Wire(Vec(plWidth+1, Vec(numLregs, UInt(pregSz.W))))
// Uops requesting changes to the map table.
val remap_pdsts = io.remap_reqs map (_.pdst)
val remap_ldsts_oh = io.remap_reqs map (req => UIntToOH(req.ldst) & Fill(numLregs, req.valid.asUInt))
// Figure out the new mappings seen by each pipeline slot.
for (i <- 0 until numLregs) {
if (i == 0 && !float) {
for (j <- 0 until plWidth+1) {
remap_table(j)(i) := 0.U
}
} else {
val remapped_row = (remap_ldsts_oh.map(ldst => ldst(i)) zip remap_pdsts)
.scanLeft(map_table(i)) {case (pdst, (ldst, new_pdst)) => Mux(ldst, new_pdst, pdst)}
for (j <- 0 until plWidth+1) {
remap_table(j)(i) := remapped_row(j)
}
}
}
// Create snapshots of new mappings.
for (i <- 0 until plWidth) {
when (io.ren_br_tags(i).valid) {
br_snapshots(io.ren_br_tags(i).bits) := remap_table(i+1)
}
}
when (io.brupdate.b2.mispredict) {
// Restore the map table to a branch snapshot.
map_table := br_snapshots(io.brupdate.b2.uop.br_tag)
} .otherwise {
// Update mappings.
map_table := remap_table(plWidth)
}
// Read out mappings.
for (i <- 0 until plWidth) {
io.map_resps(i).prs1 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs1)) ((p,k) =>
Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs1, io.remap_reqs(k).pdst, p))
io.map_resps(i).prs2 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs2)) ((p,k) =>
Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs2, io.remap_reqs(k).pdst, p))
io.map_resps(i).prs3 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs3)) ((p,k) =>
Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs3, io.remap_reqs(k).pdst, p))
io.map_resps(i).stale_pdst := (0 until i).foldLeft(map_table(io.map_reqs(i).ldst)) ((p,k) =>
Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).ldst, io.remap_reqs(k).pdst, p))
if (!float) io.map_resps(i).prs3 := DontCare
}
// Don't flag the creation of duplicate 'p0' mappings during rollback.
// These cases may occur soon after reset, as all maptable entries are initialized to 'p0'.
io.remap_reqs map (req => (req.pdst, req.valid)) foreach {case (p,r) =>
assert (!r || !map_table.contains(p) || p === 0.U && io.rollback, "[maptable] Trying to write a duplicate mapping.")}
} | module RenameMapTable_1(
input clock,
input reset,
input [5:0] io_map_reqs_0_lrs1,
input [5:0] io_map_reqs_0_lrs2,
input [5:0] io_map_reqs_0_lrs3,
input [5:0] io_map_reqs_0_ldst,
output [5:0] io_map_resps_0_prs1,
output [5:0] io_map_resps_0_prs2,
output [5:0] io_map_resps_0_prs3,
output [5:0] io_map_resps_0_stale_pdst,
input [5:0] io_remap_reqs_0_ldst,
input [5:0] io_remap_reqs_0_pdst,
input io_remap_reqs_0_valid,
input io_ren_br_tags_0_valid,
input [2:0] io_ren_br_tags_0_bits,
input [2:0] io_brupdate_b2_uop_br_tag,
input io_brupdate_b2_mispredict,
input io_rollback
);
reg [5:0] map_table_0;
reg [5:0] map_table_1;
reg [5:0] map_table_2;
reg [5:0] map_table_3;
reg [5:0] map_table_4;
reg [5:0] map_table_5;
reg [5:0] map_table_6;
reg [5:0] map_table_7;
reg [5:0] map_table_8;
reg [5:0] map_table_9;
reg [5:0] map_table_10;
reg [5:0] map_table_11;
reg [5:0] map_table_12;
reg [5:0] map_table_13;
reg [5:0] map_table_14;
reg [5:0] map_table_15;
reg [5:0] map_table_16;
reg [5:0] map_table_17;
reg [5:0] map_table_18;
reg [5:0] map_table_19;
reg [5:0] map_table_20;
reg [5:0] map_table_21;
reg [5:0] map_table_22;
reg [5:0] map_table_23;
reg [5:0] map_table_24;
reg [5:0] map_table_25;
reg [5:0] map_table_26;
reg [5:0] map_table_27;
reg [5:0] map_table_28;
reg [5:0] map_table_29;
reg [5:0] map_table_30;
reg [5:0] map_table_31;
reg [5:0] br_snapshots_0_0;
reg [5:0] br_snapshots_0_1;
reg [5:0] br_snapshots_0_2;
reg [5:0] br_snapshots_0_3;
reg [5:0] br_snapshots_0_4;
reg [5:0] br_snapshots_0_5;
reg [5:0] br_snapshots_0_6;
reg [5:0] br_snapshots_0_7;
reg [5:0] br_snapshots_0_8;
reg [5:0] br_snapshots_0_9;
reg [5:0] br_snapshots_0_10;
reg [5:0] br_snapshots_0_11;
reg [5:0] br_snapshots_0_12;
reg [5:0] br_snapshots_0_13;
reg [5:0] br_snapshots_0_14;
reg [5:0] br_snapshots_0_15;
reg [5:0] br_snapshots_0_16;
reg [5:0] br_snapshots_0_17;
reg [5:0] br_snapshots_0_18;
reg [5:0] br_snapshots_0_19;
reg [5:0] br_snapshots_0_20;
reg [5:0] br_snapshots_0_21;
reg [5:0] br_snapshots_0_22;
reg [5:0] br_snapshots_0_23;
reg [5:0] br_snapshots_0_24;
reg [5:0] br_snapshots_0_25;
reg [5:0] br_snapshots_0_26;
reg [5:0] br_snapshots_0_27;
reg [5:0] br_snapshots_0_28;
reg [5:0] br_snapshots_0_29;
reg [5:0] br_snapshots_0_30;
reg [5:0] br_snapshots_0_31;
reg [5:0] br_snapshots_1_0;
reg [5:0] br_snapshots_1_1;
reg [5:0] br_snapshots_1_2;
reg [5:0] br_snapshots_1_3;
reg [5:0] br_snapshots_1_4;
reg [5:0] br_snapshots_1_5;
reg [5:0] br_snapshots_1_6;
reg [5:0] br_snapshots_1_7;
reg [5:0] br_snapshots_1_8;
reg [5:0] br_snapshots_1_9;
reg [5:0] br_snapshots_1_10;
reg [5:0] br_snapshots_1_11;
reg [5:0] br_snapshots_1_12;
reg [5:0] br_snapshots_1_13;
reg [5:0] br_snapshots_1_14;
reg [5:0] br_snapshots_1_15;
reg [5:0] br_snapshots_1_16;
reg [5:0] br_snapshots_1_17;
reg [5:0] br_snapshots_1_18;
reg [5:0] br_snapshots_1_19;
reg [5:0] br_snapshots_1_20;
reg [5:0] br_snapshots_1_21;
reg [5:0] br_snapshots_1_22;
reg [5:0] br_snapshots_1_23;
reg [5:0] br_snapshots_1_24;
reg [5:0] br_snapshots_1_25;
reg [5:0] br_snapshots_1_26;
reg [5:0] br_snapshots_1_27;
reg [5:0] br_snapshots_1_28;
reg [5:0] br_snapshots_1_29;
reg [5:0] br_snapshots_1_30;
reg [5:0] br_snapshots_1_31;
reg [5:0] br_snapshots_2_0;
reg [5:0] br_snapshots_2_1;
reg [5:0] br_snapshots_2_2;
reg [5:0] br_snapshots_2_3;
reg [5:0] br_snapshots_2_4;
reg [5:0] br_snapshots_2_5;
reg [5:0] br_snapshots_2_6;
reg [5:0] br_snapshots_2_7;
reg [5:0] br_snapshots_2_8;
reg [5:0] br_snapshots_2_9;
reg [5:0] br_snapshots_2_10;
reg [5:0] br_snapshots_2_11;
reg [5:0] br_snapshots_2_12;
reg [5:0] br_snapshots_2_13;
reg [5:0] br_snapshots_2_14;
reg [5:0] br_snapshots_2_15;
reg [5:0] br_snapshots_2_16;
reg [5:0] br_snapshots_2_17;
reg [5:0] br_snapshots_2_18;
reg [5:0] br_snapshots_2_19;
reg [5:0] br_snapshots_2_20;
reg [5:0] br_snapshots_2_21;
reg [5:0] br_snapshots_2_22;
reg [5:0] br_snapshots_2_23;
reg [5:0] br_snapshots_2_24;
reg [5:0] br_snapshots_2_25;
reg [5:0] br_snapshots_2_26;
reg [5:0] br_snapshots_2_27;
reg [5:0] br_snapshots_2_28;
reg [5:0] br_snapshots_2_29;
reg [5:0] br_snapshots_2_30;
reg [5:0] br_snapshots_2_31;
reg [5:0] br_snapshots_3_0;
reg [5:0] br_snapshots_3_1;
reg [5:0] br_snapshots_3_2;
reg [5:0] br_snapshots_3_3;
reg [5:0] br_snapshots_3_4;
reg [5:0] br_snapshots_3_5;
reg [5:0] br_snapshots_3_6;
reg [5:0] br_snapshots_3_7;
reg [5:0] br_snapshots_3_8;
reg [5:0] br_snapshots_3_9;
reg [5:0] br_snapshots_3_10;
reg [5:0] br_snapshots_3_11;
reg [5:0] br_snapshots_3_12;
reg [5:0] br_snapshots_3_13;
reg [5:0] br_snapshots_3_14;
reg [5:0] br_snapshots_3_15;
reg [5:0] br_snapshots_3_16;
reg [5:0] br_snapshots_3_17;
reg [5:0] br_snapshots_3_18;
reg [5:0] br_snapshots_3_19;
reg [5:0] br_snapshots_3_20;
reg [5:0] br_snapshots_3_21;
reg [5:0] br_snapshots_3_22;
reg [5:0] br_snapshots_3_23;
reg [5:0] br_snapshots_3_24;
reg [5:0] br_snapshots_3_25;
reg [5:0] br_snapshots_3_26;
reg [5:0] br_snapshots_3_27;
reg [5:0] br_snapshots_3_28;
reg [5:0] br_snapshots_3_29;
reg [5:0] br_snapshots_3_30;
reg [5:0] br_snapshots_3_31;
reg [5:0] br_snapshots_4_0;
reg [5:0] br_snapshots_4_1;
reg [5:0] br_snapshots_4_2;
reg [5:0] br_snapshots_4_3;
reg [5:0] br_snapshots_4_4;
reg [5:0] br_snapshots_4_5;
reg [5:0] br_snapshots_4_6;
reg [5:0] br_snapshots_4_7;
reg [5:0] br_snapshots_4_8;
reg [5:0] br_snapshots_4_9;
reg [5:0] br_snapshots_4_10;
reg [5:0] br_snapshots_4_11;
reg [5:0] br_snapshots_4_12;
reg [5:0] br_snapshots_4_13;
reg [5:0] br_snapshots_4_14;
reg [5:0] br_snapshots_4_15;
reg [5:0] br_snapshots_4_16;
reg [5:0] br_snapshots_4_17;
reg [5:0] br_snapshots_4_18;
reg [5:0] br_snapshots_4_19;
reg [5:0] br_snapshots_4_20;
reg [5:0] br_snapshots_4_21;
reg [5:0] br_snapshots_4_22;
reg [5:0] br_snapshots_4_23;
reg [5:0] br_snapshots_4_24;
reg [5:0] br_snapshots_4_25;
reg [5:0] br_snapshots_4_26;
reg [5:0] br_snapshots_4_27;
reg [5:0] br_snapshots_4_28;
reg [5:0] br_snapshots_4_29;
reg [5:0] br_snapshots_4_30;
reg [5:0] br_snapshots_4_31;
reg [5:0] br_snapshots_5_0;
reg [5:0] br_snapshots_5_1;
reg [5:0] br_snapshots_5_2;
reg [5:0] br_snapshots_5_3;
reg [5:0] br_snapshots_5_4;
reg [5:0] br_snapshots_5_5;
reg [5:0] br_snapshots_5_6;
reg [5:0] br_snapshots_5_7;
reg [5:0] br_snapshots_5_8;
reg [5:0] br_snapshots_5_9;
reg [5:0] br_snapshots_5_10;
reg [5:0] br_snapshots_5_11;
reg [5:0] br_snapshots_5_12;
reg [5:0] br_snapshots_5_13;
reg [5:0] br_snapshots_5_14;
reg [5:0] br_snapshots_5_15;
reg [5:0] br_snapshots_5_16;
reg [5:0] br_snapshots_5_17;
reg [5:0] br_snapshots_5_18;
reg [5:0] br_snapshots_5_19;
reg [5:0] br_snapshots_5_20;
reg [5:0] br_snapshots_5_21;
reg [5:0] br_snapshots_5_22;
reg [5:0] br_snapshots_5_23;
reg [5:0] br_snapshots_5_24;
reg [5:0] br_snapshots_5_25;
reg [5:0] br_snapshots_5_26;
reg [5:0] br_snapshots_5_27;
reg [5:0] br_snapshots_5_28;
reg [5:0] br_snapshots_5_29;
reg [5:0] br_snapshots_5_30;
reg [5:0] br_snapshots_5_31;
reg [5:0] br_snapshots_6_0;
reg [5:0] br_snapshots_6_1;
reg [5:0] br_snapshots_6_2;
reg [5:0] br_snapshots_6_3;
reg [5:0] br_snapshots_6_4;
reg [5:0] br_snapshots_6_5;
reg [5:0] br_snapshots_6_6;
reg [5:0] br_snapshots_6_7;
reg [5:0] br_snapshots_6_8;
reg [5:0] br_snapshots_6_9;
reg [5:0] br_snapshots_6_10;
reg [5:0] br_snapshots_6_11;
reg [5:0] br_snapshots_6_12;
reg [5:0] br_snapshots_6_13;
reg [5:0] br_snapshots_6_14;
reg [5:0] br_snapshots_6_15;
reg [5:0] br_snapshots_6_16;
reg [5:0] br_snapshots_6_17;
reg [5:0] br_snapshots_6_18;
reg [5:0] br_snapshots_6_19;
reg [5:0] br_snapshots_6_20;
reg [5:0] br_snapshots_6_21;
reg [5:0] br_snapshots_6_22;
reg [5:0] br_snapshots_6_23;
reg [5:0] br_snapshots_6_24;
reg [5:0] br_snapshots_6_25;
reg [5:0] br_snapshots_6_26;
reg [5:0] br_snapshots_6_27;
reg [5:0] br_snapshots_6_28;
reg [5:0] br_snapshots_6_29;
reg [5:0] br_snapshots_6_30;
reg [5:0] br_snapshots_6_31;
reg [5:0] br_snapshots_7_0;
reg [5:0] br_snapshots_7_1;
reg [5:0] br_snapshots_7_2;
reg [5:0] br_snapshots_7_3;
reg [5:0] br_snapshots_7_4;
reg [5:0] br_snapshots_7_5;
reg [5:0] br_snapshots_7_6;
reg [5:0] br_snapshots_7_7;
reg [5:0] br_snapshots_7_8;
reg [5:0] br_snapshots_7_9;
reg [5:0] br_snapshots_7_10;
reg [5:0] br_snapshots_7_11;
reg [5:0] br_snapshots_7_12;
reg [5:0] br_snapshots_7_13;
reg [5:0] br_snapshots_7_14;
reg [5:0] br_snapshots_7_15;
reg [5:0] br_snapshots_7_16;
reg [5:0] br_snapshots_7_17;
reg [5:0] br_snapshots_7_18;
reg [5:0] br_snapshots_7_19;
reg [5:0] br_snapshots_7_20;
reg [5:0] br_snapshots_7_21;
reg [5:0] br_snapshots_7_22;
reg [5:0] br_snapshots_7_23;
reg [5:0] br_snapshots_7_24;
reg [5:0] br_snapshots_7_25;
reg [5:0] br_snapshots_7_26;
reg [5:0] br_snapshots_7_27;
reg [5:0] br_snapshots_7_28;
reg [5:0] br_snapshots_7_29;
reg [5:0] br_snapshots_7_30;
reg [5:0] br_snapshots_7_31;
wire [31:0][5:0] _GEN = {{map_table_31}, {map_table_30}, {map_table_29}, {map_table_28}, {map_table_27}, {map_table_26}, {map_table_25}, {map_table_24}, {map_table_23}, {map_table_22}, {map_table_21}, {map_table_20}, {map_table_19}, {map_table_18}, {map_table_17}, {map_table_16}, {map_table_15}, {map_table_14}, {map_table_13}, {map_table_12}, {map_table_11}, {map_table_10}, {map_table_9}, {map_table_8}, {map_table_7}, {map_table_6}, {map_table_5}, {map_table_4}, {map_table_3}, {map_table_2}, {map_table_1}, {map_table_0}};
wire [7:0][5:0] _GEN_0 = {{br_snapshots_7_0}, {br_snapshots_6_0}, {br_snapshots_5_0}, {br_snapshots_4_0}, {br_snapshots_3_0}, {br_snapshots_2_0}, {br_snapshots_1_0}, {br_snapshots_0_0}};
wire [7:0][5:0] _GEN_1 = {{br_snapshots_7_1}, {br_snapshots_6_1}, {br_snapshots_5_1}, {br_snapshots_4_1}, {br_snapshots_3_1}, {br_snapshots_2_1}, {br_snapshots_1_1}, {br_snapshots_0_1}};
wire [7:0][5:0] _GEN_2 = {{br_snapshots_7_2}, {br_snapshots_6_2}, {br_snapshots_5_2}, {br_snapshots_4_2}, {br_snapshots_3_2}, {br_snapshots_2_2}, {br_snapshots_1_2}, {br_snapshots_0_2}};
wire [7:0][5:0] _GEN_3 = {{br_snapshots_7_3}, {br_snapshots_6_3}, {br_snapshots_5_3}, {br_snapshots_4_3}, {br_snapshots_3_3}, {br_snapshots_2_3}, {br_snapshots_1_3}, {br_snapshots_0_3}};
wire [7:0][5:0] _GEN_4 = {{br_snapshots_7_4}, {br_snapshots_6_4}, {br_snapshots_5_4}, {br_snapshots_4_4}, {br_snapshots_3_4}, {br_snapshots_2_4}, {br_snapshots_1_4}, {br_snapshots_0_4}};
wire [7:0][5:0] _GEN_5 = {{br_snapshots_7_5}, {br_snapshots_6_5}, {br_snapshots_5_5}, {br_snapshots_4_5}, {br_snapshots_3_5}, {br_snapshots_2_5}, {br_snapshots_1_5}, {br_snapshots_0_5}};
wire [7:0][5:0] _GEN_6 = {{br_snapshots_7_6}, {br_snapshots_6_6}, {br_snapshots_5_6}, {br_snapshots_4_6}, {br_snapshots_3_6}, {br_snapshots_2_6}, {br_snapshots_1_6}, {br_snapshots_0_6}};
wire [7:0][5:0] _GEN_7 = {{br_snapshots_7_7}, {br_snapshots_6_7}, {br_snapshots_5_7}, {br_snapshots_4_7}, {br_snapshots_3_7}, {br_snapshots_2_7}, {br_snapshots_1_7}, {br_snapshots_0_7}};
wire [7:0][5:0] _GEN_8 = {{br_snapshots_7_8}, {br_snapshots_6_8}, {br_snapshots_5_8}, {br_snapshots_4_8}, {br_snapshots_3_8}, {br_snapshots_2_8}, {br_snapshots_1_8}, {br_snapshots_0_8}};
wire [7:0][5:0] _GEN_9 = {{br_snapshots_7_9}, {br_snapshots_6_9}, {br_snapshots_5_9}, {br_snapshots_4_9}, {br_snapshots_3_9}, {br_snapshots_2_9}, {br_snapshots_1_9}, {br_snapshots_0_9}};
wire [7:0][5:0] _GEN_10 = {{br_snapshots_7_10}, {br_snapshots_6_10}, {br_snapshots_5_10}, {br_snapshots_4_10}, {br_snapshots_3_10}, {br_snapshots_2_10}, {br_snapshots_1_10}, {br_snapshots_0_10}};
wire [7:0][5:0] _GEN_11 = {{br_snapshots_7_11}, {br_snapshots_6_11}, {br_snapshots_5_11}, {br_snapshots_4_11}, {br_snapshots_3_11}, {br_snapshots_2_11}, {br_snapshots_1_11}, {br_snapshots_0_11}};
wire [7:0][5:0] _GEN_12 = {{br_snapshots_7_12}, {br_snapshots_6_12}, {br_snapshots_5_12}, {br_snapshots_4_12}, {br_snapshots_3_12}, {br_snapshots_2_12}, {br_snapshots_1_12}, {br_snapshots_0_12}};
wire [7:0][5:0] _GEN_13 = {{br_snapshots_7_13}, {br_snapshots_6_13}, {br_snapshots_5_13}, {br_snapshots_4_13}, {br_snapshots_3_13}, {br_snapshots_2_13}, {br_snapshots_1_13}, {br_snapshots_0_13}};
wire [7:0][5:0] _GEN_14 = {{br_snapshots_7_14}, {br_snapshots_6_14}, {br_snapshots_5_14}, {br_snapshots_4_14}, {br_snapshots_3_14}, {br_snapshots_2_14}, {br_snapshots_1_14}, {br_snapshots_0_14}};
wire [7:0][5:0] _GEN_15 = {{br_snapshots_7_15}, {br_snapshots_6_15}, {br_snapshots_5_15}, {br_snapshots_4_15}, {br_snapshots_3_15}, {br_snapshots_2_15}, {br_snapshots_1_15}, {br_snapshots_0_15}};
wire [7:0][5:0] _GEN_16 = {{br_snapshots_7_16}, {br_snapshots_6_16}, {br_snapshots_5_16}, {br_snapshots_4_16}, {br_snapshots_3_16}, {br_snapshots_2_16}, {br_snapshots_1_16}, {br_snapshots_0_16}};
wire [7:0][5:0] _GEN_17 = {{br_snapshots_7_17}, {br_snapshots_6_17}, {br_snapshots_5_17}, {br_snapshots_4_17}, {br_snapshots_3_17}, {br_snapshots_2_17}, {br_snapshots_1_17}, {br_snapshots_0_17}};
wire [7:0][5:0] _GEN_18 = {{br_snapshots_7_18}, {br_snapshots_6_18}, {br_snapshots_5_18}, {br_snapshots_4_18}, {br_snapshots_3_18}, {br_snapshots_2_18}, {br_snapshots_1_18}, {br_snapshots_0_18}};
wire [7:0][5:0] _GEN_19 = {{br_snapshots_7_19}, {br_snapshots_6_19}, {br_snapshots_5_19}, {br_snapshots_4_19}, {br_snapshots_3_19}, {br_snapshots_2_19}, {br_snapshots_1_19}, {br_snapshots_0_19}};
wire [7:0][5:0] _GEN_20 = {{br_snapshots_7_20}, {br_snapshots_6_20}, {br_snapshots_5_20}, {br_snapshots_4_20}, {br_snapshots_3_20}, {br_snapshots_2_20}, {br_snapshots_1_20}, {br_snapshots_0_20}};
wire [7:0][5:0] _GEN_21 = {{br_snapshots_7_21}, {br_snapshots_6_21}, {br_snapshots_5_21}, {br_snapshots_4_21}, {br_snapshots_3_21}, {br_snapshots_2_21}, {br_snapshots_1_21}, {br_snapshots_0_21}};
wire [7:0][5:0] _GEN_22 = {{br_snapshots_7_22}, {br_snapshots_6_22}, {br_snapshots_5_22}, {br_snapshots_4_22}, {br_snapshots_3_22}, {br_snapshots_2_22}, {br_snapshots_1_22}, {br_snapshots_0_22}};
wire [7:0][5:0] _GEN_23 = {{br_snapshots_7_23}, {br_snapshots_6_23}, {br_snapshots_5_23}, {br_snapshots_4_23}, {br_snapshots_3_23}, {br_snapshots_2_23}, {br_snapshots_1_23}, {br_snapshots_0_23}};
wire [7:0][5:0] _GEN_24 = {{br_snapshots_7_24}, {br_snapshots_6_24}, {br_snapshots_5_24}, {br_snapshots_4_24}, {br_snapshots_3_24}, {br_snapshots_2_24}, {br_snapshots_1_24}, {br_snapshots_0_24}};
wire [7:0][5:0] _GEN_25 = {{br_snapshots_7_25}, {br_snapshots_6_25}, {br_snapshots_5_25}, {br_snapshots_4_25}, {br_snapshots_3_25}, {br_snapshots_2_25}, {br_snapshots_1_25}, {br_snapshots_0_25}};
wire [7:0][5:0] _GEN_26 = {{br_snapshots_7_26}, {br_snapshots_6_26}, {br_snapshots_5_26}, {br_snapshots_4_26}, {br_snapshots_3_26}, {br_snapshots_2_26}, {br_snapshots_1_26}, {br_snapshots_0_26}};
wire [7:0][5:0] _GEN_27 = {{br_snapshots_7_27}, {br_snapshots_6_27}, {br_snapshots_5_27}, {br_snapshots_4_27}, {br_snapshots_3_27}, {br_snapshots_2_27}, {br_snapshots_1_27}, {br_snapshots_0_27}};
wire [7:0][5:0] _GEN_28 = {{br_snapshots_7_28}, {br_snapshots_6_28}, {br_snapshots_5_28}, {br_snapshots_4_28}, {br_snapshots_3_28}, {br_snapshots_2_28}, {br_snapshots_1_28}, {br_snapshots_0_28}};
wire [7:0][5:0] _GEN_29 = {{br_snapshots_7_29}, {br_snapshots_6_29}, {br_snapshots_5_29}, {br_snapshots_4_29}, {br_snapshots_3_29}, {br_snapshots_2_29}, {br_snapshots_1_29}, {br_snapshots_0_29}};
wire [7:0][5:0] _GEN_30 = {{br_snapshots_7_30}, {br_snapshots_6_30}, {br_snapshots_5_30}, {br_snapshots_4_30}, {br_snapshots_3_30}, {br_snapshots_2_30}, {br_snapshots_1_30}, {br_snapshots_0_30}};
wire [7:0][5:0] _GEN_31 = {{br_snapshots_7_31}, {br_snapshots_6_31}, {br_snapshots_5_31}, {br_snapshots_4_31}, {br_snapshots_3_31}, {br_snapshots_2_31}, {br_snapshots_1_31}, {br_snapshots_0_31}};
wire [63:0] _remap_ldsts_oh_T = 64'h1 << io_remap_reqs_0_ldst;
wire [31:0] _GEN_32 = _remap_ldsts_oh_T[31:0] & {32{io_remap_reqs_0_valid}};
wire [5:0] remapped_row_1 = _GEN_32[0] ? io_remap_reqs_0_pdst : map_table_0;
wire [5:0] remap_table_1_1 = _GEN_32[1] ? io_remap_reqs_0_pdst : map_table_1;
wire [5:0] remap_table_1_2 = _GEN_32[2] ? io_remap_reqs_0_pdst : map_table_2;
wire [5:0] remap_table_1_3 = _GEN_32[3] ? io_remap_reqs_0_pdst : map_table_3;
wire [5:0] remap_table_1_4 = _GEN_32[4] ? io_remap_reqs_0_pdst : map_table_4;
wire [5:0] remap_table_1_5 = _GEN_32[5] ? io_remap_reqs_0_pdst : map_table_5;
wire [5:0] remap_table_1_6 = _GEN_32[6] ? io_remap_reqs_0_pdst : map_table_6;
wire [5:0] remap_table_1_7 = _GEN_32[7] ? io_remap_reqs_0_pdst : map_table_7;
wire [5:0] remap_table_1_8 = _GEN_32[8] ? io_remap_reqs_0_pdst : map_table_8;
wire [5:0] remap_table_1_9 = _GEN_32[9] ? io_remap_reqs_0_pdst : map_table_9;
wire [5:0] remap_table_1_10 = _GEN_32[10] ? io_remap_reqs_0_pdst : map_table_10;
wire [5:0] remap_table_1_11 = _GEN_32[11] ? io_remap_reqs_0_pdst : map_table_11;
wire [5:0] remap_table_1_12 = _GEN_32[12] ? io_remap_reqs_0_pdst : map_table_12;
wire [5:0] remap_table_1_13 = _GEN_32[13] ? io_remap_reqs_0_pdst : map_table_13;
wire [5:0] remap_table_1_14 = _GEN_32[14] ? io_remap_reqs_0_pdst : map_table_14;
wire [5:0] remap_table_1_15 = _GEN_32[15] ? io_remap_reqs_0_pdst : map_table_15;
wire [5:0] remap_table_1_16 = _GEN_32[16] ? io_remap_reqs_0_pdst : map_table_16;
wire [5:0] remap_table_1_17 = _GEN_32[17] ? io_remap_reqs_0_pdst : map_table_17;
wire [5:0] remap_table_1_18 = _GEN_32[18] ? io_remap_reqs_0_pdst : map_table_18;
wire [5:0] remap_table_1_19 = _GEN_32[19] ? io_remap_reqs_0_pdst : map_table_19;
wire [5:0] remap_table_1_20 = _GEN_32[20] ? io_remap_reqs_0_pdst : map_table_20;
wire [5:0] remap_table_1_21 = _GEN_32[21] ? io_remap_reqs_0_pdst : map_table_21;
wire [5:0] remap_table_1_22 = _GEN_32[22] ? io_remap_reqs_0_pdst : map_table_22;
wire [5:0] remap_table_1_23 = _GEN_32[23] ? io_remap_reqs_0_pdst : map_table_23;
wire [5:0] remap_table_1_24 = _GEN_32[24] ? io_remap_reqs_0_pdst : map_table_24;
wire [5:0] remap_table_1_25 = _GEN_32[25] ? io_remap_reqs_0_pdst : map_table_25;
wire [5:0] remap_table_1_26 = _GEN_32[26] ? io_remap_reqs_0_pdst : map_table_26;
wire [5:0] remap_table_1_27 = _GEN_32[27] ? io_remap_reqs_0_pdst : map_table_27;
wire [5:0] remap_table_1_28 = _GEN_32[28] ? io_remap_reqs_0_pdst : map_table_28;
wire [5:0] remap_table_1_29 = _GEN_32[29] ? io_remap_reqs_0_pdst : map_table_29;
wire [5:0] remap_table_1_30 = _GEN_32[30] ? io_remap_reqs_0_pdst : map_table_30;
wire [5:0] remap_table_1_31 = _GEN_32[31] ? io_remap_reqs_0_pdst : map_table_31;
always @(posedge clock) begin
if (reset) begin
map_table_0 <= 6'h0;
map_table_1 <= 6'h0;
map_table_2 <= 6'h0;
map_table_3 <= 6'h0;
map_table_4 <= 6'h0;
map_table_5 <= 6'h0;
map_table_6 <= 6'h0;
map_table_7 <= 6'h0;
map_table_8 <= 6'h0;
map_table_9 <= 6'h0;
map_table_10 <= 6'h0;
map_table_11 <= 6'h0;
map_table_12 <= 6'h0;
map_table_13 <= 6'h0;
map_table_14 <= 6'h0;
map_table_15 <= 6'h0;
map_table_16 <= 6'h0;
map_table_17 <= 6'h0;
map_table_18 <= 6'h0;
map_table_19 <= 6'h0;
map_table_20 <= 6'h0;
map_table_21 <= 6'h0;
map_table_22 <= 6'h0;
map_table_23 <= 6'h0;
map_table_24 <= 6'h0;
map_table_25 <= 6'h0;
map_table_26 <= 6'h0;
map_table_27 <= 6'h0;
map_table_28 <= 6'h0;
map_table_29 <= 6'h0;
map_table_30 <= 6'h0;
map_table_31 <= 6'h0;
end
else if (io_brupdate_b2_mispredict) begin
map_table_0 <= _GEN_0[io_brupdate_b2_uop_br_tag];
map_table_1 <= _GEN_1[io_brupdate_b2_uop_br_tag];
map_table_2 <= _GEN_2[io_brupdate_b2_uop_br_tag];
map_table_3 <= _GEN_3[io_brupdate_b2_uop_br_tag];
map_table_4 <= _GEN_4[io_brupdate_b2_uop_br_tag];
map_table_5 <= _GEN_5[io_brupdate_b2_uop_br_tag];
map_table_6 <= _GEN_6[io_brupdate_b2_uop_br_tag];
map_table_7 <= _GEN_7[io_brupdate_b2_uop_br_tag];
map_table_8 <= _GEN_8[io_brupdate_b2_uop_br_tag];
map_table_9 <= _GEN_9[io_brupdate_b2_uop_br_tag];
map_table_10 <= _GEN_10[io_brupdate_b2_uop_br_tag];
map_table_11 <= _GEN_11[io_brupdate_b2_uop_br_tag];
map_table_12 <= _GEN_12[io_brupdate_b2_uop_br_tag];
map_table_13 <= _GEN_13[io_brupdate_b2_uop_br_tag];
map_table_14 <= _GEN_14[io_brupdate_b2_uop_br_tag];
map_table_15 <= _GEN_15[io_brupdate_b2_uop_br_tag];
map_table_16 <= _GEN_16[io_brupdate_b2_uop_br_tag];
map_table_17 <= _GEN_17[io_brupdate_b2_uop_br_tag];
map_table_18 <= _GEN_18[io_brupdate_b2_uop_br_tag];
map_table_19 <= _GEN_19[io_brupdate_b2_uop_br_tag];
map_table_20 <= _GEN_20[io_brupdate_b2_uop_br_tag];
map_table_21 <= _GEN_21[io_brupdate_b2_uop_br_tag];
map_table_22 <= _GEN_22[io_brupdate_b2_uop_br_tag];
map_table_23 <= _GEN_23[io_brupdate_b2_uop_br_tag];
map_table_24 <= _GEN_24[io_brupdate_b2_uop_br_tag];
map_table_25 <= _GEN_25[io_brupdate_b2_uop_br_tag];
map_table_26 <= _GEN_26[io_brupdate_b2_uop_br_tag];
map_table_27 <= _GEN_27[io_brupdate_b2_uop_br_tag];
map_table_28 <= _GEN_28[io_brupdate_b2_uop_br_tag];
map_table_29 <= _GEN_29[io_brupdate_b2_uop_br_tag];
map_table_30 <= _GEN_30[io_brupdate_b2_uop_br_tag];
map_table_31 <= _GEN_31[io_brupdate_b2_uop_br_tag];
end
else begin
if (_GEN_32[0])
map_table_0 <= io_remap_reqs_0_pdst;
if (_GEN_32[1])
map_table_1 <= io_remap_reqs_0_pdst;
if (_GEN_32[2])
map_table_2 <= io_remap_reqs_0_pdst;
if (_GEN_32[3])
map_table_3 <= io_remap_reqs_0_pdst;
if (_GEN_32[4])
map_table_4 <= io_remap_reqs_0_pdst;
if (_GEN_32[5])
map_table_5 <= io_remap_reqs_0_pdst;
if (_GEN_32[6])
map_table_6 <= io_remap_reqs_0_pdst;
if (_GEN_32[7])
map_table_7 <= io_remap_reqs_0_pdst;
if (_GEN_32[8])
map_table_8 <= io_remap_reqs_0_pdst;
if (_GEN_32[9])
map_table_9 <= io_remap_reqs_0_pdst;
if (_GEN_32[10])
map_table_10 <= io_remap_reqs_0_pdst;
if (_GEN_32[11])
map_table_11 <= io_remap_reqs_0_pdst;
if (_GEN_32[12])
map_table_12 <= io_remap_reqs_0_pdst;
if (_GEN_32[13])
map_table_13 <= io_remap_reqs_0_pdst;
if (_GEN_32[14])
map_table_14 <= io_remap_reqs_0_pdst;
if (_GEN_32[15])
map_table_15 <= io_remap_reqs_0_pdst;
if (_GEN_32[16])
map_table_16 <= io_remap_reqs_0_pdst;
if (_GEN_32[17])
map_table_17 <= io_remap_reqs_0_pdst;
if (_GEN_32[18])
map_table_18 <= io_remap_reqs_0_pdst;
if (_GEN_32[19])
map_table_19 <= io_remap_reqs_0_pdst;
if (_GEN_32[20])
map_table_20 <= io_remap_reqs_0_pdst;
if (_GEN_32[21])
map_table_21 <= io_remap_reqs_0_pdst;
if (_GEN_32[22])
map_table_22 <= io_remap_reqs_0_pdst;
if (_GEN_32[23])
map_table_23 <= io_remap_reqs_0_pdst;
if (_GEN_32[24])
map_table_24 <= io_remap_reqs_0_pdst;
if (_GEN_32[25])
map_table_25 <= io_remap_reqs_0_pdst;
if (_GEN_32[26])
map_table_26 <= io_remap_reqs_0_pdst;
if (_GEN_32[27])
map_table_27 <= io_remap_reqs_0_pdst;
if (_GEN_32[28])
map_table_28 <= io_remap_reqs_0_pdst;
if (_GEN_32[29])
map_table_29 <= io_remap_reqs_0_pdst;
if (_GEN_32[30])
map_table_30 <= io_remap_reqs_0_pdst;
if (_GEN_32[31])
map_table_31 <= io_remap_reqs_0_pdst;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h0) begin
br_snapshots_0_0 <= remapped_row_1;
br_snapshots_0_1 <= remap_table_1_1;
br_snapshots_0_2 <= remap_table_1_2;
br_snapshots_0_3 <= remap_table_1_3;
br_snapshots_0_4 <= remap_table_1_4;
br_snapshots_0_5 <= remap_table_1_5;
br_snapshots_0_6 <= remap_table_1_6;
br_snapshots_0_7 <= remap_table_1_7;
br_snapshots_0_8 <= remap_table_1_8;
br_snapshots_0_9 <= remap_table_1_9;
br_snapshots_0_10 <= remap_table_1_10;
br_snapshots_0_11 <= remap_table_1_11;
br_snapshots_0_12 <= remap_table_1_12;
br_snapshots_0_13 <= remap_table_1_13;
br_snapshots_0_14 <= remap_table_1_14;
br_snapshots_0_15 <= remap_table_1_15;
br_snapshots_0_16 <= remap_table_1_16;
br_snapshots_0_17 <= remap_table_1_17;
br_snapshots_0_18 <= remap_table_1_18;
br_snapshots_0_19 <= remap_table_1_19;
br_snapshots_0_20 <= remap_table_1_20;
br_snapshots_0_21 <= remap_table_1_21;
br_snapshots_0_22 <= remap_table_1_22;
br_snapshots_0_23 <= remap_table_1_23;
br_snapshots_0_24 <= remap_table_1_24;
br_snapshots_0_25 <= remap_table_1_25;
br_snapshots_0_26 <= remap_table_1_26;
br_snapshots_0_27 <= remap_table_1_27;
br_snapshots_0_28 <= remap_table_1_28;
br_snapshots_0_29 <= remap_table_1_29;
br_snapshots_0_30 <= remap_table_1_30;
br_snapshots_0_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h1) begin
br_snapshots_1_0 <= remapped_row_1;
br_snapshots_1_1 <= remap_table_1_1;
br_snapshots_1_2 <= remap_table_1_2;
br_snapshots_1_3 <= remap_table_1_3;
br_snapshots_1_4 <= remap_table_1_4;
br_snapshots_1_5 <= remap_table_1_5;
br_snapshots_1_6 <= remap_table_1_6;
br_snapshots_1_7 <= remap_table_1_7;
br_snapshots_1_8 <= remap_table_1_8;
br_snapshots_1_9 <= remap_table_1_9;
br_snapshots_1_10 <= remap_table_1_10;
br_snapshots_1_11 <= remap_table_1_11;
br_snapshots_1_12 <= remap_table_1_12;
br_snapshots_1_13 <= remap_table_1_13;
br_snapshots_1_14 <= remap_table_1_14;
br_snapshots_1_15 <= remap_table_1_15;
br_snapshots_1_16 <= remap_table_1_16;
br_snapshots_1_17 <= remap_table_1_17;
br_snapshots_1_18 <= remap_table_1_18;
br_snapshots_1_19 <= remap_table_1_19;
br_snapshots_1_20 <= remap_table_1_20;
br_snapshots_1_21 <= remap_table_1_21;
br_snapshots_1_22 <= remap_table_1_22;
br_snapshots_1_23 <= remap_table_1_23;
br_snapshots_1_24 <= remap_table_1_24;
br_snapshots_1_25 <= remap_table_1_25;
br_snapshots_1_26 <= remap_table_1_26;
br_snapshots_1_27 <= remap_table_1_27;
br_snapshots_1_28 <= remap_table_1_28;
br_snapshots_1_29 <= remap_table_1_29;
br_snapshots_1_30 <= remap_table_1_30;
br_snapshots_1_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h2) begin
br_snapshots_2_0 <= remapped_row_1;
br_snapshots_2_1 <= remap_table_1_1;
br_snapshots_2_2 <= remap_table_1_2;
br_snapshots_2_3 <= remap_table_1_3;
br_snapshots_2_4 <= remap_table_1_4;
br_snapshots_2_5 <= remap_table_1_5;
br_snapshots_2_6 <= remap_table_1_6;
br_snapshots_2_7 <= remap_table_1_7;
br_snapshots_2_8 <= remap_table_1_8;
br_snapshots_2_9 <= remap_table_1_9;
br_snapshots_2_10 <= remap_table_1_10;
br_snapshots_2_11 <= remap_table_1_11;
br_snapshots_2_12 <= remap_table_1_12;
br_snapshots_2_13 <= remap_table_1_13;
br_snapshots_2_14 <= remap_table_1_14;
br_snapshots_2_15 <= remap_table_1_15;
br_snapshots_2_16 <= remap_table_1_16;
br_snapshots_2_17 <= remap_table_1_17;
br_snapshots_2_18 <= remap_table_1_18;
br_snapshots_2_19 <= remap_table_1_19;
br_snapshots_2_20 <= remap_table_1_20;
br_snapshots_2_21 <= remap_table_1_21;
br_snapshots_2_22 <= remap_table_1_22;
br_snapshots_2_23 <= remap_table_1_23;
br_snapshots_2_24 <= remap_table_1_24;
br_snapshots_2_25 <= remap_table_1_25;
br_snapshots_2_26 <= remap_table_1_26;
br_snapshots_2_27 <= remap_table_1_27;
br_snapshots_2_28 <= remap_table_1_28;
br_snapshots_2_29 <= remap_table_1_29;
br_snapshots_2_30 <= remap_table_1_30;
br_snapshots_2_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h3) begin
br_snapshots_3_0 <= remapped_row_1;
br_snapshots_3_1 <= remap_table_1_1;
br_snapshots_3_2 <= remap_table_1_2;
br_snapshots_3_3 <= remap_table_1_3;
br_snapshots_3_4 <= remap_table_1_4;
br_snapshots_3_5 <= remap_table_1_5;
br_snapshots_3_6 <= remap_table_1_6;
br_snapshots_3_7 <= remap_table_1_7;
br_snapshots_3_8 <= remap_table_1_8;
br_snapshots_3_9 <= remap_table_1_9;
br_snapshots_3_10 <= remap_table_1_10;
br_snapshots_3_11 <= remap_table_1_11;
br_snapshots_3_12 <= remap_table_1_12;
br_snapshots_3_13 <= remap_table_1_13;
br_snapshots_3_14 <= remap_table_1_14;
br_snapshots_3_15 <= remap_table_1_15;
br_snapshots_3_16 <= remap_table_1_16;
br_snapshots_3_17 <= remap_table_1_17;
br_snapshots_3_18 <= remap_table_1_18;
br_snapshots_3_19 <= remap_table_1_19;
br_snapshots_3_20 <= remap_table_1_20;
br_snapshots_3_21 <= remap_table_1_21;
br_snapshots_3_22 <= remap_table_1_22;
br_snapshots_3_23 <= remap_table_1_23;
br_snapshots_3_24 <= remap_table_1_24;
br_snapshots_3_25 <= remap_table_1_25;
br_snapshots_3_26 <= remap_table_1_26;
br_snapshots_3_27 <= remap_table_1_27;
br_snapshots_3_28 <= remap_table_1_28;
br_snapshots_3_29 <= remap_table_1_29;
br_snapshots_3_30 <= remap_table_1_30;
br_snapshots_3_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h4) begin
br_snapshots_4_0 <= remapped_row_1;
br_snapshots_4_1 <= remap_table_1_1;
br_snapshots_4_2 <= remap_table_1_2;
br_snapshots_4_3 <= remap_table_1_3;
br_snapshots_4_4 <= remap_table_1_4;
br_snapshots_4_5 <= remap_table_1_5;
br_snapshots_4_6 <= remap_table_1_6;
br_snapshots_4_7 <= remap_table_1_7;
br_snapshots_4_8 <= remap_table_1_8;
br_snapshots_4_9 <= remap_table_1_9;
br_snapshots_4_10 <= remap_table_1_10;
br_snapshots_4_11 <= remap_table_1_11;
br_snapshots_4_12 <= remap_table_1_12;
br_snapshots_4_13 <= remap_table_1_13;
br_snapshots_4_14 <= remap_table_1_14;
br_snapshots_4_15 <= remap_table_1_15;
br_snapshots_4_16 <= remap_table_1_16;
br_snapshots_4_17 <= remap_table_1_17;
br_snapshots_4_18 <= remap_table_1_18;
br_snapshots_4_19 <= remap_table_1_19;
br_snapshots_4_20 <= remap_table_1_20;
br_snapshots_4_21 <= remap_table_1_21;
br_snapshots_4_22 <= remap_table_1_22;
br_snapshots_4_23 <= remap_table_1_23;
br_snapshots_4_24 <= remap_table_1_24;
br_snapshots_4_25 <= remap_table_1_25;
br_snapshots_4_26 <= remap_table_1_26;
br_snapshots_4_27 <= remap_table_1_27;
br_snapshots_4_28 <= remap_table_1_28;
br_snapshots_4_29 <= remap_table_1_29;
br_snapshots_4_30 <= remap_table_1_30;
br_snapshots_4_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h5) begin
br_snapshots_5_0 <= remapped_row_1;
br_snapshots_5_1 <= remap_table_1_1;
br_snapshots_5_2 <= remap_table_1_2;
br_snapshots_5_3 <= remap_table_1_3;
br_snapshots_5_4 <= remap_table_1_4;
br_snapshots_5_5 <= remap_table_1_5;
br_snapshots_5_6 <= remap_table_1_6;
br_snapshots_5_7 <= remap_table_1_7;
br_snapshots_5_8 <= remap_table_1_8;
br_snapshots_5_9 <= remap_table_1_9;
br_snapshots_5_10 <= remap_table_1_10;
br_snapshots_5_11 <= remap_table_1_11;
br_snapshots_5_12 <= remap_table_1_12;
br_snapshots_5_13 <= remap_table_1_13;
br_snapshots_5_14 <= remap_table_1_14;
br_snapshots_5_15 <= remap_table_1_15;
br_snapshots_5_16 <= remap_table_1_16;
br_snapshots_5_17 <= remap_table_1_17;
br_snapshots_5_18 <= remap_table_1_18;
br_snapshots_5_19 <= remap_table_1_19;
br_snapshots_5_20 <= remap_table_1_20;
br_snapshots_5_21 <= remap_table_1_21;
br_snapshots_5_22 <= remap_table_1_22;
br_snapshots_5_23 <= remap_table_1_23;
br_snapshots_5_24 <= remap_table_1_24;
br_snapshots_5_25 <= remap_table_1_25;
br_snapshots_5_26 <= remap_table_1_26;
br_snapshots_5_27 <= remap_table_1_27;
br_snapshots_5_28 <= remap_table_1_28;
br_snapshots_5_29 <= remap_table_1_29;
br_snapshots_5_30 <= remap_table_1_30;
br_snapshots_5_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h6) begin
br_snapshots_6_0 <= remapped_row_1;
br_snapshots_6_1 <= remap_table_1_1;
br_snapshots_6_2 <= remap_table_1_2;
br_snapshots_6_3 <= remap_table_1_3;
br_snapshots_6_4 <= remap_table_1_4;
br_snapshots_6_5 <= remap_table_1_5;
br_snapshots_6_6 <= remap_table_1_6;
br_snapshots_6_7 <= remap_table_1_7;
br_snapshots_6_8 <= remap_table_1_8;
br_snapshots_6_9 <= remap_table_1_9;
br_snapshots_6_10 <= remap_table_1_10;
br_snapshots_6_11 <= remap_table_1_11;
br_snapshots_6_12 <= remap_table_1_12;
br_snapshots_6_13 <= remap_table_1_13;
br_snapshots_6_14 <= remap_table_1_14;
br_snapshots_6_15 <= remap_table_1_15;
br_snapshots_6_16 <= remap_table_1_16;
br_snapshots_6_17 <= remap_table_1_17;
br_snapshots_6_18 <= remap_table_1_18;
br_snapshots_6_19 <= remap_table_1_19;
br_snapshots_6_20 <= remap_table_1_20;
br_snapshots_6_21 <= remap_table_1_21;
br_snapshots_6_22 <= remap_table_1_22;
br_snapshots_6_23 <= remap_table_1_23;
br_snapshots_6_24 <= remap_table_1_24;
br_snapshots_6_25 <= remap_table_1_25;
br_snapshots_6_26 <= remap_table_1_26;
br_snapshots_6_27 <= remap_table_1_27;
br_snapshots_6_28 <= remap_table_1_28;
br_snapshots_6_29 <= remap_table_1_29;
br_snapshots_6_30 <= remap_table_1_30;
br_snapshots_6_31 <= remap_table_1_31;
end
if (io_ren_br_tags_0_valid & (&io_ren_br_tags_0_bits)) begin
br_snapshots_7_0 <= remapped_row_1;
br_snapshots_7_1 <= remap_table_1_1;
br_snapshots_7_2 <= remap_table_1_2;
br_snapshots_7_3 <= remap_table_1_3;
br_snapshots_7_4 <= remap_table_1_4;
br_snapshots_7_5 <= remap_table_1_5;
br_snapshots_7_6 <= remap_table_1_6;
br_snapshots_7_7 <= remap_table_1_7;
br_snapshots_7_8 <= remap_table_1_8;
br_snapshots_7_9 <= remap_table_1_9;
br_snapshots_7_10 <= remap_table_1_10;
br_snapshots_7_11 <= remap_table_1_11;
br_snapshots_7_12 <= remap_table_1_12;
br_snapshots_7_13 <= remap_table_1_13;
br_snapshots_7_14 <= remap_table_1_14;
br_snapshots_7_15 <= remap_table_1_15;
br_snapshots_7_16 <= remap_table_1_16;
br_snapshots_7_17 <= remap_table_1_17;
br_snapshots_7_18 <= remap_table_1_18;
br_snapshots_7_19 <= remap_table_1_19;
br_snapshots_7_20 <= remap_table_1_20;
br_snapshots_7_21 <= remap_table_1_21;
br_snapshots_7_22 <= remap_table_1_22;
br_snapshots_7_23 <= remap_table_1_23;
br_snapshots_7_24 <= remap_table_1_24;
br_snapshots_7_25 <= remap_table_1_25;
br_snapshots_7_26 <= remap_table_1_26;
br_snapshots_7_27 <= remap_table_1_27;
br_snapshots_7_28 <= remap_table_1_28;
br_snapshots_7_29 <= remap_table_1_29;
br_snapshots_7_30 <= remap_table_1_30;
br_snapshots_7_31 <= remap_table_1_31;
end
end
assign io_map_resps_0_prs1 = _GEN[io_map_reqs_0_lrs1[4:0]];
assign io_map_resps_0_prs2 = _GEN[io_map_reqs_0_lrs2[4:0]];
assign io_map_resps_0_prs3 = _GEN[io_map_reqs_0_lrs3[4:0]];
assign io_map_resps_0_stale_pdst = _GEN[io_map_reqs_0_ldst[4:0]];
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
} | module AsyncResetRegVec_w2_i0(
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
reg [1:0] reg_0;
always @(posedge clock or posedge reset) begin
if (reset)
reg_0 <= 2'h0;
else
reg_0 <= io_d;
end
assign io_q = reg_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module cc_banks_1(
input [13:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import scala.collection.SortedMap
import chisel3._
import org.chipsalliance.cde.config.Parameters
/** JTAG signals, viewed from the master side
*/
class JTAGIO(hasTRSTn: Boolean = false) extends Bundle {
val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None
val TCK = Output(Clock())
val TMS = Output(Bool())
val TDI = Output(Bool())
val TDO = Input(new Tristate())
}
/** JTAG block output signals.
*/
class JtagOutput(irLength: Int) extends Bundle {
val state = Output(JtagState.State.chiselType()) // state, transitions on TCK rising edge
val instruction = Output(UInt(irLength.W)) // current active instruction
val tapIsInTestLogicReset = Output(Bool()) // synchronously asserted in Test-Logic-Reset state, should NOT hold the FSM in reset
}
class JtagControl extends Bundle {
val jtag_reset = Input(AsyncReset())
}
/** Aggregate JTAG block IO.
*/
class JtagBlockIO(irLength: Int, hasIdcode:Boolean = true) extends Bundle {
val jtag = Flipped(new JTAGIO())
val control = new JtagControl
val output = new JtagOutput(irLength)
val idcode = if (hasIdcode) Some(Input(new JTAGIdcodeBundle())) else None
}
/** Internal controller block IO with data shift outputs.
*/
class JtagControllerIO(irLength: Int) extends JtagBlockIO(irLength, false) {
val dataChainOut = Output(new ShifterIO)
val dataChainIn = Input(new ShifterIO)
}
/** JTAG TAP controller internal block, responsible for instruction decode and data register chain
* control signal generation.
*
* Misc notes:
* - Figure 6-3 and 6-4 provides examples with timing behavior
*/
class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val p: Parameters) extends Module {
require(irLength >= 2) // 7.1.1a
val io = IO(new JtagControllerIO(irLength))
val tdo = Wire(Bool()) // 4.4.1c TDI should appear here uninverted after shifting
val tdo_driven = Wire(Bool())
val clock_falling = WireInit((!clock.asUInt).asClock)
val tapIsInTestLogicReset = Wire(Bool())
//
// JTAG state machine
//
val currState = Wire(JtagState.State.chiselType())
// At this point, the TRSTn should already have been
// combined with any POR, and it should also be
// synchronized to TCK.
require(!io.jtag.TRSTn.isDefined, "TRSTn should be absorbed into jtckPOReset outside of JtagTapController.")
withReset(io.control.jtag_reset) {
val stateMachine = Module(new JtagStateMachine)
stateMachine.suggestName("stateMachine")
stateMachine.io.tms := io.jtag.TMS
currState := stateMachine.io.currState
io.output.state := stateMachine.io.currState
// 4.5.1a TDO changes on falling edge of TCK, 6.1.2.1d driver active on first TCK falling edge in ShiftIR and ShiftDR states
withClock(clock_falling) {
val TDOdata = RegNext(next=tdo, init=false.B).suggestName("tdoReg")
val TDOdriven = RegNext(next=tdo_driven, init=false.B).suggestName("tdoeReg")
io.jtag.TDO.data := TDOdata
io.jtag.TDO.driven := TDOdriven
}
}
//
// Instruction Register
//
// 7.1.1d IR shifter two LSBs must be b01 pattern
// TODO: 7.1.1d allow design-specific IR bits, 7.1.1e (rec) should be a fixed pattern
// 7.2.1a behavior of instruction register and shifters
val irChain = Module(CaptureUpdateChain(UInt(irLength.W)))
irChain.suggestName("irChain")
irChain.io.chainIn.shift := currState === JtagState.ShiftIR.U
irChain.io.chainIn.data := io.jtag.TDI
irChain.io.chainIn.capture := currState === JtagState.CaptureIR.U
irChain.io.chainIn.update := currState === JtagState.UpdateIR.U
irChain.io.capture.bits := "b01".U
withClockAndReset(clock_falling, io.control.jtag_reset) {
val activeInstruction = RegInit(initialInstruction.U(irLength.W))
when (tapIsInTestLogicReset) {
activeInstruction := initialInstruction.U
}.elsewhen (currState === JtagState.UpdateIR.U) {
activeInstruction := irChain.io.update.bits
}
io.output.instruction := activeInstruction
}
tapIsInTestLogicReset := currState === JtagState.TestLogicReset.U
io.output.tapIsInTestLogicReset := tapIsInTestLogicReset
//
// Data Register
//
io.dataChainOut.shift := currState === JtagState.ShiftDR.U
io.dataChainOut.data := io.jtag.TDI
io.dataChainOut.capture := currState === JtagState.CaptureDR.U
io.dataChainOut.update := currState === JtagState.UpdateDR.U
//
// Output Control
//
when (currState === JtagState.ShiftDR.U) {
tdo := io.dataChainIn.data
tdo_driven := true.B
} .elsewhen (currState === JtagState.ShiftIR.U) {
tdo := irChain.io.chainOut.data
tdo_driven := true.B
} .otherwise {
// Needed when using chisel3._ (See #1160)
tdo := DontCare
tdo_driven := false.B
}
}
object JtagTapGenerator {
/** JTAG TAP generator, enclosed module must be clocked from TCK and reset from output of this
* block.
*
* @param irLength length, in bits, of instruction register, must be at least 2
* @param instructions map of instruction codes to data register chains that select that data
* register; multiple instructions may map to the same data chain
* @param idcode optional idcode instruction. idcode UInt will come from outside this core.
*
* @note all other instruction codes (not part of instructions or idcode) map to BYPASS
* @note initial instruction is idcode (if supported), otherwise all ones BYPASS
*
* Usage notes:
* - 4.3.1b TMS must appear high when undriven
* - 4.3.1c (rec) minimize load presented by TMS
* - 4.4.1b TDI must appear high when undriven
* - 4.5.1b TDO must be inactive except when shifting data (undriven? 6.1.2)
* - 6.1.3.1b TAP controller must not be (re-?)initialized by system reset (allows
* boundary-scan testing of reset pin)
* - 6.1 TAP controller can be initialized by a on-chip power on reset generator, the same one
* that would initialize system logic
*
* TODO:
* - support concatenated scan chains
*/
def apply(irLength: Int, instructions: Map[BigInt, Chain], icode: Option[BigInt] = None)(implicit p: Parameters): JtagBlockIO = {
val internalIo = Wire(new JtagBlockIO(irLength, icode.isDefined))
// Create IDCODE chain if needed
val allInstructions = icode match {
case (Some(icode)) => {
require(!(instructions contains icode), "instructions may not contain IDCODE")
val idcodeChain = Module(CaptureChain(new JTAGIdcodeBundle()))
idcodeChain.suggestName("idcodeChain")
val i = internalIo.idcode.get.asUInt
assert(i % 2.U === 1.U, "LSB must be set in IDCODE, see 12.1.1d")
assert(((i >> 1) & ((1.U << 11) - 1.U)) =/= JtagIdcode.dummyMfrId.U,
"IDCODE must not have 0b00001111111 as manufacturer identity, see 12.2.1b")
idcodeChain.io.capture.bits := internalIo.idcode.get
instructions + (icode -> idcodeChain)
}
case None => instructions
}
val bypassIcode = (BigInt(1) << irLength) - 1 // required BYPASS instruction
val initialInstruction = icode.getOrElse(bypassIcode) // 7.2.1e load IDCODE or BYPASS instruction after entry into TestLogicReset
require(!(allInstructions contains bypassIcode), "instructions may not contain BYPASS code")
val controllerInternal = Module(new JtagTapController(irLength, initialInstruction))
val unusedChainOut = Wire(new ShifterIO) // De-selected chain output
unusedChainOut.shift := false.B
unusedChainOut.data := false.B
unusedChainOut.capture := false.B
unusedChainOut.update := false.B
val bypassChain = Module(JtagBypassChain())
// The Great Data Register Chain Mux
bypassChain.io.chainIn := controllerInternal.io.dataChainOut // for simplicity, doesn't visibly affect anything else
require(allInstructions.size > 0, "Seriously? JTAG TAP with no instructions?")
// Need to ensure that this mapping is ordered to produce deterministic verilog,
// and neither Map nor groupBy are deterministic.
// Therefore, we first sort by IDCODE, then sort the groups by the first IDCODE in each group.
val chainToIcode = (SortedMap(allInstructions.toList:_*).groupBy { case (icode, chain) => chain } map {
case (chain, icodeToChain) => chain -> icodeToChain.keys
}).toList.sortBy(_._2.head)
val chainToSelect = chainToIcode map {
case (chain, icodes) => {
assume(icodes.size > 0)
val icodeSelects = icodes map { controllerInternal.io.output.instruction === _.asUInt(irLength.W) }
chain -> icodeSelects.reduceLeft(_||_)
}
}
controllerInternal.io.dataChainIn := bypassChain.io.chainOut // default
def foldOutSelect(res: WhenContext, x: (Chain, Bool)): WhenContext = {
val (chain, select) = x
// Continue the WhenContext with if this chain is selected
res.elsewhen(select) {
controllerInternal.io.dataChainIn := chain.io.chainOut
}
}
val emptyWhen = when (false.B) { } // Empty WhenContext to start things off
chainToSelect.toSeq.foldLeft(emptyWhen)(foldOutSelect).otherwise {
controllerInternal.io.dataChainIn := bypassChain.io.chainOut
}
def mapInSelect(x: (Chain, Bool)): Unit = {
val (chain, select) = x
when (select) {
chain.io.chainIn := controllerInternal.io.dataChainOut
} .otherwise {
chain.io.chainIn := unusedChainOut
}
}
chainToSelect.map(mapInSelect)
internalIo.jtag <> controllerInternal.io.jtag
internalIo.control <> controllerInternal.io.control
internalIo.output <> controllerInternal.io.output
internalIo
}
} | module JtagTapController(
input clock,
input reset,
input io_jtag_TMS,
input io_jtag_TDI,
output io_jtag_TDO_data,
input io_control_jtag_reset,
output [4:0] io_output_instruction,
output io_output_tapIsInTestLogicReset,
output io_dataChainOut_shift,
output io_dataChainOut_data,
output io_dataChainOut_capture,
output io_dataChainOut_update,
input io_dataChainIn_data
);
wire _irChain_io_chainOut_data;
wire [4:0] _irChain_io_update_bits;
wire [3:0] _stateMachine_io_currState;
wire clock_falling = ~clock;
reg tdoReg;
wire irChain_io_chainIn_update = _stateMachine_io_currState == 4'hD;
reg [4:0] activeInstruction;
wire io_dataChainOut_shift_0 = _stateMachine_io_currState == 4'h2;
always @(posedge clock_falling or posedge io_control_jtag_reset) begin
if (io_control_jtag_reset) begin
tdoReg <= 1'h0;
activeInstruction <= 5'h1;
end
else begin
tdoReg <= io_dataChainOut_shift_0 ? io_dataChainIn_data : _irChain_io_chainOut_data;
if (&_stateMachine_io_currState)
activeInstruction <= 5'h1;
else if (irChain_io_chainIn_update)
activeInstruction <= _irChain_io_update_bits;
end
end
JtagStateMachine stateMachine (
.clock (clock),
.reset (io_control_jtag_reset),
.io_tms (io_jtag_TMS),
.io_currState (_stateMachine_io_currState)
);
CaptureUpdateChain_UInt5_To_UInt5 irChain (
.clock (clock),
.reset (reset),
.io_chainIn_shift (_stateMachine_io_currState == 4'hA),
.io_chainIn_data (io_jtag_TDI),
.io_chainIn_capture (_stateMachine_io_currState == 4'hE),
.io_chainIn_update (irChain_io_chainIn_update),
.io_chainOut_data (_irChain_io_chainOut_data),
.io_update_bits (_irChain_io_update_bits)
);
assign io_jtag_TDO_data = tdoReg;
assign io_output_instruction = activeInstruction;
assign io_output_tapIsInTestLogicReset = &_stateMachine_io_currState;
assign io_dataChainOut_shift = io_dataChainOut_shift_0;
assign io_dataChainOut_data = io_jtag_TDI;
assign io_dataChainOut_capture = _stateMachine_io_currState == 4'h6;
assign io_dataChainOut_update = _stateMachine_io_currState == 4'h5;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Rename BusyTable
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import boom.v3.common._
import boom.v3.util._
import org.chipsalliance.cde.config.Parameters
class BusyResp extends Bundle
{
val prs1_busy = Bool()
val prs2_busy = Bool()
val prs3_busy = Bool()
}
class RenameBusyTable(
val plWidth: Int,
val numPregs: Int,
val numWbPorts: Int,
val bypass: Boolean,
val float: Boolean)
(implicit p: Parameters) extends BoomModule
{
val pregSz = log2Ceil(numPregs)
val io = IO(new BoomBundle()(p) {
val ren_uops = Input(Vec(plWidth, new MicroOp))
val busy_resps = Output(Vec(plWidth, new BusyResp))
val rebusy_reqs = Input(Vec(plWidth, Bool()))
val wb_pdsts = Input(Vec(numWbPorts, UInt(pregSz.W)))
val wb_valids = Input(Vec(numWbPorts, Bool()))
val debug = new Bundle { val busytable = Output(Bits(numPregs.W)) }
})
val busy_table = RegInit(0.U(numPregs.W))
// Unbusy written back registers.
val busy_table_wb = busy_table & ~(io.wb_pdsts zip io.wb_valids)
.map {case (pdst, valid) => UIntToOH(pdst) & Fill(numPregs, valid.asUInt)}.reduce(_|_)
// Rebusy newly allocated registers.
val busy_table_next = busy_table_wb | (io.ren_uops zip io.rebusy_reqs)
.map {case (uop, req) => UIntToOH(uop.pdst) & Fill(numPregs, req.asUInt)}.reduce(_|_)
busy_table := busy_table_next
// Read the busy table.
for (i <- 0 until plWidth) {
val prs1_was_bypassed = (0 until i).map(j =>
io.ren_uops(i).lrs1 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)
val prs2_was_bypassed = (0 until i).map(j =>
io.ren_uops(i).lrs2 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)
val prs3_was_bypassed = (0 until i).map(j =>
io.ren_uops(i).lrs3 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)
io.busy_resps(i).prs1_busy := busy_table(io.ren_uops(i).prs1) || prs1_was_bypassed && bypass.B
io.busy_resps(i).prs2_busy := busy_table(io.ren_uops(i).prs2) || prs2_was_bypassed && bypass.B
io.busy_resps(i).prs3_busy := busy_table(io.ren_uops(i).prs3) || prs3_was_bypassed && bypass.B
if (!float) io.busy_resps(i).prs3_busy := false.B
}
io.debug.busytable := busy_table
} | module RenameBusyTable(
input clock,
input reset,
input [5:0] io_ren_uops_0_pdst,
input [5:0] io_ren_uops_0_prs1,
input [5:0] io_ren_uops_0_prs2,
output io_busy_resps_0_prs1_busy,
output io_busy_resps_0_prs2_busy,
input io_rebusy_reqs_0,
input [5:0] io_wb_pdsts_0,
input [5:0] io_wb_pdsts_1,
input [5:0] io_wb_pdsts_2,
input io_wb_valids_0,
input io_wb_valids_1,
input io_wb_valids_2
);
reg [51:0] busy_table;
wire [51:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1;
wire [51:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2;
wire [63:0] _busy_table_next_T = 64'h1 << io_ren_uops_0_pdst;
wire [63:0] _busy_table_wb_T_6 = 64'h1 << io_wb_pdsts_2;
wire [63:0] _busy_table_wb_T_3 = 64'h1 << io_wb_pdsts_1;
wire [63:0] _busy_table_wb_T = 64'h1 << io_wb_pdsts_0;
always @(posedge clock) begin
if (reset)
busy_table <= 52'h0;
else
busy_table <= ~(_busy_table_wb_T[51:0] & {52{io_wb_valids_0}} | _busy_table_wb_T_3[51:0] & {52{io_wb_valids_1}} | _busy_table_wb_T_6[51:0] & {52{io_wb_valids_2}}) & busy_table | _busy_table_next_T[51:0] & {52{io_rebusy_reqs_0}};
end
assign io_busy_resps_0_prs1_busy = _io_busy_resps_0_prs1_busy_T[0];
assign io_busy_resps_0_prs2_busy = _io_busy_resps_0_prs2_busy_T[0];
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Re-order Buffer
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Bank the ROB, such that each "dispatch" group gets its own row of the ROB,
// and each instruction in the dispatch group goes to a different bank.
// We can compress out the PC by only saving the high-order bits!
//
// ASSUMPTIONS:
// - dispatch groups are aligned to the PC.
//
// NOTES:
// - Currently we do not compress out bubbles in the ROB.
// - Exceptions are only taken when at the head of the commit bundle --
// this helps deal with loads, stores, and refetch instructions.
package boom.v3.exu
import scala.math.ceil
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import boom.v3.common._
import boom.v3.util._
/**
* IO bundle to interact with the ROB
*
* @param numWakeupPorts number of wakeup ports to the rob
* @param numFpuPorts number of fpu ports that will write back fflags
*/
class RobIo(
val numWakeupPorts: Int,
val numFpuPorts: Int
)(implicit p: Parameters) extends BoomBundle
{
// Decode Stage
// (Allocate, write instruction to ROB).
val enq_valids = Input(Vec(coreWidth, Bool()))
val enq_uops = Input(Vec(coreWidth, new MicroOp()))
val enq_partial_stall= Input(Bool()) // we're dispatching only a partial packet,
// and stalling on the rest of it (don't
// advance the tail ptr)
val xcpt_fetch_pc = Input(UInt(vaddrBitsExtended.W))
val rob_tail_idx = Output(UInt(robAddrSz.W))
val rob_pnr_idx = Output(UInt(robAddrSz.W))
val rob_head_idx = Output(UInt(robAddrSz.W))
// Handle Branch Misspeculations
val brupdate = Input(new BrUpdateInfo())
// Write-back Stage
// (Update of ROB)
// Instruction is no longer busy and can be committed
val wb_resps = Flipped(Vec(numWakeupPorts, Valid(new ExeUnitResp(xLen max fLen+1))))
// Unbusying ports for stores.
// +1 for fpstdata
val lsu_clr_bsy = Input(Vec(memWidth + 1, Valid(UInt(robAddrSz.W))))
// Port for unmarking loads/stores as speculation hazards..
val lsu_clr_unsafe = Input(Vec(memWidth, Valid(UInt(robAddrSz.W))))
// Track side-effects for debug purposes.
// Also need to know when loads write back, whereas we don't need loads to unbusy.
val debug_wb_valids = Input(Vec(numWakeupPorts, Bool()))
val debug_wb_wdata = Input(Vec(numWakeupPorts, Bits(xLen.W)))
val fflags = Flipped(Vec(numFpuPorts, new ValidIO(new FFlagsResp())))
val lxcpt = Input(Valid(new Exception())) // LSU
val csr_replay = Input(Valid(new Exception()))
// Commit stage (free resources; also used for rollback).
val commit = Output(new CommitSignals())
// tell the LSU that the head of the ROB is a load
// (some loads can only execute once they are at the head of the ROB).
val com_load_is_at_rob_head = Output(Bool())
// Communicate exceptions to the CSRFile
val com_xcpt = Valid(new CommitExceptionSignals())
// Let the CSRFile stall us (e.g., wfi).
val csr_stall = Input(Bool())
// Flush signals (including exceptions, pipeline replays, and memory ordering failures)
// to send to the frontend for redirection.
val flush = Valid(new CommitExceptionSignals)
// Stall Decode as appropriate
val empty = Output(Bool())
val ready = Output(Bool()) // ROB is busy unrolling rename state...
// Stall the frontend if we know we will redirect the PC
val flush_frontend = Output(Bool())
val debug_tsc = Input(UInt(xLen.W))
}
/**
* Bundle to send commit signals across processor
*/
class CommitSignals(implicit p: Parameters) extends BoomBundle
{
val valids = Vec(retireWidth, Bool()) // These instructions may not correspond to an architecturally executed insn
val arch_valids = Vec(retireWidth, Bool())
val uops = Vec(retireWidth, new MicroOp())
val fflags = Valid(UInt(5.W))
// These come a cycle later
val debug_insts = Vec(retireWidth, UInt(32.W))
// Perform rollback of rename state (in conjuction with commit.uops).
val rbk_valids = Vec(retireWidth, Bool())
val rollback = Bool()
val debug_wdata = Vec(retireWidth, UInt(xLen.W))
}
/**
* Bundle to communicate exceptions to CSRFile
*
* TODO combine FlushSignals and ExceptionSignals (currently timed to different cycles).
*/
class CommitExceptionSignals(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val edge_inst = Bool()
val is_rvc = Bool()
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
val cause = UInt(xLen.W)
val badvaddr = UInt(xLen.W)
// The ROB needs to tell the FTQ if there's a pipeline flush (and what type)
// so the FTQ can drive the frontend with the correct redirected PC.
val flush_typ = FlushTypes()
}
/**
* Tell the frontend the type of flush so it can set up the next PC properly.
*/
object FlushTypes
{
def SZ = 3
def apply() = UInt(SZ.W)
def none = 0.U
def xcpt = 1.U // An exception occurred.
def eret = (2+1).U // Execute an environment return instruction.
def refetch = 2.U // Flush and refetch the head instruction.
def next = 4.U // Flush and fetch the next instruction.
def useCsrEvec(typ: UInt): Bool = typ(0) // typ === xcpt.U || typ === eret.U
def useSamePC(typ: UInt): Bool = typ === refetch
def usePCplus4(typ: UInt): Bool = typ === next
def getType(valid: Bool, i_xcpt: Bool, i_eret: Bool, i_refetch: Bool): UInt = {
val ret =
Mux(!valid, none,
Mux(i_eret, eret,
Mux(i_xcpt, xcpt,
Mux(i_refetch, refetch,
next))))
ret
}
}
/**
* Bundle of signals indicating that an exception occurred
*/
class Exception(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val cause = Bits(log2Ceil(freechips.rocketchip.rocket.Causes.all.max+2).W)
val badvaddr = UInt(coreMaxAddrBits.W)
}
/**
* Bundle for debug ROB signals
* These should not be synthesized!
*/
class DebugRobSignals(implicit p: Parameters) extends BoomBundle
{
val state = UInt()
val rob_head = UInt(robAddrSz.W)
val rob_pnr = UInt(robAddrSz.W)
val xcpt_val = Bool()
val xcpt_uop = new MicroOp()
val xcpt_badvaddr = UInt(xLen.W)
}
/**
* Reorder Buffer to keep track of dependencies and inflight instructions
*
* @param numWakeupPorts number of wakeup ports to the ROB
* @param numFpuPorts number of FPU units that will write back fflags
*/
class Rob(
val numWakeupPorts: Int,
val numFpuPorts: Int
)(implicit p: Parameters) extends BoomModule
{
val io = IO(new RobIo(numWakeupPorts, numFpuPorts))
// ROB Finite State Machine
val s_reset :: s_normal :: s_rollback :: s_wait_till_empty :: Nil = Enum(4)
val rob_state = RegInit(s_reset)
//commit entries at the head, and unwind exceptions from the tail
val rob_head = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_head_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W)) // TODO: Accurately track head LSB (currently always 0)
val rob_head_idx = if (coreWidth == 1) rob_head else Cat(rob_head, rob_head_lsb)
val rob_tail = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_tail_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_tail_idx = if (coreWidth == 1) rob_tail else Cat(rob_tail, rob_tail_lsb)
val rob_pnr = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_pnr_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_pnr_idx = if (coreWidth == 1) rob_pnr else Cat(rob_pnr , rob_pnr_lsb)
val com_idx = Mux(rob_state === s_rollback, rob_tail, rob_head)
val maybe_full = RegInit(false.B)
val full = Wire(Bool())
val empty = Wire(Bool())
val will_commit = Wire(Vec(coreWidth, Bool()))
val can_commit = Wire(Vec(coreWidth, Bool()))
val can_throw_exception = Wire(Vec(coreWidth, Bool()))
val rob_pnr_unsafe = Wire(Vec(coreWidth, Bool())) // are the instructions at the pnr unsafe?
val rob_head_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the head valid?
val rob_tail_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the tail valid? (to track partial row dispatches)
val rob_head_uses_stq = Wire(Vec(coreWidth, Bool()))
val rob_head_uses_ldq = Wire(Vec(coreWidth, Bool()))
val rob_head_fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))
val exception_thrown = Wire(Bool())
// exception info
// TODO compress xcpt cause size. Most bits in the middle are zero.
val r_xcpt_val = RegInit(false.B)
val r_xcpt_uop = Reg(new MicroOp())
val r_xcpt_badvaddr = Reg(UInt(coreMaxAddrBits.W))
io.flush_frontend := r_xcpt_val
//--------------------------------------------------
// Utility
def GetRowIdx(rob_idx: UInt): UInt = {
if (coreWidth == 1) return rob_idx
else return rob_idx >> log2Ceil(coreWidth).U
}
def GetBankIdx(rob_idx: UInt): UInt = {
if(coreWidth == 1) { return 0.U }
else { return rob_idx(log2Ceil(coreWidth)-1, 0).asUInt }
}
// **************************************************************************
// Debug
class DebugRobBundle extends BoomBundle
{
val valid = Bool()
val busy = Bool()
val unsafe = Bool()
val uop = new MicroOp()
val exception = Bool()
}
val debug_entry = Wire(Vec(numRobEntries, new DebugRobBundle))
debug_entry := DontCare // override in statements below
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// Contains all information the PNR needs to find the oldest instruction which can't be safely speculated past.
val rob_unsafe_masked = WireInit(VecInit(Seq.fill(numRobRows << log2Ceil(coreWidth)){false.B}))
// Used for trace port, for debug purposes only
val rob_debug_inst_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(32.W)))
val rob_debug_inst_wmask = WireInit(VecInit(0.U(coreWidth.W).asBools))
val rob_debug_inst_wdata = Wire(Vec(coreWidth, UInt(32.W)))
rob_debug_inst_mem.write(rob_tail, rob_debug_inst_wdata, rob_debug_inst_wmask)
val rob_debug_inst_rdata = rob_debug_inst_mem.read(rob_head, will_commit.reduce(_||_))
val rob_fflags = Seq.fill(coreWidth)(Reg(Vec(numRobRows, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
for (w <- 0 until coreWidth) {
def MatchBank(bank_idx: UInt): Bool = (bank_idx === w.U)
// one bank
val rob_val = RegInit(VecInit(Seq.fill(numRobRows){false.B}))
val rob_bsy = Reg(Vec(numRobRows, Bool()))
val rob_unsafe = Reg(Vec(numRobRows, Bool()))
val rob_uop = Reg(Vec(numRobRows, new MicroOp()))
val rob_exception = Reg(Vec(numRobRows, Bool()))
val rob_predicated = Reg(Vec(numRobRows, Bool())) // Was this instruction predicated out?
val rob_debug_wdata = Mem(numRobRows, UInt(xLen.W))
//-----------------------------------------------
// Dispatch: Add Entry to ROB
rob_debug_inst_wmask(w) := io.enq_valids(w)
rob_debug_inst_wdata(w) := io.enq_uops(w).debug_inst
when (io.enq_valids(w)) {
rob_val(rob_tail) := true.B
rob_bsy(rob_tail) := !(io.enq_uops(w).is_fence ||
io.enq_uops(w).is_fencei)
rob_unsafe(rob_tail) := io.enq_uops(w).unsafe
rob_uop(rob_tail) := io.enq_uops(w)
rob_exception(rob_tail) := io.enq_uops(w).exception
rob_predicated(rob_tail) := false.B
rob_fflags(w)(rob_tail) := 0.U
assert (rob_val(rob_tail) === false.B, "[rob] overwriting a valid entry.")
assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)
} .elsewhen (io.enq_valids.reduce(_|_) && !rob_val(rob_tail)) {
rob_uop(rob_tail).debug_inst := BUBBLE // just for debug purposes
}
//-----------------------------------------------
// Writeback
for (i <- 0 until numWakeupPorts) {
val wb_resp = io.wb_resps(i)
val wb_uop = wb_resp.bits.uop
val row_idx = GetRowIdx(wb_uop.rob_idx)
when (wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx))) {
rob_bsy(row_idx) := false.B
rob_unsafe(row_idx) := false.B
rob_predicated(row_idx) := wb_resp.bits.predicated
}
// TODO check that fflags aren't overwritten
// TODO check that the wb is to a valid ROB entry, give it a time stamp
// assert (!(wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx)) &&
// wb_uop.fp_val && !(wb_uop.is_load || wb_uop.is_store) &&
// rob_exc_cause(row_idx) =/= 0.U),
// "FP instruction writing back exc bits is overriding an existing exception.")
}
// Stores have a separate method to clear busy bits
for (clr_rob_idx <- io.lsu_clr_bsy) {
when (clr_rob_idx.valid && MatchBank(GetBankIdx(clr_rob_idx.bits))) {
val cidx = GetRowIdx(clr_rob_idx.bits)
rob_bsy(cidx) := false.B
rob_unsafe(cidx) := false.B
assert (rob_val(cidx) === true.B, "[rob] store writing back to invalid entry.")
assert (rob_bsy(cidx) === true.B, "[rob] store writing back to a not-busy entry.")
}
}
for (clr <- io.lsu_clr_unsafe) {
when (clr.valid && MatchBank(GetBankIdx(clr.bits))) {
val cidx = GetRowIdx(clr.bits)
rob_unsafe(cidx) := false.B
}
}
//-----------------------------------------------
// Accruing fflags
for (i <- 0 until numFpuPorts) {
val fflag_uop = io.fflags(i).bits.uop
when (io.fflags(i).valid && MatchBank(GetBankIdx(fflag_uop.rob_idx))) {
rob_fflags(w)(GetRowIdx(fflag_uop.rob_idx)) := io.fflags(i).bits.flags
}
}
//-----------------------------------------------------
// Exceptions
// (the cause bits are compressed and stored elsewhere)
when (io.lxcpt.valid && MatchBank(GetBankIdx(io.lxcpt.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.lxcpt.bits.uop.rob_idx)) := true.B
when (io.lxcpt.bits.cause =/= MINI_EXCEPTION_MEM_ORDERING) {
// In the case of a mem-ordering failure, the failing load will have been marked safe already.
assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),
"An instruction marked as safe is causing an exception")
}
}
when (io.csr_replay.valid && MatchBank(GetBankIdx(io.csr_replay.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.csr_replay.bits.uop.rob_idx)) := true.B
}
can_throw_exception(w) := rob_val(rob_head) && rob_exception(rob_head)
//-----------------------------------------------
// Commit or Rollback
// Can this instruction commit? (the check for exceptions/rob_state happens later).
can_commit(w) := rob_val(rob_head) && !(rob_bsy(rob_head)) && !io.csr_stall
// use the same "com_uop" for both rollback AND commit
// Perform Commit
io.commit.valids(w) := will_commit(w)
io.commit.arch_valids(w) := will_commit(w) && !rob_predicated(com_idx)
io.commit.uops(w) := rob_uop(com_idx)
io.commit.debug_insts(w) := rob_debug_inst_rdata(w)
// We unbusy branches in b1, but its easier to mark the taken/provider src in b2,
// when the branch might be committing
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx)) &&
GetRowIdx(io.brupdate.b2.uop.rob_idx) === com_idx) {
io.commit.uops(w).debug_fsrc := BSRC_C
io.commit.uops(w).taken := io.brupdate.b2.taken
}
// Don't attempt to rollback the tail's row when the rob is full.
val rbk_row = rob_state === s_rollback && !full
io.commit.rbk_valids(w) := rbk_row && rob_val(com_idx) && !(enableCommitMapTable.B)
io.commit.rollback := (rob_state === s_rollback)
assert (!(io.commit.valids.reduce(_||_) && io.commit.rbk_valids.reduce(_||_)),
"com_valids and rbk_valids are mutually exclusive")
when (rbk_row) {
rob_val(com_idx) := false.B
rob_exception(com_idx) := false.B
}
if (enableCommitMapTable) {
when (RegNext(exception_thrown)) {
for (i <- 0 until numRobRows) {
rob_val(i) := false.B
rob_bsy(i) := false.B
rob_uop(i).debug_inst := BUBBLE
}
}
}
// -----------------------------------------------
// Kill speculated entries on branch mispredict
for (i <- 0 until numRobRows) {
val br_mask = rob_uop(i).br_mask
//kill instruction if mispredict & br mask match
when (IsKilledByBranch(io.brupdate, br_mask))
{
rob_val(i) := false.B
rob_uop(i.U).debug_inst := BUBBLE
} .elsewhen (rob_val(i)) {
// clear speculation bit even on correct speculation
rob_uop(i).br_mask := GetNewBrMask(io.brupdate, br_mask)
}
}
// Debug signal to figure out which prediction structure
// or core resolved a branch correctly
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx))) {
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).debug_fsrc := BSRC_C
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).taken := io.brupdate.b2.taken
}
// -----------------------------------------------
// Commit
when (will_commit(w)) {
rob_val(rob_head) := false.B
}
// -----------------------------------------------
// Outputs
rob_head_vals(w) := rob_val(rob_head)
rob_tail_vals(w) := rob_val(rob_tail)
rob_head_fflags(w) := rob_fflags(w)(rob_head)
rob_head_uses_stq(w) := rob_uop(rob_head).uses_stq
rob_head_uses_ldq(w) := rob_uop(rob_head).uses_ldq
//------------------------------------------------
// Invalid entries are safe; thrown exceptions are unsafe.
for (i <- 0 until numRobRows) {
rob_unsafe_masked((i << log2Ceil(coreWidth)) + w) := rob_val(i) && (rob_unsafe(i) || rob_exception(i))
}
// Read unsafe status of PNR row.
rob_pnr_unsafe(w) := rob_val(rob_pnr) && (rob_unsafe(rob_pnr) || rob_exception(rob_pnr))
// -----------------------------------------------
// debugging write ports that should not be synthesized
when (will_commit(w)) {
rob_uop(rob_head).debug_inst := BUBBLE
} .elsewhen (rbk_row)
{
rob_uop(rob_tail).debug_inst := BUBBLE
}
//--------------------------------------------------
// Debug: for debug purposes, track side-effects to all register destinations
for (i <- 0 until numWakeupPorts) {
val rob_idx = io.wb_resps(i).bits.uop.rob_idx
when (io.debug_wb_valids(i) && MatchBank(GetBankIdx(rob_idx))) {
rob_debug_wdata(GetRowIdx(rob_idx)) := io.debug_wb_wdata(i)
}
val temp_uop = rob_uop(GetRowIdx(rob_idx))
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_val(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to an invalid ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_bsy(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to a not-busy ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
temp_uop.ldst_val && temp_uop.pdst =/= io.wb_resps(i).bits.uop.pdst),
"[rob] writeback (" + i + ") occurred to the wrong pdst.")
}
io.commit.debug_wdata(w) := rob_debug_wdata(rob_head)
} //for (w <- 0 until coreWidth)
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// -----------------------------------------------
// Commit Logic
// need to take a "can_commit" array, and let the first can_commits commit
// previous instructions may block the commit of younger instructions in the commit bundle
// e.g., exception, or (valid && busy).
// Finally, don't throw an exception if there are instructions in front of
// it that want to commit (only throw exception when head of the bundle).
var block_commit = (rob_state =/= s_normal) && (rob_state =/= s_wait_till_empty) || RegNext(exception_thrown) || RegNext(RegNext(exception_thrown))
var will_throw_exception = false.B
var block_xcpt = false.B
for (w <- 0 until coreWidth) {
will_throw_exception = (can_throw_exception(w) && !block_commit && !block_xcpt) || will_throw_exception
will_commit(w) := can_commit(w) && !can_throw_exception(w) && !block_commit
block_commit = (rob_head_vals(w) &&
(!can_commit(w) || can_throw_exception(w))) || block_commit
block_xcpt = will_commit(w)
}
// Note: exception must be in the commit bundle.
// Note: exception must be the first valid instruction in the commit bundle.
exception_thrown := will_throw_exception
val is_mini_exception = io.com_xcpt.bits.cause.isOneOf(MINI_EXCEPTION_MEM_ORDERING, MINI_EXCEPTION_CSR_REPLAY)
io.com_xcpt.valid := exception_thrown && !is_mini_exception
io.com_xcpt.bits := DontCare
io.com_xcpt.bits.cause := r_xcpt_uop.exc_cause
io.com_xcpt.bits.badvaddr := Sext(r_xcpt_badvaddr, xLen)
val insn_sys_pc2epc =
rob_head_vals.reduce(_|_) && PriorityMux(rob_head_vals, io.commit.uops.map{u => u.is_sys_pc2epc})
val refetch_inst = exception_thrown || insn_sys_pc2epc
val com_xcpt_uop = PriorityMux(rob_head_vals, io.commit.uops)
io.com_xcpt.bits.ftq_idx := com_xcpt_uop.ftq_idx
io.com_xcpt.bits.edge_inst := com_xcpt_uop.edge_inst
io.com_xcpt.bits.is_rvc := com_xcpt_uop.is_rvc
io.com_xcpt.bits.pc_lob := com_xcpt_uop.pc_lob
val flush_commit_mask = Range(0,coreWidth).map{i => io.commit.valids(i) && io.commit.uops(i).flush_on_commit}
val flush_commit = flush_commit_mask.reduce(_|_)
val flush_val = exception_thrown || flush_commit
assert(!(PopCount(flush_commit_mask) > 1.U),
"[rob] Can't commit multiple flush_on_commit instructions on one cycle")
val flush_uop = Mux(exception_thrown, com_xcpt_uop, Mux1H(flush_commit_mask, io.commit.uops))
// delay a cycle for critical path considerations
io.flush.valid := flush_val
io.flush.bits := DontCare
io.flush.bits.ftq_idx := flush_uop.ftq_idx
io.flush.bits.pc_lob := flush_uop.pc_lob
io.flush.bits.edge_inst := flush_uop.edge_inst
io.flush.bits.is_rvc := flush_uop.is_rvc
io.flush.bits.flush_typ := FlushTypes.getType(flush_val,
exception_thrown && !is_mini_exception,
flush_commit && flush_uop.uopc === uopERET,
refetch_inst)
// -----------------------------------------------
// FP Exceptions
// send fflags bits to the CSRFile to accrue
val fflags_val = Wire(Vec(coreWidth, Bool()))
val fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))
for (w <- 0 until coreWidth) {
fflags_val(w) :=
io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
!io.commit.uops(w).uses_stq
fflags(w) := Mux(fflags_val(w), rob_head_fflags(w), 0.U)
assert (!(io.commit.valids(w) &&
!io.commit.uops(w).fp_val &&
rob_head_fflags(w) =/= 0.U),
"Committed non-FP instruction has non-zero fflag bits.")
assert (!(io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
(io.commit.uops(w).uses_ldq || io.commit.uops(w).uses_stq) &&
rob_head_fflags(w) =/= 0.U),
"Committed FP load or store has non-zero fflag bits.")
}
io.commit.fflags.valid := fflags_val.reduce(_|_)
io.commit.fflags.bits := fflags.reduce(_|_)
// -----------------------------------------------
// Exception Tracking Logic
// only store the oldest exception, since only one can happen!
val next_xcpt_uop = Wire(new MicroOp())
next_xcpt_uop := r_xcpt_uop
val enq_xcpts = Wire(Vec(coreWidth, Bool()))
for (i <- 0 until coreWidth) {
enq_xcpts(i) := io.enq_valids(i) && io.enq_uops(i).exception
}
when (!(io.flush.valid || exception_thrown) && rob_state =/= s_rollback) {
val new_xcpt_valid = io.lxcpt.valid || io.csr_replay.valid
val lxcpt_older = !io.csr_replay.valid || (IsOlder(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx, rob_head_idx) && io.lxcpt.valid)
val new_xcpt = Mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits)
when (new_xcpt_valid) {
when (!r_xcpt_val || IsOlder(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx, rob_head_idx)) {
r_xcpt_val := true.B
next_xcpt_uop := new_xcpt.uop
next_xcpt_uop.exc_cause := new_xcpt.cause
r_xcpt_badvaddr := new_xcpt.badvaddr
}
} .elsewhen (!r_xcpt_val && enq_xcpts.reduce(_|_)) {
val idx = enq_xcpts.indexWhere{i: Bool => i}
// if no exception yet, dispatch exception wins
r_xcpt_val := true.B
next_xcpt_uop := io.enq_uops(idx)
r_xcpt_badvaddr := AlignPCToBoundary(io.xcpt_fetch_pc, icBlockBytes) | io.enq_uops(idx).pc_lob
}
}
r_xcpt_uop := next_xcpt_uop
r_xcpt_uop.br_mask := GetNewBrMask(io.brupdate, next_xcpt_uop)
when (io.flush.valid || IsKilledByBranch(io.brupdate, next_xcpt_uop)) {
r_xcpt_val := false.B
}
assert (!(exception_thrown && !r_xcpt_val),
"ROB trying to throw an exception, but it doesn't have a valid xcpt_cause")
assert (!(empty && r_xcpt_val),
"ROB is empty, but believes it has an outstanding exception.")
assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),
"ROB is throwing an exception, but the stored exception information's " +
"rob_idx does not match the rob_head")
// -----------------------------------------------
// ROB Head Logic
// remember if we're still waiting on the rest of the dispatch packet, and prevent
// the rob_head from advancing if it commits a partial parket before we
// dispatch the rest of it.
// update when committed ALL valid instructions in commit_bundle
val rob_deq = WireInit(false.B)
val r_partial_row = RegInit(false.B)
when (io.enq_valids.reduce(_|_)) {
r_partial_row := io.enq_partial_stall
}
val finished_committing_row =
(io.commit.valids.asUInt =/= 0.U) &&
((will_commit.asUInt ^ rob_head_vals.asUInt) === 0.U) &&
!(r_partial_row && rob_head === rob_tail && !maybe_full)
when (finished_committing_row) {
rob_head := WrapInc(rob_head, numRobRows)
rob_head_lsb := 0.U
rob_deq := true.B
} .otherwise {
rob_head_lsb := OHToUInt(PriorityEncoderOH(rob_head_vals.asUInt))
}
// -----------------------------------------------
// ROB Point-of-No-Return (PNR) Logic
// Acts as a second head, but only waits on busy instructions which might cause misspeculation.
// TODO is it worth it to add an extra 'parity' bit to all rob pointer logic?
// Makes 'older than' comparisons ~3x cheaper, in case we're going to use the PNR to do a large number of those.
// Also doesn't require the rob tail (or head) to be exported to whatever we want to compare with the PNR.
if (enableFastPNR) {
val unsafe_entry_in_rob = rob_unsafe_masked.reduce(_||_)
val next_rob_pnr_idx = Mux(unsafe_entry_in_rob,
AgePriorityEncoder(rob_unsafe_masked, rob_head_idx),
rob_tail << log2Ceil(coreWidth) | PriorityEncoder(~rob_tail_vals.asUInt))
rob_pnr := next_rob_pnr_idx >> log2Ceil(coreWidth)
if (coreWidth > 1)
rob_pnr_lsb := next_rob_pnr_idx(log2Ceil(coreWidth)-1, 0)
} else {
// Distinguish between PNR being at head/tail when ROB is full.
// Works the same as maybe_full tracking for the ROB tail.
val pnr_maybe_at_tail = RegInit(false.B)
val safe_to_inc = rob_state === s_normal || rob_state === s_wait_till_empty
val do_inc_row = !rob_pnr_unsafe.reduce(_||_) && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))
when (empty && io.enq_valids.asUInt =/= 0.U) {
// Unforunately for us, the ROB does not use its entries in monotonically
// increasing order, even in the case of no exceptions. The edge case
// arises when partial rows are enqueued and committed, leaving an empty
// ROB.
rob_pnr := rob_head
rob_pnr_lsb := PriorityEncoder(io.enq_valids)
} .elsewhen (safe_to_inc && do_inc_row) {
rob_pnr := WrapInc(rob_pnr, numRobRows)
rob_pnr_lsb := 0.U
} .elsewhen (safe_to_inc && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe)
} .elsewhen (safe_to_inc && !full && !empty) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe.asUInt | ~MaskLower(rob_tail_vals.asUInt))
} .elsewhen (full && pnr_maybe_at_tail) {
rob_pnr_lsb := 0.U
}
pnr_maybe_at_tail := !rob_deq && (do_inc_row || pnr_maybe_at_tail)
}
// Head overrunning PNR likely means an entry hasn't been marked as safe when it should have been.
assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)
// PNR overrunning tail likely means an entry has been marked as safe when it shouldn't have been.
assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)
// -----------------------------------------------
// ROB Tail Logic
val rob_enq = WireInit(false.B)
when (rob_state === s_rollback && (rob_tail =/= rob_head || maybe_full)) {
// Rollback a row
rob_tail := WrapDec(rob_tail, numRobRows)
rob_tail_lsb := (coreWidth-1).U
rob_deq := true.B
} .elsewhen (rob_state === s_rollback && (rob_tail === rob_head) && !maybe_full) {
// Rollback an entry
rob_tail_lsb := rob_head_lsb
} .elsewhen (io.brupdate.b2.mispredict) {
rob_tail := WrapInc(GetRowIdx(io.brupdate.b2.uop.rob_idx), numRobRows)
rob_tail_lsb := 0.U
} .elsewhen (io.enq_valids.asUInt =/= 0.U && !io.enq_partial_stall) {
rob_tail := WrapInc(rob_tail, numRobRows)
rob_tail_lsb := 0.U
rob_enq := true.B
} .elsewhen (io.enq_valids.asUInt =/= 0.U && io.enq_partial_stall) {
rob_tail_lsb := PriorityEncoder(~MaskLower(io.enq_valids.asUInt))
}
if (enableCommitMapTable) {
when (RegNext(exception_thrown)) {
rob_tail := 0.U
rob_tail_lsb := 0.U
rob_head := 0.U
rob_pnr := 0.U
rob_pnr_lsb := 0.U
}
}
// -----------------------------------------------
// Full/Empty Logic
// The ROB can be completely full, but only if it did not dispatch a row in the prior cycle.
// I.E. at least one entry will be empty when in a steady state of dispatching and committing a row each cycle.
// TODO should we add an extra 'parity bit' onto the ROB pointers to simplify this logic?
maybe_full := !rob_deq && (rob_enq || maybe_full) || io.brupdate.b1.mispredict_mask =/= 0.U
full := rob_tail === rob_head && maybe_full
empty := (rob_head === rob_tail) && (rob_head_vals.asUInt === 0.U)
io.rob_head_idx := rob_head_idx
io.rob_tail_idx := rob_tail_idx
io.rob_pnr_idx := rob_pnr_idx
io.empty := empty
io.ready := (rob_state === s_normal) && !full && !r_xcpt_val
//-----------------------------------------------
//-----------------------------------------------
//-----------------------------------------------
// ROB FSM
if (!enableCommitMapTable) {
switch (rob_state) {
is (s_reset) {
rob_state := s_normal
}
is (s_normal) {
// Delay rollback 2 cycles so branch mispredictions can drain
when (RegNext(RegNext(exception_thrown))) {
rob_state := s_rollback
} .otherwise {
for (w <- 0 until coreWidth) {
when (io.enq_valids(w) && io.enq_uops(w).is_unique) {
rob_state := s_wait_till_empty
}
}
}
}
is (s_rollback) {
when (empty) {
rob_state := s_normal
}
}
is (s_wait_till_empty) {
when (RegNext(exception_thrown)) {
rob_state := s_rollback
} .elsewhen (empty) {
rob_state := s_normal
}
}
}
} else {
switch (rob_state) {
is (s_reset) {
rob_state := s_normal
}
is (s_normal) {
when (exception_thrown) {
; //rob_state := s_rollback
} .otherwise {
for (w <- 0 until coreWidth) {
when (io.enq_valids(w) && io.enq_uops(w).is_unique) {
rob_state := s_wait_till_empty
}
}
}
}
is (s_rollback) {
when (rob_tail_idx === rob_head_idx) {
rob_state := s_normal
}
}
is (s_wait_till_empty) {
when (exception_thrown) {
; //rob_state := s_rollback
} .elsewhen (rob_tail === rob_head) {
rob_state := s_normal
}
}
}
}
// -----------------------------------------------
// Outputs
io.com_load_is_at_rob_head := RegNext(rob_head_uses_ldq(PriorityEncoder(rob_head_vals.asUInt)) &&
!will_commit.reduce(_||_))
override def toString: String = BoomCoreStringPrefix(
"==ROB==",
"Machine Width : " + coreWidth,
"Rob Entries : " + numRobEntries,
"Rob Rows : " + numRobRows,
"Rob Row size : " + log2Ceil(numRobRows),
"log2Ceil(coreWidth): " + log2Ceil(coreWidth),
"FPU FFlag Ports : " + numFpuPorts)
} | module rob_debug_inst_mem_0(
input [4:0] R0_addr,
input R0_en,
input R0_clk,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [31:0] W0_data
);
rob_debug_inst_mem_0_ext rob_debug_inst_mem_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (/* unused */),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module head_40x6(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data,
input [5:0] W1_addr,
input W1_en,
input W1_clk,
input [5:0] W1_data
);
reg [5:0] Memory[0:39];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
} | module FPUFMAPipe_l4_f64(
input clock,
input reset,
input io_in_valid,
input io_in_bits_ren3,
input io_in_bits_swap23,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_fmaCmd,
input [64:0] io_in_bits_in1,
input [64:0] io_in_bits_in2,
input [64:0] io_in_bits_in3,
output io_out_valid,
output [64:0] io_out_bits_data,
output [4:0] io_out_bits_exc
);
wire [64:0] _fma_io_out;
wire [4:0] _fma_io_exceptionFlags;
wire _fma_io_validout;
reg valid;
reg [2:0] in_rm;
reg [1:0] in_fmaCmd;
reg [64:0] in_in1;
reg [64:0] in_in2;
reg [64:0] in_in3;
reg io_out_pipe_v;
reg [64:0] io_out_pipe_b_data;
reg [4:0] io_out_pipe_b_exc;
always @(posedge clock) begin
valid <= io_in_valid;
if (io_in_valid) begin
in_rm <= io_in_bits_rm;
in_fmaCmd <= io_in_bits_fmaCmd;
in_in1 <= io_in_bits_in1;
in_in2 <= io_in_bits_swap23 ? 65'h8000000000000000 : io_in_bits_in2;
in_in3 <= io_in_bits_ren3 | io_in_bits_swap23 ? io_in_bits_in3 : (io_in_bits_in1 ^ io_in_bits_in2) & 65'h10000000000000000;
end
if (_fma_io_validout) begin
io_out_pipe_b_data <= ({65{_fma_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) & _fma_io_out;
io_out_pipe_b_exc <= _fma_io_exceptionFlags;
end
if (reset)
io_out_pipe_v <= 1'h0;
else
io_out_pipe_v <= _fma_io_validout;
end
MulAddRecFNPipe_l2_e11_s53 fma (
.clock (clock),
.reset (reset),
.io_validin (valid),
.io_op (in_fmaCmd),
.io_a (in_in1),
.io_b (in_in2),
.io_c (in_in3),
.io_roundingMode (in_rm),
.io_out (_fma_io_out),
.io_exceptionFlags (_fma_io_exceptionFlags),
.io_validout (_fma_io_validout)
);
assign io_out_valid = io_out_pipe_v;
assign io_out_bits_data = io_out_pipe_b_data;
assign io_out_bits_exc = io_out_pipe_b_exc;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module MulAddRecFNToRaw_preMul_e11_s53(
input [1:0] io_op,
input [64:0] io_a,
input [64:0] io_b,
input [64:0] io_c,
output [52:0] io_mulAddA,
output [52:0] io_mulAddB,
output [105:0] io_mulAddC,
output io_toPostMul_isSigNaNAny,
output io_toPostMul_isNaNAOrB,
output io_toPostMul_isInfA,
output io_toPostMul_isZeroA,
output io_toPostMul_isInfB,
output io_toPostMul_isZeroB,
output io_toPostMul_signProd,
output io_toPostMul_isNaNC,
output io_toPostMul_isInfC,
output io_toPostMul_isZeroC,
output [12:0] io_toPostMul_sExpSum,
output io_toPostMul_doSubMags,
output io_toPostMul_CIsDominant,
output [5:0] io_toPostMul_CDom_CAlignDist,
output [54:0] io_toPostMul_highAlignedSigC,
output io_toPostMul_bit0AlignedSigC
);
wire rawA_isNaN = (&(io_a[63:62])) & io_a[61];
wire rawB_isNaN = (&(io_b[63:62])) & io_b[61];
wire rawC_isNaN = (&(io_c[63:62])) & io_c[61];
wire signProd = io_a[64] ^ io_b[64] ^ io_op[1];
wire [13:0] _sExpAlignedProd_T_1 = {2'h0, io_a[63:52]} + {2'h0, io_b[63:52]} - 14'h7C8;
wire doSubMags = signProd ^ io_c[64] ^ io_op[0];
wire [13:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[63:52]};
wire isMinCAlign = ~(|(io_a[63:61])) | ~(|(io_b[63:61])) | $signed(_sNatCAlignDist_T) < 14'sh0;
wire CIsDominant = (|(io_c[63:61])) & (isMinCAlign | _sNatCAlignDist_T[12:0] < 13'h36);
wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _sNatCAlignDist_T[12:0] < 13'hA1 ? _sNatCAlignDist_T[7:0] : 8'hA1;
wire [164:0] mainAlignedSigC = $signed($signed({doSubMags ? {1'h1, ~(|(io_c[63:61])), ~(io_c[51:0])} : {1'h0, |(io_c[63:61]), io_c[51:0]}, {111{doSubMags}}}) >>> CAlignDist);
wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> CAlignDist[7:2]);
wire [12:0] _GEN = {|(io_c[51:48]), |(io_c[47:44]), |(io_c[43:40]), |(io_c[39:36]), |(io_c[35:32]), |(io_c[31:28]), |(io_c[27:24]), |(io_c[23:20]), |(io_c[19:16]), |(io_c[15:12]), |(io_c[11:8]), |(io_c[7:4]), |(io_c[3:0])} & {reduced4CExtra_shift[24], reduced4CExtra_shift[25], reduced4CExtra_shift[26], reduced4CExtra_shift[27], reduced4CExtra_shift[28], reduced4CExtra_shift[29], reduced4CExtra_shift[30], reduced4CExtra_shift[31], reduced4CExtra_shift[32], reduced4CExtra_shift[33], reduced4CExtra_shift[34], reduced4CExtra_shift[35], reduced4CExtra_shift[36]};
assign io_mulAddA = {|(io_a[63:61]), io_a[51:0]};
assign io_mulAddB = {|(io_b[63:61]), io_b[51:0]};
assign io_mulAddC = mainAlignedSigC[108:3];
assign io_toPostMul_isSigNaNAny = rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | rawC_isNaN & ~(io_c[51]);
assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;
assign io_toPostMul_isInfA = (&(io_a[63:62])) & ~(io_a[61]);
assign io_toPostMul_isZeroA = ~(|(io_a[63:61]));
assign io_toPostMul_isInfB = (&(io_b[63:62])) & ~(io_b[61]);
assign io_toPostMul_isZeroB = ~(|(io_b[63:61]));
assign io_toPostMul_signProd = signProd;
assign io_toPostMul_isNaNC = rawC_isNaN;
assign io_toPostMul_isInfC = (&(io_c[63:62])) & ~(io_c[61]);
assign io_toPostMul_isZeroC = ~(|(io_c[63:61]));
assign io_toPostMul_sExpSum = CIsDominant ? {1'h0, io_c[63:52]} : _sExpAlignedProd_T_1[12:0] - 13'h35;
assign io_toPostMul_doSubMags = doSubMags;
assign io_toPostMul_CIsDominant = CIsDominant;
assign io_toPostMul_CDom_CAlignDist = CAlignDist[5:0];
assign io_toPostMul_highAlignedSigC = mainAlignedSigC[163:109];
assign io_toPostMul_bit0AlignedSigC = doSubMags ? (&(mainAlignedSigC[2:0])) & _GEN == 13'h0 : (|{mainAlignedSigC[2:0], _GEN});
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module PhitArbiter_p32_f32_n5_TestHarness_UNIQUIFIED(
input clock,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [31:0] io_in_0_bits_phit,
output io_in_1_ready,
input io_in_1_valid,
input [31:0] io_in_1_bits_phit,
output io_in_2_ready,
input io_in_2_valid,
input [31:0] io_in_2_bits_phit,
output io_in_3_ready,
input io_in_3_valid,
input [31:0] io_in_3_bits_phit,
output io_in_4_ready,
input io_in_4_valid,
input [31:0] io_in_4_bits_phit,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_phit
);
reg beat;
reg [2:0] chosen_reg;
wire [2:0] chosen_prio = io_in_0_valid ? 3'h0 : io_in_1_valid ? 3'h1 : io_in_2_valid ? 3'h2 : io_in_3_valid ? 3'h3 : 3'h4;
wire [2:0] chosen = beat ? chosen_reg : chosen_prio;
wire [7:0] _GEN = {{io_in_0_valid}, {io_in_0_valid}, {io_in_0_valid}, {io_in_4_valid}, {io_in_3_valid}, {io_in_2_valid}, {io_in_1_valid}, {io_in_0_valid}};
wire [7:0][31:0] _GEN_0 = {{io_in_0_bits_phit}, {io_in_0_bits_phit}, {io_in_0_bits_phit}, {io_in_4_bits_phit}, {io_in_3_bits_phit}, {io_in_2_bits_phit}, {io_in_1_bits_phit}, {io_in_0_bits_phit}};
wire _GEN_1 = io_out_ready & _GEN[chosen];
always @(posedge clock) begin
if (reset)
beat <= 1'h0;
else if (_GEN_1)
beat <= ~beat & beat - 1'h1;
if (_GEN_1 & ~beat)
chosen_reg <= chosen_prio;
end
assign io_in_0_ready = io_out_ready & beat & chosen_reg == 3'h0;
assign io_in_1_ready = io_out_ready & beat & chosen_reg == 3'h1;
assign io_in_2_ready = io_out_ready & beat & chosen_reg == 3'h2;
assign io_in_3_ready = io_out_ready & beat & chosen_reg == 3'h3;
assign io_in_4_ready = io_out_ready & beat & chosen_reg == 3'h4;
assign io_out_valid = _GEN[chosen];
assign io_out_bits_phit = beat ? _GEN_0[chosen] : {29'h0, chosen};
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2012 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Out-of-Order Load/Store Unit
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Load/Store Unit is made up of the Load Queue, the Store Queue (LDQ and STQ).
//
// Stores are sent to memory at (well, after) commit, loads are executed
// optimstically ASAP. If a misspeculation was discovered, the pipeline is
// cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match,
// the Load can receive its data by forwarding data out of the Store Queue.
//
// Currently, loads are sent to memory immediately, and in parallel do an
// associative search of the STQ, on entering the LSU. If a hit on the STQ
// search, the memory request is killed on the next cycle, and if the STQ entry
// is valid, the store data is forwarded to the load (delayed to match the
// load-use delay to delay with the write-port structural hazard). If the store
// data is not present, or it's only a partial match (SB->LH), the load is put
// to sleep in the LDQ.
//
// Memory ordering violations are detected by stores at their addr-gen time by
// associatively searching the LDQ for newer loads that have been issued to
// memory.
//
// The store queue contains both speculated and committed stores.
//
// Only one port to memory... loads and stores have to fight for it, West Side
// Story style.
//
// TODO:
// - Add predicting structure for ordering failures
// - currently won't STD forward if DMEM is busy
// - ability to turn off things if VM is disabled
// - reconsider port count of the wakeup, retry stuff
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.Str
import boom.v3.common._
import boom.v3.exu.{BrUpdateInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp}
import boom.v3.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask}
class LSUExeIO(implicit p: Parameters) extends BoomBundle()(p)
{
// The "resp" of the maddrcalc is really a "req" to the LSU
val req = Flipped(new ValidIO(new FuncUnitResp(xLen)))
// Send load data to regfiles
val iresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen))
val fresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen+1)) // TODO: Should this be fLen?
}
class BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomUOP
{
val addr = UInt(coreMaxAddrBits.W)
val data = Bits(coreDataBits.W)
val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ
}
class BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomUOP
{
val data = Bits(coreDataBits.W)
val is_hella = Bool()
}
class LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p)
{
// In LSU's dmem stage, send the request
val req = new DecoupledIO(Vec(memWidth, Valid(new BoomDCacheReq)))
// In LSU's LCAM search stage, kill if order fail (or forwarding possible)
val s1_kill = Output(Vec(memWidth, Bool()))
// Get a request any cycle
val resp = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheResp)))
// In our response stage, if we get a nack, we need to reexecute
val nack = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheReq)))
val brupdate = Output(new BrUpdateInfo)
val exception = Output(Bool())
val rob_pnr_idx = Output(UInt(robAddrSz.W))
val rob_head_idx = Output(UInt(robAddrSz.W))
val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle)))
// Clears prefetching MSHRs
val force_order = Output(Bool())
val ordered = Input(Bool())
val perf = Input(new Bundle {
val acquire = Bool()
val release = Bool()
})
}
class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p)
{
val exe = Vec(memWidth, new LSUExeIO)
val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp)))
val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W)))
val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W)))
val ldq_full = Output(Vec(coreWidth, Bool()))
val stq_full = Output(Vec(coreWidth, Bool()))
val fp_stdata = Flipped(Decoupled(new ExeUnitResp(fLen)))
val commit = Input(new CommitSignals)
val commit_load_at_rob_head = Input(Bool())
// Stores clear busy bit when stdata is received
// memWidth for int, 1 for fp (to avoid back-pressure fpstdat)
val clr_bsy = Output(Vec(memWidth + 1, Valid(UInt(robAddrSz.W))))
// Speculatively safe load (barring memory ordering failure)
val clr_unsafe = Output(Vec(memWidth, Valid(UInt(robAddrSz.W))))
// Tell the DCache to clear prefetches/speculating misses
val fence_dmem = Input(Bool())
// Speculatively tell the IQs that we'll get load data back next cycle
val spec_ld_wakeup = Output(Vec(memWidth, Valid(UInt(maxPregSz.W))))
// Tell the IQs that the load we speculated last cycle was misspeculated
val ld_miss = Output(Bool())
val brupdate = Input(new BrUpdateInfo)
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val exception = Input(Bool())
val fencei_rdy = Output(Bool())
val lxcpt = Output(Valid(new Exception))
val tsc_reg = Input(UInt())
val perf = Output(new Bundle {
val acquire = Bool()
val release = Bool()
val tlbMiss = Bool()
})
}
class LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p)
{
val ptw = new rocket.TLBPTWIO
val core = new LSUCoreIO
val dmem = new LSUDMemIO
val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO)
}
class LDQEntry(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomUOP
{
val addr = Valid(UInt(coreMaxAddrBits.W))
val addr_is_virtual = Bool() // Virtual address, we got a TLB miss
val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute
val executed = Bool() // load sent to memory, reset by NACKs
val succeeded = Bool()
val order_fail = Bool()
val observed = Bool()
val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us
val youngest_stq_idx = UInt(stqAddrSz.W) // index of the oldest store younger than us
val forward_std_val = Bool()
val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from?
val debug_wb_data = UInt(xLen.W)
}
class STQEntry(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomUOP
{
val addr = Valid(UInt(coreMaxAddrBits.W))
val addr_is_virtual = Bool() // Virtual address, we got a TLB miss
val data = Valid(UInt(xLen.W))
val committed = Bool() // committed by ROB
val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore
val debug_wb_data = UInt(xLen.W)
}
class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)
with rocket.HasL1HellaCacheParameters
{
val io = IO(new LSUIO)
io.hellacache := DontCare
val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry)))
val stq = Reg(Vec(numStqEntries, Valid(new STQEntry)))
val ldq_head = Reg(UInt(ldqAddrSz.W))
val ldq_tail = Reg(UInt(ldqAddrSz.W))
val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory)
val stq_tail = Reg(UInt(stqAddrSz.W))
val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit
val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute
// If we got a mispredict, the tail will be misaligned for 1 extra cycle
assert (io.core.brupdate.b2.mispredict ||
stq(stq_execute_head).valid ||
stq_head === stq_execute_head ||
stq_tail === stq_execute_head,
"stq_execute_head got off track.")
val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7)
// s1 : do TLB, if success and not killed, fire request go to h_s2
// store s1_data to register
// if tlb miss, go to s2_nack
// if don't get TLB, go to s2_nack
// store tlb xcpt
// s2 : If kill, go to dead
// If tlb xcpt, send tlb xcpt, go to dead
// s2_nack : send nack, go to dead
// wait : wait for response, if nack, go to replay
// replay : refire request, use already translated address
// dead : wait for response, ignore it
val hella_state = RegInit(h_ready)
val hella_req = Reg(new rocket.HellaCacheReq)
val hella_data = Reg(new rocket.HellaCacheWriteData)
val hella_paddr = Reg(UInt(paddrBits.W))
val hella_xcpt = Reg(new rocket.HellaCacheExceptions)
val dtlb = Module(new NBDTLB(
instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays)))
io.ptw <> dtlb.io.ptw
io.core.perf.tlbMiss := io.ptw.req.fire
io.core.perf.acquire := io.dmem.perf.acquire
io.core.perf.release := io.dmem.perf.release
val clear_store = WireInit(false.B)
val live_store_mask = RegInit(0.U(numStqEntries.W))
var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head),
live_store_mask)
def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
//-------------------------------------------------------------
//-------------------------------------------------------------
// Enqueue new entries
//-------------------------------------------------------------
//-------------------------------------------------------------
// This is a newer store than existing loads, so clear the bit in all the store dependency masks
for (i <- 0 until numLdqEntries)
{
when (clear_store)
{
ldq(i).bits.st_dep_mask := ldq(i).bits.st_dep_mask & ~(1.U << stq_head)
}
}
// Decode stage
var ld_enq_idx = ldq_tail
var st_enq_idx = stq_tail
val stq_nonempty = (0 until numStqEntries).map{ i => stq(i).valid }.reduce(_||_) =/= 0.U
var ldq_full = Bool()
var stq_full = Bool()
for (w <- 0 until coreWidth)
{
ldq_full = WrapInc(ld_enq_idx, numLdqEntries) === ldq_head
io.core.ldq_full(w) := ldq_full
io.core.dis_ldq_idx(w) := ld_enq_idx
stq_full = WrapInc(st_enq_idx, numStqEntries) === stq_head
io.core.stq_full(w) := stq_full
io.core.dis_stq_idx(w) := st_enq_idx
val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception
val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception
when (dis_ld_val)
{
ldq(ld_enq_idx).valid := true.B
ldq(ld_enq_idx).bits.uop := io.core.dis_uops(w).bits
ldq(ld_enq_idx).bits.youngest_stq_idx := st_enq_idx
ldq(ld_enq_idx).bits.st_dep_mask := next_live_store_mask
ldq(ld_enq_idx).bits.addr.valid := false.B
ldq(ld_enq_idx).bits.executed := false.B
ldq(ld_enq_idx).bits.succeeded := false.B
ldq(ld_enq_idx).bits.order_fail := false.B
ldq(ld_enq_idx).bits.observed := false.B
ldq(ld_enq_idx).bits.forward_std_val := false.B
assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, "[lsu] mismatch enq load tag.")
assert (!ldq(ld_enq_idx).valid, "[lsu] Enqueuing uop is overwriting ldq entries")
}
.elsewhen (dis_st_val)
{
stq(st_enq_idx).valid := true.B
stq(st_enq_idx).bits.uop := io.core.dis_uops(w).bits
stq(st_enq_idx).bits.addr.valid := false.B
stq(st_enq_idx).bits.data.valid := false.B
stq(st_enq_idx).bits.committed := false.B
stq(st_enq_idx).bits.succeeded := false.B
assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, "[lsu] mismatch enq store tag.")
assert (!stq(st_enq_idx).valid, "[lsu] Enqueuing uop is overwriting stq entries")
}
ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries),
ld_enq_idx)
next_live_store_mask = Mux(dis_st_val, next_live_store_mask | (1.U << st_enq_idx),
next_live_store_mask)
st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries),
st_enq_idx)
assert(!(dis_ld_val && dis_st_val), "A UOP is trying to go into both the LDQ and the STQ")
}
ldq_tail := ld_enq_idx
stq_tail := st_enq_idx
io.dmem.force_order := io.core.fence_dmem
io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered
//-------------------------------------------------------------
//-------------------------------------------------------------
// Execute stage (access TLB, send requests to Memory)
//-------------------------------------------------------------
//-------------------------------------------------------------
// We can only report 1 exception per cycle.
// Just be sure to report the youngest one
val mem_xcpt_valid = Wire(Bool())
val mem_xcpt_cause = Wire(UInt())
val mem_xcpt_uop = Wire(new MicroOp)
val mem_xcpt_vaddr = Wire(UInt())
//---------------------------------------
// Can-fire logic and wakeup/retry select
//
// First we determine what operations are waiting to execute.
// These are the "can_fire"/"will_fire" signals
val will_fire_load_incoming = Wire(Vec(memWidth, Bool()))
val will_fire_stad_incoming = Wire(Vec(memWidth, Bool()))
val will_fire_sta_incoming = Wire(Vec(memWidth, Bool()))
val will_fire_std_incoming = Wire(Vec(memWidth, Bool()))
val will_fire_sfence = Wire(Vec(memWidth, Bool()))
val will_fire_hella_incoming = Wire(Vec(memWidth, Bool()))
val will_fire_hella_wakeup = Wire(Vec(memWidth, Bool()))
val will_fire_release = Wire(Vec(memWidth, Bool()))
val will_fire_load_retry = Wire(Vec(memWidth, Bool()))
val will_fire_sta_retry = Wire(Vec(memWidth, Bool()))
val will_fire_store_commit = Wire(Vec(memWidth, Bool()))
val will_fire_load_wakeup = Wire(Vec(memWidth, Bool()))
val exe_req = WireInit(VecInit(io.core.exe.map(_.req)))
// Sfence goes through all pipes
for (i <- 0 until memWidth) {
when (io.core.exe(i).req.bits.sfence.valid) {
exe_req := VecInit(Seq.fill(memWidth) { io.core.exe(i).req })
}
}
// -------------------------------
// Assorted signals for scheduling
// Don't wakeup a load if we just sent it last cycle or two cycles ago
// The block_load_mask may be wrong, but the executing_load mask must be accurate
val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B)))
val p1_block_load_mask = RegNext(block_load_mask)
val p2_block_load_mask = RegNext(p1_block_load_mask)
// Prioritize emptying the store queue when it is almost full
val stq_almost_full = RegNext(WrapInc(WrapInc(st_enq_idx, numStqEntries), numStqEntries) === stq_head ||
WrapInc(st_enq_idx, numStqEntries) === stq_head)
// The store at the commit head needs the DCache to appear ordered
// Delay firing load wakeups and retries now
val store_needs_order = WireInit(false.B)
val ldq_incoming_idx = widthMap(i => exe_req(i).bits.uop.ldq_idx)
val ldq_incoming_e = widthMap(i => ldq(ldq_incoming_idx(i)))
val stq_incoming_idx = widthMap(i => exe_req(i).bits.uop.stq_idx)
val stq_incoming_e = widthMap(i => stq(stq_incoming_idx(i)))
val ldq_retry_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i => {
val e = ldq(i).bits
val block = block_load_mask(i) || p1_block_load_mask(i)
e.addr.valid && e.addr_is_virtual && !block
}), ldq_head))
val ldq_retry_e = ldq(ldq_retry_idx)
val stq_retry_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => {
val e = stq(i).bits
e.addr.valid && e.addr_is_virtual
}), stq_commit_head))
val stq_retry_e = stq(stq_retry_idx)
val stq_commit_e = stq(stq_execute_head)
val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> {
val e = ldq(i).bits
val block = block_load_mask(i) || p1_block_load_mask(i)
e.addr.valid && !e.executed && !e.succeeded && !e.addr_is_virtual && !block
}), ldq_head))
val ldq_wakeup_e = ldq(ldq_wakeup_idx)
// -----------------------
// Determine what can fire
// Can we fire a incoming load
val can_fire_load_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_load)
// Can we fire an incoming store addrgen + store datagen
val can_fire_stad_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta
&& exe_req(w).bits.uop.ctrl.is_std)
// Can we fire an incoming store addrgen
val can_fire_sta_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta
&& !exe_req(w).bits.uop.ctrl.is_std)
// Can we fire an incoming store datagen
val can_fire_std_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_std
&& !exe_req(w).bits.uop.ctrl.is_sta)
// Can we fire an incoming sfence
val can_fire_sfence = widthMap(w => exe_req(w).valid && exe_req(w).bits.sfence.valid)
// Can we fire a request from dcache to release a line
// This needs to go through LDQ search to mark loads as dangerous
val can_fire_release = widthMap(w => (w == memWidth-1).B && io.dmem.release.valid)
io.dmem.release.ready := will_fire_release.reduce(_||_)
// Can we retry a load that missed in the TLB
val can_fire_load_retry = widthMap(w =>
( ldq_retry_e.valid &&
ldq_retry_e.bits.addr.valid &&
ldq_retry_e.bits.addr_is_virtual &&
!p1_block_load_mask(ldq_retry_idx) &&
!p2_block_load_mask(ldq_retry_idx) &&
RegNext(dtlb.io.miss_rdy) &&
!store_needs_order &&
(w == memWidth-1).B && // TODO: Is this best scheduling?
!ldq_retry_e.bits.order_fail))
// Can we retry a store addrgen that missed in the TLB
// - Weird edge case when sta_retry and std_incoming for same entry in same cycle. Delay this
val can_fire_sta_retry = widthMap(w =>
( stq_retry_e.valid &&
stq_retry_e.bits.addr.valid &&
stq_retry_e.bits.addr_is_virtual &&
(w == memWidth-1).B &&
RegNext(dtlb.io.miss_rdy) &&
!(widthMap(i => (i != w).B &&
can_fire_std_incoming(i) &&
stq_incoming_idx(i) === stq_retry_idx).reduce(_||_))
))
// Can we commit a store
val can_fire_store_commit = widthMap(w =>
( stq_commit_e.valid &&
!stq_commit_e.bits.uop.is_fence &&
!mem_xcpt_valid &&
!stq_commit_e.bits.uop.exception &&
(w == 0).B &&
(stq_commit_e.bits.committed || ( stq_commit_e.bits.uop.is_amo &&
stq_commit_e.bits.addr.valid &&
!stq_commit_e.bits.addr_is_virtual &&
stq_commit_e.bits.data.valid))))
// Can we wakeup a load that was nack'd
val block_load_wakeup = WireInit(false.B)
val can_fire_load_wakeup = widthMap(w =>
( ldq_wakeup_e.valid &&
ldq_wakeup_e.bits.addr.valid &&
!ldq_wakeup_e.bits.succeeded &&
!ldq_wakeup_e.bits.addr_is_virtual &&
!ldq_wakeup_e.bits.executed &&
!ldq_wakeup_e.bits.order_fail &&
!p1_block_load_mask(ldq_wakeup_idx) &&
!p2_block_load_mask(ldq_wakeup_idx) &&
!store_needs_order &&
!block_load_wakeup &&
(w == memWidth-1).B &&
(!ldq_wakeup_e.bits.addr_is_uncacheable || (io.core.commit_load_at_rob_head &&
ldq_head === ldq_wakeup_idx &&
ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U))))
// Can we fire an incoming hellacache request
val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller
// Can we fire a hellacache request that the dcache nack'd
val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller
//---------------------------------------------------------
// Controller logic. Arbitrate which request actually fires
val exe_tlb_valid = Wire(Vec(memWidth, Bool()))
for (w <- 0 until memWidth) {
var tlb_avail = true.B
var dc_avail = true.B
var lcam_avail = true.B
var rob_avail = true.B
def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean, uses_rob:Boolean): Bool = {
val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) &&
!(uses_lcam.B && !lcam_avail) &&
!(uses_dc.B && !dc_avail) &&
!(uses_rob.B && !rob_avail)
tlb_avail = tlb_avail && !(will_fire && uses_tlb.B)
lcam_avail = lcam_avail && !(will_fire && uses_lcam.B)
dc_avail = dc_avail && !(will_fire && uses_dc.B)
rob_avail = rob_avail && !(will_fire && uses_rob.B)
dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals
will_fire
}
// The order of these statements is the priority
// Some restrictions
// - Incoming ops must get precedence, can't backpresure memaddrgen
// - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation)
// Notes on performance
// - Prioritize releases, this speeds up cache line writebacks and refills
// - Store commits are lowest priority, since they don't "block" younger instructions unless stq fills up
will_fire_load_incoming (w) := lsu_sched(can_fire_load_incoming (w) , true , true , true , false) // TLB , DC , LCAM
will_fire_stad_incoming (w) := lsu_sched(can_fire_stad_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB
will_fire_sta_incoming (w) := lsu_sched(can_fire_sta_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB
will_fire_std_incoming (w) := lsu_sched(can_fire_std_incoming (w) , false, false, false, true) // , ROB
will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false, true) // TLB , , , ROB
will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true , false) // LCAM
will_fire_hella_incoming(w) := lsu_sched(can_fire_hella_incoming(w) , true , true , false, false) // TLB , DC
will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false, false) // , DC
will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true , false) // TLB , DC , LCAM
will_fire_sta_retry (w) := lsu_sched(can_fire_sta_retry (w) , true , false, true , true) // TLB , , LCAM , ROB // TODO: This should be higher priority
will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true , false) // , DC , LCAM1
will_fire_store_commit (w) := lsu_sched(can_fire_store_commit (w) , false, true , false, false) // , DC
assert(!(exe_req(w).valid && !(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_std_incoming(w) || will_fire_sfence(w))))
when (will_fire_load_wakeup(w)) {
block_load_mask(ldq_wakeup_idx) := true.B
} .elsewhen (will_fire_load_incoming(w)) {
block_load_mask(exe_req(w).bits.uop.ldq_idx) := true.B
} .elsewhen (will_fire_load_retry(w)) {
block_load_mask(ldq_retry_idx) := true.B
}
exe_tlb_valid(w) := !tlb_avail
}
assert((memWidth == 1).B ||
(!(will_fire_sfence.reduce(_||_) && !will_fire_sfence.reduce(_&&_)) &&
!will_fire_hella_incoming.reduce(_&&_) &&
!will_fire_hella_wakeup.reduce(_&&_) &&
!will_fire_load_retry.reduce(_&&_) &&
!will_fire_sta_retry.reduce(_&&_) &&
!will_fire_store_commit.reduce(_&&_) &&
!will_fire_load_wakeup.reduce(_&&_)),
"Some operations is proceeding down multiple pipes")
require(memWidth <= 2)
//--------------------------------------------
// TLB Access
assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE),
"SFENCE through hella interface not supported")
val exe_tlb_uop = widthMap(w =>
Mux(will_fire_load_incoming (w) ||
will_fire_stad_incoming (w) ||
will_fire_sta_incoming (w) ||
will_fire_sfence (w) , exe_req(w).bits.uop,
Mux(will_fire_load_retry (w) , ldq_retry_e.bits.uop,
Mux(will_fire_sta_retry (w) , stq_retry_e.bits.uop,
Mux(will_fire_hella_incoming(w) , NullMicroOp,
NullMicroOp)))))
val exe_tlb_vaddr = widthMap(w =>
Mux(will_fire_load_incoming (w) ||
will_fire_stad_incoming (w) ||
will_fire_sta_incoming (w) , exe_req(w).bits.addr,
Mux(will_fire_sfence (w) , exe_req(w).bits.sfence.bits.addr,
Mux(will_fire_load_retry (w) , ldq_retry_e.bits.addr.bits,
Mux(will_fire_sta_retry (w) , stq_retry_e.bits.addr.bits,
Mux(will_fire_hella_incoming(w) , hella_req.addr,
0.U))))))
val exe_sfence = WireInit((0.U).asTypeOf(Valid(new rocket.SFenceReq)))
for (w <- 0 until memWidth) {
when (will_fire_sfence(w)) {
exe_sfence := exe_req(w).bits.sfence
}
}
val exe_size = widthMap(w =>
Mux(will_fire_load_incoming (w) ||
will_fire_stad_incoming (w) ||
will_fire_sta_incoming (w) ||
will_fire_sfence (w) ||
will_fire_load_retry (w) ||
will_fire_sta_retry (w) , exe_tlb_uop(w).mem_size,
Mux(will_fire_hella_incoming(w) , hella_req.size,
0.U)))
val exe_cmd = widthMap(w =>
Mux(will_fire_load_incoming (w) ||
will_fire_stad_incoming (w) ||
will_fire_sta_incoming (w) ||
will_fire_sfence (w) ||
will_fire_load_retry (w) ||
will_fire_sta_retry (w) , exe_tlb_uop(w).mem_cmd,
Mux(will_fire_hella_incoming(w) , hella_req.cmd,
0.U)))
val exe_passthr= widthMap(w =>
Mux(will_fire_hella_incoming(w) , hella_req.phys,
false.B))
val exe_kill = widthMap(w =>
Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill,
false.B))
for (w <- 0 until memWidth) {
dtlb.io.req(w).valid := exe_tlb_valid(w)
dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w)
dtlb.io.req(w).bits.size := exe_size(w)
dtlb.io.req(w).bits.cmd := exe_cmd(w)
dtlb.io.req(w).bits.passthrough := exe_passthr(w)
dtlb.io.req(w).bits.v := io.ptw.status.v
dtlb.io.req(w).bits.prv := io.ptw.status.prv
}
dtlb.io.kill := exe_kill.reduce(_||_)
dtlb.io.sfence := exe_sfence
// exceptions
val ma_ld = widthMap(w => will_fire_load_incoming(w) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc
val ma_st = widthMap(w => (will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc
val pf_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq)
val pf_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq)
val ae_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq)
val ae_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq)
// TODO check for xcpt_if and verify that never happens on non-speculative instructions.
val mem_xcpt_valids = RegNext(widthMap(w =>
(pf_ld(w) || pf_st(w) || ae_ld(w) || ae_st(w) || ma_ld(w) || ma_st(w)) &&
!io.core.exception &&
!IsKilledByBranch(io.core.brupdate, exe_tlb_uop(w))))
val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w))))
val mem_xcpt_causes = RegNext(widthMap(w =>
Mux(ma_ld(w), rocket.Causes.misaligned_load.U,
Mux(ma_st(w), rocket.Causes.misaligned_store.U,
Mux(pf_ld(w), rocket.Causes.load_page_fault.U,
Mux(pf_st(w), rocket.Causes.store_page_fault.U,
Mux(ae_ld(w), rocket.Causes.load_access.U,
rocket.Causes.store_access.U)))))))
val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr)
for (w <- 0 until memWidth) {
assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), "Fence is pretending to talk to the TLB")
assert (!((will_fire_load_incoming(w) || will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) &&
exe_req(w).bits.mxcpt.valid && dtlb.io.req(w).valid &&
!(exe_tlb_uop(w).ctrl.is_load || exe_tlb_uop(w).ctrl.is_sta)),
"A uop that's not a load or store-address is throwing a memory exception.")
}
mem_xcpt_valid := mem_xcpt_valids.reduce(_||_)
mem_xcpt_cause := mem_xcpt_causes(0)
mem_xcpt_uop := mem_xcpt_uops(0)
mem_xcpt_vaddr := mem_xcpt_vaddrs(0)
var xcpt_found = mem_xcpt_valids(0)
var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx
for (w <- 1 until memWidth) {
val is_older = WireInit(false.B)
when (mem_xcpt_valids(w) &&
(IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) || !xcpt_found)) {
is_older := true.B
mem_xcpt_cause := mem_xcpt_causes(w)
mem_xcpt_uop := mem_xcpt_uops(w)
mem_xcpt_vaddr := mem_xcpt_vaddrs(w)
}
xcpt_found = xcpt_found || mem_xcpt_valids(w)
oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx)
}
val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss || !dtlb.io.req(w).ready))
val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits),
exe_tlb_vaddr(w)(corePgIdxBits-1,0)))
val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable))
for (w <- 0 until memWidth) {
assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr || exe_req(w).bits.sfence.valid, "[lsu] paddrs should match.")
when (mem_xcpt_valids(w))
{
assert(RegNext(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) ||
will_fire_load_retry(w) || will_fire_sta_retry(w)))
// Technically only faulting AMOs need this
assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq)
when (mem_xcpt_uops(w).uses_ldq)
{
ldq(mem_xcpt_uops(w).ldq_idx).bits.uop.exception := true.B
}
.otherwise
{
stq(mem_xcpt_uops(w).stq_idx).bits.uop.exception := true.B
}
}
}
//------------------------------
// Issue Someting to Memory
//
// A memory op can come from many different places
// The address either was freshly translated, or we are
// reading a physical address from the LDQ,STQ, or the HellaCache adapter
// defaults
io.dmem.brupdate := io.core.brupdate
io.dmem.exception := io.core.exception
io.dmem.rob_head_idx := io.core.rob_head_idx
io.dmem.rob_pnr_idx := io.core.rob_pnr_idx
val dmem_req = Wire(Vec(memWidth, Valid(new BoomDCacheReq)))
io.dmem.req.valid := dmem_req.map(_.valid).reduce(_||_)
io.dmem.req.bits := dmem_req
val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire)
val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B)))
for (w <- 0 until memWidth) {
dmem_req(w).valid := false.B
dmem_req(w).bits.uop := NullMicroOp
dmem_req(w).bits.addr := 0.U
dmem_req(w).bits.data := 0.U
dmem_req(w).bits.is_hella := false.B
io.dmem.s1_kill(w) := false.B
when (will_fire_load_incoming(w)) {
dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w)
dmem_req(w).bits.addr := exe_tlb_paddr(w)
dmem_req(w).bits.uop := exe_tlb_uop(w)
s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w)
assert(!ldq_incoming_e(w).bits.executed)
} .elsewhen (will_fire_load_retry(w)) {
dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w)
dmem_req(w).bits.addr := exe_tlb_paddr(w)
dmem_req(w).bits.uop := exe_tlb_uop(w)
s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w)
assert(!ldq_retry_e.bits.executed)
} .elsewhen (will_fire_store_commit(w)) {
dmem_req(w).valid := true.B
dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits
dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(
stq_commit_e.bits.uop.mem_size, 0.U,
stq_commit_e.bits.data.bits,
coreDataBytes)).data
dmem_req(w).bits.uop := stq_commit_e.bits.uop
stq_execute_head := Mux(dmem_req_fire(w),
WrapInc(stq_execute_head, numStqEntries),
stq_execute_head)
stq(stq_execute_head).bits.succeeded := false.B
} .elsewhen (will_fire_load_wakeup(w)) {
dmem_req(w).valid := true.B
dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits
dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop
s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w)
assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual)
} .elsewhen (will_fire_hella_incoming(w)) {
assert(hella_state === h_s1)
dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) || hella_req.phys)
dmem_req(w).bits.addr := exe_tlb_paddr(w)
dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(
hella_req.size, 0.U,
io.hellacache.s1_data.data,
coreDataBytes)).data
dmem_req(w).bits.uop.mem_cmd := hella_req.cmd
dmem_req(w).bits.uop.mem_size := hella_req.size
dmem_req(w).bits.uop.mem_signed := hella_req.signed
dmem_req(w).bits.is_hella := true.B
hella_paddr := exe_tlb_paddr(w)
}
.elsewhen (will_fire_hella_wakeup(w))
{
assert(hella_state === h_replay)
dmem_req(w).valid := true.B
dmem_req(w).bits.addr := hella_paddr
dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(
hella_req.size, 0.U,
hella_data.data,
coreDataBytes)).data
dmem_req(w).bits.uop.mem_cmd := hella_req.cmd
dmem_req(w).bits.uop.mem_size := hella_req.size
dmem_req(w).bits.uop.mem_signed := hella_req.signed
dmem_req(w).bits.is_hella := true.B
}
//-------------------------------------------------------------
// Write Addr into the LAQ/SAQ
when (will_fire_load_incoming(w) || will_fire_load_retry(w))
{
val ldq_idx = Mux(will_fire_load_incoming(w), ldq_incoming_idx(w), ldq_retry_idx)
ldq(ldq_idx).bits.addr.valid := true.B
ldq(ldq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w))
ldq(ldq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst
ldq(ldq_idx).bits.addr_is_virtual := exe_tlb_miss(w)
ldq(ldq_idx).bits.addr_is_uncacheable := exe_tlb_uncacheable(w) && !exe_tlb_miss(w)
assert(!(will_fire_load_incoming(w) && ldq_incoming_e(w).bits.addr.valid),
"[lsu] Incoming load is overwriting a valid address")
}
when (will_fire_sta_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_retry(w))
{
val stq_idx = Mux(will_fire_sta_incoming(w) || will_fire_stad_incoming(w),
stq_incoming_idx(w), stq_retry_idx)
stq(stq_idx).bits.addr.valid := !pf_st(w) // Prevent AMOs from executing!
stq(stq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w))
stq(stq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst // Needed for AMOs
stq(stq_idx).bits.addr_is_virtual := exe_tlb_miss(w)
assert(!(will_fire_sta_incoming(w) && stq_incoming_e(w).bits.addr.valid),
"[lsu] Incoming store is overwriting a valid address")
}
//-------------------------------------------------------------
// Write data into the STQ
if (w == 0)
io.core.fp_stdata.ready := !will_fire_std_incoming(w) && !will_fire_stad_incoming(w)
val fp_stdata_fire = io.core.fp_stdata.fire && (w == 0).B
when (will_fire_std_incoming(w) || will_fire_stad_incoming(w) || fp_stdata_fire)
{
val sidx = Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w),
stq_incoming_idx(w),
io.core.fp_stdata.bits.uop.stq_idx)
stq(sidx).bits.data.valid := true.B
stq(sidx).bits.data.bits := Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w),
exe_req(w).bits.data,
io.core.fp_stdata.bits.data)
assert(!(stq(sidx).bits.data.valid),
"[lsu] Incoming store is overwriting a valid data entry")
}
}
val will_fire_stdf_incoming = io.core.fp_stdata.fire
require (xLen >= fLen) // for correct SDQ size
//-------------------------------------------------------------
//-------------------------------------------------------------
// Cache Access Cycle (Mem)
//-------------------------------------------------------------
//-------------------------------------------------------------
// Note the DCache may not have accepted our request
val exe_req_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, exe_req(w).bits.uop))
val stdf_killed = IsKilledByBranch(io.core.brupdate, io.core.fp_stdata.bits.uop)
val fired_load_incoming = widthMap(w => RegNext(will_fire_load_incoming(w) && !exe_req_killed(w)))
val fired_stad_incoming = widthMap(w => RegNext(will_fire_stad_incoming(w) && !exe_req_killed(w)))
val fired_sta_incoming = widthMap(w => RegNext(will_fire_sta_incoming (w) && !exe_req_killed(w)))
val fired_std_incoming = widthMap(w => RegNext(will_fire_std_incoming (w) && !exe_req_killed(w)))
val fired_stdf_incoming = RegNext(will_fire_stdf_incoming && !stdf_killed)
val fired_sfence = RegNext(will_fire_sfence)
val fired_release = RegNext(will_fire_release)
val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, ldq_retry_e.bits.uop)))
val fired_sta_retry = widthMap(w => RegNext(will_fire_sta_retry (w) && !IsKilledByBranch(io.core.brupdate, stq_retry_e.bits.uop)))
val fired_store_commit = RegNext(will_fire_store_commit)
val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, ldq_wakeup_e.bits.uop)))
val fired_hella_incoming = RegNext(will_fire_hella_incoming)
val fired_hella_wakeup = RegNext(will_fire_hella_wakeup)
val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_req(w).bits.uop)))
val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, ldq_incoming_e(w))))
val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, stq_incoming_e(w))))
val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_wakeup_e))
val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_retry_e))
val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, stq_retry_e))
val mem_ldq_e = widthMap(w =>
Mux(fired_load_incoming(w), mem_ldq_incoming_e(w),
Mux(fired_load_retry (w), mem_ldq_retry_e,
Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry))))))
val mem_stq_e = widthMap(w =>
Mux(fired_stad_incoming(w) ||
fired_sta_incoming (w), mem_stq_incoming_e(w),
Mux(fired_sta_retry (w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry)))))
val mem_stdf_uop = RegNext(UpdateBrMask(io.core.brupdate, io.core.fp_stdata.bits.uop))
val mem_tlb_miss = RegNext(exe_tlb_miss)
val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable)
val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr))
// Task 1: Clr ROB busy bit
val clr_bsy_valid = RegInit(widthMap(w => false.B))
val clr_bsy_rob_idx = Reg(Vec(memWidth, UInt(robAddrSz.W)))
val clr_bsy_brmask = Reg(Vec(memWidth, UInt(maxBrCount.W)))
for (w <- 0 until memWidth) {
clr_bsy_valid (w) := false.B
clr_bsy_rob_idx (w) := 0.U
clr_bsy_brmask (w) := 0.U
when (fired_stad_incoming(w)) {
clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&
!mem_tlb_miss(w) &&
!mem_stq_incoming_e(w).bits.uop.is_amo &&
!IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)
clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx
clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)
} .elsewhen (fired_sta_incoming(w)) {
clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&
mem_stq_incoming_e(w).bits.data.valid &&
!mem_tlb_miss(w) &&
!mem_stq_incoming_e(w).bits.uop.is_amo &&
!IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)
clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx
clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)
} .elsewhen (fired_std_incoming(w)) {
clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&
mem_stq_incoming_e(w).bits.addr.valid &&
!mem_stq_incoming_e(w).bits.addr_is_virtual &&
!mem_stq_incoming_e(w).bits.uop.is_amo &&
!IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)
clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx
clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)
} .elsewhen (fired_sfence(w)) {
clr_bsy_valid (w) := (w == 0).B // SFence proceeds down all paths, only allow one to clr the rob
clr_bsy_rob_idx (w) := mem_incoming_uop(w).rob_idx
clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_incoming_uop(w))
} .elsewhen (fired_sta_retry(w)) {
clr_bsy_valid (w) := mem_stq_retry_e.valid &&
mem_stq_retry_e.bits.data.valid &&
!mem_tlb_miss(w) &&
!mem_stq_retry_e.bits.uop.is_amo &&
!IsKilledByBranch(io.core.brupdate, mem_stq_retry_e.bits.uop)
clr_bsy_rob_idx (w) := mem_stq_retry_e.bits.uop.rob_idx
clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_retry_e.bits.uop)
}
io.core.clr_bsy(w).valid := clr_bsy_valid(w) &&
!IsKilledByBranch(io.core.brupdate, clr_bsy_brmask(w)) &&
!io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception))
io.core.clr_bsy(w).bits := clr_bsy_rob_idx(w)
}
val stdf_clr_bsy_valid = RegInit(false.B)
val stdf_clr_bsy_rob_idx = Reg(UInt(robAddrSz.W))
val stdf_clr_bsy_brmask = Reg(UInt(maxBrCount.W))
stdf_clr_bsy_valid := false.B
stdf_clr_bsy_rob_idx := 0.U
stdf_clr_bsy_brmask := 0.U
when (fired_stdf_incoming) {
val s_idx = mem_stdf_uop.stq_idx
stdf_clr_bsy_valid := stq(s_idx).valid &&
stq(s_idx).bits.addr.valid &&
!stq(s_idx).bits.addr_is_virtual &&
!stq(s_idx).bits.uop.is_amo &&
!IsKilledByBranch(io.core.brupdate, mem_stdf_uop)
stdf_clr_bsy_rob_idx := mem_stdf_uop.rob_idx
stdf_clr_bsy_brmask := GetNewBrMask(io.core.brupdate, mem_stdf_uop)
}
io.core.clr_bsy(memWidth).valid := stdf_clr_bsy_valid &&
!IsKilledByBranch(io.core.brupdate, stdf_clr_bsy_brmask) &&
!io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception))
io.core.clr_bsy(memWidth).bits := stdf_clr_bsy_rob_idx
// Task 2: Do LD-LD. ST-LD searches for ordering failures
// Do LD-ST search for forwarding opportunities
// We have the opportunity to kill a request we sent last cycle. Use it wisely!
// We translated a store last cycle
val do_st_search = widthMap(w => (fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w)) && !mem_tlb_miss(w))
// We translated a load last cycle
val do_ld_search = widthMap(w => ((fired_load_incoming(w) || fired_load_retry(w)) && !mem_tlb_miss(w)) ||
fired_load_wakeup(w))
// We are making a local line visible to other harts
val do_release_search = widthMap(w => fired_release(w))
// Store addrs don't go to memory yet, get it from the TLB response
// Load wakeups don't go through TLB, get it through memory
// Load incoming and load retries go through both
val lcam_addr = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w),
RegNext(exe_tlb_paddr(w)),
Mux(fired_release(w), RegNext(io.dmem.release.bits.address),
mem_paddr(w))))
val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop,
Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp)))
val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size))
val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask)
val lcam_is_release = widthMap(w => fired_release(w))
val lcam_ldq_idx = widthMap(w =>
Mux(fired_load_incoming(w), mem_incoming_uop(w).ldq_idx,
Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx),
Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U))))
val lcam_stq_idx = widthMap(w =>
Mux(fired_stad_incoming(w) ||
fired_sta_incoming (w), mem_incoming_uop(w).stq_idx,
Mux(fired_sta_retry (w), RegNext(stq_retry_idx), 0.U)))
val can_forward = WireInit(widthMap(w =>
Mux(fired_load_incoming(w) || fired_load_retry(w), !mem_tlb_uncacheable(w),
!ldq(lcam_ldq_idx(w)).bits.addr_is_uncacheable)))
// Mask of stores which we conflict on address with
val ldst_addr_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B))))
// Mask of stores which we can forward from
val ldst_forward_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B))))
val failed_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which we will report as failures (throws a mini-exception)
val nacking_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which are being nacked by dcache in the next stage
val s1_executing_loads = RegNext(s0_executing_loads)
val s1_set_execute = WireInit(s1_executing_loads)
val mem_forward_valid = Wire(Vec(memWidth, Bool()))
val mem_forward_ldq_idx = lcam_ldq_idx
val mem_forward_ld_addr = lcam_addr
val mem_forward_stq_idx = Wire(Vec(memWidth, UInt(log2Ceil(numStqEntries).W)))
val wb_forward_valid = RegNext(mem_forward_valid)
val wb_forward_ldq_idx = RegNext(mem_forward_ldq_idx)
val wb_forward_ld_addr = RegNext(mem_forward_ld_addr)
val wb_forward_stq_idx = RegNext(mem_forward_stq_idx)
for (i <- 0 until numLdqEntries) {
val l_valid = ldq(i).valid
val l_bits = ldq(i).bits
val l_addr = ldq(i).bits.addr.bits
val l_mask = GenByteMask(l_addr, l_bits.uop.mem_size)
val l_forwarders = widthMap(w => wb_forward_valid(w) && wb_forward_ldq_idx(w) === i.U)
val l_is_forwarding = l_forwarders.reduce(_||_)
val l_forward_stq_idx = Mux(l_is_forwarding, Mux1H(l_forwarders, wb_forward_stq_idx), l_bits.forward_stq_idx)
val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr >> blockOffBits)
val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr(blockOffBits-1,3))
val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask)
val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR)
// Searcher is a store
for (w <- 0 until memWidth) {
when (do_release_search(w) &&
l_valid &&
l_bits.addr.valid &&
block_addr_matches(w)) {
// This load has been observed, so if a younger load to the same address has not
// executed yet, this load must be squashed
ldq(i).bits.observed := true.B
} .elsewhen (do_st_search(w) &&
l_valid &&
l_bits.addr.valid &&
(l_bits.executed || l_bits.succeeded || l_is_forwarding) &&
!l_bits.addr_is_virtual &&
l_bits.st_dep_mask(lcam_stq_idx(w)) &&
dword_addr_matches(w) &&
mask_overlap(w)) {
val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_bits.youngest_stq_idx)
// We are older than this load, which overlapped us.
when (!l_bits.forward_std_val || // If the load wasn't forwarded, it definitely failed
((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok
ldq(i).bits.order_fail := true.B
failed_loads(i) := true.B
}
} .elsewhen (do_ld_search(w) &&
l_valid &&
l_bits.addr.valid &&
!l_bits.addr_is_virtual &&
dword_addr_matches(w) &&
mask_overlap(w)) {
val searcher_is_older = IsOlder(lcam_ldq_idx(w), i.U, ldq_head)
when (searcher_is_older) {
when ((l_bits.executed || l_bits.succeeded || l_is_forwarding) &&
!s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it
l_bits.observed) { // Its only a ordering failure if the cache line was observed between the younger load and us
ldq(i).bits.order_fail := true.B
failed_loads(i) := true.B
}
} .elsewhen (lcam_ldq_idx(w) =/= i.U) {
// The load is older, and either it hasn't executed, it was nacked, or it is ignoring its response
// we need to kill ourselves, and prevent forwarding
val older_nacked = nacking_loads(i) || RegNext(nacking_loads(i))
when (!(l_bits.executed || l_bits.succeeded) || older_nacked) {
s1_set_execute(lcam_ldq_idx(w)) := false.B
io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))
can_forward(w) := false.B
}
}
}
}
}
for (i <- 0 until numStqEntries) {
val s_addr = stq(i).bits.addr.bits
val s_uop = stq(i).bits.uop
val dword_addr_matches = widthMap(w =>
( stq(i).bits.addr.valid &&
!stq(i).bits.addr_is_virtual &&
(s_addr(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3))))
val write_mask = GenByteMask(s_addr, s_uop.mem_size)
for (w <- 0 until memWidth) {
when (do_ld_search(w) && stq(i).valid && lcam_st_dep_mask(w)(i)) {
when (((lcam_mask(w) & write_mask) === lcam_mask(w)) && !s_uop.is_fence && !s_uop.is_amo && dword_addr_matches(w) && can_forward(w))
{
ldst_addr_matches(w)(i) := true.B
ldst_forward_matches(w)(i) := true.B
io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))
s1_set_execute(lcam_ldq_idx(w)) := false.B
}
.elsewhen (((lcam_mask(w) & write_mask) =/= 0.U) && dword_addr_matches(w))
{
ldst_addr_matches(w)(i) := true.B
io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))
s1_set_execute(lcam_ldq_idx(w)) := false.B
}
.elsewhen (s_uop.is_fence || s_uop.is_amo)
{
ldst_addr_matches(w)(i) := true.B
io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))
s1_set_execute(lcam_ldq_idx(w)) := false.B
}
}
}
}
// Set execute bit in LDQ
for (i <- 0 until numLdqEntries) {
when (s1_set_execute(i)) { ldq(i).bits.executed := true.B }
}
// Find the youngest store which the load is dependent on
val forwarding_age_logic = Seq.fill(memWidth) { Module(new ForwardingAgeLogic(numStqEntries)) }
for (w <- 0 until memWidth) {
forwarding_age_logic(w).io.addr_matches := ldst_addr_matches(w).asUInt
forwarding_age_logic(w).io.youngest_st_idx := lcam_uop(w).stq_idx
}
val forwarding_idx = widthMap(w => forwarding_age_logic(w).io.forwarding_idx)
// Forward if st-ld forwarding is possible from the writemask and loadmask
mem_forward_valid := widthMap(w =>
(ldst_forward_matches(w)(forwarding_idx(w)) &&
!IsKilledByBranch(io.core.brupdate, lcam_uop(w)) &&
!io.core.exception && !RegNext(io.core.exception)))
mem_forward_stq_idx := forwarding_idx
// Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits
// On a 2W machine, load wakeups and store commits occupy separate pipelines,
// so only add this logic for 1-w LSU
if (memWidth == 1) {
// Wakeups may repeatedly find a st->ld addr conflict and fail to forward,
// repeated wakeups may block the store from ever committing
// Disallow load wakeups 1 cycle after this happens to allow the stores to drain
when (RegNext(ldst_addr_matches(0).reduce(_||_) && !mem_forward_valid(0))) {
block_load_wakeup := true.B
}
// If stores remain blocked for 15 cycles, block load wakeups to get a store through
val store_blocked_counter = Reg(UInt(4.W))
when (will_fire_store_commit(0) || !can_fire_store_commit(0)) {
store_blocked_counter := 0.U
} .elsewhen (can_fire_store_commit(0) && !will_fire_store_commit(0)) {
store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U)
}
when (store_blocked_counter === 15.U) {
block_load_wakeup := true.B
}
}
// Task 3: Clr unsafe bit in ROB for succesful translations
// Delay this a cycle to avoid going ahead of the exception broadcast
// The unsafe bit is cleared on the first translation, so no need to fire for load wakeups
for (w <- 0 until memWidth) {
io.core.clr_unsafe(w).valid := RegNext((do_st_search(w) || do_ld_search(w)) && !fired_load_wakeup(w)) && false.B
io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx)
}
// detect which loads get marked as failures, but broadcast to the ROB the oldest failing load
// TODO encapsulate this in an age-based priority-encoder
// val l_idx = AgePriorityEncoder((Vec(Vec.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= laq_head)
// ++ failed_loads)).asUInt)
val temp_bits = (VecInit(VecInit.tabulate(numLdqEntries)(i =>
failed_loads(i) && i.U >= ldq_head) ++ failed_loads)).asUInt
val l_idx = PriorityEncoder(temp_bits)
// one exception port, but multiple causes!
// - 1) the incoming store-address finds a faulting load (it is by definition younger)
// - 2) the incoming load or store address is excepting. It must be older and thus takes precedent.
val r_xcpt_valid = RegInit(false.B)
val r_xcpt = Reg(new Exception)
val ld_xcpt_valid = failed_loads.reduce(_|_)
val ld_xcpt_uop = ldq(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx)).bits.uop
val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) || !ld_xcpt_valid
val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop)
r_xcpt_valid := (ld_xcpt_valid || mem_xcpt_valid) &&
!io.core.exception &&
!IsKilledByBranch(io.core.brupdate, xcpt_uop)
r_xcpt.uop := xcpt_uop
r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop)
r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING)
r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead?
io.core.lxcpt.valid := r_xcpt_valid && !io.core.exception && !IsKilledByBranch(io.core.brupdate, r_xcpt.uop)
io.core.lxcpt.bits := r_xcpt
// Task 4: Speculatively wakeup loads 1 cycle before they come back
for (w <- 0 until memWidth) {
io.core.spec_ld_wakeup(w).valid := enableFastLoadUse.B &&
fired_load_incoming(w) &&
!mem_incoming_uop(w).fp_val &&
mem_incoming_uop(w).pdst =/= 0.U
io.core.spec_ld_wakeup(w).bits := mem_incoming_uop(w).pdst
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// Writeback Cycle (St->Ld Forwarding Path)
//-------------------------------------------------------------
//-------------------------------------------------------------
// Handle Memory Responses and nacks
//----------------------------------
for (w <- 0 until memWidth) {
io.core.exe(w).iresp.valid := false.B
io.core.exe(w).iresp.bits := DontCare
io.core.exe(w).fresp.valid := false.B
io.core.exe(w).fresp.bits := DontCare
}
val dmem_resp_fired = WireInit(widthMap(w => false.B))
for (w <- 0 until memWidth) {
// Handle nacks
when (io.dmem.nack(w).valid)
{
// We have to re-execute this!
when (io.dmem.nack(w).bits.is_hella)
{
assert(hella_state === h_wait || hella_state === h_dead)
}
.elsewhen (io.dmem.nack(w).bits.uop.uses_ldq)
{
assert(ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed)
ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed := false.B
nacking_loads(io.dmem.nack(w).bits.uop.ldq_idx) := true.B
}
.otherwise
{
assert(io.dmem.nack(w).bits.uop.uses_stq)
when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) {
stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx
}
}
}
// Handle the response
when (io.dmem.resp(w).valid)
{
when (io.dmem.resp(w).bits.uop.uses_ldq)
{
assert(!io.dmem.resp(w).bits.is_hella)
val ldq_idx = io.dmem.resp(w).bits.uop.ldq_idx
val send_iresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FIX
val send_fresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FLT
io.core.exe(w).iresp.bits.uop := ldq(ldq_idx).bits.uop
io.core.exe(w).fresp.bits.uop := ldq(ldq_idx).bits.uop
io.core.exe(w).iresp.valid := send_iresp
io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data
io.core.exe(w).fresp.valid := send_fresp
io.core.exe(w).fresp.bits.data := io.dmem.resp(w).bits.data
assert(send_iresp ^ send_fresp)
dmem_resp_fired(w) := true.B
ldq(ldq_idx).bits.succeeded := io.core.exe(w).iresp.valid || io.core.exe(w).fresp.valid
ldq(ldq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data
}
.elsewhen (io.dmem.resp(w).bits.uop.uses_stq)
{
assert(!io.dmem.resp(w).bits.is_hella)
stq(io.dmem.resp(w).bits.uop.stq_idx).bits.succeeded := true.B
when (io.dmem.resp(w).bits.uop.is_amo) {
dmem_resp_fired(w) := true.B
io.core.exe(w).iresp.valid := true.B
io.core.exe(w).iresp.bits.uop := stq(io.dmem.resp(w).bits.uop.stq_idx).bits.uop
io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data
stq(io.dmem.resp(w).bits.uop.stq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data
}
}
}
when (dmem_resp_fired(w) && wb_forward_valid(w))
{
// Twiddle thumbs. Can't forward because dcache response takes precedence
}
.elsewhen (!dmem_resp_fired(w) && wb_forward_valid(w))
{
val f_idx = wb_forward_ldq_idx(w)
val forward_uop = ldq(f_idx).bits.uop
val stq_e = stq(wb_forward_stq_idx(w))
val data_ready = stq_e.bits.data.valid
val live = !IsKilledByBranch(io.core.brupdate, forward_uop)
val storegen = new freechips.rocketchip.rocket.StoreGen(
stq_e.bits.uop.mem_size, stq_e.bits.addr.bits,
stq_e.bits.data.bits, coreDataBytes)
val loadgen = new freechips.rocketchip.rocket.LoadGen(
forward_uop.mem_size, forward_uop.mem_signed,
wb_forward_ld_addr(w),
storegen.data, false.B, coreDataBytes)
io.core.exe(w).iresp.valid := (forward_uop.dst_rtype === RT_FIX) && data_ready && live
io.core.exe(w).fresp.valid := (forward_uop.dst_rtype === RT_FLT) && data_ready && live
io.core.exe(w).iresp.bits.uop := forward_uop
io.core.exe(w).fresp.bits.uop := forward_uop
io.core.exe(w).iresp.bits.data := loadgen.data
io.core.exe(w).fresp.bits.data := loadgen.data
when (data_ready && live) {
ldq(f_idx).bits.succeeded := data_ready
ldq(f_idx).bits.forward_std_val := true.B
ldq(f_idx).bits.forward_stq_idx := wb_forward_stq_idx(w)
ldq(f_idx).bits.debug_wb_data := loadgen.data
}
}
}
// Initially assume the speculative load wakeup failed
io.core.ld_miss := RegNext(io.core.spec_ld_wakeup.map(_.valid).reduce(_||_))
val spec_ld_succeed = widthMap(w =>
!RegNext(io.core.spec_ld_wakeup(w).valid) ||
(io.core.exe(w).iresp.valid &&
io.core.exe(w).iresp.bits.uop.ldq_idx === RegNext(mem_incoming_uop(w).ldq_idx)
)
).reduce(_&&_)
when (spec_ld_succeed) {
io.core.ld_miss := false.B
}
//-------------------------------------------------------------
// Kill speculated entries on branch mispredict
//-------------------------------------------------------------
//-------------------------------------------------------------
// Kill stores
val st_brkilled_mask = Wire(Vec(numStqEntries, Bool()))
for (i <- 0 until numStqEntries)
{
st_brkilled_mask(i) := false.B
when (stq(i).valid)
{
stq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, stq(i).bits.uop.br_mask)
when (IsKilledByBranch(io.core.brupdate, stq(i).bits.uop))
{
stq(i).valid := false.B
stq(i).bits.addr.valid := false.B
stq(i).bits.data.valid := false.B
st_brkilled_mask(i) := true.B
}
}
assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),
"Branch is trying to clear a committed store.")
}
// Kill loads
for (i <- 0 until numLdqEntries)
{
when (ldq(i).valid)
{
ldq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, ldq(i).bits.uop.br_mask)
when (IsKilledByBranch(io.core.brupdate, ldq(i).bits.uop))
{
ldq(i).valid := false.B
ldq(i).bits.addr.valid := false.B
}
}
}
//-------------------------------------------------------------
when (io.core.brupdate.b2.mispredict && !io.core.exception)
{
stq_tail := io.core.brupdate.b2.uop.stq_idx
ldq_tail := io.core.brupdate.b2.uop.ldq_idx
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// dequeue old entries on commit
//-------------------------------------------------------------
//-------------------------------------------------------------
var temp_stq_commit_head = stq_commit_head
var temp_ldq_head = ldq_head
for (w <- 0 until coreWidth)
{
val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq
val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq
val idx = Mux(commit_store, temp_stq_commit_head, temp_ldq_head)
when (commit_store)
{
stq(idx).bits.committed := true.B
} .elsewhen (commit_load) {
assert (ldq(idx).valid, "[lsu] trying to commit an un-allocated load entry.")
assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded ,
"[lsu] trying to commit an un-executed load entry.")
ldq(idx).valid := false.B
ldq(idx).bits.addr.valid := false.B
ldq(idx).bits.executed := false.B
ldq(idx).bits.succeeded := false.B
ldq(idx).bits.order_fail := false.B
ldq(idx).bits.forward_std_val := false.B
}
if (MEMTRACE_PRINTF) {
when (commit_store || commit_load) {
val uop = Mux(commit_store, stq(idx).bits.uop, ldq(idx).bits.uop)
val addr = Mux(commit_store, stq(idx).bits.addr.bits, ldq(idx).bits.addr.bits)
val stdata = Mux(commit_store, stq(idx).bits.data.bits, 0.U)
val wbdata = Mux(commit_store, stq(idx).bits.debug_wb_data, ldq(idx).bits.debug_wb_data)
printf("MT %x %x %x %x %x %x %x\n",
io.core.tsc_reg, uop.uopc, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata)
}
}
temp_stq_commit_head = Mux(commit_store,
WrapInc(temp_stq_commit_head, numStqEntries),
temp_stq_commit_head)
temp_ldq_head = Mux(commit_load,
WrapInc(temp_ldq_head, numLdqEntries),
temp_ldq_head)
}
stq_commit_head := temp_stq_commit_head
ldq_head := temp_ldq_head
// store has been committed AND successfully sent data to memory
when (stq(stq_head).valid && stq(stq_head).bits.committed)
{
when (stq(stq_head).bits.uop.is_fence && !io.dmem.ordered) {
io.dmem.force_order := true.B
store_needs_order := true.B
}
clear_store := Mux(stq(stq_head).bits.uop.is_fence, io.dmem.ordered,
stq(stq_head).bits.succeeded)
}
when (clear_store)
{
stq(stq_head).valid := false.B
stq(stq_head).bits.addr.valid := false.B
stq(stq_head).bits.data.valid := false.B
stq(stq_head).bits.succeeded := false.B
stq(stq_head).bits.committed := false.B
stq_head := WrapInc(stq_head, numStqEntries)
when (stq(stq_head).bits.uop.is_fence)
{
stq_execute_head := WrapInc(stq_execute_head, numStqEntries)
}
}
// -----------------------
// Hellacache interface
// We need to time things like a HellaCache would
io.hellacache.req.ready := false.B
io.hellacache.s2_nack := false.B
io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions)
io.hellacache.resp.valid := false.B
io.hellacache.store_pending := stq.map(_.valid).reduce(_||_)
when (hella_state === h_ready) {
io.hellacache.req.ready := true.B
when (io.hellacache.req.fire) {
hella_req := io.hellacache.req.bits
hella_state := h_s1
}
} .elsewhen (hella_state === h_s1) {
can_fire_hella_incoming(memWidth-1) := true.B
hella_data := io.hellacache.s1_data
hella_xcpt := dtlb.io.resp(memWidth-1)
when (io.hellacache.s1_kill) {
when (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) {
hella_state := h_dead
} .otherwise {
hella_state := h_ready
}
} .elsewhen (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) {
hella_state := h_s2
} .otherwise {
hella_state := h_s2_nack
}
} .elsewhen (hella_state === h_s2_nack) {
io.hellacache.s2_nack := true.B
hella_state := h_ready
} .elsewhen (hella_state === h_s2) {
io.hellacache.s2_xcpt := hella_xcpt
when (io.hellacache.s2_kill || hella_xcpt.asUInt =/= 0.U) {
hella_state := h_dead
} .otherwise {
hella_state := h_wait
}
} .elsewhen (hella_state === h_wait) {
for (w <- 0 until memWidth) {
when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) {
hella_state := h_ready
io.hellacache.resp.valid := true.B
io.hellacache.resp.bits.addr := hella_req.addr
io.hellacache.resp.bits.tag := hella_req.tag
io.hellacache.resp.bits.cmd := hella_req.cmd
io.hellacache.resp.bits.signed := hella_req.signed
io.hellacache.resp.bits.size := hella_req.size
io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data
} .elsewhen (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) {
hella_state := h_replay
}
}
} .elsewhen (hella_state === h_replay) {
can_fire_hella_wakeup(memWidth-1) := true.B
when (will_fire_hella_wakeup(memWidth-1) && dmem_req_fire(memWidth-1)) {
hella_state := h_wait
}
} .elsewhen (hella_state === h_dead) {
for (w <- 0 until memWidth) {
when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) {
hella_state := h_ready
}
}
}
//-------------------------------------------------------------
// Exception / Reset
// for the live_store_mask, need to kill stores that haven't been committed
val st_exc_killed_mask = WireInit(VecInit((0 until numStqEntries).map(x=>false.B)))
when (reset.asBool || io.core.exception)
{
ldq_head := 0.U
ldq_tail := 0.U
when (reset.asBool)
{
stq_head := 0.U
stq_tail := 0.U
stq_commit_head := 0.U
stq_execute_head := 0.U
for (i <- 0 until numStqEntries)
{
stq(i).valid := false.B
stq(i).bits.addr.valid := false.B
stq(i).bits.data.valid := false.B
stq(i).bits.uop := NullMicroOp
}
}
.otherwise // exception
{
stq_tail := stq_commit_head
for (i <- 0 until numStqEntries)
{
when (!stq(i).bits.committed && !stq(i).bits.succeeded)
{
stq(i).valid := false.B
stq(i).bits.addr.valid := false.B
stq(i).bits.data.valid := false.B
st_exc_killed_mask(i) := true.B
}
}
}
for (i <- 0 until numLdqEntries)
{
ldq(i).valid := false.B
ldq(i).bits.addr.valid := false.B
ldq(i).bits.executed := false.B
}
}
//-------------------------------------------------------------
// Live Store Mask
// track a bit-array of stores that are alive
// (could maybe be re-produced from the stq_head/stq_tail, but need to know include spec_killed entries)
// TODO is this the most efficient way to compute the live store mask?
live_store_mask := next_live_store_mask &
~(st_brkilled_mask.asUInt) &
~(st_exc_killed_mask.asUInt)
}
/**
* Object to take an address and generate an 8-bit mask of which bytes within a
* double-word.
*/
object GenByteMask
{
def apply(addr: UInt, size: UInt): UInt =
{
val mask = Wire(UInt(8.W))
mask := MuxCase(255.U(8.W), Array(
(size === 0.U) -> (1.U(8.W) << addr(2,0)),
(size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)),
(size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)),
(size === 3.U) -> 255.U(8.W)))
mask
}
}
/**
* ...
*/
class ForwardingAgeLogic(num_entries: Int)(implicit p: Parameters) extends BoomModule()(p)
{
val io = IO(new Bundle
{
val addr_matches = Input(UInt(num_entries.W)) // bit vector of addresses that match
// between the load and the SAQ
val youngest_st_idx = Input(UInt(stqAddrSz.W)) // needed to get "age"
val forwarding_val = Output(Bool())
val forwarding_idx = Output(UInt(stqAddrSz.W))
})
// generating mask that zeroes out anything younger than tail
val age_mask = Wire(Vec(num_entries, Bool()))
for (i <- 0 until num_entries)
{
age_mask(i) := true.B
when (i.U >= io.youngest_st_idx) // currently the tail points PAST last store, so use >=
{
age_mask(i) := false.B
}
}
// Priority encoder with moving tail: double length
val matches = Wire(UInt((2*num_entries).W))
matches := Cat(io.addr_matches & age_mask.asUInt,
io.addr_matches)
val found_match = Wire(Bool())
found_match := false.B
io.forwarding_idx := 0.U
// look for youngest, approach from the oldest side, let the last one found stick
for (i <- 0 until (2*num_entries))
{
when (matches(i))
{
found_match := true.B
io.forwarding_idx := (i % num_entries).U
}
}
io.forwarding_val := found_match
} | module LSU(
input clock,
input reset,
input io_ptw_req_ready,
output io_ptw_req_valid,
output io_ptw_req_bits_valid,
output [26:0] io_ptw_req_bits_bits_addr,
input io_ptw_resp_valid,
input io_ptw_resp_bits_ae_final,
input [43:0] io_ptw_resp_bits_pte_ppn,
input io_ptw_resp_bits_pte_d,
input io_ptw_resp_bits_pte_a,
input io_ptw_resp_bits_pte_g,
input io_ptw_resp_bits_pte_u,
input io_ptw_resp_bits_pte_x,
input io_ptw_resp_bits_pte_w,
input io_ptw_resp_bits_pte_r,
input io_ptw_resp_bits_pte_v,
input [1:0] io_ptw_resp_bits_level,
input io_ptw_resp_bits_homogeneous,
input [3:0] io_ptw_ptbr_mode,
input [1:0] io_ptw_status_dprv,
input io_ptw_status_mxr,
input io_ptw_status_sum,
input io_ptw_pmp_0_cfg_l,
input [1:0] io_ptw_pmp_0_cfg_a,
input io_ptw_pmp_0_cfg_x,
input io_ptw_pmp_0_cfg_w,
input io_ptw_pmp_0_cfg_r,
input [29:0] io_ptw_pmp_0_addr,
input [31:0] io_ptw_pmp_0_mask,
input io_ptw_pmp_1_cfg_l,
input [1:0] io_ptw_pmp_1_cfg_a,
input io_ptw_pmp_1_cfg_x,
input io_ptw_pmp_1_cfg_w,
input io_ptw_pmp_1_cfg_r,
input [29:0] io_ptw_pmp_1_addr,
input [31:0] io_ptw_pmp_1_mask,
input io_ptw_pmp_2_cfg_l,
input [1:0] io_ptw_pmp_2_cfg_a,
input io_ptw_pmp_2_cfg_x,
input io_ptw_pmp_2_cfg_w,
input io_ptw_pmp_2_cfg_r,
input [29:0] io_ptw_pmp_2_addr,
input [31:0] io_ptw_pmp_2_mask,
input io_ptw_pmp_3_cfg_l,
input [1:0] io_ptw_pmp_3_cfg_a,
input io_ptw_pmp_3_cfg_x,
input io_ptw_pmp_3_cfg_w,
input io_ptw_pmp_3_cfg_r,
input [29:0] io_ptw_pmp_3_addr,
input [31:0] io_ptw_pmp_3_mask,
input io_ptw_pmp_4_cfg_l,
input [1:0] io_ptw_pmp_4_cfg_a,
input io_ptw_pmp_4_cfg_x,
input io_ptw_pmp_4_cfg_w,
input io_ptw_pmp_4_cfg_r,
input [29:0] io_ptw_pmp_4_addr,
input [31:0] io_ptw_pmp_4_mask,
input io_ptw_pmp_5_cfg_l,
input [1:0] io_ptw_pmp_5_cfg_a,
input io_ptw_pmp_5_cfg_x,
input io_ptw_pmp_5_cfg_w,
input io_ptw_pmp_5_cfg_r,
input [29:0] io_ptw_pmp_5_addr,
input [31:0] io_ptw_pmp_5_mask,
input io_ptw_pmp_6_cfg_l,
input [1:0] io_ptw_pmp_6_cfg_a,
input io_ptw_pmp_6_cfg_x,
input io_ptw_pmp_6_cfg_w,
input io_ptw_pmp_6_cfg_r,
input [29:0] io_ptw_pmp_6_addr,
input [31:0] io_ptw_pmp_6_mask,
input io_ptw_pmp_7_cfg_l,
input [1:0] io_ptw_pmp_7_cfg_a,
input io_ptw_pmp_7_cfg_x,
input io_ptw_pmp_7_cfg_w,
input io_ptw_pmp_7_cfg_r,
input [29:0] io_ptw_pmp_7_addr,
input [31:0] io_ptw_pmp_7_mask,
input io_core_exe_0_req_valid,
input [6:0] io_core_exe_0_req_bits_uop_uopc,
input [31:0] io_core_exe_0_req_bits_uop_inst,
input [31:0] io_core_exe_0_req_bits_uop_debug_inst,
input io_core_exe_0_req_bits_uop_is_rvc,
input [39:0] io_core_exe_0_req_bits_uop_debug_pc,
input [2:0] io_core_exe_0_req_bits_uop_iq_type,
input [9:0] io_core_exe_0_req_bits_uop_fu_code,
input [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type,
input [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel,
input [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel,
input [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel,
input [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn,
input io_core_exe_0_req_bits_uop_ctrl_fcn_dw,
input [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd,
input io_core_exe_0_req_bits_uop_ctrl_is_load,
input io_core_exe_0_req_bits_uop_ctrl_is_sta,
input io_core_exe_0_req_bits_uop_ctrl_is_std,
input [1:0] io_core_exe_0_req_bits_uop_iw_state,
input io_core_exe_0_req_bits_uop_is_br,
input io_core_exe_0_req_bits_uop_is_jalr,
input io_core_exe_0_req_bits_uop_is_jal,
input io_core_exe_0_req_bits_uop_is_sfb,
input [7:0] io_core_exe_0_req_bits_uop_br_mask,
input [2:0] io_core_exe_0_req_bits_uop_br_tag,
input [3:0] io_core_exe_0_req_bits_uop_ftq_idx,
input io_core_exe_0_req_bits_uop_edge_inst,
input [5:0] io_core_exe_0_req_bits_uop_pc_lob,
input io_core_exe_0_req_bits_uop_taken,
input [19:0] io_core_exe_0_req_bits_uop_imm_packed,
input [11:0] io_core_exe_0_req_bits_uop_csr_addr,
input [4:0] io_core_exe_0_req_bits_uop_rob_idx,
input [2:0] io_core_exe_0_req_bits_uop_ldq_idx,
input [2:0] io_core_exe_0_req_bits_uop_stq_idx,
input [1:0] io_core_exe_0_req_bits_uop_rxq_idx,
input [5:0] io_core_exe_0_req_bits_uop_pdst,
input [5:0] io_core_exe_0_req_bits_uop_prs1,
input [5:0] io_core_exe_0_req_bits_uop_prs2,
input [5:0] io_core_exe_0_req_bits_uop_prs3,
input [3:0] io_core_exe_0_req_bits_uop_ppred,
input io_core_exe_0_req_bits_uop_prs1_busy,
input io_core_exe_0_req_bits_uop_prs2_busy,
input io_core_exe_0_req_bits_uop_prs3_busy,
input io_core_exe_0_req_bits_uop_ppred_busy,
input [5:0] io_core_exe_0_req_bits_uop_stale_pdst,
input io_core_exe_0_req_bits_uop_exception,
input [63:0] io_core_exe_0_req_bits_uop_exc_cause,
input io_core_exe_0_req_bits_uop_bypassable,
input [4:0] io_core_exe_0_req_bits_uop_mem_cmd,
input [1:0] io_core_exe_0_req_bits_uop_mem_size,
input io_core_exe_0_req_bits_uop_mem_signed,
input io_core_exe_0_req_bits_uop_is_fence,
input io_core_exe_0_req_bits_uop_is_fencei,
input io_core_exe_0_req_bits_uop_is_amo,
input io_core_exe_0_req_bits_uop_uses_ldq,
input io_core_exe_0_req_bits_uop_uses_stq,
input io_core_exe_0_req_bits_uop_is_sys_pc2epc,
input io_core_exe_0_req_bits_uop_is_unique,
input io_core_exe_0_req_bits_uop_flush_on_commit,
input io_core_exe_0_req_bits_uop_ldst_is_rs1,
input [5:0] io_core_exe_0_req_bits_uop_ldst,
input [5:0] io_core_exe_0_req_bits_uop_lrs1,
input [5:0] io_core_exe_0_req_bits_uop_lrs2,
input [5:0] io_core_exe_0_req_bits_uop_lrs3,
input io_core_exe_0_req_bits_uop_ldst_val,
input [1:0] io_core_exe_0_req_bits_uop_dst_rtype,
input [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype,
input [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype,
input io_core_exe_0_req_bits_uop_frs3_en,
input io_core_exe_0_req_bits_uop_fp_val,
input io_core_exe_0_req_bits_uop_fp_single,
input io_core_exe_0_req_bits_uop_xcpt_pf_if,
input io_core_exe_0_req_bits_uop_xcpt_ae_if,
input io_core_exe_0_req_bits_uop_xcpt_ma_if,
input io_core_exe_0_req_bits_uop_bp_debug_if,
input io_core_exe_0_req_bits_uop_bp_xcpt_if,
input [1:0] io_core_exe_0_req_bits_uop_debug_fsrc,
input [1:0] io_core_exe_0_req_bits_uop_debug_tsrc,
input [63:0] io_core_exe_0_req_bits_data,
input [39:0] io_core_exe_0_req_bits_addr,
input io_core_exe_0_req_bits_mxcpt_valid,
input io_core_exe_0_req_bits_sfence_valid,
input io_core_exe_0_req_bits_sfence_bits_rs1,
input io_core_exe_0_req_bits_sfence_bits_rs2,
input [38:0] io_core_exe_0_req_bits_sfence_bits_addr,
output io_core_exe_0_iresp_valid,
output [4:0] io_core_exe_0_iresp_bits_uop_rob_idx,
output [5:0] io_core_exe_0_iresp_bits_uop_pdst,
output io_core_exe_0_iresp_bits_uop_is_amo,
output io_core_exe_0_iresp_bits_uop_uses_stq,
output [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype,
output [63:0] io_core_exe_0_iresp_bits_data,
output io_core_exe_0_fresp_valid,
output [6:0] io_core_exe_0_fresp_bits_uop_uopc,
output [7:0] io_core_exe_0_fresp_bits_uop_br_mask,
output [4:0] io_core_exe_0_fresp_bits_uop_rob_idx,
output [2:0] io_core_exe_0_fresp_bits_uop_stq_idx,
output [5:0] io_core_exe_0_fresp_bits_uop_pdst,
output [1:0] io_core_exe_0_fresp_bits_uop_mem_size,
output io_core_exe_0_fresp_bits_uop_is_amo,
output io_core_exe_0_fresp_bits_uop_uses_stq,
output [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype,
output io_core_exe_0_fresp_bits_uop_fp_val,
output [64:0] io_core_exe_0_fresp_bits_data,
input io_core_dis_uops_0_valid,
input [6:0] io_core_dis_uops_0_bits_uopc,
input [31:0] io_core_dis_uops_0_bits_inst,
input [31:0] io_core_dis_uops_0_bits_debug_inst,
input io_core_dis_uops_0_bits_is_rvc,
input [39:0] io_core_dis_uops_0_bits_debug_pc,
input [2:0] io_core_dis_uops_0_bits_iq_type,
input [9:0] io_core_dis_uops_0_bits_fu_code,
input [3:0] io_core_dis_uops_0_bits_ctrl_br_type,
input [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel,
input [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel,
input [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel,
input [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn,
input io_core_dis_uops_0_bits_ctrl_fcn_dw,
input [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd,
input io_core_dis_uops_0_bits_ctrl_is_load,
input io_core_dis_uops_0_bits_ctrl_is_sta,
input io_core_dis_uops_0_bits_ctrl_is_std,
input [1:0] io_core_dis_uops_0_bits_iw_state,
input io_core_dis_uops_0_bits_iw_p1_poisoned,
input io_core_dis_uops_0_bits_iw_p2_poisoned,
input io_core_dis_uops_0_bits_is_br,
input io_core_dis_uops_0_bits_is_jalr,
input io_core_dis_uops_0_bits_is_jal,
input io_core_dis_uops_0_bits_is_sfb,
input [7:0] io_core_dis_uops_0_bits_br_mask,
input [2:0] io_core_dis_uops_0_bits_br_tag,
input [3:0] io_core_dis_uops_0_bits_ftq_idx,
input io_core_dis_uops_0_bits_edge_inst,
input [5:0] io_core_dis_uops_0_bits_pc_lob,
input io_core_dis_uops_0_bits_taken,
input [19:0] io_core_dis_uops_0_bits_imm_packed,
input [11:0] io_core_dis_uops_0_bits_csr_addr,
input [4:0] io_core_dis_uops_0_bits_rob_idx,
input [2:0] io_core_dis_uops_0_bits_ldq_idx,
input [2:0] io_core_dis_uops_0_bits_stq_idx,
input [1:0] io_core_dis_uops_0_bits_rxq_idx,
input [5:0] io_core_dis_uops_0_bits_pdst,
input [5:0] io_core_dis_uops_0_bits_prs1,
input [5:0] io_core_dis_uops_0_bits_prs2,
input [5:0] io_core_dis_uops_0_bits_prs3,
input io_core_dis_uops_0_bits_prs1_busy,
input io_core_dis_uops_0_bits_prs2_busy,
input io_core_dis_uops_0_bits_prs3_busy,
input [5:0] io_core_dis_uops_0_bits_stale_pdst,
input io_core_dis_uops_0_bits_exception,
input [63:0] io_core_dis_uops_0_bits_exc_cause,
input io_core_dis_uops_0_bits_bypassable,
input [4:0] io_core_dis_uops_0_bits_mem_cmd,
input [1:0] io_core_dis_uops_0_bits_mem_size,
input io_core_dis_uops_0_bits_mem_signed,
input io_core_dis_uops_0_bits_is_fence,
input io_core_dis_uops_0_bits_is_fencei,
input io_core_dis_uops_0_bits_is_amo,
input io_core_dis_uops_0_bits_uses_ldq,
input io_core_dis_uops_0_bits_uses_stq,
input io_core_dis_uops_0_bits_is_sys_pc2epc,
input io_core_dis_uops_0_bits_is_unique,
input io_core_dis_uops_0_bits_flush_on_commit,
input io_core_dis_uops_0_bits_ldst_is_rs1,
input [5:0] io_core_dis_uops_0_bits_ldst,
input [5:0] io_core_dis_uops_0_bits_lrs1,
input [5:0] io_core_dis_uops_0_bits_lrs2,
input [5:0] io_core_dis_uops_0_bits_lrs3,
input io_core_dis_uops_0_bits_ldst_val,
input [1:0] io_core_dis_uops_0_bits_dst_rtype,
input [1:0] io_core_dis_uops_0_bits_lrs1_rtype,
input [1:0] io_core_dis_uops_0_bits_lrs2_rtype,
input io_core_dis_uops_0_bits_frs3_en,
input io_core_dis_uops_0_bits_fp_val,
input io_core_dis_uops_0_bits_fp_single,
input io_core_dis_uops_0_bits_xcpt_pf_if,
input io_core_dis_uops_0_bits_xcpt_ae_if,
input io_core_dis_uops_0_bits_xcpt_ma_if,
input io_core_dis_uops_0_bits_bp_debug_if,
input io_core_dis_uops_0_bits_bp_xcpt_if,
input [1:0] io_core_dis_uops_0_bits_debug_fsrc,
input [1:0] io_core_dis_uops_0_bits_debug_tsrc,
output [2:0] io_core_dis_ldq_idx_0,
output [2:0] io_core_dis_stq_idx_0,
output io_core_ldq_full_0,
output io_core_stq_full_0,
output io_core_fp_stdata_ready,
input io_core_fp_stdata_valid,
input [7:0] io_core_fp_stdata_bits_uop_br_mask,
input [4:0] io_core_fp_stdata_bits_uop_rob_idx,
input [2:0] io_core_fp_stdata_bits_uop_stq_idx,
input [63:0] io_core_fp_stdata_bits_data,
input io_core_commit_valids_0,
input io_core_commit_uops_0_uses_ldq,
input io_core_commit_uops_0_uses_stq,
input io_core_commit_load_at_rob_head,
output io_core_clr_bsy_0_valid,
output [4:0] io_core_clr_bsy_0_bits,
output io_core_clr_bsy_1_valid,
output [4:0] io_core_clr_bsy_1_bits,
input io_core_fence_dmem,
output io_core_spec_ld_wakeup_0_valid,
output [5:0] io_core_spec_ld_wakeup_0_bits,
output io_core_ld_miss,
input [7:0] io_core_brupdate_b1_resolve_mask,
input [7:0] io_core_brupdate_b1_mispredict_mask,
input [2:0] io_core_brupdate_b2_uop_ldq_idx,
input [2:0] io_core_brupdate_b2_uop_stq_idx,
input io_core_brupdate_b2_mispredict,
input [4:0] io_core_rob_head_idx,
input io_core_exception,
output io_core_fencei_rdy,
output io_core_lxcpt_valid,
output [7:0] io_core_lxcpt_bits_uop_br_mask,
output [4:0] io_core_lxcpt_bits_uop_rob_idx,
output [4:0] io_core_lxcpt_bits_cause,
output [39:0] io_core_lxcpt_bits_badvaddr,
output io_core_perf_acquire,
output io_core_perf_release,
output io_core_perf_tlbMiss,
input io_dmem_req_ready,
output io_dmem_req_valid,
output io_dmem_req_bits_0_valid,
output [6:0] io_dmem_req_bits_0_bits_uop_uopc,
output [31:0] io_dmem_req_bits_0_bits_uop_inst,
output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst,
output io_dmem_req_bits_0_bits_uop_is_rvc,
output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc,
output [2:0] io_dmem_req_bits_0_bits_uop_iq_type,
output [9:0] io_dmem_req_bits_0_bits_uop_fu_code,
output [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type,
output [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel,
output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel,
output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel,
output [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn,
output io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw,
output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd,
output io_dmem_req_bits_0_bits_uop_ctrl_is_load,
output io_dmem_req_bits_0_bits_uop_ctrl_is_sta,
output io_dmem_req_bits_0_bits_uop_ctrl_is_std,
output [1:0] io_dmem_req_bits_0_bits_uop_iw_state,
output io_dmem_req_bits_0_bits_uop_iw_p1_poisoned,
output io_dmem_req_bits_0_bits_uop_iw_p2_poisoned,
output io_dmem_req_bits_0_bits_uop_is_br,
output io_dmem_req_bits_0_bits_uop_is_jalr,
output io_dmem_req_bits_0_bits_uop_is_jal,
output io_dmem_req_bits_0_bits_uop_is_sfb,
output [7:0] io_dmem_req_bits_0_bits_uop_br_mask,
output [2:0] io_dmem_req_bits_0_bits_uop_br_tag,
output [3:0] io_dmem_req_bits_0_bits_uop_ftq_idx,
output io_dmem_req_bits_0_bits_uop_edge_inst,
output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob,
output io_dmem_req_bits_0_bits_uop_taken,
output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed,
output [11:0] io_dmem_req_bits_0_bits_uop_csr_addr,
output [4:0] io_dmem_req_bits_0_bits_uop_rob_idx,
output [2:0] io_dmem_req_bits_0_bits_uop_ldq_idx,
output [2:0] io_dmem_req_bits_0_bits_uop_stq_idx,
output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx,
output [5:0] io_dmem_req_bits_0_bits_uop_pdst,
output [5:0] io_dmem_req_bits_0_bits_uop_prs1,
output [5:0] io_dmem_req_bits_0_bits_uop_prs2,
output [5:0] io_dmem_req_bits_0_bits_uop_prs3,
output [3:0] io_dmem_req_bits_0_bits_uop_ppred,
output io_dmem_req_bits_0_bits_uop_prs1_busy,
output io_dmem_req_bits_0_bits_uop_prs2_busy,
output io_dmem_req_bits_0_bits_uop_prs3_busy,
output io_dmem_req_bits_0_bits_uop_ppred_busy,
output [5:0] io_dmem_req_bits_0_bits_uop_stale_pdst,
output io_dmem_req_bits_0_bits_uop_exception,
output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause,
output io_dmem_req_bits_0_bits_uop_bypassable,
output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd,
output [1:0] io_dmem_req_bits_0_bits_uop_mem_size,
output io_dmem_req_bits_0_bits_uop_mem_signed,
output io_dmem_req_bits_0_bits_uop_is_fence,
output io_dmem_req_bits_0_bits_uop_is_fencei,
output io_dmem_req_bits_0_bits_uop_is_amo,
output io_dmem_req_bits_0_bits_uop_uses_ldq,
output io_dmem_req_bits_0_bits_uop_uses_stq,
output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc,
output io_dmem_req_bits_0_bits_uop_is_unique,
output io_dmem_req_bits_0_bits_uop_flush_on_commit,
output io_dmem_req_bits_0_bits_uop_ldst_is_rs1,
output [5:0] io_dmem_req_bits_0_bits_uop_ldst,
output [5:0] io_dmem_req_bits_0_bits_uop_lrs1,
output [5:0] io_dmem_req_bits_0_bits_uop_lrs2,
output [5:0] io_dmem_req_bits_0_bits_uop_lrs3,
output io_dmem_req_bits_0_bits_uop_ldst_val,
output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype,
output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype,
output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype,
output io_dmem_req_bits_0_bits_uop_frs3_en,
output io_dmem_req_bits_0_bits_uop_fp_val,
output io_dmem_req_bits_0_bits_uop_fp_single,
output io_dmem_req_bits_0_bits_uop_xcpt_pf_if,
output io_dmem_req_bits_0_bits_uop_xcpt_ae_if,
output io_dmem_req_bits_0_bits_uop_xcpt_ma_if,
output io_dmem_req_bits_0_bits_uop_bp_debug_if,
output io_dmem_req_bits_0_bits_uop_bp_xcpt_if,
output [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc,
output [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc,
output [39:0] io_dmem_req_bits_0_bits_addr,
output [63:0] io_dmem_req_bits_0_bits_data,
output io_dmem_req_bits_0_bits_is_hella,
output io_dmem_s1_kill_0,
input io_dmem_resp_0_valid,
input [2:0] io_dmem_resp_0_bits_uop_ldq_idx,
input [2:0] io_dmem_resp_0_bits_uop_stq_idx,
input io_dmem_resp_0_bits_uop_is_amo,
input io_dmem_resp_0_bits_uop_uses_ldq,
input io_dmem_resp_0_bits_uop_uses_stq,
input [63:0] io_dmem_resp_0_bits_data,
input io_dmem_resp_0_bits_is_hella,
input io_dmem_nack_0_valid,
input [2:0] io_dmem_nack_0_bits_uop_ldq_idx,
input [2:0] io_dmem_nack_0_bits_uop_stq_idx,
input io_dmem_nack_0_bits_uop_uses_ldq,
input io_dmem_nack_0_bits_uop_uses_stq,
input io_dmem_nack_0_bits_is_hella,
output [7:0] io_dmem_brupdate_b1_resolve_mask,
output [7:0] io_dmem_brupdate_b1_mispredict_mask,
output io_dmem_exception,
output io_dmem_release_ready,
input io_dmem_release_valid,
input [31:0] io_dmem_release_bits_address,
output io_dmem_force_order,
input io_dmem_ordered,
input io_dmem_perf_acquire,
input io_dmem_perf_release,
output io_hellacache_req_ready,
input io_hellacache_req_valid,
input [39:0] io_hellacache_req_bits_addr,
input io_hellacache_s1_kill,
output io_hellacache_s2_nack,
output io_hellacache_resp_valid,
output [63:0] io_hellacache_resp_bits_data,
output io_hellacache_s2_xcpt_ae_ld
);
wire _GEN;
wire _GEN_0;
wire store_needs_order;
wire nacking_loads_7;
wire nacking_loads_6;
wire nacking_loads_5;
wire nacking_loads_4;
wire nacking_loads_3;
wire nacking_loads_2;
wire nacking_loads_1;
wire nacking_loads_0;
wire block_load_wakeup;
wire _GEN_1;
wire _GEN_2;
reg mem_xcpt_valids_0;
wire _will_fire_store_commit_0_T_2;
wire [2:0] _forwarding_age_logic_0_io_forwarding_idx;
wire _dtlb_io_miss_rdy;
wire _dtlb_io_resp_0_miss;
wire [31:0] _dtlb_io_resp_0_paddr;
wire _dtlb_io_resp_0_pf_ld;
wire _dtlb_io_resp_0_pf_st;
wire _dtlb_io_resp_0_ae_ld;
wire _dtlb_io_resp_0_ae_st;
wire _dtlb_io_resp_0_ma_ld;
wire _dtlb_io_resp_0_ma_st;
wire _dtlb_io_resp_0_cacheable;
wire _dtlb_io_ptw_req_valid;
reg ldq_0_valid;
reg [6:0] ldq_0_bits_uop_uopc;
reg [31:0] ldq_0_bits_uop_inst;
reg [31:0] ldq_0_bits_uop_debug_inst;
reg ldq_0_bits_uop_is_rvc;
reg [39:0] ldq_0_bits_uop_debug_pc;
reg [2:0] ldq_0_bits_uop_iq_type;
reg [9:0] ldq_0_bits_uop_fu_code;
reg [3:0] ldq_0_bits_uop_ctrl_br_type;
reg [1:0] ldq_0_bits_uop_ctrl_op1_sel;
reg [2:0] ldq_0_bits_uop_ctrl_op2_sel;
reg [2:0] ldq_0_bits_uop_ctrl_imm_sel;
reg [4:0] ldq_0_bits_uop_ctrl_op_fcn;
reg ldq_0_bits_uop_ctrl_fcn_dw;
reg [2:0] ldq_0_bits_uop_ctrl_csr_cmd;
reg ldq_0_bits_uop_ctrl_is_load;
reg ldq_0_bits_uop_ctrl_is_sta;
reg ldq_0_bits_uop_ctrl_is_std;
reg [1:0] ldq_0_bits_uop_iw_state;
reg ldq_0_bits_uop_iw_p1_poisoned;
reg ldq_0_bits_uop_iw_p2_poisoned;
reg ldq_0_bits_uop_is_br;
reg ldq_0_bits_uop_is_jalr;
reg ldq_0_bits_uop_is_jal;
reg ldq_0_bits_uop_is_sfb;
reg [7:0] ldq_0_bits_uop_br_mask;
reg [2:0] ldq_0_bits_uop_br_tag;
reg [3:0] ldq_0_bits_uop_ftq_idx;
reg ldq_0_bits_uop_edge_inst;
reg [5:0] ldq_0_bits_uop_pc_lob;
reg ldq_0_bits_uop_taken;
reg [19:0] ldq_0_bits_uop_imm_packed;
reg [11:0] ldq_0_bits_uop_csr_addr;
reg [4:0] ldq_0_bits_uop_rob_idx;
reg [2:0] ldq_0_bits_uop_ldq_idx;
reg [2:0] ldq_0_bits_uop_stq_idx;
reg [1:0] ldq_0_bits_uop_rxq_idx;
reg [5:0] ldq_0_bits_uop_pdst;
reg [5:0] ldq_0_bits_uop_prs1;
reg [5:0] ldq_0_bits_uop_prs2;
reg [5:0] ldq_0_bits_uop_prs3;
reg ldq_0_bits_uop_prs1_busy;
reg ldq_0_bits_uop_prs2_busy;
reg ldq_0_bits_uop_prs3_busy;
reg [5:0] ldq_0_bits_uop_stale_pdst;
reg ldq_0_bits_uop_exception;
reg [63:0] ldq_0_bits_uop_exc_cause;
reg ldq_0_bits_uop_bypassable;
reg [4:0] ldq_0_bits_uop_mem_cmd;
reg [1:0] ldq_0_bits_uop_mem_size;
reg ldq_0_bits_uop_mem_signed;
reg ldq_0_bits_uop_is_fence;
reg ldq_0_bits_uop_is_fencei;
reg ldq_0_bits_uop_is_amo;
reg ldq_0_bits_uop_uses_ldq;
reg ldq_0_bits_uop_uses_stq;
reg ldq_0_bits_uop_is_sys_pc2epc;
reg ldq_0_bits_uop_is_unique;
reg ldq_0_bits_uop_flush_on_commit;
reg ldq_0_bits_uop_ldst_is_rs1;
reg [5:0] ldq_0_bits_uop_ldst;
reg [5:0] ldq_0_bits_uop_lrs1;
reg [5:0] ldq_0_bits_uop_lrs2;
reg [5:0] ldq_0_bits_uop_lrs3;
reg ldq_0_bits_uop_ldst_val;
reg [1:0] ldq_0_bits_uop_dst_rtype;
reg [1:0] ldq_0_bits_uop_lrs1_rtype;
reg [1:0] ldq_0_bits_uop_lrs2_rtype;
reg ldq_0_bits_uop_frs3_en;
reg ldq_0_bits_uop_fp_val;
reg ldq_0_bits_uop_fp_single;
reg ldq_0_bits_uop_xcpt_pf_if;
reg ldq_0_bits_uop_xcpt_ae_if;
reg ldq_0_bits_uop_xcpt_ma_if;
reg ldq_0_bits_uop_bp_debug_if;
reg ldq_0_bits_uop_bp_xcpt_if;
reg [1:0] ldq_0_bits_uop_debug_fsrc;
reg [1:0] ldq_0_bits_uop_debug_tsrc;
reg ldq_0_bits_addr_valid;
reg [39:0] ldq_0_bits_addr_bits;
reg ldq_0_bits_addr_is_virtual;
reg ldq_0_bits_addr_is_uncacheable;
reg ldq_0_bits_executed;
reg ldq_0_bits_succeeded;
reg ldq_0_bits_order_fail;
reg ldq_0_bits_observed;
reg [7:0] ldq_0_bits_st_dep_mask;
reg [2:0] ldq_0_bits_youngest_stq_idx;
reg ldq_0_bits_forward_std_val;
reg [2:0] ldq_0_bits_forward_stq_idx;
reg ldq_1_valid;
reg [6:0] ldq_1_bits_uop_uopc;
reg [31:0] ldq_1_bits_uop_inst;
reg [31:0] ldq_1_bits_uop_debug_inst;
reg ldq_1_bits_uop_is_rvc;
reg [39:0] ldq_1_bits_uop_debug_pc;
reg [2:0] ldq_1_bits_uop_iq_type;
reg [9:0] ldq_1_bits_uop_fu_code;
reg [3:0] ldq_1_bits_uop_ctrl_br_type;
reg [1:0] ldq_1_bits_uop_ctrl_op1_sel;
reg [2:0] ldq_1_bits_uop_ctrl_op2_sel;
reg [2:0] ldq_1_bits_uop_ctrl_imm_sel;
reg [4:0] ldq_1_bits_uop_ctrl_op_fcn;
reg ldq_1_bits_uop_ctrl_fcn_dw;
reg [2:0] ldq_1_bits_uop_ctrl_csr_cmd;
reg ldq_1_bits_uop_ctrl_is_load;
reg ldq_1_bits_uop_ctrl_is_sta;
reg ldq_1_bits_uop_ctrl_is_std;
reg [1:0] ldq_1_bits_uop_iw_state;
reg ldq_1_bits_uop_iw_p1_poisoned;
reg ldq_1_bits_uop_iw_p2_poisoned;
reg ldq_1_bits_uop_is_br;
reg ldq_1_bits_uop_is_jalr;
reg ldq_1_bits_uop_is_jal;
reg ldq_1_bits_uop_is_sfb;
reg [7:0] ldq_1_bits_uop_br_mask;
reg [2:0] ldq_1_bits_uop_br_tag;
reg [3:0] ldq_1_bits_uop_ftq_idx;
reg ldq_1_bits_uop_edge_inst;
reg [5:0] ldq_1_bits_uop_pc_lob;
reg ldq_1_bits_uop_taken;
reg [19:0] ldq_1_bits_uop_imm_packed;
reg [11:0] ldq_1_bits_uop_csr_addr;
reg [4:0] ldq_1_bits_uop_rob_idx;
reg [2:0] ldq_1_bits_uop_ldq_idx;
reg [2:0] ldq_1_bits_uop_stq_idx;
reg [1:0] ldq_1_bits_uop_rxq_idx;
reg [5:0] ldq_1_bits_uop_pdst;
reg [5:0] ldq_1_bits_uop_prs1;
reg [5:0] ldq_1_bits_uop_prs2;
reg [5:0] ldq_1_bits_uop_prs3;
reg ldq_1_bits_uop_prs1_busy;
reg ldq_1_bits_uop_prs2_busy;
reg ldq_1_bits_uop_prs3_busy;
reg [5:0] ldq_1_bits_uop_stale_pdst;
reg ldq_1_bits_uop_exception;
reg [63:0] ldq_1_bits_uop_exc_cause;
reg ldq_1_bits_uop_bypassable;
reg [4:0] ldq_1_bits_uop_mem_cmd;
reg [1:0] ldq_1_bits_uop_mem_size;
reg ldq_1_bits_uop_mem_signed;
reg ldq_1_bits_uop_is_fence;
reg ldq_1_bits_uop_is_fencei;
reg ldq_1_bits_uop_is_amo;
reg ldq_1_bits_uop_uses_ldq;
reg ldq_1_bits_uop_uses_stq;
reg ldq_1_bits_uop_is_sys_pc2epc;
reg ldq_1_bits_uop_is_unique;
reg ldq_1_bits_uop_flush_on_commit;
reg ldq_1_bits_uop_ldst_is_rs1;
reg [5:0] ldq_1_bits_uop_ldst;
reg [5:0] ldq_1_bits_uop_lrs1;
reg [5:0] ldq_1_bits_uop_lrs2;
reg [5:0] ldq_1_bits_uop_lrs3;
reg ldq_1_bits_uop_ldst_val;
reg [1:0] ldq_1_bits_uop_dst_rtype;
reg [1:0] ldq_1_bits_uop_lrs1_rtype;
reg [1:0] ldq_1_bits_uop_lrs2_rtype;
reg ldq_1_bits_uop_frs3_en;
reg ldq_1_bits_uop_fp_val;
reg ldq_1_bits_uop_fp_single;
reg ldq_1_bits_uop_xcpt_pf_if;
reg ldq_1_bits_uop_xcpt_ae_if;
reg ldq_1_bits_uop_xcpt_ma_if;
reg ldq_1_bits_uop_bp_debug_if;
reg ldq_1_bits_uop_bp_xcpt_if;
reg [1:0] ldq_1_bits_uop_debug_fsrc;
reg [1:0] ldq_1_bits_uop_debug_tsrc;
reg ldq_1_bits_addr_valid;
reg [39:0] ldq_1_bits_addr_bits;
reg ldq_1_bits_addr_is_virtual;
reg ldq_1_bits_addr_is_uncacheable;
reg ldq_1_bits_executed;
reg ldq_1_bits_succeeded;
reg ldq_1_bits_order_fail;
reg ldq_1_bits_observed;
reg [7:0] ldq_1_bits_st_dep_mask;
reg [2:0] ldq_1_bits_youngest_stq_idx;
reg ldq_1_bits_forward_std_val;
reg [2:0] ldq_1_bits_forward_stq_idx;
reg ldq_2_valid;
reg [6:0] ldq_2_bits_uop_uopc;
reg [31:0] ldq_2_bits_uop_inst;
reg [31:0] ldq_2_bits_uop_debug_inst;
reg ldq_2_bits_uop_is_rvc;
reg [39:0] ldq_2_bits_uop_debug_pc;
reg [2:0] ldq_2_bits_uop_iq_type;
reg [9:0] ldq_2_bits_uop_fu_code;
reg [3:0] ldq_2_bits_uop_ctrl_br_type;
reg [1:0] ldq_2_bits_uop_ctrl_op1_sel;
reg [2:0] ldq_2_bits_uop_ctrl_op2_sel;
reg [2:0] ldq_2_bits_uop_ctrl_imm_sel;
reg [4:0] ldq_2_bits_uop_ctrl_op_fcn;
reg ldq_2_bits_uop_ctrl_fcn_dw;
reg [2:0] ldq_2_bits_uop_ctrl_csr_cmd;
reg ldq_2_bits_uop_ctrl_is_load;
reg ldq_2_bits_uop_ctrl_is_sta;
reg ldq_2_bits_uop_ctrl_is_std;
reg [1:0] ldq_2_bits_uop_iw_state;
reg ldq_2_bits_uop_iw_p1_poisoned;
reg ldq_2_bits_uop_iw_p2_poisoned;
reg ldq_2_bits_uop_is_br;
reg ldq_2_bits_uop_is_jalr;
reg ldq_2_bits_uop_is_jal;
reg ldq_2_bits_uop_is_sfb;
reg [7:0] ldq_2_bits_uop_br_mask;
reg [2:0] ldq_2_bits_uop_br_tag;
reg [3:0] ldq_2_bits_uop_ftq_idx;
reg ldq_2_bits_uop_edge_inst;
reg [5:0] ldq_2_bits_uop_pc_lob;
reg ldq_2_bits_uop_taken;
reg [19:0] ldq_2_bits_uop_imm_packed;
reg [11:0] ldq_2_bits_uop_csr_addr;
reg [4:0] ldq_2_bits_uop_rob_idx;
reg [2:0] ldq_2_bits_uop_ldq_idx;
reg [2:0] ldq_2_bits_uop_stq_idx;
reg [1:0] ldq_2_bits_uop_rxq_idx;
reg [5:0] ldq_2_bits_uop_pdst;
reg [5:0] ldq_2_bits_uop_prs1;
reg [5:0] ldq_2_bits_uop_prs2;
reg [5:0] ldq_2_bits_uop_prs3;
reg ldq_2_bits_uop_prs1_busy;
reg ldq_2_bits_uop_prs2_busy;
reg ldq_2_bits_uop_prs3_busy;
reg [5:0] ldq_2_bits_uop_stale_pdst;
reg ldq_2_bits_uop_exception;
reg [63:0] ldq_2_bits_uop_exc_cause;
reg ldq_2_bits_uop_bypassable;
reg [4:0] ldq_2_bits_uop_mem_cmd;
reg [1:0] ldq_2_bits_uop_mem_size;
reg ldq_2_bits_uop_mem_signed;
reg ldq_2_bits_uop_is_fence;
reg ldq_2_bits_uop_is_fencei;
reg ldq_2_bits_uop_is_amo;
reg ldq_2_bits_uop_uses_ldq;
reg ldq_2_bits_uop_uses_stq;
reg ldq_2_bits_uop_is_sys_pc2epc;
reg ldq_2_bits_uop_is_unique;
reg ldq_2_bits_uop_flush_on_commit;
reg ldq_2_bits_uop_ldst_is_rs1;
reg [5:0] ldq_2_bits_uop_ldst;
reg [5:0] ldq_2_bits_uop_lrs1;
reg [5:0] ldq_2_bits_uop_lrs2;
reg [5:0] ldq_2_bits_uop_lrs3;
reg ldq_2_bits_uop_ldst_val;
reg [1:0] ldq_2_bits_uop_dst_rtype;
reg [1:0] ldq_2_bits_uop_lrs1_rtype;
reg [1:0] ldq_2_bits_uop_lrs2_rtype;
reg ldq_2_bits_uop_frs3_en;
reg ldq_2_bits_uop_fp_val;
reg ldq_2_bits_uop_fp_single;
reg ldq_2_bits_uop_xcpt_pf_if;
reg ldq_2_bits_uop_xcpt_ae_if;
reg ldq_2_bits_uop_xcpt_ma_if;
reg ldq_2_bits_uop_bp_debug_if;
reg ldq_2_bits_uop_bp_xcpt_if;
reg [1:0] ldq_2_bits_uop_debug_fsrc;
reg [1:0] ldq_2_bits_uop_debug_tsrc;
reg ldq_2_bits_addr_valid;
reg [39:0] ldq_2_bits_addr_bits;
reg ldq_2_bits_addr_is_virtual;
reg ldq_2_bits_addr_is_uncacheable;
reg ldq_2_bits_executed;
reg ldq_2_bits_succeeded;
reg ldq_2_bits_order_fail;
reg ldq_2_bits_observed;
reg [7:0] ldq_2_bits_st_dep_mask;
reg [2:0] ldq_2_bits_youngest_stq_idx;
reg ldq_2_bits_forward_std_val;
reg [2:0] ldq_2_bits_forward_stq_idx;
reg ldq_3_valid;
reg [6:0] ldq_3_bits_uop_uopc;
reg [31:0] ldq_3_bits_uop_inst;
reg [31:0] ldq_3_bits_uop_debug_inst;
reg ldq_3_bits_uop_is_rvc;
reg [39:0] ldq_3_bits_uop_debug_pc;
reg [2:0] ldq_3_bits_uop_iq_type;
reg [9:0] ldq_3_bits_uop_fu_code;
reg [3:0] ldq_3_bits_uop_ctrl_br_type;
reg [1:0] ldq_3_bits_uop_ctrl_op1_sel;
reg [2:0] ldq_3_bits_uop_ctrl_op2_sel;
reg [2:0] ldq_3_bits_uop_ctrl_imm_sel;
reg [4:0] ldq_3_bits_uop_ctrl_op_fcn;
reg ldq_3_bits_uop_ctrl_fcn_dw;
reg [2:0] ldq_3_bits_uop_ctrl_csr_cmd;
reg ldq_3_bits_uop_ctrl_is_load;
reg ldq_3_bits_uop_ctrl_is_sta;
reg ldq_3_bits_uop_ctrl_is_std;
reg [1:0] ldq_3_bits_uop_iw_state;
reg ldq_3_bits_uop_iw_p1_poisoned;
reg ldq_3_bits_uop_iw_p2_poisoned;
reg ldq_3_bits_uop_is_br;
reg ldq_3_bits_uop_is_jalr;
reg ldq_3_bits_uop_is_jal;
reg ldq_3_bits_uop_is_sfb;
reg [7:0] ldq_3_bits_uop_br_mask;
reg [2:0] ldq_3_bits_uop_br_tag;
reg [3:0] ldq_3_bits_uop_ftq_idx;
reg ldq_3_bits_uop_edge_inst;
reg [5:0] ldq_3_bits_uop_pc_lob;
reg ldq_3_bits_uop_taken;
reg [19:0] ldq_3_bits_uop_imm_packed;
reg [11:0] ldq_3_bits_uop_csr_addr;
reg [4:0] ldq_3_bits_uop_rob_idx;
reg [2:0] ldq_3_bits_uop_ldq_idx;
reg [2:0] ldq_3_bits_uop_stq_idx;
reg [1:0] ldq_3_bits_uop_rxq_idx;
reg [5:0] ldq_3_bits_uop_pdst;
reg [5:0] ldq_3_bits_uop_prs1;
reg [5:0] ldq_3_bits_uop_prs2;
reg [5:0] ldq_3_bits_uop_prs3;
reg ldq_3_bits_uop_prs1_busy;
reg ldq_3_bits_uop_prs2_busy;
reg ldq_3_bits_uop_prs3_busy;
reg [5:0] ldq_3_bits_uop_stale_pdst;
reg ldq_3_bits_uop_exception;
reg [63:0] ldq_3_bits_uop_exc_cause;
reg ldq_3_bits_uop_bypassable;
reg [4:0] ldq_3_bits_uop_mem_cmd;
reg [1:0] ldq_3_bits_uop_mem_size;
reg ldq_3_bits_uop_mem_signed;
reg ldq_3_bits_uop_is_fence;
reg ldq_3_bits_uop_is_fencei;
reg ldq_3_bits_uop_is_amo;
reg ldq_3_bits_uop_uses_ldq;
reg ldq_3_bits_uop_uses_stq;
reg ldq_3_bits_uop_is_sys_pc2epc;
reg ldq_3_bits_uop_is_unique;
reg ldq_3_bits_uop_flush_on_commit;
reg ldq_3_bits_uop_ldst_is_rs1;
reg [5:0] ldq_3_bits_uop_ldst;
reg [5:0] ldq_3_bits_uop_lrs1;
reg [5:0] ldq_3_bits_uop_lrs2;
reg [5:0] ldq_3_bits_uop_lrs3;
reg ldq_3_bits_uop_ldst_val;
reg [1:0] ldq_3_bits_uop_dst_rtype;
reg [1:0] ldq_3_bits_uop_lrs1_rtype;
reg [1:0] ldq_3_bits_uop_lrs2_rtype;
reg ldq_3_bits_uop_frs3_en;
reg ldq_3_bits_uop_fp_val;
reg ldq_3_bits_uop_fp_single;
reg ldq_3_bits_uop_xcpt_pf_if;
reg ldq_3_bits_uop_xcpt_ae_if;
reg ldq_3_bits_uop_xcpt_ma_if;
reg ldq_3_bits_uop_bp_debug_if;
reg ldq_3_bits_uop_bp_xcpt_if;
reg [1:0] ldq_3_bits_uop_debug_fsrc;
reg [1:0] ldq_3_bits_uop_debug_tsrc;
reg ldq_3_bits_addr_valid;
reg [39:0] ldq_3_bits_addr_bits;
reg ldq_3_bits_addr_is_virtual;
reg ldq_3_bits_addr_is_uncacheable;
reg ldq_3_bits_executed;
reg ldq_3_bits_succeeded;
reg ldq_3_bits_order_fail;
reg ldq_3_bits_observed;
reg [7:0] ldq_3_bits_st_dep_mask;
reg [2:0] ldq_3_bits_youngest_stq_idx;
reg ldq_3_bits_forward_std_val;
reg [2:0] ldq_3_bits_forward_stq_idx;
reg ldq_4_valid;
reg [6:0] ldq_4_bits_uop_uopc;
reg [31:0] ldq_4_bits_uop_inst;
reg [31:0] ldq_4_bits_uop_debug_inst;
reg ldq_4_bits_uop_is_rvc;
reg [39:0] ldq_4_bits_uop_debug_pc;
reg [2:0] ldq_4_bits_uop_iq_type;
reg [9:0] ldq_4_bits_uop_fu_code;
reg [3:0] ldq_4_bits_uop_ctrl_br_type;
reg [1:0] ldq_4_bits_uop_ctrl_op1_sel;
reg [2:0] ldq_4_bits_uop_ctrl_op2_sel;
reg [2:0] ldq_4_bits_uop_ctrl_imm_sel;
reg [4:0] ldq_4_bits_uop_ctrl_op_fcn;
reg ldq_4_bits_uop_ctrl_fcn_dw;
reg [2:0] ldq_4_bits_uop_ctrl_csr_cmd;
reg ldq_4_bits_uop_ctrl_is_load;
reg ldq_4_bits_uop_ctrl_is_sta;
reg ldq_4_bits_uop_ctrl_is_std;
reg [1:0] ldq_4_bits_uop_iw_state;
reg ldq_4_bits_uop_iw_p1_poisoned;
reg ldq_4_bits_uop_iw_p2_poisoned;
reg ldq_4_bits_uop_is_br;
reg ldq_4_bits_uop_is_jalr;
reg ldq_4_bits_uop_is_jal;
reg ldq_4_bits_uop_is_sfb;
reg [7:0] ldq_4_bits_uop_br_mask;
reg [2:0] ldq_4_bits_uop_br_tag;
reg [3:0] ldq_4_bits_uop_ftq_idx;
reg ldq_4_bits_uop_edge_inst;
reg [5:0] ldq_4_bits_uop_pc_lob;
reg ldq_4_bits_uop_taken;
reg [19:0] ldq_4_bits_uop_imm_packed;
reg [11:0] ldq_4_bits_uop_csr_addr;
reg [4:0] ldq_4_bits_uop_rob_idx;
reg [2:0] ldq_4_bits_uop_ldq_idx;
reg [2:0] ldq_4_bits_uop_stq_idx;
reg [1:0] ldq_4_bits_uop_rxq_idx;
reg [5:0] ldq_4_bits_uop_pdst;
reg [5:0] ldq_4_bits_uop_prs1;
reg [5:0] ldq_4_bits_uop_prs2;
reg [5:0] ldq_4_bits_uop_prs3;
reg ldq_4_bits_uop_prs1_busy;
reg ldq_4_bits_uop_prs2_busy;
reg ldq_4_bits_uop_prs3_busy;
reg [5:0] ldq_4_bits_uop_stale_pdst;
reg ldq_4_bits_uop_exception;
reg [63:0] ldq_4_bits_uop_exc_cause;
reg ldq_4_bits_uop_bypassable;
reg [4:0] ldq_4_bits_uop_mem_cmd;
reg [1:0] ldq_4_bits_uop_mem_size;
reg ldq_4_bits_uop_mem_signed;
reg ldq_4_bits_uop_is_fence;
reg ldq_4_bits_uop_is_fencei;
reg ldq_4_bits_uop_is_amo;
reg ldq_4_bits_uop_uses_ldq;
reg ldq_4_bits_uop_uses_stq;
reg ldq_4_bits_uop_is_sys_pc2epc;
reg ldq_4_bits_uop_is_unique;
reg ldq_4_bits_uop_flush_on_commit;
reg ldq_4_bits_uop_ldst_is_rs1;
reg [5:0] ldq_4_bits_uop_ldst;
reg [5:0] ldq_4_bits_uop_lrs1;
reg [5:0] ldq_4_bits_uop_lrs2;
reg [5:0] ldq_4_bits_uop_lrs3;
reg ldq_4_bits_uop_ldst_val;
reg [1:0] ldq_4_bits_uop_dst_rtype;
reg [1:0] ldq_4_bits_uop_lrs1_rtype;
reg [1:0] ldq_4_bits_uop_lrs2_rtype;
reg ldq_4_bits_uop_frs3_en;
reg ldq_4_bits_uop_fp_val;
reg ldq_4_bits_uop_fp_single;
reg ldq_4_bits_uop_xcpt_pf_if;
reg ldq_4_bits_uop_xcpt_ae_if;
reg ldq_4_bits_uop_xcpt_ma_if;
reg ldq_4_bits_uop_bp_debug_if;
reg ldq_4_bits_uop_bp_xcpt_if;
reg [1:0] ldq_4_bits_uop_debug_fsrc;
reg [1:0] ldq_4_bits_uop_debug_tsrc;
reg ldq_4_bits_addr_valid;
reg [39:0] ldq_4_bits_addr_bits;
reg ldq_4_bits_addr_is_virtual;
reg ldq_4_bits_addr_is_uncacheable;
reg ldq_4_bits_executed;
reg ldq_4_bits_succeeded;
reg ldq_4_bits_order_fail;
reg ldq_4_bits_observed;
reg [7:0] ldq_4_bits_st_dep_mask;
reg [2:0] ldq_4_bits_youngest_stq_idx;
reg ldq_4_bits_forward_std_val;
reg [2:0] ldq_4_bits_forward_stq_idx;
reg ldq_5_valid;
reg [6:0] ldq_5_bits_uop_uopc;
reg [31:0] ldq_5_bits_uop_inst;
reg [31:0] ldq_5_bits_uop_debug_inst;
reg ldq_5_bits_uop_is_rvc;
reg [39:0] ldq_5_bits_uop_debug_pc;
reg [2:0] ldq_5_bits_uop_iq_type;
reg [9:0] ldq_5_bits_uop_fu_code;
reg [3:0] ldq_5_bits_uop_ctrl_br_type;
reg [1:0] ldq_5_bits_uop_ctrl_op1_sel;
reg [2:0] ldq_5_bits_uop_ctrl_op2_sel;
reg [2:0] ldq_5_bits_uop_ctrl_imm_sel;
reg [4:0] ldq_5_bits_uop_ctrl_op_fcn;
reg ldq_5_bits_uop_ctrl_fcn_dw;
reg [2:0] ldq_5_bits_uop_ctrl_csr_cmd;
reg ldq_5_bits_uop_ctrl_is_load;
reg ldq_5_bits_uop_ctrl_is_sta;
reg ldq_5_bits_uop_ctrl_is_std;
reg [1:0] ldq_5_bits_uop_iw_state;
reg ldq_5_bits_uop_iw_p1_poisoned;
reg ldq_5_bits_uop_iw_p2_poisoned;
reg ldq_5_bits_uop_is_br;
reg ldq_5_bits_uop_is_jalr;
reg ldq_5_bits_uop_is_jal;
reg ldq_5_bits_uop_is_sfb;
reg [7:0] ldq_5_bits_uop_br_mask;
reg [2:0] ldq_5_bits_uop_br_tag;
reg [3:0] ldq_5_bits_uop_ftq_idx;
reg ldq_5_bits_uop_edge_inst;
reg [5:0] ldq_5_bits_uop_pc_lob;
reg ldq_5_bits_uop_taken;
reg [19:0] ldq_5_bits_uop_imm_packed;
reg [11:0] ldq_5_bits_uop_csr_addr;
reg [4:0] ldq_5_bits_uop_rob_idx;
reg [2:0] ldq_5_bits_uop_ldq_idx;
reg [2:0] ldq_5_bits_uop_stq_idx;
reg [1:0] ldq_5_bits_uop_rxq_idx;
reg [5:0] ldq_5_bits_uop_pdst;
reg [5:0] ldq_5_bits_uop_prs1;
reg [5:0] ldq_5_bits_uop_prs2;
reg [5:0] ldq_5_bits_uop_prs3;
reg ldq_5_bits_uop_prs1_busy;
reg ldq_5_bits_uop_prs2_busy;
reg ldq_5_bits_uop_prs3_busy;
reg [5:0] ldq_5_bits_uop_stale_pdst;
reg ldq_5_bits_uop_exception;
reg [63:0] ldq_5_bits_uop_exc_cause;
reg ldq_5_bits_uop_bypassable;
reg [4:0] ldq_5_bits_uop_mem_cmd;
reg [1:0] ldq_5_bits_uop_mem_size;
reg ldq_5_bits_uop_mem_signed;
reg ldq_5_bits_uop_is_fence;
reg ldq_5_bits_uop_is_fencei;
reg ldq_5_bits_uop_is_amo;
reg ldq_5_bits_uop_uses_ldq;
reg ldq_5_bits_uop_uses_stq;
reg ldq_5_bits_uop_is_sys_pc2epc;
reg ldq_5_bits_uop_is_unique;
reg ldq_5_bits_uop_flush_on_commit;
reg ldq_5_bits_uop_ldst_is_rs1;
reg [5:0] ldq_5_bits_uop_ldst;
reg [5:0] ldq_5_bits_uop_lrs1;
reg [5:0] ldq_5_bits_uop_lrs2;
reg [5:0] ldq_5_bits_uop_lrs3;
reg ldq_5_bits_uop_ldst_val;
reg [1:0] ldq_5_bits_uop_dst_rtype;
reg [1:0] ldq_5_bits_uop_lrs1_rtype;
reg [1:0] ldq_5_bits_uop_lrs2_rtype;
reg ldq_5_bits_uop_frs3_en;
reg ldq_5_bits_uop_fp_val;
reg ldq_5_bits_uop_fp_single;
reg ldq_5_bits_uop_xcpt_pf_if;
reg ldq_5_bits_uop_xcpt_ae_if;
reg ldq_5_bits_uop_xcpt_ma_if;
reg ldq_5_bits_uop_bp_debug_if;
reg ldq_5_bits_uop_bp_xcpt_if;
reg [1:0] ldq_5_bits_uop_debug_fsrc;
reg [1:0] ldq_5_bits_uop_debug_tsrc;
reg ldq_5_bits_addr_valid;
reg [39:0] ldq_5_bits_addr_bits;
reg ldq_5_bits_addr_is_virtual;
reg ldq_5_bits_addr_is_uncacheable;
reg ldq_5_bits_executed;
reg ldq_5_bits_succeeded;
reg ldq_5_bits_order_fail;
reg ldq_5_bits_observed;
reg [7:0] ldq_5_bits_st_dep_mask;
reg [2:0] ldq_5_bits_youngest_stq_idx;
reg ldq_5_bits_forward_std_val;
reg [2:0] ldq_5_bits_forward_stq_idx;
reg ldq_6_valid;
reg [6:0] ldq_6_bits_uop_uopc;
reg [31:0] ldq_6_bits_uop_inst;
reg [31:0] ldq_6_bits_uop_debug_inst;
reg ldq_6_bits_uop_is_rvc;
reg [39:0] ldq_6_bits_uop_debug_pc;
reg [2:0] ldq_6_bits_uop_iq_type;
reg [9:0] ldq_6_bits_uop_fu_code;
reg [3:0] ldq_6_bits_uop_ctrl_br_type;
reg [1:0] ldq_6_bits_uop_ctrl_op1_sel;
reg [2:0] ldq_6_bits_uop_ctrl_op2_sel;
reg [2:0] ldq_6_bits_uop_ctrl_imm_sel;
reg [4:0] ldq_6_bits_uop_ctrl_op_fcn;
reg ldq_6_bits_uop_ctrl_fcn_dw;
reg [2:0] ldq_6_bits_uop_ctrl_csr_cmd;
reg ldq_6_bits_uop_ctrl_is_load;
reg ldq_6_bits_uop_ctrl_is_sta;
reg ldq_6_bits_uop_ctrl_is_std;
reg [1:0] ldq_6_bits_uop_iw_state;
reg ldq_6_bits_uop_iw_p1_poisoned;
reg ldq_6_bits_uop_iw_p2_poisoned;
reg ldq_6_bits_uop_is_br;
reg ldq_6_bits_uop_is_jalr;
reg ldq_6_bits_uop_is_jal;
reg ldq_6_bits_uop_is_sfb;
reg [7:0] ldq_6_bits_uop_br_mask;
reg [2:0] ldq_6_bits_uop_br_tag;
reg [3:0] ldq_6_bits_uop_ftq_idx;
reg ldq_6_bits_uop_edge_inst;
reg [5:0] ldq_6_bits_uop_pc_lob;
reg ldq_6_bits_uop_taken;
reg [19:0] ldq_6_bits_uop_imm_packed;
reg [11:0] ldq_6_bits_uop_csr_addr;
reg [4:0] ldq_6_bits_uop_rob_idx;
reg [2:0] ldq_6_bits_uop_ldq_idx;
reg [2:0] ldq_6_bits_uop_stq_idx;
reg [1:0] ldq_6_bits_uop_rxq_idx;
reg [5:0] ldq_6_bits_uop_pdst;
reg [5:0] ldq_6_bits_uop_prs1;
reg [5:0] ldq_6_bits_uop_prs2;
reg [5:0] ldq_6_bits_uop_prs3;
reg ldq_6_bits_uop_prs1_busy;
reg ldq_6_bits_uop_prs2_busy;
reg ldq_6_bits_uop_prs3_busy;
reg [5:0] ldq_6_bits_uop_stale_pdst;
reg ldq_6_bits_uop_exception;
reg [63:0] ldq_6_bits_uop_exc_cause;
reg ldq_6_bits_uop_bypassable;
reg [4:0] ldq_6_bits_uop_mem_cmd;
reg [1:0] ldq_6_bits_uop_mem_size;
reg ldq_6_bits_uop_mem_signed;
reg ldq_6_bits_uop_is_fence;
reg ldq_6_bits_uop_is_fencei;
reg ldq_6_bits_uop_is_amo;
reg ldq_6_bits_uop_uses_ldq;
reg ldq_6_bits_uop_uses_stq;
reg ldq_6_bits_uop_is_sys_pc2epc;
reg ldq_6_bits_uop_is_unique;
reg ldq_6_bits_uop_flush_on_commit;
reg ldq_6_bits_uop_ldst_is_rs1;
reg [5:0] ldq_6_bits_uop_ldst;
reg [5:0] ldq_6_bits_uop_lrs1;
reg [5:0] ldq_6_bits_uop_lrs2;
reg [5:0] ldq_6_bits_uop_lrs3;
reg ldq_6_bits_uop_ldst_val;
reg [1:0] ldq_6_bits_uop_dst_rtype;
reg [1:0] ldq_6_bits_uop_lrs1_rtype;
reg [1:0] ldq_6_bits_uop_lrs2_rtype;
reg ldq_6_bits_uop_frs3_en;
reg ldq_6_bits_uop_fp_val;
reg ldq_6_bits_uop_fp_single;
reg ldq_6_bits_uop_xcpt_pf_if;
reg ldq_6_bits_uop_xcpt_ae_if;
reg ldq_6_bits_uop_xcpt_ma_if;
reg ldq_6_bits_uop_bp_debug_if;
reg ldq_6_bits_uop_bp_xcpt_if;
reg [1:0] ldq_6_bits_uop_debug_fsrc;
reg [1:0] ldq_6_bits_uop_debug_tsrc;
reg ldq_6_bits_addr_valid;
reg [39:0] ldq_6_bits_addr_bits;
reg ldq_6_bits_addr_is_virtual;
reg ldq_6_bits_addr_is_uncacheable;
reg ldq_6_bits_executed;
reg ldq_6_bits_succeeded;
reg ldq_6_bits_order_fail;
reg ldq_6_bits_observed;
reg [7:0] ldq_6_bits_st_dep_mask;
reg [2:0] ldq_6_bits_youngest_stq_idx;
reg ldq_6_bits_forward_std_val;
reg [2:0] ldq_6_bits_forward_stq_idx;
reg ldq_7_valid;
reg [6:0] ldq_7_bits_uop_uopc;
reg [31:0] ldq_7_bits_uop_inst;
reg [31:0] ldq_7_bits_uop_debug_inst;
reg ldq_7_bits_uop_is_rvc;
reg [39:0] ldq_7_bits_uop_debug_pc;
reg [2:0] ldq_7_bits_uop_iq_type;
reg [9:0] ldq_7_bits_uop_fu_code;
reg [3:0] ldq_7_bits_uop_ctrl_br_type;
reg [1:0] ldq_7_bits_uop_ctrl_op1_sel;
reg [2:0] ldq_7_bits_uop_ctrl_op2_sel;
reg [2:0] ldq_7_bits_uop_ctrl_imm_sel;
reg [4:0] ldq_7_bits_uop_ctrl_op_fcn;
reg ldq_7_bits_uop_ctrl_fcn_dw;
reg [2:0] ldq_7_bits_uop_ctrl_csr_cmd;
reg ldq_7_bits_uop_ctrl_is_load;
reg ldq_7_bits_uop_ctrl_is_sta;
reg ldq_7_bits_uop_ctrl_is_std;
reg [1:0] ldq_7_bits_uop_iw_state;
reg ldq_7_bits_uop_iw_p1_poisoned;
reg ldq_7_bits_uop_iw_p2_poisoned;
reg ldq_7_bits_uop_is_br;
reg ldq_7_bits_uop_is_jalr;
reg ldq_7_bits_uop_is_jal;
reg ldq_7_bits_uop_is_sfb;
reg [7:0] ldq_7_bits_uop_br_mask;
reg [2:0] ldq_7_bits_uop_br_tag;
reg [3:0] ldq_7_bits_uop_ftq_idx;
reg ldq_7_bits_uop_edge_inst;
reg [5:0] ldq_7_bits_uop_pc_lob;
reg ldq_7_bits_uop_taken;
reg [19:0] ldq_7_bits_uop_imm_packed;
reg [11:0] ldq_7_bits_uop_csr_addr;
reg [4:0] ldq_7_bits_uop_rob_idx;
reg [2:0] ldq_7_bits_uop_ldq_idx;
reg [2:0] ldq_7_bits_uop_stq_idx;
reg [1:0] ldq_7_bits_uop_rxq_idx;
reg [5:0] ldq_7_bits_uop_pdst;
reg [5:0] ldq_7_bits_uop_prs1;
reg [5:0] ldq_7_bits_uop_prs2;
reg [5:0] ldq_7_bits_uop_prs3;
reg ldq_7_bits_uop_prs1_busy;
reg ldq_7_bits_uop_prs2_busy;
reg ldq_7_bits_uop_prs3_busy;
reg [5:0] ldq_7_bits_uop_stale_pdst;
reg ldq_7_bits_uop_exception;
reg [63:0] ldq_7_bits_uop_exc_cause;
reg ldq_7_bits_uop_bypassable;
reg [4:0] ldq_7_bits_uop_mem_cmd;
reg [1:0] ldq_7_bits_uop_mem_size;
reg ldq_7_bits_uop_mem_signed;
reg ldq_7_bits_uop_is_fence;
reg ldq_7_bits_uop_is_fencei;
reg ldq_7_bits_uop_is_amo;
reg ldq_7_bits_uop_uses_ldq;
reg ldq_7_bits_uop_uses_stq;
reg ldq_7_bits_uop_is_sys_pc2epc;
reg ldq_7_bits_uop_is_unique;
reg ldq_7_bits_uop_flush_on_commit;
reg ldq_7_bits_uop_ldst_is_rs1;
reg [5:0] ldq_7_bits_uop_ldst;
reg [5:0] ldq_7_bits_uop_lrs1;
reg [5:0] ldq_7_bits_uop_lrs2;
reg [5:0] ldq_7_bits_uop_lrs3;
reg ldq_7_bits_uop_ldst_val;
reg [1:0] ldq_7_bits_uop_dst_rtype;
reg [1:0] ldq_7_bits_uop_lrs1_rtype;
reg [1:0] ldq_7_bits_uop_lrs2_rtype;
reg ldq_7_bits_uop_frs3_en;
reg ldq_7_bits_uop_fp_val;
reg ldq_7_bits_uop_fp_single;
reg ldq_7_bits_uop_xcpt_pf_if;
reg ldq_7_bits_uop_xcpt_ae_if;
reg ldq_7_bits_uop_xcpt_ma_if;
reg ldq_7_bits_uop_bp_debug_if;
reg ldq_7_bits_uop_bp_xcpt_if;
reg [1:0] ldq_7_bits_uop_debug_fsrc;
reg [1:0] ldq_7_bits_uop_debug_tsrc;
reg ldq_7_bits_addr_valid;
reg [39:0] ldq_7_bits_addr_bits;
reg ldq_7_bits_addr_is_virtual;
reg ldq_7_bits_addr_is_uncacheable;
reg ldq_7_bits_executed;
reg ldq_7_bits_succeeded;
reg ldq_7_bits_order_fail;
reg ldq_7_bits_observed;
reg [7:0] ldq_7_bits_st_dep_mask;
reg [2:0] ldq_7_bits_youngest_stq_idx;
reg ldq_7_bits_forward_std_val;
reg [2:0] ldq_7_bits_forward_stq_idx;
reg stq_0_valid;
reg [6:0] stq_0_bits_uop_uopc;
reg [31:0] stq_0_bits_uop_inst;
reg [31:0] stq_0_bits_uop_debug_inst;
reg stq_0_bits_uop_is_rvc;
reg [39:0] stq_0_bits_uop_debug_pc;
reg [2:0] stq_0_bits_uop_iq_type;
reg [9:0] stq_0_bits_uop_fu_code;
reg [3:0] stq_0_bits_uop_ctrl_br_type;
reg [1:0] stq_0_bits_uop_ctrl_op1_sel;
reg [2:0] stq_0_bits_uop_ctrl_op2_sel;
reg [2:0] stq_0_bits_uop_ctrl_imm_sel;
reg [4:0] stq_0_bits_uop_ctrl_op_fcn;
reg stq_0_bits_uop_ctrl_fcn_dw;
reg [2:0] stq_0_bits_uop_ctrl_csr_cmd;
reg stq_0_bits_uop_ctrl_is_load;
reg stq_0_bits_uop_ctrl_is_sta;
reg stq_0_bits_uop_ctrl_is_std;
reg [1:0] stq_0_bits_uop_iw_state;
reg stq_0_bits_uop_iw_p1_poisoned;
reg stq_0_bits_uop_iw_p2_poisoned;
reg stq_0_bits_uop_is_br;
reg stq_0_bits_uop_is_jalr;
reg stq_0_bits_uop_is_jal;
reg stq_0_bits_uop_is_sfb;
reg [7:0] stq_0_bits_uop_br_mask;
reg [2:0] stq_0_bits_uop_br_tag;
reg [3:0] stq_0_bits_uop_ftq_idx;
reg stq_0_bits_uop_edge_inst;
reg [5:0] stq_0_bits_uop_pc_lob;
reg stq_0_bits_uop_taken;
reg [19:0] stq_0_bits_uop_imm_packed;
reg [11:0] stq_0_bits_uop_csr_addr;
reg [4:0] stq_0_bits_uop_rob_idx;
reg [2:0] stq_0_bits_uop_ldq_idx;
reg [2:0] stq_0_bits_uop_stq_idx;
reg [1:0] stq_0_bits_uop_rxq_idx;
reg [5:0] stq_0_bits_uop_pdst;
reg [5:0] stq_0_bits_uop_prs1;
reg [5:0] stq_0_bits_uop_prs2;
reg [5:0] stq_0_bits_uop_prs3;
reg [3:0] stq_0_bits_uop_ppred;
reg stq_0_bits_uop_prs1_busy;
reg stq_0_bits_uop_prs2_busy;
reg stq_0_bits_uop_prs3_busy;
reg stq_0_bits_uop_ppred_busy;
reg [5:0] stq_0_bits_uop_stale_pdst;
reg stq_0_bits_uop_exception;
reg [63:0] stq_0_bits_uop_exc_cause;
reg stq_0_bits_uop_bypassable;
reg [4:0] stq_0_bits_uop_mem_cmd;
reg [1:0] stq_0_bits_uop_mem_size;
reg stq_0_bits_uop_mem_signed;
reg stq_0_bits_uop_is_fence;
reg stq_0_bits_uop_is_fencei;
reg stq_0_bits_uop_is_amo;
reg stq_0_bits_uop_uses_ldq;
reg stq_0_bits_uop_uses_stq;
reg stq_0_bits_uop_is_sys_pc2epc;
reg stq_0_bits_uop_is_unique;
reg stq_0_bits_uop_flush_on_commit;
reg stq_0_bits_uop_ldst_is_rs1;
reg [5:0] stq_0_bits_uop_ldst;
reg [5:0] stq_0_bits_uop_lrs1;
reg [5:0] stq_0_bits_uop_lrs2;
reg [5:0] stq_0_bits_uop_lrs3;
reg stq_0_bits_uop_ldst_val;
reg [1:0] stq_0_bits_uop_dst_rtype;
reg [1:0] stq_0_bits_uop_lrs1_rtype;
reg [1:0] stq_0_bits_uop_lrs2_rtype;
reg stq_0_bits_uop_frs3_en;
reg stq_0_bits_uop_fp_val;
reg stq_0_bits_uop_fp_single;
reg stq_0_bits_uop_xcpt_pf_if;
reg stq_0_bits_uop_xcpt_ae_if;
reg stq_0_bits_uop_xcpt_ma_if;
reg stq_0_bits_uop_bp_debug_if;
reg stq_0_bits_uop_bp_xcpt_if;
reg [1:0] stq_0_bits_uop_debug_fsrc;
reg [1:0] stq_0_bits_uop_debug_tsrc;
reg stq_0_bits_addr_valid;
reg [39:0] stq_0_bits_addr_bits;
reg stq_0_bits_addr_is_virtual;
reg stq_0_bits_data_valid;
reg [63:0] stq_0_bits_data_bits;
reg stq_0_bits_committed;
reg stq_0_bits_succeeded;
reg stq_1_valid;
reg [6:0] stq_1_bits_uop_uopc;
reg [31:0] stq_1_bits_uop_inst;
reg [31:0] stq_1_bits_uop_debug_inst;
reg stq_1_bits_uop_is_rvc;
reg [39:0] stq_1_bits_uop_debug_pc;
reg [2:0] stq_1_bits_uop_iq_type;
reg [9:0] stq_1_bits_uop_fu_code;
reg [3:0] stq_1_bits_uop_ctrl_br_type;
reg [1:0] stq_1_bits_uop_ctrl_op1_sel;
reg [2:0] stq_1_bits_uop_ctrl_op2_sel;
reg [2:0] stq_1_bits_uop_ctrl_imm_sel;
reg [4:0] stq_1_bits_uop_ctrl_op_fcn;
reg stq_1_bits_uop_ctrl_fcn_dw;
reg [2:0] stq_1_bits_uop_ctrl_csr_cmd;
reg stq_1_bits_uop_ctrl_is_load;
reg stq_1_bits_uop_ctrl_is_sta;
reg stq_1_bits_uop_ctrl_is_std;
reg [1:0] stq_1_bits_uop_iw_state;
reg stq_1_bits_uop_iw_p1_poisoned;
reg stq_1_bits_uop_iw_p2_poisoned;
reg stq_1_bits_uop_is_br;
reg stq_1_bits_uop_is_jalr;
reg stq_1_bits_uop_is_jal;
reg stq_1_bits_uop_is_sfb;
reg [7:0] stq_1_bits_uop_br_mask;
reg [2:0] stq_1_bits_uop_br_tag;
reg [3:0] stq_1_bits_uop_ftq_idx;
reg stq_1_bits_uop_edge_inst;
reg [5:0] stq_1_bits_uop_pc_lob;
reg stq_1_bits_uop_taken;
reg [19:0] stq_1_bits_uop_imm_packed;
reg [11:0] stq_1_bits_uop_csr_addr;
reg [4:0] stq_1_bits_uop_rob_idx;
reg [2:0] stq_1_bits_uop_ldq_idx;
reg [2:0] stq_1_bits_uop_stq_idx;
reg [1:0] stq_1_bits_uop_rxq_idx;
reg [5:0] stq_1_bits_uop_pdst;
reg [5:0] stq_1_bits_uop_prs1;
reg [5:0] stq_1_bits_uop_prs2;
reg [5:0] stq_1_bits_uop_prs3;
reg [3:0] stq_1_bits_uop_ppred;
reg stq_1_bits_uop_prs1_busy;
reg stq_1_bits_uop_prs2_busy;
reg stq_1_bits_uop_prs3_busy;
reg stq_1_bits_uop_ppred_busy;
reg [5:0] stq_1_bits_uop_stale_pdst;
reg stq_1_bits_uop_exception;
reg [63:0] stq_1_bits_uop_exc_cause;
reg stq_1_bits_uop_bypassable;
reg [4:0] stq_1_bits_uop_mem_cmd;
reg [1:0] stq_1_bits_uop_mem_size;
reg stq_1_bits_uop_mem_signed;
reg stq_1_bits_uop_is_fence;
reg stq_1_bits_uop_is_fencei;
reg stq_1_bits_uop_is_amo;
reg stq_1_bits_uop_uses_ldq;
reg stq_1_bits_uop_uses_stq;
reg stq_1_bits_uop_is_sys_pc2epc;
reg stq_1_bits_uop_is_unique;
reg stq_1_bits_uop_flush_on_commit;
reg stq_1_bits_uop_ldst_is_rs1;
reg [5:0] stq_1_bits_uop_ldst;
reg [5:0] stq_1_bits_uop_lrs1;
reg [5:0] stq_1_bits_uop_lrs2;
reg [5:0] stq_1_bits_uop_lrs3;
reg stq_1_bits_uop_ldst_val;
reg [1:0] stq_1_bits_uop_dst_rtype;
reg [1:0] stq_1_bits_uop_lrs1_rtype;
reg [1:0] stq_1_bits_uop_lrs2_rtype;
reg stq_1_bits_uop_frs3_en;
reg stq_1_bits_uop_fp_val;
reg stq_1_bits_uop_fp_single;
reg stq_1_bits_uop_xcpt_pf_if;
reg stq_1_bits_uop_xcpt_ae_if;
reg stq_1_bits_uop_xcpt_ma_if;
reg stq_1_bits_uop_bp_debug_if;
reg stq_1_bits_uop_bp_xcpt_if;
reg [1:0] stq_1_bits_uop_debug_fsrc;
reg [1:0] stq_1_bits_uop_debug_tsrc;
reg stq_1_bits_addr_valid;
reg [39:0] stq_1_bits_addr_bits;
reg stq_1_bits_addr_is_virtual;
reg stq_1_bits_data_valid;
reg [63:0] stq_1_bits_data_bits;
reg stq_1_bits_committed;
reg stq_1_bits_succeeded;
reg stq_2_valid;
reg [6:0] stq_2_bits_uop_uopc;
reg [31:0] stq_2_bits_uop_inst;
reg [31:0] stq_2_bits_uop_debug_inst;
reg stq_2_bits_uop_is_rvc;
reg [39:0] stq_2_bits_uop_debug_pc;
reg [2:0] stq_2_bits_uop_iq_type;
reg [9:0] stq_2_bits_uop_fu_code;
reg [3:0] stq_2_bits_uop_ctrl_br_type;
reg [1:0] stq_2_bits_uop_ctrl_op1_sel;
reg [2:0] stq_2_bits_uop_ctrl_op2_sel;
reg [2:0] stq_2_bits_uop_ctrl_imm_sel;
reg [4:0] stq_2_bits_uop_ctrl_op_fcn;
reg stq_2_bits_uop_ctrl_fcn_dw;
reg [2:0] stq_2_bits_uop_ctrl_csr_cmd;
reg stq_2_bits_uop_ctrl_is_load;
reg stq_2_bits_uop_ctrl_is_sta;
reg stq_2_bits_uop_ctrl_is_std;
reg [1:0] stq_2_bits_uop_iw_state;
reg stq_2_bits_uop_iw_p1_poisoned;
reg stq_2_bits_uop_iw_p2_poisoned;
reg stq_2_bits_uop_is_br;
reg stq_2_bits_uop_is_jalr;
reg stq_2_bits_uop_is_jal;
reg stq_2_bits_uop_is_sfb;
reg [7:0] stq_2_bits_uop_br_mask;
reg [2:0] stq_2_bits_uop_br_tag;
reg [3:0] stq_2_bits_uop_ftq_idx;
reg stq_2_bits_uop_edge_inst;
reg [5:0] stq_2_bits_uop_pc_lob;
reg stq_2_bits_uop_taken;
reg [19:0] stq_2_bits_uop_imm_packed;
reg [11:0] stq_2_bits_uop_csr_addr;
reg [4:0] stq_2_bits_uop_rob_idx;
reg [2:0] stq_2_bits_uop_ldq_idx;
reg [2:0] stq_2_bits_uop_stq_idx;
reg [1:0] stq_2_bits_uop_rxq_idx;
reg [5:0] stq_2_bits_uop_pdst;
reg [5:0] stq_2_bits_uop_prs1;
reg [5:0] stq_2_bits_uop_prs2;
reg [5:0] stq_2_bits_uop_prs3;
reg [3:0] stq_2_bits_uop_ppred;
reg stq_2_bits_uop_prs1_busy;
reg stq_2_bits_uop_prs2_busy;
reg stq_2_bits_uop_prs3_busy;
reg stq_2_bits_uop_ppred_busy;
reg [5:0] stq_2_bits_uop_stale_pdst;
reg stq_2_bits_uop_exception;
reg [63:0] stq_2_bits_uop_exc_cause;
reg stq_2_bits_uop_bypassable;
reg [4:0] stq_2_bits_uop_mem_cmd;
reg [1:0] stq_2_bits_uop_mem_size;
reg stq_2_bits_uop_mem_signed;
reg stq_2_bits_uop_is_fence;
reg stq_2_bits_uop_is_fencei;
reg stq_2_bits_uop_is_amo;
reg stq_2_bits_uop_uses_ldq;
reg stq_2_bits_uop_uses_stq;
reg stq_2_bits_uop_is_sys_pc2epc;
reg stq_2_bits_uop_is_unique;
reg stq_2_bits_uop_flush_on_commit;
reg stq_2_bits_uop_ldst_is_rs1;
reg [5:0] stq_2_bits_uop_ldst;
reg [5:0] stq_2_bits_uop_lrs1;
reg [5:0] stq_2_bits_uop_lrs2;
reg [5:0] stq_2_bits_uop_lrs3;
reg stq_2_bits_uop_ldst_val;
reg [1:0] stq_2_bits_uop_dst_rtype;
reg [1:0] stq_2_bits_uop_lrs1_rtype;
reg [1:0] stq_2_bits_uop_lrs2_rtype;
reg stq_2_bits_uop_frs3_en;
reg stq_2_bits_uop_fp_val;
reg stq_2_bits_uop_fp_single;
reg stq_2_bits_uop_xcpt_pf_if;
reg stq_2_bits_uop_xcpt_ae_if;
reg stq_2_bits_uop_xcpt_ma_if;
reg stq_2_bits_uop_bp_debug_if;
reg stq_2_bits_uop_bp_xcpt_if;
reg [1:0] stq_2_bits_uop_debug_fsrc;
reg [1:0] stq_2_bits_uop_debug_tsrc;
reg stq_2_bits_addr_valid;
reg [39:0] stq_2_bits_addr_bits;
reg stq_2_bits_addr_is_virtual;
reg stq_2_bits_data_valid;
reg [63:0] stq_2_bits_data_bits;
reg stq_2_bits_committed;
reg stq_2_bits_succeeded;
reg stq_3_valid;
reg [6:0] stq_3_bits_uop_uopc;
reg [31:0] stq_3_bits_uop_inst;
reg [31:0] stq_3_bits_uop_debug_inst;
reg stq_3_bits_uop_is_rvc;
reg [39:0] stq_3_bits_uop_debug_pc;
reg [2:0] stq_3_bits_uop_iq_type;
reg [9:0] stq_3_bits_uop_fu_code;
reg [3:0] stq_3_bits_uop_ctrl_br_type;
reg [1:0] stq_3_bits_uop_ctrl_op1_sel;
reg [2:0] stq_3_bits_uop_ctrl_op2_sel;
reg [2:0] stq_3_bits_uop_ctrl_imm_sel;
reg [4:0] stq_3_bits_uop_ctrl_op_fcn;
reg stq_3_bits_uop_ctrl_fcn_dw;
reg [2:0] stq_3_bits_uop_ctrl_csr_cmd;
reg stq_3_bits_uop_ctrl_is_load;
reg stq_3_bits_uop_ctrl_is_sta;
reg stq_3_bits_uop_ctrl_is_std;
reg [1:0] stq_3_bits_uop_iw_state;
reg stq_3_bits_uop_iw_p1_poisoned;
reg stq_3_bits_uop_iw_p2_poisoned;
reg stq_3_bits_uop_is_br;
reg stq_3_bits_uop_is_jalr;
reg stq_3_bits_uop_is_jal;
reg stq_3_bits_uop_is_sfb;
reg [7:0] stq_3_bits_uop_br_mask;
reg [2:0] stq_3_bits_uop_br_tag;
reg [3:0] stq_3_bits_uop_ftq_idx;
reg stq_3_bits_uop_edge_inst;
reg [5:0] stq_3_bits_uop_pc_lob;
reg stq_3_bits_uop_taken;
reg [19:0] stq_3_bits_uop_imm_packed;
reg [11:0] stq_3_bits_uop_csr_addr;
reg [4:0] stq_3_bits_uop_rob_idx;
reg [2:0] stq_3_bits_uop_ldq_idx;
reg [2:0] stq_3_bits_uop_stq_idx;
reg [1:0] stq_3_bits_uop_rxq_idx;
reg [5:0] stq_3_bits_uop_pdst;
reg [5:0] stq_3_bits_uop_prs1;
reg [5:0] stq_3_bits_uop_prs2;
reg [5:0] stq_3_bits_uop_prs3;
reg [3:0] stq_3_bits_uop_ppred;
reg stq_3_bits_uop_prs1_busy;
reg stq_3_bits_uop_prs2_busy;
reg stq_3_bits_uop_prs3_busy;
reg stq_3_bits_uop_ppred_busy;
reg [5:0] stq_3_bits_uop_stale_pdst;
reg stq_3_bits_uop_exception;
reg [63:0] stq_3_bits_uop_exc_cause;
reg stq_3_bits_uop_bypassable;
reg [4:0] stq_3_bits_uop_mem_cmd;
reg [1:0] stq_3_bits_uop_mem_size;
reg stq_3_bits_uop_mem_signed;
reg stq_3_bits_uop_is_fence;
reg stq_3_bits_uop_is_fencei;
reg stq_3_bits_uop_is_amo;
reg stq_3_bits_uop_uses_ldq;
reg stq_3_bits_uop_uses_stq;
reg stq_3_bits_uop_is_sys_pc2epc;
reg stq_3_bits_uop_is_unique;
reg stq_3_bits_uop_flush_on_commit;
reg stq_3_bits_uop_ldst_is_rs1;
reg [5:0] stq_3_bits_uop_ldst;
reg [5:0] stq_3_bits_uop_lrs1;
reg [5:0] stq_3_bits_uop_lrs2;
reg [5:0] stq_3_bits_uop_lrs3;
reg stq_3_bits_uop_ldst_val;
reg [1:0] stq_3_bits_uop_dst_rtype;
reg [1:0] stq_3_bits_uop_lrs1_rtype;
reg [1:0] stq_3_bits_uop_lrs2_rtype;
reg stq_3_bits_uop_frs3_en;
reg stq_3_bits_uop_fp_val;
reg stq_3_bits_uop_fp_single;
reg stq_3_bits_uop_xcpt_pf_if;
reg stq_3_bits_uop_xcpt_ae_if;
reg stq_3_bits_uop_xcpt_ma_if;
reg stq_3_bits_uop_bp_debug_if;
reg stq_3_bits_uop_bp_xcpt_if;
reg [1:0] stq_3_bits_uop_debug_fsrc;
reg [1:0] stq_3_bits_uop_debug_tsrc;
reg stq_3_bits_addr_valid;
reg [39:0] stq_3_bits_addr_bits;
reg stq_3_bits_addr_is_virtual;
reg stq_3_bits_data_valid;
reg [63:0] stq_3_bits_data_bits;
reg stq_3_bits_committed;
reg stq_3_bits_succeeded;
reg stq_4_valid;
reg [6:0] stq_4_bits_uop_uopc;
reg [31:0] stq_4_bits_uop_inst;
reg [31:0] stq_4_bits_uop_debug_inst;
reg stq_4_bits_uop_is_rvc;
reg [39:0] stq_4_bits_uop_debug_pc;
reg [2:0] stq_4_bits_uop_iq_type;
reg [9:0] stq_4_bits_uop_fu_code;
reg [3:0] stq_4_bits_uop_ctrl_br_type;
reg [1:0] stq_4_bits_uop_ctrl_op1_sel;
reg [2:0] stq_4_bits_uop_ctrl_op2_sel;
reg [2:0] stq_4_bits_uop_ctrl_imm_sel;
reg [4:0] stq_4_bits_uop_ctrl_op_fcn;
reg stq_4_bits_uop_ctrl_fcn_dw;
reg [2:0] stq_4_bits_uop_ctrl_csr_cmd;
reg stq_4_bits_uop_ctrl_is_load;
reg stq_4_bits_uop_ctrl_is_sta;
reg stq_4_bits_uop_ctrl_is_std;
reg [1:0] stq_4_bits_uop_iw_state;
reg stq_4_bits_uop_iw_p1_poisoned;
reg stq_4_bits_uop_iw_p2_poisoned;
reg stq_4_bits_uop_is_br;
reg stq_4_bits_uop_is_jalr;
reg stq_4_bits_uop_is_jal;
reg stq_4_bits_uop_is_sfb;
reg [7:0] stq_4_bits_uop_br_mask;
reg [2:0] stq_4_bits_uop_br_tag;
reg [3:0] stq_4_bits_uop_ftq_idx;
reg stq_4_bits_uop_edge_inst;
reg [5:0] stq_4_bits_uop_pc_lob;
reg stq_4_bits_uop_taken;
reg [19:0] stq_4_bits_uop_imm_packed;
reg [11:0] stq_4_bits_uop_csr_addr;
reg [4:0] stq_4_bits_uop_rob_idx;
reg [2:0] stq_4_bits_uop_ldq_idx;
reg [2:0] stq_4_bits_uop_stq_idx;
reg [1:0] stq_4_bits_uop_rxq_idx;
reg [5:0] stq_4_bits_uop_pdst;
reg [5:0] stq_4_bits_uop_prs1;
reg [5:0] stq_4_bits_uop_prs2;
reg [5:0] stq_4_bits_uop_prs3;
reg [3:0] stq_4_bits_uop_ppred;
reg stq_4_bits_uop_prs1_busy;
reg stq_4_bits_uop_prs2_busy;
reg stq_4_bits_uop_prs3_busy;
reg stq_4_bits_uop_ppred_busy;
reg [5:0] stq_4_bits_uop_stale_pdst;
reg stq_4_bits_uop_exception;
reg [63:0] stq_4_bits_uop_exc_cause;
reg stq_4_bits_uop_bypassable;
reg [4:0] stq_4_bits_uop_mem_cmd;
reg [1:0] stq_4_bits_uop_mem_size;
reg stq_4_bits_uop_mem_signed;
reg stq_4_bits_uop_is_fence;
reg stq_4_bits_uop_is_fencei;
reg stq_4_bits_uop_is_amo;
reg stq_4_bits_uop_uses_ldq;
reg stq_4_bits_uop_uses_stq;
reg stq_4_bits_uop_is_sys_pc2epc;
reg stq_4_bits_uop_is_unique;
reg stq_4_bits_uop_flush_on_commit;
reg stq_4_bits_uop_ldst_is_rs1;
reg [5:0] stq_4_bits_uop_ldst;
reg [5:0] stq_4_bits_uop_lrs1;
reg [5:0] stq_4_bits_uop_lrs2;
reg [5:0] stq_4_bits_uop_lrs3;
reg stq_4_bits_uop_ldst_val;
reg [1:0] stq_4_bits_uop_dst_rtype;
reg [1:0] stq_4_bits_uop_lrs1_rtype;
reg [1:0] stq_4_bits_uop_lrs2_rtype;
reg stq_4_bits_uop_frs3_en;
reg stq_4_bits_uop_fp_val;
reg stq_4_bits_uop_fp_single;
reg stq_4_bits_uop_xcpt_pf_if;
reg stq_4_bits_uop_xcpt_ae_if;
reg stq_4_bits_uop_xcpt_ma_if;
reg stq_4_bits_uop_bp_debug_if;
reg stq_4_bits_uop_bp_xcpt_if;
reg [1:0] stq_4_bits_uop_debug_fsrc;
reg [1:0] stq_4_bits_uop_debug_tsrc;
reg stq_4_bits_addr_valid;
reg [39:0] stq_4_bits_addr_bits;
reg stq_4_bits_addr_is_virtual;
reg stq_4_bits_data_valid;
reg [63:0] stq_4_bits_data_bits;
reg stq_4_bits_committed;
reg stq_4_bits_succeeded;
reg stq_5_valid;
reg [6:0] stq_5_bits_uop_uopc;
reg [31:0] stq_5_bits_uop_inst;
reg [31:0] stq_5_bits_uop_debug_inst;
reg stq_5_bits_uop_is_rvc;
reg [39:0] stq_5_bits_uop_debug_pc;
reg [2:0] stq_5_bits_uop_iq_type;
reg [9:0] stq_5_bits_uop_fu_code;
reg [3:0] stq_5_bits_uop_ctrl_br_type;
reg [1:0] stq_5_bits_uop_ctrl_op1_sel;
reg [2:0] stq_5_bits_uop_ctrl_op2_sel;
reg [2:0] stq_5_bits_uop_ctrl_imm_sel;
reg [4:0] stq_5_bits_uop_ctrl_op_fcn;
reg stq_5_bits_uop_ctrl_fcn_dw;
reg [2:0] stq_5_bits_uop_ctrl_csr_cmd;
reg stq_5_bits_uop_ctrl_is_load;
reg stq_5_bits_uop_ctrl_is_sta;
reg stq_5_bits_uop_ctrl_is_std;
reg [1:0] stq_5_bits_uop_iw_state;
reg stq_5_bits_uop_iw_p1_poisoned;
reg stq_5_bits_uop_iw_p2_poisoned;
reg stq_5_bits_uop_is_br;
reg stq_5_bits_uop_is_jalr;
reg stq_5_bits_uop_is_jal;
reg stq_5_bits_uop_is_sfb;
reg [7:0] stq_5_bits_uop_br_mask;
reg [2:0] stq_5_bits_uop_br_tag;
reg [3:0] stq_5_bits_uop_ftq_idx;
reg stq_5_bits_uop_edge_inst;
reg [5:0] stq_5_bits_uop_pc_lob;
reg stq_5_bits_uop_taken;
reg [19:0] stq_5_bits_uop_imm_packed;
reg [11:0] stq_5_bits_uop_csr_addr;
reg [4:0] stq_5_bits_uop_rob_idx;
reg [2:0] stq_5_bits_uop_ldq_idx;
reg [2:0] stq_5_bits_uop_stq_idx;
reg [1:0] stq_5_bits_uop_rxq_idx;
reg [5:0] stq_5_bits_uop_pdst;
reg [5:0] stq_5_bits_uop_prs1;
reg [5:0] stq_5_bits_uop_prs2;
reg [5:0] stq_5_bits_uop_prs3;
reg [3:0] stq_5_bits_uop_ppred;
reg stq_5_bits_uop_prs1_busy;
reg stq_5_bits_uop_prs2_busy;
reg stq_5_bits_uop_prs3_busy;
reg stq_5_bits_uop_ppred_busy;
reg [5:0] stq_5_bits_uop_stale_pdst;
reg stq_5_bits_uop_exception;
reg [63:0] stq_5_bits_uop_exc_cause;
reg stq_5_bits_uop_bypassable;
reg [4:0] stq_5_bits_uop_mem_cmd;
reg [1:0] stq_5_bits_uop_mem_size;
reg stq_5_bits_uop_mem_signed;
reg stq_5_bits_uop_is_fence;
reg stq_5_bits_uop_is_fencei;
reg stq_5_bits_uop_is_amo;
reg stq_5_bits_uop_uses_ldq;
reg stq_5_bits_uop_uses_stq;
reg stq_5_bits_uop_is_sys_pc2epc;
reg stq_5_bits_uop_is_unique;
reg stq_5_bits_uop_flush_on_commit;
reg stq_5_bits_uop_ldst_is_rs1;
reg [5:0] stq_5_bits_uop_ldst;
reg [5:0] stq_5_bits_uop_lrs1;
reg [5:0] stq_5_bits_uop_lrs2;
reg [5:0] stq_5_bits_uop_lrs3;
reg stq_5_bits_uop_ldst_val;
reg [1:0] stq_5_bits_uop_dst_rtype;
reg [1:0] stq_5_bits_uop_lrs1_rtype;
reg [1:0] stq_5_bits_uop_lrs2_rtype;
reg stq_5_bits_uop_frs3_en;
reg stq_5_bits_uop_fp_val;
reg stq_5_bits_uop_fp_single;
reg stq_5_bits_uop_xcpt_pf_if;
reg stq_5_bits_uop_xcpt_ae_if;
reg stq_5_bits_uop_xcpt_ma_if;
reg stq_5_bits_uop_bp_debug_if;
reg stq_5_bits_uop_bp_xcpt_if;
reg [1:0] stq_5_bits_uop_debug_fsrc;
reg [1:0] stq_5_bits_uop_debug_tsrc;
reg stq_5_bits_addr_valid;
reg [39:0] stq_5_bits_addr_bits;
reg stq_5_bits_addr_is_virtual;
reg stq_5_bits_data_valid;
reg [63:0] stq_5_bits_data_bits;
reg stq_5_bits_committed;
reg stq_5_bits_succeeded;
reg stq_6_valid;
reg [6:0] stq_6_bits_uop_uopc;
reg [31:0] stq_6_bits_uop_inst;
reg [31:0] stq_6_bits_uop_debug_inst;
reg stq_6_bits_uop_is_rvc;
reg [39:0] stq_6_bits_uop_debug_pc;
reg [2:0] stq_6_bits_uop_iq_type;
reg [9:0] stq_6_bits_uop_fu_code;
reg [3:0] stq_6_bits_uop_ctrl_br_type;
reg [1:0] stq_6_bits_uop_ctrl_op1_sel;
reg [2:0] stq_6_bits_uop_ctrl_op2_sel;
reg [2:0] stq_6_bits_uop_ctrl_imm_sel;
reg [4:0] stq_6_bits_uop_ctrl_op_fcn;
reg stq_6_bits_uop_ctrl_fcn_dw;
reg [2:0] stq_6_bits_uop_ctrl_csr_cmd;
reg stq_6_bits_uop_ctrl_is_load;
reg stq_6_bits_uop_ctrl_is_sta;
reg stq_6_bits_uop_ctrl_is_std;
reg [1:0] stq_6_bits_uop_iw_state;
reg stq_6_bits_uop_iw_p1_poisoned;
reg stq_6_bits_uop_iw_p2_poisoned;
reg stq_6_bits_uop_is_br;
reg stq_6_bits_uop_is_jalr;
reg stq_6_bits_uop_is_jal;
reg stq_6_bits_uop_is_sfb;
reg [7:0] stq_6_bits_uop_br_mask;
reg [2:0] stq_6_bits_uop_br_tag;
reg [3:0] stq_6_bits_uop_ftq_idx;
reg stq_6_bits_uop_edge_inst;
reg [5:0] stq_6_bits_uop_pc_lob;
reg stq_6_bits_uop_taken;
reg [19:0] stq_6_bits_uop_imm_packed;
reg [11:0] stq_6_bits_uop_csr_addr;
reg [4:0] stq_6_bits_uop_rob_idx;
reg [2:0] stq_6_bits_uop_ldq_idx;
reg [2:0] stq_6_bits_uop_stq_idx;
reg [1:0] stq_6_bits_uop_rxq_idx;
reg [5:0] stq_6_bits_uop_pdst;
reg [5:0] stq_6_bits_uop_prs1;
reg [5:0] stq_6_bits_uop_prs2;
reg [5:0] stq_6_bits_uop_prs3;
reg [3:0] stq_6_bits_uop_ppred;
reg stq_6_bits_uop_prs1_busy;
reg stq_6_bits_uop_prs2_busy;
reg stq_6_bits_uop_prs3_busy;
reg stq_6_bits_uop_ppred_busy;
reg [5:0] stq_6_bits_uop_stale_pdst;
reg stq_6_bits_uop_exception;
reg [63:0] stq_6_bits_uop_exc_cause;
reg stq_6_bits_uop_bypassable;
reg [4:0] stq_6_bits_uop_mem_cmd;
reg [1:0] stq_6_bits_uop_mem_size;
reg stq_6_bits_uop_mem_signed;
reg stq_6_bits_uop_is_fence;
reg stq_6_bits_uop_is_fencei;
reg stq_6_bits_uop_is_amo;
reg stq_6_bits_uop_uses_ldq;
reg stq_6_bits_uop_uses_stq;
reg stq_6_bits_uop_is_sys_pc2epc;
reg stq_6_bits_uop_is_unique;
reg stq_6_bits_uop_flush_on_commit;
reg stq_6_bits_uop_ldst_is_rs1;
reg [5:0] stq_6_bits_uop_ldst;
reg [5:0] stq_6_bits_uop_lrs1;
reg [5:0] stq_6_bits_uop_lrs2;
reg [5:0] stq_6_bits_uop_lrs3;
reg stq_6_bits_uop_ldst_val;
reg [1:0] stq_6_bits_uop_dst_rtype;
reg [1:0] stq_6_bits_uop_lrs1_rtype;
reg [1:0] stq_6_bits_uop_lrs2_rtype;
reg stq_6_bits_uop_frs3_en;
reg stq_6_bits_uop_fp_val;
reg stq_6_bits_uop_fp_single;
reg stq_6_bits_uop_xcpt_pf_if;
reg stq_6_bits_uop_xcpt_ae_if;
reg stq_6_bits_uop_xcpt_ma_if;
reg stq_6_bits_uop_bp_debug_if;
reg stq_6_bits_uop_bp_xcpt_if;
reg [1:0] stq_6_bits_uop_debug_fsrc;
reg [1:0] stq_6_bits_uop_debug_tsrc;
reg stq_6_bits_addr_valid;
reg [39:0] stq_6_bits_addr_bits;
reg stq_6_bits_addr_is_virtual;
reg stq_6_bits_data_valid;
reg [63:0] stq_6_bits_data_bits;
reg stq_6_bits_committed;
reg stq_6_bits_succeeded;
reg stq_7_valid;
reg [6:0] stq_7_bits_uop_uopc;
reg [31:0] stq_7_bits_uop_inst;
reg [31:0] stq_7_bits_uop_debug_inst;
reg stq_7_bits_uop_is_rvc;
reg [39:0] stq_7_bits_uop_debug_pc;
reg [2:0] stq_7_bits_uop_iq_type;
reg [9:0] stq_7_bits_uop_fu_code;
reg [3:0] stq_7_bits_uop_ctrl_br_type;
reg [1:0] stq_7_bits_uop_ctrl_op1_sel;
reg [2:0] stq_7_bits_uop_ctrl_op2_sel;
reg [2:0] stq_7_bits_uop_ctrl_imm_sel;
reg [4:0] stq_7_bits_uop_ctrl_op_fcn;
reg stq_7_bits_uop_ctrl_fcn_dw;
reg [2:0] stq_7_bits_uop_ctrl_csr_cmd;
reg stq_7_bits_uop_ctrl_is_load;
reg stq_7_bits_uop_ctrl_is_sta;
reg stq_7_bits_uop_ctrl_is_std;
reg [1:0] stq_7_bits_uop_iw_state;
reg stq_7_bits_uop_iw_p1_poisoned;
reg stq_7_bits_uop_iw_p2_poisoned;
reg stq_7_bits_uop_is_br;
reg stq_7_bits_uop_is_jalr;
reg stq_7_bits_uop_is_jal;
reg stq_7_bits_uop_is_sfb;
reg [7:0] stq_7_bits_uop_br_mask;
reg [2:0] stq_7_bits_uop_br_tag;
reg [3:0] stq_7_bits_uop_ftq_idx;
reg stq_7_bits_uop_edge_inst;
reg [5:0] stq_7_bits_uop_pc_lob;
reg stq_7_bits_uop_taken;
reg [19:0] stq_7_bits_uop_imm_packed;
reg [11:0] stq_7_bits_uop_csr_addr;
reg [4:0] stq_7_bits_uop_rob_idx;
reg [2:0] stq_7_bits_uop_ldq_idx;
reg [2:0] stq_7_bits_uop_stq_idx;
reg [1:0] stq_7_bits_uop_rxq_idx;
reg [5:0] stq_7_bits_uop_pdst;
reg [5:0] stq_7_bits_uop_prs1;
reg [5:0] stq_7_bits_uop_prs2;
reg [5:0] stq_7_bits_uop_prs3;
reg [3:0] stq_7_bits_uop_ppred;
reg stq_7_bits_uop_prs1_busy;
reg stq_7_bits_uop_prs2_busy;
reg stq_7_bits_uop_prs3_busy;
reg stq_7_bits_uop_ppred_busy;
reg [5:0] stq_7_bits_uop_stale_pdst;
reg stq_7_bits_uop_exception;
reg [63:0] stq_7_bits_uop_exc_cause;
reg stq_7_bits_uop_bypassable;
reg [4:0] stq_7_bits_uop_mem_cmd;
reg [1:0] stq_7_bits_uop_mem_size;
reg stq_7_bits_uop_mem_signed;
reg stq_7_bits_uop_is_fence;
reg stq_7_bits_uop_is_fencei;
reg stq_7_bits_uop_is_amo;
reg stq_7_bits_uop_uses_ldq;
reg stq_7_bits_uop_uses_stq;
reg stq_7_bits_uop_is_sys_pc2epc;
reg stq_7_bits_uop_is_unique;
reg stq_7_bits_uop_flush_on_commit;
reg stq_7_bits_uop_ldst_is_rs1;
reg [5:0] stq_7_bits_uop_ldst;
reg [5:0] stq_7_bits_uop_lrs1;
reg [5:0] stq_7_bits_uop_lrs2;
reg [5:0] stq_7_bits_uop_lrs3;
reg stq_7_bits_uop_ldst_val;
reg [1:0] stq_7_bits_uop_dst_rtype;
reg [1:0] stq_7_bits_uop_lrs1_rtype;
reg [1:0] stq_7_bits_uop_lrs2_rtype;
reg stq_7_bits_uop_frs3_en;
reg stq_7_bits_uop_fp_val;
reg stq_7_bits_uop_fp_single;
reg stq_7_bits_uop_xcpt_pf_if;
reg stq_7_bits_uop_xcpt_ae_if;
reg stq_7_bits_uop_xcpt_ma_if;
reg stq_7_bits_uop_bp_debug_if;
reg stq_7_bits_uop_bp_xcpt_if;
reg [1:0] stq_7_bits_uop_debug_fsrc;
reg [1:0] stq_7_bits_uop_debug_tsrc;
reg stq_7_bits_addr_valid;
reg [39:0] stq_7_bits_addr_bits;
reg stq_7_bits_addr_is_virtual;
reg stq_7_bits_data_valid;
reg [63:0] stq_7_bits_data_bits;
reg stq_7_bits_committed;
reg stq_7_bits_succeeded;
reg [2:0] ldq_head;
reg [2:0] ldq_tail;
reg [2:0] stq_head;
reg [2:0] stq_tail;
reg [2:0] stq_commit_head;
reg [2:0] stq_execute_head;
wire [7:0] _GEN_3 = {{stq_7_valid}, {stq_6_valid}, {stq_5_valid}, {stq_4_valid}, {stq_3_valid}, {stq_2_valid}, {stq_1_valid}, {stq_0_valid}};
wire _GEN_4 = _GEN_3[stq_execute_head];
wire [7:0][6:0] _GEN_5 = {{stq_7_bits_uop_uopc}, {stq_6_bits_uop_uopc}, {stq_5_bits_uop_uopc}, {stq_4_bits_uop_uopc}, {stq_3_bits_uop_uopc}, {stq_2_bits_uop_uopc}, {stq_1_bits_uop_uopc}, {stq_0_bits_uop_uopc}};
wire [7:0][31:0] _GEN_6 = {{stq_7_bits_uop_inst}, {stq_6_bits_uop_inst}, {stq_5_bits_uop_inst}, {stq_4_bits_uop_inst}, {stq_3_bits_uop_inst}, {stq_2_bits_uop_inst}, {stq_1_bits_uop_inst}, {stq_0_bits_uop_inst}};
wire [7:0][31:0] _GEN_7 = {{stq_7_bits_uop_debug_inst}, {stq_6_bits_uop_debug_inst}, {stq_5_bits_uop_debug_inst}, {stq_4_bits_uop_debug_inst}, {stq_3_bits_uop_debug_inst}, {stq_2_bits_uop_debug_inst}, {stq_1_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}};
wire [7:0] _GEN_8 = {{stq_7_bits_uop_is_rvc}, {stq_6_bits_uop_is_rvc}, {stq_5_bits_uop_is_rvc}, {stq_4_bits_uop_is_rvc}, {stq_3_bits_uop_is_rvc}, {stq_2_bits_uop_is_rvc}, {stq_1_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}};
wire [7:0][39:0] _GEN_9 = {{stq_7_bits_uop_debug_pc}, {stq_6_bits_uop_debug_pc}, {stq_5_bits_uop_debug_pc}, {stq_4_bits_uop_debug_pc}, {stq_3_bits_uop_debug_pc}, {stq_2_bits_uop_debug_pc}, {stq_1_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}};
wire [7:0][2:0] _GEN_10 = {{stq_7_bits_uop_iq_type}, {stq_6_bits_uop_iq_type}, {stq_5_bits_uop_iq_type}, {stq_4_bits_uop_iq_type}, {stq_3_bits_uop_iq_type}, {stq_2_bits_uop_iq_type}, {stq_1_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}};
wire [7:0][9:0] _GEN_11 = {{stq_7_bits_uop_fu_code}, {stq_6_bits_uop_fu_code}, {stq_5_bits_uop_fu_code}, {stq_4_bits_uop_fu_code}, {stq_3_bits_uop_fu_code}, {stq_2_bits_uop_fu_code}, {stq_1_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}};
wire [7:0][3:0] _GEN_12 = {{stq_7_bits_uop_ctrl_br_type}, {stq_6_bits_uop_ctrl_br_type}, {stq_5_bits_uop_ctrl_br_type}, {stq_4_bits_uop_ctrl_br_type}, {stq_3_bits_uop_ctrl_br_type}, {stq_2_bits_uop_ctrl_br_type}, {stq_1_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}};
wire [7:0][1:0] _GEN_13 = {{stq_7_bits_uop_ctrl_op1_sel}, {stq_6_bits_uop_ctrl_op1_sel}, {stq_5_bits_uop_ctrl_op1_sel}, {stq_4_bits_uop_ctrl_op1_sel}, {stq_3_bits_uop_ctrl_op1_sel}, {stq_2_bits_uop_ctrl_op1_sel}, {stq_1_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}};
wire [7:0][2:0] _GEN_14 = {{stq_7_bits_uop_ctrl_op2_sel}, {stq_6_bits_uop_ctrl_op2_sel}, {stq_5_bits_uop_ctrl_op2_sel}, {stq_4_bits_uop_ctrl_op2_sel}, {stq_3_bits_uop_ctrl_op2_sel}, {stq_2_bits_uop_ctrl_op2_sel}, {stq_1_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}};
wire [7:0][2:0] _GEN_15 = {{stq_7_bits_uop_ctrl_imm_sel}, {stq_6_bits_uop_ctrl_imm_sel}, {stq_5_bits_uop_ctrl_imm_sel}, {stq_4_bits_uop_ctrl_imm_sel}, {stq_3_bits_uop_ctrl_imm_sel}, {stq_2_bits_uop_ctrl_imm_sel}, {stq_1_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}};
wire [7:0][4:0] _GEN_16 = {{stq_7_bits_uop_ctrl_op_fcn}, {stq_6_bits_uop_ctrl_op_fcn}, {stq_5_bits_uop_ctrl_op_fcn}, {stq_4_bits_uop_ctrl_op_fcn}, {stq_3_bits_uop_ctrl_op_fcn}, {stq_2_bits_uop_ctrl_op_fcn}, {stq_1_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}};
wire [7:0] _GEN_17 = {{stq_7_bits_uop_ctrl_fcn_dw}, {stq_6_bits_uop_ctrl_fcn_dw}, {stq_5_bits_uop_ctrl_fcn_dw}, {stq_4_bits_uop_ctrl_fcn_dw}, {stq_3_bits_uop_ctrl_fcn_dw}, {stq_2_bits_uop_ctrl_fcn_dw}, {stq_1_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}};
wire [7:0][2:0] _GEN_18 = {{stq_7_bits_uop_ctrl_csr_cmd}, {stq_6_bits_uop_ctrl_csr_cmd}, {stq_5_bits_uop_ctrl_csr_cmd}, {stq_4_bits_uop_ctrl_csr_cmd}, {stq_3_bits_uop_ctrl_csr_cmd}, {stq_2_bits_uop_ctrl_csr_cmd}, {stq_1_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}};
wire [7:0] _GEN_19 = {{stq_7_bits_uop_ctrl_is_load}, {stq_6_bits_uop_ctrl_is_load}, {stq_5_bits_uop_ctrl_is_load}, {stq_4_bits_uop_ctrl_is_load}, {stq_3_bits_uop_ctrl_is_load}, {stq_2_bits_uop_ctrl_is_load}, {stq_1_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}};
wire [7:0] _GEN_20 = {{stq_7_bits_uop_ctrl_is_sta}, {stq_6_bits_uop_ctrl_is_sta}, {stq_5_bits_uop_ctrl_is_sta}, {stq_4_bits_uop_ctrl_is_sta}, {stq_3_bits_uop_ctrl_is_sta}, {stq_2_bits_uop_ctrl_is_sta}, {stq_1_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}};
wire [7:0] _GEN_21 = {{stq_7_bits_uop_ctrl_is_std}, {stq_6_bits_uop_ctrl_is_std}, {stq_5_bits_uop_ctrl_is_std}, {stq_4_bits_uop_ctrl_is_std}, {stq_3_bits_uop_ctrl_is_std}, {stq_2_bits_uop_ctrl_is_std}, {stq_1_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}};
wire [7:0][1:0] _GEN_22 = {{stq_7_bits_uop_iw_state}, {stq_6_bits_uop_iw_state}, {stq_5_bits_uop_iw_state}, {stq_4_bits_uop_iw_state}, {stq_3_bits_uop_iw_state}, {stq_2_bits_uop_iw_state}, {stq_1_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}};
wire [7:0] _GEN_23 = {{stq_7_bits_uop_iw_p1_poisoned}, {stq_6_bits_uop_iw_p1_poisoned}, {stq_5_bits_uop_iw_p1_poisoned}, {stq_4_bits_uop_iw_p1_poisoned}, {stq_3_bits_uop_iw_p1_poisoned}, {stq_2_bits_uop_iw_p1_poisoned}, {stq_1_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}};
wire [7:0] _GEN_24 = {{stq_7_bits_uop_iw_p2_poisoned}, {stq_6_bits_uop_iw_p2_poisoned}, {stq_5_bits_uop_iw_p2_poisoned}, {stq_4_bits_uop_iw_p2_poisoned}, {stq_3_bits_uop_iw_p2_poisoned}, {stq_2_bits_uop_iw_p2_poisoned}, {stq_1_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}};
wire [7:0] _GEN_25 = {{stq_7_bits_uop_is_br}, {stq_6_bits_uop_is_br}, {stq_5_bits_uop_is_br}, {stq_4_bits_uop_is_br}, {stq_3_bits_uop_is_br}, {stq_2_bits_uop_is_br}, {stq_1_bits_uop_is_br}, {stq_0_bits_uop_is_br}};
wire [7:0] _GEN_26 = {{stq_7_bits_uop_is_jalr}, {stq_6_bits_uop_is_jalr}, {stq_5_bits_uop_is_jalr}, {stq_4_bits_uop_is_jalr}, {stq_3_bits_uop_is_jalr}, {stq_2_bits_uop_is_jalr}, {stq_1_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}};
wire [7:0] _GEN_27 = {{stq_7_bits_uop_is_jal}, {stq_6_bits_uop_is_jal}, {stq_5_bits_uop_is_jal}, {stq_4_bits_uop_is_jal}, {stq_3_bits_uop_is_jal}, {stq_2_bits_uop_is_jal}, {stq_1_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}};
wire [7:0] _GEN_28 = {{stq_7_bits_uop_is_sfb}, {stq_6_bits_uop_is_sfb}, {stq_5_bits_uop_is_sfb}, {stq_4_bits_uop_is_sfb}, {stq_3_bits_uop_is_sfb}, {stq_2_bits_uop_is_sfb}, {stq_1_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}};
wire [7:0][7:0] _GEN_29 = {{stq_7_bits_uop_br_mask}, {stq_6_bits_uop_br_mask}, {stq_5_bits_uop_br_mask}, {stq_4_bits_uop_br_mask}, {stq_3_bits_uop_br_mask}, {stq_2_bits_uop_br_mask}, {stq_1_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}};
wire [7:0][2:0] _GEN_30 = {{stq_7_bits_uop_br_tag}, {stq_6_bits_uop_br_tag}, {stq_5_bits_uop_br_tag}, {stq_4_bits_uop_br_tag}, {stq_3_bits_uop_br_tag}, {stq_2_bits_uop_br_tag}, {stq_1_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}};
wire [7:0][3:0] _GEN_31 = {{stq_7_bits_uop_ftq_idx}, {stq_6_bits_uop_ftq_idx}, {stq_5_bits_uop_ftq_idx}, {stq_4_bits_uop_ftq_idx}, {stq_3_bits_uop_ftq_idx}, {stq_2_bits_uop_ftq_idx}, {stq_1_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}};
wire [7:0] _GEN_32 = {{stq_7_bits_uop_edge_inst}, {stq_6_bits_uop_edge_inst}, {stq_5_bits_uop_edge_inst}, {stq_4_bits_uop_edge_inst}, {stq_3_bits_uop_edge_inst}, {stq_2_bits_uop_edge_inst}, {stq_1_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}};
wire [7:0][5:0] _GEN_33 = {{stq_7_bits_uop_pc_lob}, {stq_6_bits_uop_pc_lob}, {stq_5_bits_uop_pc_lob}, {stq_4_bits_uop_pc_lob}, {stq_3_bits_uop_pc_lob}, {stq_2_bits_uop_pc_lob}, {stq_1_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}};
wire [7:0] _GEN_34 = {{stq_7_bits_uop_taken}, {stq_6_bits_uop_taken}, {stq_5_bits_uop_taken}, {stq_4_bits_uop_taken}, {stq_3_bits_uop_taken}, {stq_2_bits_uop_taken}, {stq_1_bits_uop_taken}, {stq_0_bits_uop_taken}};
wire [7:0][19:0] _GEN_35 = {{stq_7_bits_uop_imm_packed}, {stq_6_bits_uop_imm_packed}, {stq_5_bits_uop_imm_packed}, {stq_4_bits_uop_imm_packed}, {stq_3_bits_uop_imm_packed}, {stq_2_bits_uop_imm_packed}, {stq_1_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}};
wire [7:0][11:0] _GEN_36 = {{stq_7_bits_uop_csr_addr}, {stq_6_bits_uop_csr_addr}, {stq_5_bits_uop_csr_addr}, {stq_4_bits_uop_csr_addr}, {stq_3_bits_uop_csr_addr}, {stq_2_bits_uop_csr_addr}, {stq_1_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}};
wire [7:0][4:0] _GEN_37 = {{stq_7_bits_uop_rob_idx}, {stq_6_bits_uop_rob_idx}, {stq_5_bits_uop_rob_idx}, {stq_4_bits_uop_rob_idx}, {stq_3_bits_uop_rob_idx}, {stq_2_bits_uop_rob_idx}, {stq_1_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}};
wire [7:0][2:0] _GEN_38 = {{stq_7_bits_uop_ldq_idx}, {stq_6_bits_uop_ldq_idx}, {stq_5_bits_uop_ldq_idx}, {stq_4_bits_uop_ldq_idx}, {stq_3_bits_uop_ldq_idx}, {stq_2_bits_uop_ldq_idx}, {stq_1_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}};
wire [7:0][2:0] _GEN_39 = {{stq_7_bits_uop_stq_idx}, {stq_6_bits_uop_stq_idx}, {stq_5_bits_uop_stq_idx}, {stq_4_bits_uop_stq_idx}, {stq_3_bits_uop_stq_idx}, {stq_2_bits_uop_stq_idx}, {stq_1_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}};
wire [7:0][1:0] _GEN_40 = {{stq_7_bits_uop_rxq_idx}, {stq_6_bits_uop_rxq_idx}, {stq_5_bits_uop_rxq_idx}, {stq_4_bits_uop_rxq_idx}, {stq_3_bits_uop_rxq_idx}, {stq_2_bits_uop_rxq_idx}, {stq_1_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}};
wire [7:0][5:0] _GEN_41 = {{stq_7_bits_uop_pdst}, {stq_6_bits_uop_pdst}, {stq_5_bits_uop_pdst}, {stq_4_bits_uop_pdst}, {stq_3_bits_uop_pdst}, {stq_2_bits_uop_pdst}, {stq_1_bits_uop_pdst}, {stq_0_bits_uop_pdst}};
wire [7:0][5:0] _GEN_42 = {{stq_7_bits_uop_prs1}, {stq_6_bits_uop_prs1}, {stq_5_bits_uop_prs1}, {stq_4_bits_uop_prs1}, {stq_3_bits_uop_prs1}, {stq_2_bits_uop_prs1}, {stq_1_bits_uop_prs1}, {stq_0_bits_uop_prs1}};
wire [7:0][5:0] _GEN_43 = {{stq_7_bits_uop_prs2}, {stq_6_bits_uop_prs2}, {stq_5_bits_uop_prs2}, {stq_4_bits_uop_prs2}, {stq_3_bits_uop_prs2}, {stq_2_bits_uop_prs2}, {stq_1_bits_uop_prs2}, {stq_0_bits_uop_prs2}};
wire [7:0][5:0] _GEN_44 = {{stq_7_bits_uop_prs3}, {stq_6_bits_uop_prs3}, {stq_5_bits_uop_prs3}, {stq_4_bits_uop_prs3}, {stq_3_bits_uop_prs3}, {stq_2_bits_uop_prs3}, {stq_1_bits_uop_prs3}, {stq_0_bits_uop_prs3}};
wire [7:0][3:0] _GEN_45 = {{stq_7_bits_uop_ppred}, {stq_6_bits_uop_ppred}, {stq_5_bits_uop_ppred}, {stq_4_bits_uop_ppred}, {stq_3_bits_uop_ppred}, {stq_2_bits_uop_ppred}, {stq_1_bits_uop_ppred}, {stq_0_bits_uop_ppred}};
wire [7:0] _GEN_46 = {{stq_7_bits_uop_prs1_busy}, {stq_6_bits_uop_prs1_busy}, {stq_5_bits_uop_prs1_busy}, {stq_4_bits_uop_prs1_busy}, {stq_3_bits_uop_prs1_busy}, {stq_2_bits_uop_prs1_busy}, {stq_1_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}};
wire [7:0] _GEN_47 = {{stq_7_bits_uop_prs2_busy}, {stq_6_bits_uop_prs2_busy}, {stq_5_bits_uop_prs2_busy}, {stq_4_bits_uop_prs2_busy}, {stq_3_bits_uop_prs2_busy}, {stq_2_bits_uop_prs2_busy}, {stq_1_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}};
wire [7:0] _GEN_48 = {{stq_7_bits_uop_prs3_busy}, {stq_6_bits_uop_prs3_busy}, {stq_5_bits_uop_prs3_busy}, {stq_4_bits_uop_prs3_busy}, {stq_3_bits_uop_prs3_busy}, {stq_2_bits_uop_prs3_busy}, {stq_1_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}};
wire [7:0] _GEN_49 = {{stq_7_bits_uop_ppred_busy}, {stq_6_bits_uop_ppred_busy}, {stq_5_bits_uop_ppred_busy}, {stq_4_bits_uop_ppred_busy}, {stq_3_bits_uop_ppred_busy}, {stq_2_bits_uop_ppred_busy}, {stq_1_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}};
wire [7:0][5:0] _GEN_50 = {{stq_7_bits_uop_stale_pdst}, {stq_6_bits_uop_stale_pdst}, {stq_5_bits_uop_stale_pdst}, {stq_4_bits_uop_stale_pdst}, {stq_3_bits_uop_stale_pdst}, {stq_2_bits_uop_stale_pdst}, {stq_1_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}};
wire [7:0] _GEN_51 = {{stq_7_bits_uop_exception}, {stq_6_bits_uop_exception}, {stq_5_bits_uop_exception}, {stq_4_bits_uop_exception}, {stq_3_bits_uop_exception}, {stq_2_bits_uop_exception}, {stq_1_bits_uop_exception}, {stq_0_bits_uop_exception}};
wire _GEN_52 = _GEN_51[stq_execute_head];
wire [7:0][63:0] _GEN_53 = {{stq_7_bits_uop_exc_cause}, {stq_6_bits_uop_exc_cause}, {stq_5_bits_uop_exc_cause}, {stq_4_bits_uop_exc_cause}, {stq_3_bits_uop_exc_cause}, {stq_2_bits_uop_exc_cause}, {stq_1_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}};
wire [7:0] _GEN_54 = {{stq_7_bits_uop_bypassable}, {stq_6_bits_uop_bypassable}, {stq_5_bits_uop_bypassable}, {stq_4_bits_uop_bypassable}, {stq_3_bits_uop_bypassable}, {stq_2_bits_uop_bypassable}, {stq_1_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}};
wire [7:0][4:0] _GEN_55 = {{stq_7_bits_uop_mem_cmd}, {stq_6_bits_uop_mem_cmd}, {stq_5_bits_uop_mem_cmd}, {stq_4_bits_uop_mem_cmd}, {stq_3_bits_uop_mem_cmd}, {stq_2_bits_uop_mem_cmd}, {stq_1_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}};
wire [7:0][1:0] _GEN_56 = {{stq_7_bits_uop_mem_size}, {stq_6_bits_uop_mem_size}, {stq_5_bits_uop_mem_size}, {stq_4_bits_uop_mem_size}, {stq_3_bits_uop_mem_size}, {stq_2_bits_uop_mem_size}, {stq_1_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}};
wire [1:0] dmem_req_0_bits_data_size = _GEN_56[stq_execute_head];
wire [7:0] _GEN_57 = {{stq_7_bits_uop_mem_signed}, {stq_6_bits_uop_mem_signed}, {stq_5_bits_uop_mem_signed}, {stq_4_bits_uop_mem_signed}, {stq_3_bits_uop_mem_signed}, {stq_2_bits_uop_mem_signed}, {stq_1_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}};
wire [7:0] _GEN_58 = {{stq_7_bits_uop_is_fence}, {stq_6_bits_uop_is_fence}, {stq_5_bits_uop_is_fence}, {stq_4_bits_uop_is_fence}, {stq_3_bits_uop_is_fence}, {stq_2_bits_uop_is_fence}, {stq_1_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}};
wire _GEN_59 = _GEN_58[stq_execute_head];
wire [7:0] _GEN_60 = {{stq_7_bits_uop_is_fencei}, {stq_6_bits_uop_is_fencei}, {stq_5_bits_uop_is_fencei}, {stq_4_bits_uop_is_fencei}, {stq_3_bits_uop_is_fencei}, {stq_2_bits_uop_is_fencei}, {stq_1_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}};
wire [7:0] _GEN_61 = {{stq_7_bits_uop_is_amo}, {stq_6_bits_uop_is_amo}, {stq_5_bits_uop_is_amo}, {stq_4_bits_uop_is_amo}, {stq_3_bits_uop_is_amo}, {stq_2_bits_uop_is_amo}, {stq_1_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}};
wire _GEN_62 = _GEN_61[stq_execute_head];
wire [7:0] _GEN_63 = {{stq_7_bits_uop_uses_ldq}, {stq_6_bits_uop_uses_ldq}, {stq_5_bits_uop_uses_ldq}, {stq_4_bits_uop_uses_ldq}, {stq_3_bits_uop_uses_ldq}, {stq_2_bits_uop_uses_ldq}, {stq_1_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}};
wire [7:0] _GEN_64 = {{stq_7_bits_uop_uses_stq}, {stq_6_bits_uop_uses_stq}, {stq_5_bits_uop_uses_stq}, {stq_4_bits_uop_uses_stq}, {stq_3_bits_uop_uses_stq}, {stq_2_bits_uop_uses_stq}, {stq_1_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}};
wire [7:0] _GEN_65 = {{stq_7_bits_uop_is_sys_pc2epc}, {stq_6_bits_uop_is_sys_pc2epc}, {stq_5_bits_uop_is_sys_pc2epc}, {stq_4_bits_uop_is_sys_pc2epc}, {stq_3_bits_uop_is_sys_pc2epc}, {stq_2_bits_uop_is_sys_pc2epc}, {stq_1_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}};
wire [7:0] _GEN_66 = {{stq_7_bits_uop_is_unique}, {stq_6_bits_uop_is_unique}, {stq_5_bits_uop_is_unique}, {stq_4_bits_uop_is_unique}, {stq_3_bits_uop_is_unique}, {stq_2_bits_uop_is_unique}, {stq_1_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}};
wire [7:0] _GEN_67 = {{stq_7_bits_uop_flush_on_commit}, {stq_6_bits_uop_flush_on_commit}, {stq_5_bits_uop_flush_on_commit}, {stq_4_bits_uop_flush_on_commit}, {stq_3_bits_uop_flush_on_commit}, {stq_2_bits_uop_flush_on_commit}, {stq_1_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}};
wire [7:0] _GEN_68 = {{stq_7_bits_uop_ldst_is_rs1}, {stq_6_bits_uop_ldst_is_rs1}, {stq_5_bits_uop_ldst_is_rs1}, {stq_4_bits_uop_ldst_is_rs1}, {stq_3_bits_uop_ldst_is_rs1}, {stq_2_bits_uop_ldst_is_rs1}, {stq_1_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}};
wire [7:0][5:0] _GEN_69 = {{stq_7_bits_uop_ldst}, {stq_6_bits_uop_ldst}, {stq_5_bits_uop_ldst}, {stq_4_bits_uop_ldst}, {stq_3_bits_uop_ldst}, {stq_2_bits_uop_ldst}, {stq_1_bits_uop_ldst}, {stq_0_bits_uop_ldst}};
wire [7:0][5:0] _GEN_70 = {{stq_7_bits_uop_lrs1}, {stq_6_bits_uop_lrs1}, {stq_5_bits_uop_lrs1}, {stq_4_bits_uop_lrs1}, {stq_3_bits_uop_lrs1}, {stq_2_bits_uop_lrs1}, {stq_1_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}};
wire [7:0][5:0] _GEN_71 = {{stq_7_bits_uop_lrs2}, {stq_6_bits_uop_lrs2}, {stq_5_bits_uop_lrs2}, {stq_4_bits_uop_lrs2}, {stq_3_bits_uop_lrs2}, {stq_2_bits_uop_lrs2}, {stq_1_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}};
wire [7:0][5:0] _GEN_72 = {{stq_7_bits_uop_lrs3}, {stq_6_bits_uop_lrs3}, {stq_5_bits_uop_lrs3}, {stq_4_bits_uop_lrs3}, {stq_3_bits_uop_lrs3}, {stq_2_bits_uop_lrs3}, {stq_1_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}};
wire [7:0] _GEN_73 = {{stq_7_bits_uop_ldst_val}, {stq_6_bits_uop_ldst_val}, {stq_5_bits_uop_ldst_val}, {stq_4_bits_uop_ldst_val}, {stq_3_bits_uop_ldst_val}, {stq_2_bits_uop_ldst_val}, {stq_1_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}};
wire [7:0][1:0] _GEN_74 = {{stq_7_bits_uop_dst_rtype}, {stq_6_bits_uop_dst_rtype}, {stq_5_bits_uop_dst_rtype}, {stq_4_bits_uop_dst_rtype}, {stq_3_bits_uop_dst_rtype}, {stq_2_bits_uop_dst_rtype}, {stq_1_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}};
wire [7:0][1:0] _GEN_75 = {{stq_7_bits_uop_lrs1_rtype}, {stq_6_bits_uop_lrs1_rtype}, {stq_5_bits_uop_lrs1_rtype}, {stq_4_bits_uop_lrs1_rtype}, {stq_3_bits_uop_lrs1_rtype}, {stq_2_bits_uop_lrs1_rtype}, {stq_1_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}};
wire [7:0][1:0] _GEN_76 = {{stq_7_bits_uop_lrs2_rtype}, {stq_6_bits_uop_lrs2_rtype}, {stq_5_bits_uop_lrs2_rtype}, {stq_4_bits_uop_lrs2_rtype}, {stq_3_bits_uop_lrs2_rtype}, {stq_2_bits_uop_lrs2_rtype}, {stq_1_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}};
wire [7:0] _GEN_77 = {{stq_7_bits_uop_frs3_en}, {stq_6_bits_uop_frs3_en}, {stq_5_bits_uop_frs3_en}, {stq_4_bits_uop_frs3_en}, {stq_3_bits_uop_frs3_en}, {stq_2_bits_uop_frs3_en}, {stq_1_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}};
wire [7:0] _GEN_78 = {{stq_7_bits_uop_fp_val}, {stq_6_bits_uop_fp_val}, {stq_5_bits_uop_fp_val}, {stq_4_bits_uop_fp_val}, {stq_3_bits_uop_fp_val}, {stq_2_bits_uop_fp_val}, {stq_1_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}};
wire [7:0] _GEN_79 = {{stq_7_bits_uop_fp_single}, {stq_6_bits_uop_fp_single}, {stq_5_bits_uop_fp_single}, {stq_4_bits_uop_fp_single}, {stq_3_bits_uop_fp_single}, {stq_2_bits_uop_fp_single}, {stq_1_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}};
wire [7:0] _GEN_80 = {{stq_7_bits_uop_xcpt_pf_if}, {stq_6_bits_uop_xcpt_pf_if}, {stq_5_bits_uop_xcpt_pf_if}, {stq_4_bits_uop_xcpt_pf_if}, {stq_3_bits_uop_xcpt_pf_if}, {stq_2_bits_uop_xcpt_pf_if}, {stq_1_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}};
wire [7:0] _GEN_81 = {{stq_7_bits_uop_xcpt_ae_if}, {stq_6_bits_uop_xcpt_ae_if}, {stq_5_bits_uop_xcpt_ae_if}, {stq_4_bits_uop_xcpt_ae_if}, {stq_3_bits_uop_xcpt_ae_if}, {stq_2_bits_uop_xcpt_ae_if}, {stq_1_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}};
wire [7:0] _GEN_82 = {{stq_7_bits_uop_xcpt_ma_if}, {stq_6_bits_uop_xcpt_ma_if}, {stq_5_bits_uop_xcpt_ma_if}, {stq_4_bits_uop_xcpt_ma_if}, {stq_3_bits_uop_xcpt_ma_if}, {stq_2_bits_uop_xcpt_ma_if}, {stq_1_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}};
wire [7:0] _GEN_83 = {{stq_7_bits_uop_bp_debug_if}, {stq_6_bits_uop_bp_debug_if}, {stq_5_bits_uop_bp_debug_if}, {stq_4_bits_uop_bp_debug_if}, {stq_3_bits_uop_bp_debug_if}, {stq_2_bits_uop_bp_debug_if}, {stq_1_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}};
wire [7:0] _GEN_84 = {{stq_7_bits_uop_bp_xcpt_if}, {stq_6_bits_uop_bp_xcpt_if}, {stq_5_bits_uop_bp_xcpt_if}, {stq_4_bits_uop_bp_xcpt_if}, {stq_3_bits_uop_bp_xcpt_if}, {stq_2_bits_uop_bp_xcpt_if}, {stq_1_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}};
wire [7:0][1:0] _GEN_85 = {{stq_7_bits_uop_debug_fsrc}, {stq_6_bits_uop_debug_fsrc}, {stq_5_bits_uop_debug_fsrc}, {stq_4_bits_uop_debug_fsrc}, {stq_3_bits_uop_debug_fsrc}, {stq_2_bits_uop_debug_fsrc}, {stq_1_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}};
wire [7:0][1:0] _GEN_86 = {{stq_7_bits_uop_debug_tsrc}, {stq_6_bits_uop_debug_tsrc}, {stq_5_bits_uop_debug_tsrc}, {stq_4_bits_uop_debug_tsrc}, {stq_3_bits_uop_debug_tsrc}, {stq_2_bits_uop_debug_tsrc}, {stq_1_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}};
wire [7:0] _GEN_87 = {{stq_7_bits_addr_valid}, {stq_6_bits_addr_valid}, {stq_5_bits_addr_valid}, {stq_4_bits_addr_valid}, {stq_3_bits_addr_valid}, {stq_2_bits_addr_valid}, {stq_1_bits_addr_valid}, {stq_0_bits_addr_valid}};
wire [7:0][39:0] _GEN_88 = {{stq_7_bits_addr_bits}, {stq_6_bits_addr_bits}, {stq_5_bits_addr_bits}, {stq_4_bits_addr_bits}, {stq_3_bits_addr_bits}, {stq_2_bits_addr_bits}, {stq_1_bits_addr_bits}, {stq_0_bits_addr_bits}};
wire [7:0] _GEN_89 = {{stq_7_bits_addr_is_virtual}, {stq_6_bits_addr_is_virtual}, {stq_5_bits_addr_is_virtual}, {stq_4_bits_addr_is_virtual}, {stq_3_bits_addr_is_virtual}, {stq_2_bits_addr_is_virtual}, {stq_1_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}};
wire [7:0] _GEN_90 = {{stq_7_bits_data_valid}, {stq_6_bits_data_valid}, {stq_5_bits_data_valid}, {stq_4_bits_data_valid}, {stq_3_bits_data_valid}, {stq_2_bits_data_valid}, {stq_1_bits_data_valid}, {stq_0_bits_data_valid}};
wire [7:0][63:0] _GEN_91 = {{stq_7_bits_data_bits}, {stq_6_bits_data_bits}, {stq_5_bits_data_bits}, {stq_4_bits_data_bits}, {stq_3_bits_data_bits}, {stq_2_bits_data_bits}, {stq_1_bits_data_bits}, {stq_0_bits_data_bits}};
wire [63:0] _GEN_92 = _GEN_91[stq_execute_head];
wire [7:0] _GEN_93 = {{stq_7_bits_committed}, {stq_6_bits_committed}, {stq_5_bits_committed}, {stq_4_bits_committed}, {stq_3_bits_committed}, {stq_2_bits_committed}, {stq_1_bits_committed}, {stq_0_bits_committed}};
reg [2:0] hella_state;
reg [39:0] hella_req_addr;
reg [63:0] hella_data_data;
reg [31:0] hella_paddr;
reg hella_xcpt_ma_ld;
reg hella_xcpt_ma_st;
reg hella_xcpt_pf_ld;
reg hella_xcpt_pf_st;
reg hella_xcpt_gf_ld;
reg hella_xcpt_gf_st;
reg hella_xcpt_ae_ld;
reg hella_xcpt_ae_st;
reg [7:0] live_store_mask;
wire [2:0] _GEN_94 = ldq_tail + 3'h1;
wire [2:0] _GEN_95 = stq_tail + 3'h1;
wire dis_ld_val = io_core_dis_uops_0_valid & io_core_dis_uops_0_bits_uses_ldq & ~io_core_dis_uops_0_bits_exception;
wire dis_st_val = io_core_dis_uops_0_valid & io_core_dis_uops_0_bits_uses_stq & ~io_core_dis_uops_0_bits_exception;
wire [7:0] _GEN_96 = {{ldq_7_valid}, {ldq_6_valid}, {ldq_5_valid}, {ldq_4_valid}, {ldq_3_valid}, {ldq_2_valid}, {ldq_1_valid}, {ldq_0_valid}};
reg p1_block_load_mask_0;
reg p1_block_load_mask_1;
reg p1_block_load_mask_2;
reg p1_block_load_mask_3;
reg p1_block_load_mask_4;
reg p1_block_load_mask_5;
reg p1_block_load_mask_6;
reg p1_block_load_mask_7;
reg p2_block_load_mask_0;
reg p2_block_load_mask_1;
reg p2_block_load_mask_2;
reg p2_block_load_mask_3;
reg p2_block_load_mask_4;
reg p2_block_load_mask_5;
reg p2_block_load_mask_6;
reg p2_block_load_mask_7;
wire [7:0][7:0] _GEN_97 = {{ldq_7_bits_uop_br_mask}, {ldq_6_bits_uop_br_mask}, {ldq_5_bits_uop_br_mask}, {ldq_4_bits_uop_br_mask}, {ldq_3_bits_uop_br_mask}, {ldq_2_bits_uop_br_mask}, {ldq_1_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}};
wire [7:0][2:0] _GEN_98 = {{ldq_7_bits_uop_stq_idx}, {ldq_6_bits_uop_stq_idx}, {ldq_5_bits_uop_stq_idx}, {ldq_4_bits_uop_stq_idx}, {ldq_3_bits_uop_stq_idx}, {ldq_2_bits_uop_stq_idx}, {ldq_1_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}};
wire [7:0][1:0] _GEN_99 = {{ldq_7_bits_uop_mem_size}, {ldq_6_bits_uop_mem_size}, {ldq_5_bits_uop_mem_size}, {ldq_4_bits_uop_mem_size}, {ldq_3_bits_uop_mem_size}, {ldq_2_bits_uop_mem_size}, {ldq_1_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}};
wire [7:0] _GEN_100 = {{ldq_7_bits_addr_valid}, {ldq_6_bits_addr_valid}, {ldq_5_bits_addr_valid}, {ldq_4_bits_addr_valid}, {ldq_3_bits_addr_valid}, {ldq_2_bits_addr_valid}, {ldq_1_bits_addr_valid}, {ldq_0_bits_addr_valid}};
wire [7:0] _GEN_101 = {{ldq_7_bits_executed}, {ldq_6_bits_executed}, {ldq_5_bits_executed}, {ldq_4_bits_executed}, {ldq_3_bits_executed}, {ldq_2_bits_executed}, {ldq_1_bits_executed}, {ldq_0_bits_executed}};
wire [7:0][7:0] _GEN_102 = {{ldq_7_bits_st_dep_mask}, {ldq_6_bits_st_dep_mask}, {ldq_5_bits_st_dep_mask}, {ldq_4_bits_st_dep_mask}, {ldq_3_bits_st_dep_mask}, {ldq_2_bits_st_dep_mask}, {ldq_1_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}};
reg [2:0] ldq_retry_idx;
reg [2:0] stq_retry_idx;
reg [2:0] ldq_wakeup_idx;
wire will_fire_load_incoming_0_will_fire = io_core_exe_0_req_valid & io_core_exe_0_req_bits_uop_ctrl_is_load;
wire _can_fire_sta_incoming_T = io_core_exe_0_req_valid & io_core_exe_0_req_bits_uop_ctrl_is_sta;
wire [7:0][6:0] _GEN_103 = {{ldq_7_bits_uop_uopc}, {ldq_6_bits_uop_uopc}, {ldq_5_bits_uop_uopc}, {ldq_4_bits_uop_uopc}, {ldq_3_bits_uop_uopc}, {ldq_2_bits_uop_uopc}, {ldq_1_bits_uop_uopc}, {ldq_0_bits_uop_uopc}};
wire [7:0][31:0] _GEN_104 = {{ldq_7_bits_uop_inst}, {ldq_6_bits_uop_inst}, {ldq_5_bits_uop_inst}, {ldq_4_bits_uop_inst}, {ldq_3_bits_uop_inst}, {ldq_2_bits_uop_inst}, {ldq_1_bits_uop_inst}, {ldq_0_bits_uop_inst}};
wire [7:0][31:0] _GEN_105 = {{ldq_7_bits_uop_debug_inst}, {ldq_6_bits_uop_debug_inst}, {ldq_5_bits_uop_debug_inst}, {ldq_4_bits_uop_debug_inst}, {ldq_3_bits_uop_debug_inst}, {ldq_2_bits_uop_debug_inst}, {ldq_1_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}};
wire [7:0] _GEN_106 = {{ldq_7_bits_uop_is_rvc}, {ldq_6_bits_uop_is_rvc}, {ldq_5_bits_uop_is_rvc}, {ldq_4_bits_uop_is_rvc}, {ldq_3_bits_uop_is_rvc}, {ldq_2_bits_uop_is_rvc}, {ldq_1_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}};
wire [7:0][39:0] _GEN_107 = {{ldq_7_bits_uop_debug_pc}, {ldq_6_bits_uop_debug_pc}, {ldq_5_bits_uop_debug_pc}, {ldq_4_bits_uop_debug_pc}, {ldq_3_bits_uop_debug_pc}, {ldq_2_bits_uop_debug_pc}, {ldq_1_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}};
wire [7:0][2:0] _GEN_108 = {{ldq_7_bits_uop_iq_type}, {ldq_6_bits_uop_iq_type}, {ldq_5_bits_uop_iq_type}, {ldq_4_bits_uop_iq_type}, {ldq_3_bits_uop_iq_type}, {ldq_2_bits_uop_iq_type}, {ldq_1_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}};
wire [7:0][9:0] _GEN_109 = {{ldq_7_bits_uop_fu_code}, {ldq_6_bits_uop_fu_code}, {ldq_5_bits_uop_fu_code}, {ldq_4_bits_uop_fu_code}, {ldq_3_bits_uop_fu_code}, {ldq_2_bits_uop_fu_code}, {ldq_1_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}};
wire [7:0][3:0] _GEN_110 = {{ldq_7_bits_uop_ctrl_br_type}, {ldq_6_bits_uop_ctrl_br_type}, {ldq_5_bits_uop_ctrl_br_type}, {ldq_4_bits_uop_ctrl_br_type}, {ldq_3_bits_uop_ctrl_br_type}, {ldq_2_bits_uop_ctrl_br_type}, {ldq_1_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}};
wire [7:0][1:0] _GEN_111 = {{ldq_7_bits_uop_ctrl_op1_sel}, {ldq_6_bits_uop_ctrl_op1_sel}, {ldq_5_bits_uop_ctrl_op1_sel}, {ldq_4_bits_uop_ctrl_op1_sel}, {ldq_3_bits_uop_ctrl_op1_sel}, {ldq_2_bits_uop_ctrl_op1_sel}, {ldq_1_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}};
wire [7:0][2:0] _GEN_112 = {{ldq_7_bits_uop_ctrl_op2_sel}, {ldq_6_bits_uop_ctrl_op2_sel}, {ldq_5_bits_uop_ctrl_op2_sel}, {ldq_4_bits_uop_ctrl_op2_sel}, {ldq_3_bits_uop_ctrl_op2_sel}, {ldq_2_bits_uop_ctrl_op2_sel}, {ldq_1_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}};
wire [7:0][2:0] _GEN_113 = {{ldq_7_bits_uop_ctrl_imm_sel}, {ldq_6_bits_uop_ctrl_imm_sel}, {ldq_5_bits_uop_ctrl_imm_sel}, {ldq_4_bits_uop_ctrl_imm_sel}, {ldq_3_bits_uop_ctrl_imm_sel}, {ldq_2_bits_uop_ctrl_imm_sel}, {ldq_1_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}};
wire [7:0][4:0] _GEN_114 = {{ldq_7_bits_uop_ctrl_op_fcn}, {ldq_6_bits_uop_ctrl_op_fcn}, {ldq_5_bits_uop_ctrl_op_fcn}, {ldq_4_bits_uop_ctrl_op_fcn}, {ldq_3_bits_uop_ctrl_op_fcn}, {ldq_2_bits_uop_ctrl_op_fcn}, {ldq_1_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}};
wire [7:0] _GEN_115 = {{ldq_7_bits_uop_ctrl_fcn_dw}, {ldq_6_bits_uop_ctrl_fcn_dw}, {ldq_5_bits_uop_ctrl_fcn_dw}, {ldq_4_bits_uop_ctrl_fcn_dw}, {ldq_3_bits_uop_ctrl_fcn_dw}, {ldq_2_bits_uop_ctrl_fcn_dw}, {ldq_1_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}};
wire [7:0][2:0] _GEN_116 = {{ldq_7_bits_uop_ctrl_csr_cmd}, {ldq_6_bits_uop_ctrl_csr_cmd}, {ldq_5_bits_uop_ctrl_csr_cmd}, {ldq_4_bits_uop_ctrl_csr_cmd}, {ldq_3_bits_uop_ctrl_csr_cmd}, {ldq_2_bits_uop_ctrl_csr_cmd}, {ldq_1_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}};
wire [7:0] _GEN_117 = {{ldq_7_bits_uop_ctrl_is_load}, {ldq_6_bits_uop_ctrl_is_load}, {ldq_5_bits_uop_ctrl_is_load}, {ldq_4_bits_uop_ctrl_is_load}, {ldq_3_bits_uop_ctrl_is_load}, {ldq_2_bits_uop_ctrl_is_load}, {ldq_1_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}};
wire [7:0] _GEN_118 = {{ldq_7_bits_uop_ctrl_is_sta}, {ldq_6_bits_uop_ctrl_is_sta}, {ldq_5_bits_uop_ctrl_is_sta}, {ldq_4_bits_uop_ctrl_is_sta}, {ldq_3_bits_uop_ctrl_is_sta}, {ldq_2_bits_uop_ctrl_is_sta}, {ldq_1_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}};
wire [7:0] _GEN_119 = {{ldq_7_bits_uop_ctrl_is_std}, {ldq_6_bits_uop_ctrl_is_std}, {ldq_5_bits_uop_ctrl_is_std}, {ldq_4_bits_uop_ctrl_is_std}, {ldq_3_bits_uop_ctrl_is_std}, {ldq_2_bits_uop_ctrl_is_std}, {ldq_1_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}};
wire [7:0][1:0] _GEN_120 = {{ldq_7_bits_uop_iw_state}, {ldq_6_bits_uop_iw_state}, {ldq_5_bits_uop_iw_state}, {ldq_4_bits_uop_iw_state}, {ldq_3_bits_uop_iw_state}, {ldq_2_bits_uop_iw_state}, {ldq_1_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}};
wire [7:0] _GEN_121 = {{ldq_7_bits_uop_iw_p1_poisoned}, {ldq_6_bits_uop_iw_p1_poisoned}, {ldq_5_bits_uop_iw_p1_poisoned}, {ldq_4_bits_uop_iw_p1_poisoned}, {ldq_3_bits_uop_iw_p1_poisoned}, {ldq_2_bits_uop_iw_p1_poisoned}, {ldq_1_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}};
wire [7:0] _GEN_122 = {{ldq_7_bits_uop_iw_p2_poisoned}, {ldq_6_bits_uop_iw_p2_poisoned}, {ldq_5_bits_uop_iw_p2_poisoned}, {ldq_4_bits_uop_iw_p2_poisoned}, {ldq_3_bits_uop_iw_p2_poisoned}, {ldq_2_bits_uop_iw_p2_poisoned}, {ldq_1_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}};
wire [7:0] _GEN_123 = {{ldq_7_bits_uop_is_br}, {ldq_6_bits_uop_is_br}, {ldq_5_bits_uop_is_br}, {ldq_4_bits_uop_is_br}, {ldq_3_bits_uop_is_br}, {ldq_2_bits_uop_is_br}, {ldq_1_bits_uop_is_br}, {ldq_0_bits_uop_is_br}};
wire [7:0] _GEN_124 = {{ldq_7_bits_uop_is_jalr}, {ldq_6_bits_uop_is_jalr}, {ldq_5_bits_uop_is_jalr}, {ldq_4_bits_uop_is_jalr}, {ldq_3_bits_uop_is_jalr}, {ldq_2_bits_uop_is_jalr}, {ldq_1_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}};
wire [7:0] _GEN_125 = {{ldq_7_bits_uop_is_jal}, {ldq_6_bits_uop_is_jal}, {ldq_5_bits_uop_is_jal}, {ldq_4_bits_uop_is_jal}, {ldq_3_bits_uop_is_jal}, {ldq_2_bits_uop_is_jal}, {ldq_1_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}};
wire [7:0] _GEN_126 = {{ldq_7_bits_uop_is_sfb}, {ldq_6_bits_uop_is_sfb}, {ldq_5_bits_uop_is_sfb}, {ldq_4_bits_uop_is_sfb}, {ldq_3_bits_uop_is_sfb}, {ldq_2_bits_uop_is_sfb}, {ldq_1_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}};
wire [7:0] _GEN_127 = _GEN_97[ldq_retry_idx];
wire [7:0][2:0] _GEN_128 = {{ldq_7_bits_uop_br_tag}, {ldq_6_bits_uop_br_tag}, {ldq_5_bits_uop_br_tag}, {ldq_4_bits_uop_br_tag}, {ldq_3_bits_uop_br_tag}, {ldq_2_bits_uop_br_tag}, {ldq_1_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}};
wire [7:0][3:0] _GEN_129 = {{ldq_7_bits_uop_ftq_idx}, {ldq_6_bits_uop_ftq_idx}, {ldq_5_bits_uop_ftq_idx}, {ldq_4_bits_uop_ftq_idx}, {ldq_3_bits_uop_ftq_idx}, {ldq_2_bits_uop_ftq_idx}, {ldq_1_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}};
wire [7:0] _GEN_130 = {{ldq_7_bits_uop_edge_inst}, {ldq_6_bits_uop_edge_inst}, {ldq_5_bits_uop_edge_inst}, {ldq_4_bits_uop_edge_inst}, {ldq_3_bits_uop_edge_inst}, {ldq_2_bits_uop_edge_inst}, {ldq_1_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}};
wire [7:0][5:0] _GEN_131 = {{ldq_7_bits_uop_pc_lob}, {ldq_6_bits_uop_pc_lob}, {ldq_5_bits_uop_pc_lob}, {ldq_4_bits_uop_pc_lob}, {ldq_3_bits_uop_pc_lob}, {ldq_2_bits_uop_pc_lob}, {ldq_1_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}};
wire [7:0] _GEN_132 = {{ldq_7_bits_uop_taken}, {ldq_6_bits_uop_taken}, {ldq_5_bits_uop_taken}, {ldq_4_bits_uop_taken}, {ldq_3_bits_uop_taken}, {ldq_2_bits_uop_taken}, {ldq_1_bits_uop_taken}, {ldq_0_bits_uop_taken}};
wire [7:0][19:0] _GEN_133 = {{ldq_7_bits_uop_imm_packed}, {ldq_6_bits_uop_imm_packed}, {ldq_5_bits_uop_imm_packed}, {ldq_4_bits_uop_imm_packed}, {ldq_3_bits_uop_imm_packed}, {ldq_2_bits_uop_imm_packed}, {ldq_1_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}};
wire [7:0][11:0] _GEN_134 = {{ldq_7_bits_uop_csr_addr}, {ldq_6_bits_uop_csr_addr}, {ldq_5_bits_uop_csr_addr}, {ldq_4_bits_uop_csr_addr}, {ldq_3_bits_uop_csr_addr}, {ldq_2_bits_uop_csr_addr}, {ldq_1_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}};
wire [7:0][4:0] _GEN_135 = {{ldq_7_bits_uop_rob_idx}, {ldq_6_bits_uop_rob_idx}, {ldq_5_bits_uop_rob_idx}, {ldq_4_bits_uop_rob_idx}, {ldq_3_bits_uop_rob_idx}, {ldq_2_bits_uop_rob_idx}, {ldq_1_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}};
wire [7:0][2:0] _GEN_136 = {{ldq_7_bits_uop_ldq_idx}, {ldq_6_bits_uop_ldq_idx}, {ldq_5_bits_uop_ldq_idx}, {ldq_4_bits_uop_ldq_idx}, {ldq_3_bits_uop_ldq_idx}, {ldq_2_bits_uop_ldq_idx}, {ldq_1_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}};
wire [2:0] mem_ldq_retry_e_out_bits_uop_stq_idx = _GEN_98[ldq_retry_idx];
wire [7:0][1:0] _GEN_137 = {{ldq_7_bits_uop_rxq_idx}, {ldq_6_bits_uop_rxq_idx}, {ldq_5_bits_uop_rxq_idx}, {ldq_4_bits_uop_rxq_idx}, {ldq_3_bits_uop_rxq_idx}, {ldq_2_bits_uop_rxq_idx}, {ldq_1_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}};
wire [7:0][5:0] _GEN_138 = {{ldq_7_bits_uop_pdst}, {ldq_6_bits_uop_pdst}, {ldq_5_bits_uop_pdst}, {ldq_4_bits_uop_pdst}, {ldq_3_bits_uop_pdst}, {ldq_2_bits_uop_pdst}, {ldq_1_bits_uop_pdst}, {ldq_0_bits_uop_pdst}};
wire [5:0] _GEN_139 = _GEN_138[ldq_retry_idx];
wire [7:0][5:0] _GEN_140 = {{ldq_7_bits_uop_prs1}, {ldq_6_bits_uop_prs1}, {ldq_5_bits_uop_prs1}, {ldq_4_bits_uop_prs1}, {ldq_3_bits_uop_prs1}, {ldq_2_bits_uop_prs1}, {ldq_1_bits_uop_prs1}, {ldq_0_bits_uop_prs1}};
wire [7:0][5:0] _GEN_141 = {{ldq_7_bits_uop_prs2}, {ldq_6_bits_uop_prs2}, {ldq_5_bits_uop_prs2}, {ldq_4_bits_uop_prs2}, {ldq_3_bits_uop_prs2}, {ldq_2_bits_uop_prs2}, {ldq_1_bits_uop_prs2}, {ldq_0_bits_uop_prs2}};
wire [7:0][5:0] _GEN_142 = {{ldq_7_bits_uop_prs3}, {ldq_6_bits_uop_prs3}, {ldq_5_bits_uop_prs3}, {ldq_4_bits_uop_prs3}, {ldq_3_bits_uop_prs3}, {ldq_2_bits_uop_prs3}, {ldq_1_bits_uop_prs3}, {ldq_0_bits_uop_prs3}};
wire [7:0] _GEN_143 = {{ldq_7_bits_uop_prs1_busy}, {ldq_6_bits_uop_prs1_busy}, {ldq_5_bits_uop_prs1_busy}, {ldq_4_bits_uop_prs1_busy}, {ldq_3_bits_uop_prs1_busy}, {ldq_2_bits_uop_prs1_busy}, {ldq_1_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}};
wire [7:0] _GEN_144 = {{ldq_7_bits_uop_prs2_busy}, {ldq_6_bits_uop_prs2_busy}, {ldq_5_bits_uop_prs2_busy}, {ldq_4_bits_uop_prs2_busy}, {ldq_3_bits_uop_prs2_busy}, {ldq_2_bits_uop_prs2_busy}, {ldq_1_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}};
wire [7:0] _GEN_145 = {{ldq_7_bits_uop_prs3_busy}, {ldq_6_bits_uop_prs3_busy}, {ldq_5_bits_uop_prs3_busy}, {ldq_4_bits_uop_prs3_busy}, {ldq_3_bits_uop_prs3_busy}, {ldq_2_bits_uop_prs3_busy}, {ldq_1_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}};
wire [7:0][5:0] _GEN_146 = {{ldq_7_bits_uop_stale_pdst}, {ldq_6_bits_uop_stale_pdst}, {ldq_5_bits_uop_stale_pdst}, {ldq_4_bits_uop_stale_pdst}, {ldq_3_bits_uop_stale_pdst}, {ldq_2_bits_uop_stale_pdst}, {ldq_1_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}};
wire [7:0] _GEN_147 = {{ldq_7_bits_uop_exception}, {ldq_6_bits_uop_exception}, {ldq_5_bits_uop_exception}, {ldq_4_bits_uop_exception}, {ldq_3_bits_uop_exception}, {ldq_2_bits_uop_exception}, {ldq_1_bits_uop_exception}, {ldq_0_bits_uop_exception}};
wire [7:0][63:0] _GEN_148 = {{ldq_7_bits_uop_exc_cause}, {ldq_6_bits_uop_exc_cause}, {ldq_5_bits_uop_exc_cause}, {ldq_4_bits_uop_exc_cause}, {ldq_3_bits_uop_exc_cause}, {ldq_2_bits_uop_exc_cause}, {ldq_1_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}};
wire [7:0] _GEN_149 = {{ldq_7_bits_uop_bypassable}, {ldq_6_bits_uop_bypassable}, {ldq_5_bits_uop_bypassable}, {ldq_4_bits_uop_bypassable}, {ldq_3_bits_uop_bypassable}, {ldq_2_bits_uop_bypassable}, {ldq_1_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}};
wire [7:0][4:0] _GEN_150 = {{ldq_7_bits_uop_mem_cmd}, {ldq_6_bits_uop_mem_cmd}, {ldq_5_bits_uop_mem_cmd}, {ldq_4_bits_uop_mem_cmd}, {ldq_3_bits_uop_mem_cmd}, {ldq_2_bits_uop_mem_cmd}, {ldq_1_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}};
wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = _GEN_99[ldq_retry_idx];
wire [7:0] _GEN_151 = {{ldq_7_bits_uop_mem_signed}, {ldq_6_bits_uop_mem_signed}, {ldq_5_bits_uop_mem_signed}, {ldq_4_bits_uop_mem_signed}, {ldq_3_bits_uop_mem_signed}, {ldq_2_bits_uop_mem_signed}, {ldq_1_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}};
wire [7:0] _GEN_152 = {{ldq_7_bits_uop_is_fence}, {ldq_6_bits_uop_is_fence}, {ldq_5_bits_uop_is_fence}, {ldq_4_bits_uop_is_fence}, {ldq_3_bits_uop_is_fence}, {ldq_2_bits_uop_is_fence}, {ldq_1_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}};
wire [7:0] _GEN_153 = {{ldq_7_bits_uop_is_fencei}, {ldq_6_bits_uop_is_fencei}, {ldq_5_bits_uop_is_fencei}, {ldq_4_bits_uop_is_fencei}, {ldq_3_bits_uop_is_fencei}, {ldq_2_bits_uop_is_fencei}, {ldq_1_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}};
wire [7:0] _GEN_154 = {{ldq_7_bits_uop_is_amo}, {ldq_6_bits_uop_is_amo}, {ldq_5_bits_uop_is_amo}, {ldq_4_bits_uop_is_amo}, {ldq_3_bits_uop_is_amo}, {ldq_2_bits_uop_is_amo}, {ldq_1_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}};
wire [7:0] _GEN_155 = {{ldq_7_bits_uop_uses_ldq}, {ldq_6_bits_uop_uses_ldq}, {ldq_5_bits_uop_uses_ldq}, {ldq_4_bits_uop_uses_ldq}, {ldq_3_bits_uop_uses_ldq}, {ldq_2_bits_uop_uses_ldq}, {ldq_1_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}};
wire [7:0] _GEN_156 = {{ldq_7_bits_uop_uses_stq}, {ldq_6_bits_uop_uses_stq}, {ldq_5_bits_uop_uses_stq}, {ldq_4_bits_uop_uses_stq}, {ldq_3_bits_uop_uses_stq}, {ldq_2_bits_uop_uses_stq}, {ldq_1_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}};
wire [7:0] _GEN_157 = {{ldq_7_bits_uop_is_sys_pc2epc}, {ldq_6_bits_uop_is_sys_pc2epc}, {ldq_5_bits_uop_is_sys_pc2epc}, {ldq_4_bits_uop_is_sys_pc2epc}, {ldq_3_bits_uop_is_sys_pc2epc}, {ldq_2_bits_uop_is_sys_pc2epc}, {ldq_1_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}};
wire [7:0] _GEN_158 = {{ldq_7_bits_uop_is_unique}, {ldq_6_bits_uop_is_unique}, {ldq_5_bits_uop_is_unique}, {ldq_4_bits_uop_is_unique}, {ldq_3_bits_uop_is_unique}, {ldq_2_bits_uop_is_unique}, {ldq_1_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}};
wire [7:0] _GEN_159 = {{ldq_7_bits_uop_flush_on_commit}, {ldq_6_bits_uop_flush_on_commit}, {ldq_5_bits_uop_flush_on_commit}, {ldq_4_bits_uop_flush_on_commit}, {ldq_3_bits_uop_flush_on_commit}, {ldq_2_bits_uop_flush_on_commit}, {ldq_1_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}};
wire [7:0] _GEN_160 = {{ldq_7_bits_uop_ldst_is_rs1}, {ldq_6_bits_uop_ldst_is_rs1}, {ldq_5_bits_uop_ldst_is_rs1}, {ldq_4_bits_uop_ldst_is_rs1}, {ldq_3_bits_uop_ldst_is_rs1}, {ldq_2_bits_uop_ldst_is_rs1}, {ldq_1_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}};
wire [7:0][5:0] _GEN_161 = {{ldq_7_bits_uop_ldst}, {ldq_6_bits_uop_ldst}, {ldq_5_bits_uop_ldst}, {ldq_4_bits_uop_ldst}, {ldq_3_bits_uop_ldst}, {ldq_2_bits_uop_ldst}, {ldq_1_bits_uop_ldst}, {ldq_0_bits_uop_ldst}};
wire [7:0][5:0] _GEN_162 = {{ldq_7_bits_uop_lrs1}, {ldq_6_bits_uop_lrs1}, {ldq_5_bits_uop_lrs1}, {ldq_4_bits_uop_lrs1}, {ldq_3_bits_uop_lrs1}, {ldq_2_bits_uop_lrs1}, {ldq_1_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}};
wire [7:0][5:0] _GEN_163 = {{ldq_7_bits_uop_lrs2}, {ldq_6_bits_uop_lrs2}, {ldq_5_bits_uop_lrs2}, {ldq_4_bits_uop_lrs2}, {ldq_3_bits_uop_lrs2}, {ldq_2_bits_uop_lrs2}, {ldq_1_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}};
wire [7:0][5:0] _GEN_164 = {{ldq_7_bits_uop_lrs3}, {ldq_6_bits_uop_lrs3}, {ldq_5_bits_uop_lrs3}, {ldq_4_bits_uop_lrs3}, {ldq_3_bits_uop_lrs3}, {ldq_2_bits_uop_lrs3}, {ldq_1_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}};
wire [7:0] _GEN_165 = {{ldq_7_bits_uop_ldst_val}, {ldq_6_bits_uop_ldst_val}, {ldq_5_bits_uop_ldst_val}, {ldq_4_bits_uop_ldst_val}, {ldq_3_bits_uop_ldst_val}, {ldq_2_bits_uop_ldst_val}, {ldq_1_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}};
wire [7:0][1:0] _GEN_166 = {{ldq_7_bits_uop_dst_rtype}, {ldq_6_bits_uop_dst_rtype}, {ldq_5_bits_uop_dst_rtype}, {ldq_4_bits_uop_dst_rtype}, {ldq_3_bits_uop_dst_rtype}, {ldq_2_bits_uop_dst_rtype}, {ldq_1_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}};
wire [7:0][1:0] _GEN_167 = {{ldq_7_bits_uop_lrs1_rtype}, {ldq_6_bits_uop_lrs1_rtype}, {ldq_5_bits_uop_lrs1_rtype}, {ldq_4_bits_uop_lrs1_rtype}, {ldq_3_bits_uop_lrs1_rtype}, {ldq_2_bits_uop_lrs1_rtype}, {ldq_1_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}};
wire [7:0][1:0] _GEN_168 = {{ldq_7_bits_uop_lrs2_rtype}, {ldq_6_bits_uop_lrs2_rtype}, {ldq_5_bits_uop_lrs2_rtype}, {ldq_4_bits_uop_lrs2_rtype}, {ldq_3_bits_uop_lrs2_rtype}, {ldq_2_bits_uop_lrs2_rtype}, {ldq_1_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}};
wire [7:0] _GEN_169 = {{ldq_7_bits_uop_frs3_en}, {ldq_6_bits_uop_frs3_en}, {ldq_5_bits_uop_frs3_en}, {ldq_4_bits_uop_frs3_en}, {ldq_3_bits_uop_frs3_en}, {ldq_2_bits_uop_frs3_en}, {ldq_1_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}};
wire [7:0] _GEN_170 = {{ldq_7_bits_uop_fp_val}, {ldq_6_bits_uop_fp_val}, {ldq_5_bits_uop_fp_val}, {ldq_4_bits_uop_fp_val}, {ldq_3_bits_uop_fp_val}, {ldq_2_bits_uop_fp_val}, {ldq_1_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}};
wire [7:0] _GEN_171 = {{ldq_7_bits_uop_fp_single}, {ldq_6_bits_uop_fp_single}, {ldq_5_bits_uop_fp_single}, {ldq_4_bits_uop_fp_single}, {ldq_3_bits_uop_fp_single}, {ldq_2_bits_uop_fp_single}, {ldq_1_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}};
wire [7:0] _GEN_172 = {{ldq_7_bits_uop_xcpt_pf_if}, {ldq_6_bits_uop_xcpt_pf_if}, {ldq_5_bits_uop_xcpt_pf_if}, {ldq_4_bits_uop_xcpt_pf_if}, {ldq_3_bits_uop_xcpt_pf_if}, {ldq_2_bits_uop_xcpt_pf_if}, {ldq_1_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}};
wire [7:0] _GEN_173 = {{ldq_7_bits_uop_xcpt_ae_if}, {ldq_6_bits_uop_xcpt_ae_if}, {ldq_5_bits_uop_xcpt_ae_if}, {ldq_4_bits_uop_xcpt_ae_if}, {ldq_3_bits_uop_xcpt_ae_if}, {ldq_2_bits_uop_xcpt_ae_if}, {ldq_1_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}};
wire [7:0] _GEN_174 = {{ldq_7_bits_uop_xcpt_ma_if}, {ldq_6_bits_uop_xcpt_ma_if}, {ldq_5_bits_uop_xcpt_ma_if}, {ldq_4_bits_uop_xcpt_ma_if}, {ldq_3_bits_uop_xcpt_ma_if}, {ldq_2_bits_uop_xcpt_ma_if}, {ldq_1_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}};
wire [7:0] _GEN_175 = {{ldq_7_bits_uop_bp_debug_if}, {ldq_6_bits_uop_bp_debug_if}, {ldq_5_bits_uop_bp_debug_if}, {ldq_4_bits_uop_bp_debug_if}, {ldq_3_bits_uop_bp_debug_if}, {ldq_2_bits_uop_bp_debug_if}, {ldq_1_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}};
wire [7:0] _GEN_176 = {{ldq_7_bits_uop_bp_xcpt_if}, {ldq_6_bits_uop_bp_xcpt_if}, {ldq_5_bits_uop_bp_xcpt_if}, {ldq_4_bits_uop_bp_xcpt_if}, {ldq_3_bits_uop_bp_xcpt_if}, {ldq_2_bits_uop_bp_xcpt_if}, {ldq_1_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}};
wire [7:0][1:0] _GEN_177 = {{ldq_7_bits_uop_debug_fsrc}, {ldq_6_bits_uop_debug_fsrc}, {ldq_5_bits_uop_debug_fsrc}, {ldq_4_bits_uop_debug_fsrc}, {ldq_3_bits_uop_debug_fsrc}, {ldq_2_bits_uop_debug_fsrc}, {ldq_1_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}};
wire [7:0][1:0] _GEN_178 = {{ldq_7_bits_uop_debug_tsrc}, {ldq_6_bits_uop_debug_tsrc}, {ldq_5_bits_uop_debug_tsrc}, {ldq_4_bits_uop_debug_tsrc}, {ldq_3_bits_uop_debug_tsrc}, {ldq_2_bits_uop_debug_tsrc}, {ldq_1_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}};
wire [7:0][39:0] _GEN_179 = {{ldq_7_bits_addr_bits}, {ldq_6_bits_addr_bits}, {ldq_5_bits_addr_bits}, {ldq_4_bits_addr_bits}, {ldq_3_bits_addr_bits}, {ldq_2_bits_addr_bits}, {ldq_1_bits_addr_bits}, {ldq_0_bits_addr_bits}};
wire [39:0] _GEN_180 = _GEN_179[ldq_retry_idx];
wire [7:0] _GEN_181 = {{ldq_7_bits_addr_is_virtual}, {ldq_6_bits_addr_is_virtual}, {ldq_5_bits_addr_is_virtual}, {ldq_4_bits_addr_is_virtual}, {ldq_3_bits_addr_is_virtual}, {ldq_2_bits_addr_is_virtual}, {ldq_1_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}};
wire [7:0] _GEN_182 = {{ldq_7_bits_order_fail}, {ldq_6_bits_order_fail}, {ldq_5_bits_order_fail}, {ldq_4_bits_order_fail}, {ldq_3_bits_order_fail}, {ldq_2_bits_order_fail}, {ldq_1_bits_order_fail}, {ldq_0_bits_order_fail}};
wire [7:0] _GEN_183 = {{p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}};
wire [7:0] _GEN_184 = {{p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}};
reg can_fire_load_retry_REG;
wire _GEN_185 = _GEN_3[stq_retry_idx];
wire [7:0] _GEN_186 = _GEN_29[stq_retry_idx];
wire [4:0] mem_stq_retry_e_out_bits_uop_rob_idx = _GEN_37[stq_retry_idx];
wire [2:0] mem_stq_retry_e_out_bits_uop_stq_idx = _GEN_39[stq_retry_idx];
wire [5:0] _GEN_187 = _GEN_41[stq_retry_idx];
wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = _GEN_56[stq_retry_idx];
wire mem_stq_retry_e_out_bits_uop_is_amo = _GEN_61[stq_retry_idx];
wire [39:0] _GEN_188 = _GEN_88[stq_retry_idx];
reg can_fire_sta_retry_REG;
wire can_fire_store_commit_0 = _GEN_4 & ~_GEN_59 & ~mem_xcpt_valids_0 & ~_GEN_52 & (_GEN_93[stq_execute_head] | _GEN_62 & _GEN_87[stq_execute_head] & ~_GEN_89[stq_execute_head] & _GEN_90[stq_execute_head]);
wire [7:0] _GEN_189 = _GEN_97[ldq_wakeup_idx];
wire [2:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = _GEN_98[ldq_wakeup_idx];
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = _GEN_99[ldq_wakeup_idx];
wire _GEN_190 = _GEN_181[ldq_wakeup_idx];
wire [7:0] _GEN_191 = {{ldq_7_bits_addr_is_uncacheable}, {ldq_6_bits_addr_is_uncacheable}, {ldq_5_bits_addr_is_uncacheable}, {ldq_4_bits_addr_is_uncacheable}, {ldq_3_bits_addr_is_uncacheable}, {ldq_2_bits_addr_is_uncacheable}, {ldq_1_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}};
wire _GEN_192 = _GEN_101[ldq_wakeup_idx];
wire [7:0] _GEN_193 = {{ldq_7_bits_succeeded}, {ldq_6_bits_succeeded}, {ldq_5_bits_succeeded}, {ldq_4_bits_succeeded}, {ldq_3_bits_succeeded}, {ldq_2_bits_succeeded}, {ldq_1_bits_succeeded}, {ldq_0_bits_succeeded}};
wire [7:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = _GEN_102[ldq_wakeup_idx];
wire will_fire_stad_incoming_0_will_fire = _can_fire_sta_incoming_T & io_core_exe_0_req_bits_uop_ctrl_is_std & ~will_fire_load_incoming_0_will_fire & ~will_fire_load_incoming_0_will_fire;
wire _will_fire_sta_incoming_0_will_fire_T_2 = ~will_fire_load_incoming_0_will_fire & ~will_fire_stad_incoming_0_will_fire;
wire _will_fire_sta_incoming_0_will_fire_T_6 = ~will_fire_load_incoming_0_will_fire & ~will_fire_stad_incoming_0_will_fire;
wire will_fire_sta_incoming_0_will_fire = _can_fire_sta_incoming_T & ~io_core_exe_0_req_bits_uop_ctrl_is_std & _will_fire_sta_incoming_0_will_fire_T_2 & _will_fire_sta_incoming_0_will_fire_T_6 & ~will_fire_stad_incoming_0_will_fire;
wire _will_fire_sfence_0_will_fire_T_2 = _will_fire_sta_incoming_0_will_fire_T_2 & ~will_fire_sta_incoming_0_will_fire;
wire _will_fire_release_0_will_fire_T_6 = _will_fire_sta_incoming_0_will_fire_T_6 & ~will_fire_sta_incoming_0_will_fire;
wire _will_fire_std_incoming_0_will_fire_T_14 = ~will_fire_stad_incoming_0_will_fire & ~will_fire_sta_incoming_0_will_fire;
wire will_fire_std_incoming_0_will_fire = io_core_exe_0_req_valid & io_core_exe_0_req_bits_uop_ctrl_is_std & ~io_core_exe_0_req_bits_uop_ctrl_is_sta & _will_fire_std_incoming_0_will_fire_T_14;
wire _will_fire_sfence_0_will_fire_T_14 = _will_fire_std_incoming_0_will_fire_T_14 & ~will_fire_std_incoming_0_will_fire;
wire will_fire_sfence_0_will_fire = io_core_exe_0_req_valid & io_core_exe_0_req_bits_sfence_valid & _will_fire_sfence_0_will_fire_T_2 & _will_fire_sfence_0_will_fire_T_14;
wire _will_fire_hella_incoming_0_will_fire_T_2 = _will_fire_sfence_0_will_fire_T_2 & ~will_fire_sfence_0_will_fire;
wire will_fire_release_0_will_fire = io_dmem_release_valid & _will_fire_release_0_will_fire_T_6;
wire _will_fire_load_retry_0_will_fire_T_6 = _will_fire_release_0_will_fire_T_6 & ~will_fire_release_0_will_fire;
wire will_fire_hella_incoming_0_will_fire = _GEN_0 & _GEN_2 & _will_fire_hella_incoming_0_will_fire_T_2 & ~will_fire_load_incoming_0_will_fire;
wire _will_fire_load_retry_0_will_fire_T_2 = _will_fire_hella_incoming_0_will_fire_T_2 & ~will_fire_hella_incoming_0_will_fire;
wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~will_fire_load_incoming_0_will_fire & ~will_fire_hella_incoming_0_will_fire;
wire will_fire_hella_wakeup_0_will_fire = _GEN & _GEN_1 & _will_fire_hella_wakeup_0_will_fire_T_10;
wire _will_fire_load_retry_0_will_fire_T_10 = _will_fire_hella_wakeup_0_will_fire_T_10 & ~will_fire_hella_wakeup_0_will_fire;
wire will_fire_load_retry_0_will_fire = _GEN_96[ldq_retry_idx] & _GEN_100[ldq_retry_idx] & _GEN_181[ldq_retry_idx] & ~_GEN_183[ldq_retry_idx] & ~_GEN_184[ldq_retry_idx] & can_fire_load_retry_REG & ~store_needs_order & ~_GEN_182[ldq_retry_idx] & _will_fire_load_retry_0_will_fire_T_2 & _will_fire_load_retry_0_will_fire_T_6 & _will_fire_load_retry_0_will_fire_T_10;
wire _will_fire_sta_retry_0_will_fire_T_2 = _will_fire_load_retry_0_will_fire_T_2 & ~will_fire_load_retry_0_will_fire;
wire _will_fire_sta_retry_0_will_fire_T_6 = _will_fire_load_retry_0_will_fire_T_6 & ~will_fire_load_retry_0_will_fire;
wire _will_fire_load_wakeup_0_will_fire_T_10 = _will_fire_load_retry_0_will_fire_T_10 & ~will_fire_load_retry_0_will_fire;
wire will_fire_sta_retry_0_will_fire = _GEN_185 & _GEN_87[stq_retry_idx] & _GEN_89[stq_retry_idx] & can_fire_sta_retry_REG & _will_fire_sta_retry_0_will_fire_T_2 & _will_fire_sta_retry_0_will_fire_T_6 & _will_fire_sfence_0_will_fire_T_14 & ~will_fire_sfence_0_will_fire;
assign _will_fire_store_commit_0_T_2 = _will_fire_sta_retry_0_will_fire_T_2 & ~will_fire_sta_retry_0_will_fire;
wire will_fire_load_wakeup_0_will_fire = _GEN_96[ldq_wakeup_idx] & _GEN_100[ldq_wakeup_idx] & ~_GEN_193[ldq_wakeup_idx] & ~_GEN_190 & ~_GEN_192 & ~_GEN_182[ldq_wakeup_idx] & ~_GEN_183[ldq_wakeup_idx] & ~_GEN_184[ldq_wakeup_idx] & ~store_needs_order & ~block_load_wakeup & (~_GEN_191[ldq_wakeup_idx] | io_core_commit_load_at_rob_head & ldq_head == ldq_wakeup_idx & mem_ldq_wakeup_e_out_bits_st_dep_mask == 8'h0) & _will_fire_sta_retry_0_will_fire_T_6 & ~will_fire_sta_retry_0_will_fire & _will_fire_load_wakeup_0_will_fire_T_10;
wire will_fire_store_commit_0_will_fire = can_fire_store_commit_0 & _will_fire_load_wakeup_0_will_fire_T_10 & ~will_fire_load_wakeup_0_will_fire;
wire _exe_cmd_T = will_fire_load_incoming_0_will_fire | will_fire_stad_incoming_0_will_fire;
wire _GEN_194 = _exe_cmd_T | will_fire_sta_incoming_0_will_fire;
wire _GEN_195 = ldq_wakeup_idx == 3'h0;
wire _GEN_196 = ldq_wakeup_idx == 3'h1;
wire _GEN_197 = ldq_wakeup_idx == 3'h2;
wire _GEN_198 = ldq_wakeup_idx == 3'h3;
wire _GEN_199 = ldq_wakeup_idx == 3'h4;
wire _GEN_200 = ldq_wakeup_idx == 3'h5;
wire _GEN_201 = ldq_wakeup_idx == 3'h6;
wire _GEN_202 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h0;
wire _GEN_203 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h1;
wire _GEN_204 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h2;
wire _GEN_205 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h3;
wire _GEN_206 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h4;
wire _GEN_207 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h5;
wire _GEN_208 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h6;
wire _GEN_209 = ldq_retry_idx == 3'h0;
wire block_load_mask_0 = will_fire_load_wakeup_0_will_fire ? _GEN_195 : will_fire_load_incoming_0_will_fire ? _GEN_202 : will_fire_load_retry_0_will_fire & _GEN_209;
wire _GEN_210 = ldq_retry_idx == 3'h1;
wire block_load_mask_1 = will_fire_load_wakeup_0_will_fire ? _GEN_196 : will_fire_load_incoming_0_will_fire ? _GEN_203 : will_fire_load_retry_0_will_fire & _GEN_210;
wire _GEN_211 = ldq_retry_idx == 3'h2;
wire block_load_mask_2 = will_fire_load_wakeup_0_will_fire ? _GEN_197 : will_fire_load_incoming_0_will_fire ? _GEN_204 : will_fire_load_retry_0_will_fire & _GEN_211;
wire _GEN_212 = ldq_retry_idx == 3'h3;
wire block_load_mask_3 = will_fire_load_wakeup_0_will_fire ? _GEN_198 : will_fire_load_incoming_0_will_fire ? _GEN_205 : will_fire_load_retry_0_will_fire & _GEN_212;
wire _GEN_213 = ldq_retry_idx == 3'h4;
wire block_load_mask_4 = will_fire_load_wakeup_0_will_fire ? _GEN_199 : will_fire_load_incoming_0_will_fire ? _GEN_206 : will_fire_load_retry_0_will_fire & _GEN_213;
wire _GEN_214 = ldq_retry_idx == 3'h5;
wire block_load_mask_5 = will_fire_load_wakeup_0_will_fire ? _GEN_200 : will_fire_load_incoming_0_will_fire ? _GEN_207 : will_fire_load_retry_0_will_fire & _GEN_214;
wire _GEN_215 = ldq_retry_idx == 3'h6;
wire block_load_mask_6 = will_fire_load_wakeup_0_will_fire ? _GEN_201 : will_fire_load_incoming_0_will_fire ? _GEN_208 : will_fire_load_retry_0_will_fire & _GEN_215;
wire block_load_mask_7 = will_fire_load_wakeup_0_will_fire ? (&ldq_wakeup_idx) : will_fire_load_incoming_0_will_fire ? (&io_core_exe_0_req_bits_uop_ldq_idx) : will_fire_load_retry_0_will_fire & (&ldq_retry_idx);
wire _exe_tlb_uop_T_2 = _exe_cmd_T | will_fire_sta_incoming_0_will_fire | will_fire_sfence_0_will_fire;
wire [5:0] _exe_tlb_uop_T_4_pdst = will_fire_sta_retry_0_will_fire ? _GEN_187 : 6'h0;
wire exe_tlb_uop_0_ctrl_is_load = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_is_load : will_fire_load_retry_0_will_fire ? _GEN_117[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_19[stq_retry_idx];
wire exe_tlb_uop_0_ctrl_is_sta = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_is_sta : will_fire_load_retry_0_will_fire ? _GEN_118[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_20[stq_retry_idx];
wire [7:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_br_mask : will_fire_load_retry_0_will_fire ? _GEN_127 : will_fire_sta_retry_0_will_fire ? _GEN_186 : 8'h0;
wire [4:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_rob_idx : will_fire_load_retry_0_will_fire ? _GEN_135[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? mem_stq_retry_e_out_bits_uop_rob_idx : 5'h0;
wire [2:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ldq_idx : will_fire_load_retry_0_will_fire ? _GEN_136[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_38[stq_retry_idx] : 3'h0;
wire [2:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_stq_idx : will_fire_load_retry_0_will_fire ? mem_ldq_retry_e_out_bits_uop_stq_idx : will_fire_sta_retry_0_will_fire ? mem_stq_retry_e_out_bits_uop_stq_idx : 3'h0;
wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_mem_cmd : will_fire_load_retry_0_will_fire ? _GEN_150[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_55[stq_retry_idx] : 5'h0;
wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_mem_size : will_fire_load_retry_0_will_fire ? mem_ldq_retry_e_out_bits_uop_mem_size : will_fire_sta_retry_0_will_fire ? mem_stq_retry_e_out_bits_uop_mem_size : 2'h0;
wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_fence : will_fire_load_retry_0_will_fire ? _GEN_152[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_58[stq_retry_idx];
wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_uses_ldq : will_fire_load_retry_0_will_fire ? _GEN_155[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_63[stq_retry_idx];
wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_uses_stq : will_fire_load_retry_0_will_fire ? _GEN_156[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_64[stq_retry_idx];
wire _exe_tlb_vaddr_T_1 = _exe_cmd_T | will_fire_sta_incoming_0_will_fire;
wire [39:0] _exe_tlb_vaddr_T_2 = will_fire_hella_incoming_0_will_fire ? hella_req_addr : 40'h0;
wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_sta_retry_0_will_fire ? _GEN_188 : _exe_tlb_vaddr_T_2;
wire [39:0] _GEN_216 = {1'h0, io_core_exe_0_req_bits_sfence_bits_addr};
wire [39:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_1 ? io_core_exe_0_req_bits_addr : will_fire_sfence_0_will_fire ? _GEN_216 : will_fire_load_retry_0_will_fire ? _GEN_180 : _exe_tlb_vaddr_T_3;
wire _stq_idx_T = will_fire_sta_incoming_0_will_fire | will_fire_stad_incoming_0_will_fire;
reg [7:0] mem_xcpt_uops_0_br_mask;
reg [4:0] mem_xcpt_uops_0_rob_idx;
reg [2:0] mem_xcpt_uops_0_ldq_idx;
reg [2:0] mem_xcpt_uops_0_stq_idx;
reg mem_xcpt_uops_0_uses_ldq;
reg mem_xcpt_uops_0_uses_stq;
reg [3:0] mem_xcpt_causes_0;
reg [39:0] mem_xcpt_vaddrs_0;
wire exe_tlb_miss_0 = ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_miss;
wire [31:0] exe_tlb_paddr_0 = {_dtlb_io_resp_0_paddr[31:12], exe_tlb_vaddr_0[11:0]};
reg REG;
wire [39:0] _GEN_217 = {8'h0, _dtlb_io_resp_0_paddr[31:12], exe_tlb_vaddr_0[11:0]};
wire [3:0][63:0] _GEN_218 = {{_GEN_92}, {{2{_GEN_92[31:0]}}}, {{2{{2{_GEN_92[15:0]}}}}}, {{2{{2{{2{_GEN_92[7:0]}}}}}}}};
wire _GEN_219 = will_fire_load_incoming_0_will_fire | will_fire_load_retry_0_will_fire;
assign _GEN_2 = hella_state == 3'h1;
wire _GEN_220 = will_fire_store_commit_0_will_fire | will_fire_load_wakeup_0_will_fire;
assign _GEN_1 = hella_state == 3'h5;
wire dmem_req_0_valid = will_fire_load_incoming_0_will_fire ? ~exe_tlb_miss_0 & _dtlb_io_resp_0_cacheable : will_fire_load_retry_0_will_fire ? ~exe_tlb_miss_0 & _dtlb_io_resp_0_cacheable : _GEN_220 | (will_fire_hella_incoming_0_will_fire ? ~io_hellacache_s1_kill : will_fire_hella_wakeup_0_will_fire);
wire [39:0] dmem_req_0_bits_addr = will_fire_load_incoming_0_will_fire | will_fire_load_retry_0_will_fire ? _GEN_217 : will_fire_store_commit_0_will_fire ? _GEN_88[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_179[ldq_wakeup_idx] : will_fire_hella_incoming_0_will_fire ? _GEN_217 : will_fire_hella_wakeup_0_will_fire ? {8'h0, hella_paddr} : 40'h0;
wire _GEN_221 = _stq_idx_T | will_fire_sta_retry_0_will_fire;
wire io_core_fp_stdata_ready_0 = ~will_fire_std_incoming_0_will_fire & ~will_fire_stad_incoming_0_will_fire;
wire fp_stdata_fire = io_core_fp_stdata_ready_0 & io_core_fp_stdata_valid;
wire _stq_bits_data_bits_T = will_fire_std_incoming_0_will_fire | will_fire_stad_incoming_0_will_fire;
wire _GEN_222 = _stq_bits_data_bits_T | fp_stdata_fire;
wire [2:0] sidx = _stq_bits_data_bits_T ? io_core_exe_0_req_bits_uop_stq_idx : io_core_fp_stdata_bits_uop_stq_idx;
reg fired_load_incoming_REG;
reg fired_stad_incoming_REG;
reg fired_sta_incoming_REG;
reg fired_std_incoming_REG;
reg fired_stdf_incoming;
reg fired_sfence_0;
reg fired_release_0;
reg fired_load_retry_REG;
reg fired_sta_retry_REG;
reg fired_load_wakeup_REG;
reg [7:0] mem_incoming_uop_0_br_mask;
reg [4:0] mem_incoming_uop_0_rob_idx;
reg [2:0] mem_incoming_uop_0_ldq_idx;
reg [2:0] mem_incoming_uop_0_stq_idx;
reg [5:0] mem_incoming_uop_0_pdst;
reg mem_incoming_uop_0_fp_val;
reg [7:0] mem_ldq_incoming_e_0_bits_uop_br_mask;
reg [2:0] mem_ldq_incoming_e_0_bits_uop_stq_idx;
reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size;
reg [7:0] mem_ldq_incoming_e_0_bits_st_dep_mask;
reg mem_stq_incoming_e_0_valid;
reg [7:0] mem_stq_incoming_e_0_bits_uop_br_mask;
reg [4:0] mem_stq_incoming_e_0_bits_uop_rob_idx;
reg [2:0] mem_stq_incoming_e_0_bits_uop_stq_idx;
reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size;
reg mem_stq_incoming_e_0_bits_uop_is_amo;
reg mem_stq_incoming_e_0_bits_addr_valid;
reg mem_stq_incoming_e_0_bits_addr_is_virtual;
reg mem_stq_incoming_e_0_bits_data_valid;
reg [7:0] mem_ldq_wakeup_e_bits_uop_br_mask;
reg [2:0] mem_ldq_wakeup_e_bits_uop_stq_idx;
reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size;
reg [7:0] mem_ldq_wakeup_e_bits_st_dep_mask;
reg [7:0] mem_ldq_retry_e_bits_uop_br_mask;
reg [2:0] mem_ldq_retry_e_bits_uop_stq_idx;
reg [1:0] mem_ldq_retry_e_bits_uop_mem_size;
reg [7:0] mem_ldq_retry_e_bits_st_dep_mask;
reg mem_stq_retry_e_valid;
reg [7:0] mem_stq_retry_e_bits_uop_br_mask;
reg [4:0] mem_stq_retry_e_bits_uop_rob_idx;
reg [2:0] mem_stq_retry_e_bits_uop_stq_idx;
reg [1:0] mem_stq_retry_e_bits_uop_mem_size;
reg mem_stq_retry_e_bits_uop_is_amo;
reg mem_stq_retry_e_bits_data_valid;
wire [7:0] lcam_st_dep_mask_0 = fired_load_incoming_REG ? mem_ldq_incoming_e_0_bits_st_dep_mask : fired_load_retry_REG ? mem_ldq_retry_e_bits_st_dep_mask : fired_load_wakeup_REG ? mem_ldq_wakeup_e_bits_st_dep_mask : 8'h0;
wire _lcam_stq_idx_T = fired_stad_incoming_REG | fired_sta_incoming_REG;
reg [7:0] mem_stdf_uop_br_mask;
reg [4:0] mem_stdf_uop_rob_idx;
reg [2:0] mem_stdf_uop_stq_idx;
reg mem_tlb_miss_0;
reg mem_tlb_uncacheable_0;
reg [39:0] mem_paddr_0;
reg clr_bsy_valid_0;
reg [4:0] clr_bsy_rob_idx_0;
reg [7:0] clr_bsy_brmask_0;
reg io_core_clr_bsy_0_valid_REG;
reg io_core_clr_bsy_0_valid_REG_1;
reg io_core_clr_bsy_0_valid_REG_2;
reg stdf_clr_bsy_valid;
reg [4:0] stdf_clr_bsy_rob_idx;
reg [7:0] stdf_clr_bsy_brmask;
reg io_core_clr_bsy_1_valid_REG;
reg io_core_clr_bsy_1_valid_REG_1;
reg io_core_clr_bsy_1_valid_REG_2;
wire do_st_search_0 = (_lcam_stq_idx_T | fired_sta_retry_REG) & ~mem_tlb_miss_0;
wire _can_forward_T = fired_load_incoming_REG | fired_load_retry_REG;
wire do_ld_search_0 = _can_forward_T & ~mem_tlb_miss_0 | fired_load_wakeup_REG;
reg [31:0] lcam_addr_REG;
reg [31:0] lcam_addr_REG_1;
wire [39:0] lcam_addr_0 = _lcam_stq_idx_T | fired_sta_retry_REG ? {8'h0, lcam_addr_REG} : fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0;
wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << lcam_addr_0[2:0];
wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << {12'h0, lcam_addr_0[2:1], 1'h0};
wire [3:0][7:0] _GEN_223 = {{8'hFF}, {lcam_addr_0[2] ? 8'hF0 : 8'hF}, {_lcam_mask_mask_T_6[7:0]}, {_lcam_mask_mask_T_2[7:0]}};
wire [7:0] lcam_mask_0 = _GEN_223[do_st_search_0 ? (_lcam_stq_idx_T ? mem_stq_incoming_e_0_bits_uop_mem_size : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_mem_size : 2'h0) : do_ld_search_0 ? (fired_load_incoming_REG ? mem_ldq_incoming_e_0_bits_uop_mem_size : fired_load_retry_REG ? mem_ldq_retry_e_bits_uop_mem_size : fired_load_wakeup_REG ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0) : 2'h0];
reg [2:0] lcam_ldq_idx_REG;
reg [2:0] lcam_ldq_idx_REG_1;
wire [2:0] lcam_ldq_idx_0 = fired_load_incoming_REG ? mem_incoming_uop_0_ldq_idx : fired_load_wakeup_REG ? lcam_ldq_idx_REG : fired_load_retry_REG ? lcam_ldq_idx_REG_1 : 3'h0;
reg [2:0] lcam_stq_idx_REG;
wire [2:0] lcam_stq_idx_0 = _lcam_stq_idx_T ? mem_incoming_uop_0_stq_idx : fired_sta_retry_REG ? lcam_stq_idx_REG : 3'h0;
reg s1_executing_loads_0;
reg s1_executing_loads_1;
reg s1_executing_loads_2;
reg s1_executing_loads_3;
reg s1_executing_loads_4;
reg s1_executing_loads_5;
reg s1_executing_loads_6;
reg s1_executing_loads_7;
reg wb_forward_valid_0;
reg [2:0] wb_forward_ldq_idx_0;
reg [39:0] wb_forward_ld_addr_0;
reg [2:0] wb_forward_stq_idx_0;
wire [14:0] _l_mask_mask_T_2 = 15'h1 << ldq_0_bits_addr_bits[2:0];
wire [14:0] _l_mask_mask_T_6 = 15'h3 << {12'h0, ldq_0_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_224 = {{8'hFF}, {ldq_0_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_6[7:0]}, {_l_mask_mask_T_2[7:0]}};
wire l_forwarders_0 = wb_forward_valid_0 & ~(|wb_forward_ldq_idx_0);
wire block_addr_matches_0 = lcam_addr_0[39:6] == ldq_0_bits_addr_bits[39:6];
wire dword_addr_matches_0 = block_addr_matches_0 & lcam_addr_0[5:3] == ldq_0_bits_addr_bits[5:3];
wire [7:0] _mask_overlap_T = _GEN_224[ldq_0_bits_uop_mem_size] & lcam_mask_0;
wire _GEN_225 = fired_release_0 & ldq_0_valid & ldq_0_bits_addr_valid & block_addr_matches_0;
wire _GEN_226 = ldq_0_bits_executed | ldq_0_bits_succeeded;
wire _GEN_227 = _GEN_226 | l_forwarders_0;
wire [7:0] _GEN_228 = {5'h0, lcam_stq_idx_0};
wire [7:0] _GEN_229 = ldq_0_bits_st_dep_mask >> _GEN_228;
wire _GEN_230 = do_st_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & _GEN_227 & ~ldq_0_bits_addr_is_virtual & _GEN_229[0] & dword_addr_matches_0 & (|_mask_overlap_T);
wire _GEN_231 = do_ld_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & ~ldq_0_bits_addr_is_virtual & dword_addr_matches_0 & (|_mask_overlap_T);
wire searcher_is_older = lcam_ldq_idx_0 < ldq_head ^ (|ldq_head);
reg older_nacked_REG;
wire _GEN_232 = ~_GEN_226 | nacking_loads_0 | older_nacked_REG;
wire _GEN_233 = _GEN_225 | _GEN_230;
wire _GEN_234 = lcam_ldq_idx_0 == 3'h1;
wire _GEN_235 = lcam_ldq_idx_0 == 3'h2;
wire _GEN_236 = lcam_ldq_idx_0 == 3'h3;
wire _GEN_237 = lcam_ldq_idx_0 == 3'h4;
wire _GEN_238 = lcam_ldq_idx_0 == 3'h5;
wire _GEN_239 = lcam_ldq_idx_0 == 3'h6;
reg io_dmem_s1_kill_0_REG;
wire _GEN_240 = (|lcam_ldq_idx_0) & _GEN_232;
wire [14:0] _l_mask_mask_T_17 = 15'h1 << ldq_1_bits_addr_bits[2:0];
wire [14:0] _l_mask_mask_T_21 = 15'h3 << {12'h0, ldq_1_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_241 = {{8'hFF}, {ldq_1_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_21[7:0]}, {_l_mask_mask_T_17[7:0]}};
wire l_forwarders_1_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h1;
wire block_addr_matches_1_0 = lcam_addr_0[39:6] == ldq_1_bits_addr_bits[39:6];
wire dword_addr_matches_1_0 = block_addr_matches_1_0 & lcam_addr_0[5:3] == ldq_1_bits_addr_bits[5:3];
wire [7:0] _mask_overlap_T_2 = _GEN_241[ldq_1_bits_uop_mem_size] & lcam_mask_0;
wire _GEN_242 = fired_release_0 & ldq_1_valid & ldq_1_bits_addr_valid & block_addr_matches_1_0;
wire _GEN_243 = ldq_1_bits_executed | ldq_1_bits_succeeded;
wire _GEN_244 = _GEN_243 | l_forwarders_1_0;
wire [7:0] _GEN_245 = ldq_1_bits_st_dep_mask >> _GEN_228;
wire _GEN_246 = do_st_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & _GEN_244 & ~ldq_1_bits_addr_is_virtual & _GEN_245[0] & dword_addr_matches_1_0 & (|_mask_overlap_T_2);
wire _GEN_247 = do_ld_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & ~ldq_1_bits_addr_is_virtual & dword_addr_matches_1_0 & (|_mask_overlap_T_2);
wire searcher_is_older_1 = lcam_ldq_idx_0 == 3'h0 ^ lcam_ldq_idx_0 < ldq_head ^ (|(ldq_head[2:1]));
reg older_nacked_REG_1;
wire _GEN_248 = ~_GEN_243 | nacking_loads_1 | older_nacked_REG_1;
wire _GEN_249 = searcher_is_older_1 | _GEN_234;
wire _GEN_250 = _GEN_242 | _GEN_246;
reg io_dmem_s1_kill_0_REG_1;
wire _GEN_251 = _GEN_250 | ~_GEN_247 | _GEN_249 | ~_GEN_248;
wire [14:0] _l_mask_mask_T_32 = 15'h1 << ldq_2_bits_addr_bits[2:0];
wire [14:0] _l_mask_mask_T_36 = 15'h3 << {12'h0, ldq_2_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_252 = {{8'hFF}, {ldq_2_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_36[7:0]}, {_l_mask_mask_T_32[7:0]}};
wire l_forwarders_2_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h2;
wire block_addr_matches_2_0 = lcam_addr_0[39:6] == ldq_2_bits_addr_bits[39:6];
wire dword_addr_matches_2_0 = block_addr_matches_2_0 & lcam_addr_0[5:3] == ldq_2_bits_addr_bits[5:3];
wire [7:0] _mask_overlap_T_4 = _GEN_252[ldq_2_bits_uop_mem_size] & lcam_mask_0;
wire _GEN_253 = fired_release_0 & ldq_2_valid & ldq_2_bits_addr_valid & block_addr_matches_2_0;
wire _GEN_254 = ldq_2_bits_executed | ldq_2_bits_succeeded;
wire _GEN_255 = _GEN_254 | l_forwarders_2_0;
wire [7:0] _GEN_256 = ldq_2_bits_st_dep_mask >> _GEN_228;
wire _GEN_257 = do_st_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & _GEN_255 & ~ldq_2_bits_addr_is_virtual & _GEN_256[0] & dword_addr_matches_2_0 & (|_mask_overlap_T_4);
wire _GEN_258 = do_ld_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & ~ldq_2_bits_addr_is_virtual & dword_addr_matches_2_0 & (|_mask_overlap_T_4);
wire searcher_is_older_2 = lcam_ldq_idx_0 < 3'h2 ^ lcam_ldq_idx_0 < ldq_head ^ ldq_head > 3'h2;
reg older_nacked_REG_2;
wire _GEN_259 = ~_GEN_254 | nacking_loads_2 | older_nacked_REG_2;
wire _GEN_260 = searcher_is_older_2 | _GEN_235;
wire _GEN_261 = _GEN_253 | _GEN_257;
reg io_dmem_s1_kill_0_REG_2;
wire _GEN_262 = _GEN_261 | ~_GEN_258 | _GEN_260 | ~_GEN_259;
wire [14:0] _l_mask_mask_T_47 = 15'h1 << ldq_3_bits_addr_bits[2:0];
wire [14:0] _l_mask_mask_T_51 = 15'h3 << {12'h0, ldq_3_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_263 = {{8'hFF}, {ldq_3_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_51[7:0]}, {_l_mask_mask_T_47[7:0]}};
wire l_forwarders_3_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h3;
wire block_addr_matches_3_0 = lcam_addr_0[39:6] == ldq_3_bits_addr_bits[39:6];
wire dword_addr_matches_3_0 = block_addr_matches_3_0 & lcam_addr_0[5:3] == ldq_3_bits_addr_bits[5:3];
wire [7:0] _mask_overlap_T_6 = _GEN_263[ldq_3_bits_uop_mem_size] & lcam_mask_0;
wire _GEN_264 = fired_release_0 & ldq_3_valid & ldq_3_bits_addr_valid & block_addr_matches_3_0;
wire _GEN_265 = ldq_3_bits_executed | ldq_3_bits_succeeded;
wire _GEN_266 = _GEN_265 | l_forwarders_3_0;
wire [7:0] _GEN_267 = ldq_3_bits_st_dep_mask >> _GEN_228;
wire _GEN_268 = do_st_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & _GEN_266 & ~ldq_3_bits_addr_is_virtual & _GEN_267[0] & dword_addr_matches_3_0 & (|_mask_overlap_T_6);
wire _GEN_269 = do_ld_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & ~ldq_3_bits_addr_is_virtual & dword_addr_matches_3_0 & (|_mask_overlap_T_6);
wire searcher_is_older_3 = lcam_ldq_idx_0 < 3'h3 ^ lcam_ldq_idx_0 < ldq_head ^ ldq_head[2];
reg older_nacked_REG_3;
wire _GEN_270 = ~_GEN_265 | nacking_loads_3 | older_nacked_REG_3;
wire _GEN_271 = searcher_is_older_3 | _GEN_236;
wire _GEN_272 = _GEN_264 | _GEN_268;
reg io_dmem_s1_kill_0_REG_3;
wire _GEN_273 = _GEN_272 | ~_GEN_269 | _GEN_271 | ~_GEN_270;
wire [14:0] _l_mask_mask_T_62 = 15'h1 << ldq_4_bits_addr_bits[2:0];
wire [14:0] _l_mask_mask_T_66 = 15'h3 << {12'h0, ldq_4_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_274 = {{8'hFF}, {ldq_4_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_66[7:0]}, {_l_mask_mask_T_62[7:0]}};
wire l_forwarders_4_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h4;
wire block_addr_matches_4_0 = lcam_addr_0[39:6] == ldq_4_bits_addr_bits[39:6];
wire dword_addr_matches_4_0 = block_addr_matches_4_0 & lcam_addr_0[5:3] == ldq_4_bits_addr_bits[5:3];
wire [7:0] _mask_overlap_T_8 = _GEN_274[ldq_4_bits_uop_mem_size] & lcam_mask_0;
wire _GEN_275 = fired_release_0 & ldq_4_valid & ldq_4_bits_addr_valid & block_addr_matches_4_0;
wire _GEN_276 = ldq_4_bits_executed | ldq_4_bits_succeeded;
wire _GEN_277 = _GEN_276 | l_forwarders_4_0;
wire [7:0] _GEN_278 = ldq_4_bits_st_dep_mask >> _GEN_228;
wire _GEN_279 = do_st_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & _GEN_277 & ~ldq_4_bits_addr_is_virtual & _GEN_278[0] & dword_addr_matches_4_0 & (|_mask_overlap_T_8);
wire _GEN_280 = do_ld_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & ~ldq_4_bits_addr_is_virtual & dword_addr_matches_4_0 & (|_mask_overlap_T_8);
wire searcher_is_older_4 = lcam_ldq_idx_0[2] ^ ldq_head > 3'h4 ^ lcam_ldq_idx_0 >= ldq_head;
reg older_nacked_REG_4;
wire _GEN_281 = ~_GEN_276 | nacking_loads_4 | older_nacked_REG_4;
wire _GEN_282 = searcher_is_older_4 | _GEN_237;
wire _GEN_283 = _GEN_275 | _GEN_279;
reg io_dmem_s1_kill_0_REG_4;
wire _GEN_284 = _GEN_283 | ~_GEN_280 | _GEN_282 | ~_GEN_281;
wire [14:0] _l_mask_mask_T_77 = 15'h1 << ldq_5_bits_addr_bits[2:0];
wire [14:0] _l_mask_mask_T_81 = 15'h3 << {12'h0, ldq_5_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_285 = {{8'hFF}, {ldq_5_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_81[7:0]}, {_l_mask_mask_T_77[7:0]}};
wire l_forwarders_5_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h5;
wire block_addr_matches_5_0 = lcam_addr_0[39:6] == ldq_5_bits_addr_bits[39:6];
wire dword_addr_matches_5_0 = block_addr_matches_5_0 & lcam_addr_0[5:3] == ldq_5_bits_addr_bits[5:3];
wire [7:0] _mask_overlap_T_10 = _GEN_285[ldq_5_bits_uop_mem_size] & lcam_mask_0;
wire _GEN_286 = fired_release_0 & ldq_5_valid & ldq_5_bits_addr_valid & block_addr_matches_5_0;
wire _GEN_287 = ldq_5_bits_executed | ldq_5_bits_succeeded;
wire _GEN_288 = _GEN_287 | l_forwarders_5_0;
wire [7:0] _GEN_289 = ldq_5_bits_st_dep_mask >> _GEN_228;
wire _GEN_290 = do_st_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & _GEN_288 & ~ldq_5_bits_addr_is_virtual & _GEN_289[0] & dword_addr_matches_5_0 & (|_mask_overlap_T_10);
wire _GEN_291 = do_ld_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & ~ldq_5_bits_addr_is_virtual & dword_addr_matches_5_0 & (|_mask_overlap_T_10);
wire searcher_is_older_5 = lcam_ldq_idx_0 < 3'h5 ^ lcam_ldq_idx_0 < ldq_head ^ ldq_head > 3'h5;
reg older_nacked_REG_5;
wire _GEN_292 = ~_GEN_287 | nacking_loads_5 | older_nacked_REG_5;
wire _GEN_293 = searcher_is_older_5 | _GEN_238;
wire _GEN_294 = _GEN_286 | _GEN_290;
reg io_dmem_s1_kill_0_REG_5;
wire _GEN_295 = _GEN_294 | ~_GEN_291 | _GEN_293 | ~_GEN_292;
wire [14:0] _l_mask_mask_T_92 = 15'h1 << ldq_6_bits_addr_bits[2:0];
wire [14:0] _l_mask_mask_T_96 = 15'h3 << {12'h0, ldq_6_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_296 = {{8'hFF}, {ldq_6_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_96[7:0]}, {_l_mask_mask_T_92[7:0]}};
wire l_forwarders_6_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h6;
wire block_addr_matches_6_0 = lcam_addr_0[39:6] == ldq_6_bits_addr_bits[39:6];
wire dword_addr_matches_6_0 = block_addr_matches_6_0 & lcam_addr_0[5:3] == ldq_6_bits_addr_bits[5:3];
wire [7:0] _mask_overlap_T_12 = _GEN_296[ldq_6_bits_uop_mem_size] & lcam_mask_0;
wire _GEN_297 = fired_release_0 & ldq_6_valid & ldq_6_bits_addr_valid & block_addr_matches_6_0;
wire _GEN_298 = ldq_6_bits_executed | ldq_6_bits_succeeded;
wire _GEN_299 = _GEN_298 | l_forwarders_6_0;
wire [7:0] _GEN_300 = ldq_6_bits_st_dep_mask >> _GEN_228;
wire _GEN_301 = do_st_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & _GEN_299 & ~ldq_6_bits_addr_is_virtual & _GEN_300[0] & dword_addr_matches_6_0 & (|_mask_overlap_T_12);
wire _GEN_302 = do_ld_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & ~ldq_6_bits_addr_is_virtual & dword_addr_matches_6_0 & (|_mask_overlap_T_12);
wire searcher_is_older_6 = lcam_ldq_idx_0[2:1] != 2'h3 ^ lcam_ldq_idx_0 < ldq_head ^ (&ldq_head);
reg older_nacked_REG_6;
wire _GEN_303 = ~_GEN_298 | nacking_loads_6 | older_nacked_REG_6;
wire _GEN_304 = searcher_is_older_6 | _GEN_239;
wire _GEN_305 = _GEN_297 | _GEN_301;
reg io_dmem_s1_kill_0_REG_6;
wire _GEN_306 = _GEN_305 | ~_GEN_302 | _GEN_304 | ~_GEN_303;
wire [14:0] _l_mask_mask_T_107 = 15'h1 << ldq_7_bits_addr_bits[2:0];
wire [14:0] _l_mask_mask_T_111 = 15'h3 << {12'h0, ldq_7_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_307 = {{8'hFF}, {ldq_7_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_111[7:0]}, {_l_mask_mask_T_107[7:0]}};
wire l_forwarders_7_0 = wb_forward_valid_0 & (&wb_forward_ldq_idx_0);
wire block_addr_matches_7_0 = lcam_addr_0[39:6] == ldq_7_bits_addr_bits[39:6];
wire dword_addr_matches_7_0 = block_addr_matches_7_0 & lcam_addr_0[5:3] == ldq_7_bits_addr_bits[5:3];
wire [7:0] _mask_overlap_T_14 = _GEN_307[ldq_7_bits_uop_mem_size] & lcam_mask_0;
wire _GEN_308 = fired_release_0 & ldq_7_valid & ldq_7_bits_addr_valid & block_addr_matches_7_0;
wire _GEN_309 = ldq_7_bits_executed | ldq_7_bits_succeeded;
wire _GEN_310 = _GEN_309 | l_forwarders_7_0;
wire [7:0] _GEN_311 = ldq_7_bits_st_dep_mask >> _GEN_228;
wire _GEN_312 = do_st_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & _GEN_310 & ~ldq_7_bits_addr_is_virtual & _GEN_311[0] & dword_addr_matches_7_0 & (|_mask_overlap_T_14);
wire _GEN_313 = do_ld_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & ~ldq_7_bits_addr_is_virtual & dword_addr_matches_7_0 & (|_mask_overlap_T_14);
wire searcher_is_older_7 = lcam_ldq_idx_0 != 3'h7 ^ lcam_ldq_idx_0 < ldq_head;
reg older_nacked_REG_7;
wire _GEN_314 = ~_GEN_309 | nacking_loads_7 | older_nacked_REG_7;
wire _GEN_315 = _GEN_308 | _GEN_312;
reg io_dmem_s1_kill_0_REG_7;
wire _GEN_316 = _GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314);
wire _GEN_317 = _GEN_316 ? (_GEN_306 ? (_GEN_295 ? (_GEN_284 ? (_GEN_273 ? (_GEN_262 ? (_GEN_251 ? ~_GEN_233 & _GEN_231 & ~searcher_is_older & _GEN_240 & io_dmem_s1_kill_0_REG : io_dmem_s1_kill_0_REG_1) : io_dmem_s1_kill_0_REG_2) : io_dmem_s1_kill_0_REG_3) : io_dmem_s1_kill_0_REG_4) : io_dmem_s1_kill_0_REG_5) : io_dmem_s1_kill_0_REG_6) : io_dmem_s1_kill_0_REG_7;
wire can_forward_0 = _GEN_316 & _GEN_306 & _GEN_295 & _GEN_284 & _GEN_273 & _GEN_262 & _GEN_251 & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~_GEN_240) & (_can_forward_T ? ~mem_tlb_uncacheable_0 : ~_GEN_191[lcam_ldq_idx_0]);
wire dword_addr_matches_8_0 = stq_0_bits_addr_valid & ~stq_0_bits_addr_is_virtual & stq_0_bits_addr_bits[31:3] == lcam_addr_0[31:3];
wire [14:0] _write_mask_mask_T_2 = 15'h1 << stq_0_bits_addr_bits[2:0];
wire [14:0] _write_mask_mask_T_6 = 15'h3 << {12'h0, stq_0_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_318 = {{8'hFF}, {stq_0_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_6[7:0]}, {_write_mask_mask_T_2[7:0]}};
wire _GEN_319 = do_ld_search_0 & stq_0_valid & lcam_st_dep_mask_0[0];
wire [7:0] _GEN_320 = lcam_mask_0 & _GEN_318[stq_0_bits_uop_mem_size];
wire _GEN_321 = _GEN_320 == lcam_mask_0 & ~stq_0_bits_uop_is_fence & ~stq_0_bits_uop_is_amo & dword_addr_matches_8_0 & can_forward_0;
reg io_dmem_s1_kill_0_REG_8;
wire _GEN_322 = (|_GEN_320) & dword_addr_matches_8_0;
reg io_dmem_s1_kill_0_REG_9;
wire _GEN_323 = stq_0_bits_uop_is_fence | stq_0_bits_uop_is_amo;
wire ldst_addr_matches_0_0 = _GEN_319 & (_GEN_321 | _GEN_322 | _GEN_323);
reg io_dmem_s1_kill_0_REG_10;
wire _GEN_324 = _GEN_319 ? (_GEN_321 ? io_dmem_s1_kill_0_REG_8 : _GEN_322 ? io_dmem_s1_kill_0_REG_9 : _GEN_323 ? io_dmem_s1_kill_0_REG_10 : _GEN_317) : _GEN_317;
wire dword_addr_matches_9_0 = stq_1_bits_addr_valid & ~stq_1_bits_addr_is_virtual & stq_1_bits_addr_bits[31:3] == lcam_addr_0[31:3];
wire [14:0] _write_mask_mask_T_17 = 15'h1 << stq_1_bits_addr_bits[2:0];
wire [14:0] _write_mask_mask_T_21 = 15'h3 << {12'h0, stq_1_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_325 = {{8'hFF}, {stq_1_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_21[7:0]}, {_write_mask_mask_T_17[7:0]}};
wire _GEN_326 = do_ld_search_0 & stq_1_valid & lcam_st_dep_mask_0[1];
wire [7:0] _GEN_327 = lcam_mask_0 & _GEN_325[stq_1_bits_uop_mem_size];
wire _GEN_328 = _GEN_327 == lcam_mask_0 & ~stq_1_bits_uop_is_fence & ~stq_1_bits_uop_is_amo & dword_addr_matches_9_0 & can_forward_0;
reg io_dmem_s1_kill_0_REG_11;
wire _GEN_329 = (|_GEN_327) & dword_addr_matches_9_0;
reg io_dmem_s1_kill_0_REG_12;
wire _GEN_330 = stq_1_bits_uop_is_fence | stq_1_bits_uop_is_amo;
wire ldst_addr_matches_0_1 = _GEN_326 & (_GEN_328 | _GEN_329 | _GEN_330);
reg io_dmem_s1_kill_0_REG_13;
wire _GEN_331 = _GEN_326 ? (_GEN_328 ? io_dmem_s1_kill_0_REG_11 : _GEN_329 ? io_dmem_s1_kill_0_REG_12 : _GEN_330 ? io_dmem_s1_kill_0_REG_13 : _GEN_324) : _GEN_324;
wire dword_addr_matches_10_0 = stq_2_bits_addr_valid & ~stq_2_bits_addr_is_virtual & stq_2_bits_addr_bits[31:3] == lcam_addr_0[31:3];
wire [14:0] _write_mask_mask_T_32 = 15'h1 << stq_2_bits_addr_bits[2:0];
wire [14:0] _write_mask_mask_T_36 = 15'h3 << {12'h0, stq_2_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_332 = {{8'hFF}, {stq_2_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_36[7:0]}, {_write_mask_mask_T_32[7:0]}};
wire _GEN_333 = do_ld_search_0 & stq_2_valid & lcam_st_dep_mask_0[2];
wire [7:0] _GEN_334 = lcam_mask_0 & _GEN_332[stq_2_bits_uop_mem_size];
wire _GEN_335 = _GEN_334 == lcam_mask_0 & ~stq_2_bits_uop_is_fence & ~stq_2_bits_uop_is_amo & dword_addr_matches_10_0 & can_forward_0;
reg io_dmem_s1_kill_0_REG_14;
wire _GEN_336 = (|_GEN_334) & dword_addr_matches_10_0;
reg io_dmem_s1_kill_0_REG_15;
wire _GEN_337 = stq_2_bits_uop_is_fence | stq_2_bits_uop_is_amo;
wire ldst_addr_matches_0_2 = _GEN_333 & (_GEN_335 | _GEN_336 | _GEN_337);
reg io_dmem_s1_kill_0_REG_16;
wire _GEN_338 = _GEN_333 ? (_GEN_335 ? io_dmem_s1_kill_0_REG_14 : _GEN_336 ? io_dmem_s1_kill_0_REG_15 : _GEN_337 ? io_dmem_s1_kill_0_REG_16 : _GEN_331) : _GEN_331;
wire dword_addr_matches_11_0 = stq_3_bits_addr_valid & ~stq_3_bits_addr_is_virtual & stq_3_bits_addr_bits[31:3] == lcam_addr_0[31:3];
wire [14:0] _write_mask_mask_T_47 = 15'h1 << stq_3_bits_addr_bits[2:0];
wire [14:0] _write_mask_mask_T_51 = 15'h3 << {12'h0, stq_3_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_339 = {{8'hFF}, {stq_3_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_51[7:0]}, {_write_mask_mask_T_47[7:0]}};
wire _GEN_340 = do_ld_search_0 & stq_3_valid & lcam_st_dep_mask_0[3];
wire [7:0] _GEN_341 = lcam_mask_0 & _GEN_339[stq_3_bits_uop_mem_size];
wire _GEN_342 = _GEN_341 == lcam_mask_0 & ~stq_3_bits_uop_is_fence & ~stq_3_bits_uop_is_amo & dword_addr_matches_11_0 & can_forward_0;
reg io_dmem_s1_kill_0_REG_17;
wire _GEN_343 = (|_GEN_341) & dword_addr_matches_11_0;
reg io_dmem_s1_kill_0_REG_18;
wire _GEN_344 = stq_3_bits_uop_is_fence | stq_3_bits_uop_is_amo;
wire ldst_addr_matches_0_3 = _GEN_340 & (_GEN_342 | _GEN_343 | _GEN_344);
reg io_dmem_s1_kill_0_REG_19;
wire _GEN_345 = _GEN_340 ? (_GEN_342 ? io_dmem_s1_kill_0_REG_17 : _GEN_343 ? io_dmem_s1_kill_0_REG_18 : _GEN_344 ? io_dmem_s1_kill_0_REG_19 : _GEN_338) : _GEN_338;
wire dword_addr_matches_12_0 = stq_4_bits_addr_valid & ~stq_4_bits_addr_is_virtual & stq_4_bits_addr_bits[31:3] == lcam_addr_0[31:3];
wire [14:0] _write_mask_mask_T_62 = 15'h1 << stq_4_bits_addr_bits[2:0];
wire [14:0] _write_mask_mask_T_66 = 15'h3 << {12'h0, stq_4_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_346 = {{8'hFF}, {stq_4_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_66[7:0]}, {_write_mask_mask_T_62[7:0]}};
wire _GEN_347 = do_ld_search_0 & stq_4_valid & lcam_st_dep_mask_0[4];
wire [7:0] _GEN_348 = lcam_mask_0 & _GEN_346[stq_4_bits_uop_mem_size];
wire _GEN_349 = _GEN_348 == lcam_mask_0 & ~stq_4_bits_uop_is_fence & ~stq_4_bits_uop_is_amo & dword_addr_matches_12_0 & can_forward_0;
reg io_dmem_s1_kill_0_REG_20;
wire _GEN_350 = (|_GEN_348) & dword_addr_matches_12_0;
reg io_dmem_s1_kill_0_REG_21;
wire _GEN_351 = stq_4_bits_uop_is_fence | stq_4_bits_uop_is_amo;
wire ldst_addr_matches_0_4 = _GEN_347 & (_GEN_349 | _GEN_350 | _GEN_351);
reg io_dmem_s1_kill_0_REG_22;
wire _GEN_352 = _GEN_347 ? (_GEN_349 ? io_dmem_s1_kill_0_REG_20 : _GEN_350 ? io_dmem_s1_kill_0_REG_21 : _GEN_351 ? io_dmem_s1_kill_0_REG_22 : _GEN_345) : _GEN_345;
wire dword_addr_matches_13_0 = stq_5_bits_addr_valid & ~stq_5_bits_addr_is_virtual & stq_5_bits_addr_bits[31:3] == lcam_addr_0[31:3];
wire [14:0] _write_mask_mask_T_77 = 15'h1 << stq_5_bits_addr_bits[2:0];
wire [14:0] _write_mask_mask_T_81 = 15'h3 << {12'h0, stq_5_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_353 = {{8'hFF}, {stq_5_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_81[7:0]}, {_write_mask_mask_T_77[7:0]}};
wire _GEN_354 = do_ld_search_0 & stq_5_valid & lcam_st_dep_mask_0[5];
wire [7:0] _GEN_355 = lcam_mask_0 & _GEN_353[stq_5_bits_uop_mem_size];
wire _GEN_356 = _GEN_355 == lcam_mask_0 & ~stq_5_bits_uop_is_fence & ~stq_5_bits_uop_is_amo & dword_addr_matches_13_0 & can_forward_0;
reg io_dmem_s1_kill_0_REG_23;
wire _GEN_357 = (|_GEN_355) & dword_addr_matches_13_0;
reg io_dmem_s1_kill_0_REG_24;
wire _GEN_358 = stq_5_bits_uop_is_fence | stq_5_bits_uop_is_amo;
wire ldst_addr_matches_0_5 = _GEN_354 & (_GEN_356 | _GEN_357 | _GEN_358);
reg io_dmem_s1_kill_0_REG_25;
wire _GEN_359 = _GEN_354 ? (_GEN_356 ? io_dmem_s1_kill_0_REG_23 : _GEN_357 ? io_dmem_s1_kill_0_REG_24 : _GEN_358 ? io_dmem_s1_kill_0_REG_25 : _GEN_352) : _GEN_352;
wire dword_addr_matches_14_0 = stq_6_bits_addr_valid & ~stq_6_bits_addr_is_virtual & stq_6_bits_addr_bits[31:3] == lcam_addr_0[31:3];
wire [14:0] _write_mask_mask_T_92 = 15'h1 << stq_6_bits_addr_bits[2:0];
wire [14:0] _write_mask_mask_T_96 = 15'h3 << {12'h0, stq_6_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_360 = {{8'hFF}, {stq_6_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_96[7:0]}, {_write_mask_mask_T_92[7:0]}};
wire _GEN_361 = do_ld_search_0 & stq_6_valid & lcam_st_dep_mask_0[6];
wire [7:0] _GEN_362 = lcam_mask_0 & _GEN_360[stq_6_bits_uop_mem_size];
wire _GEN_363 = _GEN_362 == lcam_mask_0 & ~stq_6_bits_uop_is_fence & ~stq_6_bits_uop_is_amo & dword_addr_matches_14_0 & can_forward_0;
reg io_dmem_s1_kill_0_REG_26;
wire _GEN_364 = (|_GEN_362) & dword_addr_matches_14_0;
reg io_dmem_s1_kill_0_REG_27;
wire _GEN_365 = stq_6_bits_uop_is_fence | stq_6_bits_uop_is_amo;
wire ldst_addr_matches_0_6 = _GEN_361 & (_GEN_363 | _GEN_364 | _GEN_365);
reg io_dmem_s1_kill_0_REG_28;
wire _GEN_366 = _GEN_361 ? (_GEN_363 ? io_dmem_s1_kill_0_REG_26 : _GEN_364 ? io_dmem_s1_kill_0_REG_27 : _GEN_365 ? io_dmem_s1_kill_0_REG_28 : _GEN_359) : _GEN_359;
wire dword_addr_matches_15_0 = stq_7_bits_addr_valid & ~stq_7_bits_addr_is_virtual & stq_7_bits_addr_bits[31:3] == lcam_addr_0[31:3];
wire [14:0] _write_mask_mask_T_107 = 15'h1 << stq_7_bits_addr_bits[2:0];
wire [14:0] _write_mask_mask_T_111 = 15'h3 << {12'h0, stq_7_bits_addr_bits[2:1], 1'h0};
wire [3:0][7:0] _GEN_367 = {{8'hFF}, {stq_7_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_111[7:0]}, {_write_mask_mask_T_107[7:0]}};
wire _GEN_368 = do_ld_search_0 & stq_7_valid & lcam_st_dep_mask_0[7];
wire [7:0] _GEN_369 = lcam_mask_0 & _GEN_367[stq_7_bits_uop_mem_size];
wire _GEN_370 = _GEN_369 == lcam_mask_0 & ~stq_7_bits_uop_is_fence & ~stq_7_bits_uop_is_amo & dword_addr_matches_15_0 & can_forward_0;
reg io_dmem_s1_kill_0_REG_29;
wire _GEN_371 = (|_GEN_369) & dword_addr_matches_15_0;
reg io_dmem_s1_kill_0_REG_30;
wire _GEN_372 = stq_7_bits_uop_is_fence | stq_7_bits_uop_is_amo;
wire ldst_addr_matches_0_7 = _GEN_368 & (_GEN_370 | _GEN_371 | _GEN_372);
reg io_dmem_s1_kill_0_REG_31;
reg REG_1;
reg REG_2;
reg [3:0] store_blocked_counter;
assign block_load_wakeup = (&store_blocked_counter) | REG_2;
reg r_xcpt_valid;
reg [7:0] r_xcpt_uop_br_mask;
reg [4:0] r_xcpt_uop_rob_idx;
reg [4:0] r_xcpt_cause;
reg [39:0] r_xcpt_badvaddr;
wire io_core_spec_ld_wakeup_0_valid_0 = fired_load_incoming_REG & ~mem_incoming_uop_0_fp_val & (|mem_incoming_uop_0_pdst);
wire _GEN_373 = io_dmem_nack_0_valid & io_dmem_nack_0_bits_is_hella;
wire _GEN_374 = hella_state == 3'h4;
wire _GEN_375 = hella_state == 3'h6;
wire _GEN_376 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella;
wire _GEN_377 = _GEN_376 & io_dmem_nack_0_bits_uop_uses_ldq & ~reset;
wire _GEN_378 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h0;
wire _GEN_379 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h1;
wire _GEN_380 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h2;
wire _GEN_381 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h3;
wire _GEN_382 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h4;
wire _GEN_383 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h5;
wire _GEN_384 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h6;
assign nacking_loads_0 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_378;
assign nacking_loads_1 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_379;
assign nacking_loads_2 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_380;
assign nacking_loads_3 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_381;
assign nacking_loads_4 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_382;
assign nacking_loads_5 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_383;
assign nacking_loads_6 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_384;
assign nacking_loads_7 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & (&io_dmem_nack_0_bits_uop_ldq_idx);
wire _GEN_385 = io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq;
wire send_iresp = _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx] == 2'h0;
wire send_fresp = _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx] == 2'h1;
wire _GEN_386 = io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_is_amo;
wire dmem_resp_fired_0 = io_dmem_resp_0_valid & (io_dmem_resp_0_bits_uop_uses_ldq | _GEN_386);
wire _GEN_387 = dmem_resp_fired_0 & wb_forward_valid_0;
wire _GEN_388 = ~dmem_resp_fired_0 & wb_forward_valid_0;
wire [7:0] _GEN_389 = _GEN_97[wb_forward_ldq_idx_0];
wire [4:0] _GEN_390 = _GEN_135[wb_forward_ldq_idx_0];
wire [5:0] _GEN_391 = _GEN_138[wb_forward_ldq_idx_0];
wire [1:0] size_1 = _GEN_99[wb_forward_ldq_idx_0];
wire _GEN_392 = _GEN_151[wb_forward_ldq_idx_0];
wire _GEN_393 = _GEN_154[wb_forward_ldq_idx_0];
wire _GEN_394 = _GEN_156[wb_forward_ldq_idx_0];
wire [1:0] _GEN_395 = _GEN_166[wb_forward_ldq_idx_0];
wire live = (io_core_brupdate_b1_mispredict_mask & _GEN_389) == 8'h0;
wire _GEN_396 = _GEN_90[wb_forward_stq_idx_0];
wire [63:0] _GEN_397 = _GEN_91[wb_forward_stq_idx_0];
wire [3:0][63:0] _GEN_398 = {{_GEN_397}, {{2{_GEN_397[31:0]}}}, {{2{{2{_GEN_397[15:0]}}}}}, {{2{{2{{2{_GEN_397[7:0]}}}}}}}};
wire [63:0] _GEN_399 = _GEN_398[_GEN_56[wb_forward_stq_idx_0]];
wire _GEN_400 = _GEN_387 | ~_GEN_388;
wire io_core_exe_0_iresp_valid_0 = _GEN_400 ? io_dmem_resp_0_valid & (io_dmem_resp_0_bits_uop_uses_ldq ? send_iresp : _GEN_386) : _GEN_395 == 2'h0 & _GEN_396 & live;
wire io_core_exe_0_fresp_valid_0 = _GEN_400 ? _GEN_385 & send_fresp : _GEN_395 == 2'h1 & _GEN_396 & live;
wire [31:0] io_core_exe_0_iresp_bits_data_zeroed = wb_forward_ld_addr_0[2] ? _GEN_399[63:32] : _GEN_399[31:0];
wire _ldq_bits_debug_wb_data_T_1 = size_1 == 2'h2;
wire [15:0] io_core_exe_0_iresp_bits_data_zeroed_1 = wb_forward_ld_addr_0[1] ? io_core_exe_0_iresp_bits_data_zeroed[31:16] : io_core_exe_0_iresp_bits_data_zeroed[15:0];
wire _ldq_bits_debug_wb_data_T_9 = size_1 == 2'h1;
wire [7:0] io_core_exe_0_iresp_bits_data_zeroed_2 = wb_forward_ld_addr_0[0] ? io_core_exe_0_iresp_bits_data_zeroed_1[15:8] : io_core_exe_0_iresp_bits_data_zeroed_1[7:0];
wire _ldq_bits_debug_wb_data_T_17 = size_1 == 2'h0;
wire [31:0] io_core_exe_0_fresp_bits_data_zeroed = wb_forward_ld_addr_0[2] ? _GEN_399[63:32] : _GEN_399[31:0];
wire [15:0] io_core_exe_0_fresp_bits_data_zeroed_1 = wb_forward_ld_addr_0[1] ? io_core_exe_0_fresp_bits_data_zeroed[31:16] : io_core_exe_0_fresp_bits_data_zeroed[15:0];
wire [7:0] io_core_exe_0_fresp_bits_data_zeroed_2 = wb_forward_ld_addr_0[0] ? io_core_exe_0_fresp_bits_data_zeroed_1[15:8] : io_core_exe_0_fresp_bits_data_zeroed_1[7:0];
reg io_core_ld_miss_REG;
reg spec_ld_succeed_REG;
reg [2:0] spec_ld_succeed_REG_1;
wire [7:0] _GEN_401 = io_core_brupdate_b1_mispredict_mask & stq_0_bits_uop_br_mask;
wire _GEN_402 = stq_0_valid & (|_GEN_401);
wire [7:0] _GEN_403 = io_core_brupdate_b1_mispredict_mask & stq_1_bits_uop_br_mask;
wire _GEN_404 = stq_1_valid & (|_GEN_403);
wire [7:0] _GEN_405 = io_core_brupdate_b1_mispredict_mask & stq_2_bits_uop_br_mask;
wire _GEN_406 = stq_2_valid & (|_GEN_405);
wire [7:0] _GEN_407 = io_core_brupdate_b1_mispredict_mask & stq_3_bits_uop_br_mask;
wire _GEN_408 = stq_3_valid & (|_GEN_407);
wire [7:0] _GEN_409 = io_core_brupdate_b1_mispredict_mask & stq_4_bits_uop_br_mask;
wire _GEN_410 = stq_4_valid & (|_GEN_409);
wire [7:0] _GEN_411 = io_core_brupdate_b1_mispredict_mask & stq_5_bits_uop_br_mask;
wire _GEN_412 = stq_5_valid & (|_GEN_411);
wire [7:0] _GEN_413 = io_core_brupdate_b1_mispredict_mask & stq_6_bits_uop_br_mask;
wire _GEN_414 = stq_6_valid & (|_GEN_413);
wire [7:0] _GEN_415 = io_core_brupdate_b1_mispredict_mask & stq_7_bits_uop_br_mask;
wire _GEN_416 = stq_7_valid & (|_GEN_415);
wire commit_store = io_core_commit_valids_0 & io_core_commit_uops_0_uses_stq;
wire commit_load = io_core_commit_valids_0 & io_core_commit_uops_0_uses_ldq;
wire [2:0] idx = commit_store ? stq_commit_head : ldq_head;
wire _GEN_417 = ~commit_store & commit_load & ~reset;
wire _GEN_425 = _GEN_58[stq_head];
wire [7:0] _GEN_426 = {{stq_7_bits_succeeded}, {stq_6_bits_succeeded}, {stq_5_bits_succeeded}, {stq_4_bits_succeeded}, {stq_3_bits_succeeded}, {stq_2_bits_succeeded}, {stq_1_bits_succeeded}, {stq_0_bits_succeeded}};
wire _GEN_427 = _GEN_3[stq_head] & _GEN_93[stq_head];
wire _GEN_428 = _GEN_425 & ~io_dmem_ordered;
assign store_needs_order = _GEN_427 & _GEN_428;
wire clear_store = _GEN_427 & (_GEN_425 ? io_dmem_ordered : _GEN_426[stq_head]);
wire io_hellacache_req_ready_0 = hella_state == 3'h0;
assign _GEN_0 = ~io_hellacache_req_ready_0;
wire _GEN_429 = hella_state == 3'h3;
wire _GEN_430 = io_hellacache_req_ready_0 | _GEN_2;
wire _GEN_431 = hella_state == 3'h2;
wire _GEN_432 = io_dmem_resp_0_valid & io_dmem_resp_0_bits_is_hella;
assign _GEN = ~(io_hellacache_req_ready_0 | _GEN_2 | _GEN_429 | _GEN_431 | _GEN_374);
wire [2:0] _GEN_433 = _GEN_375 & _GEN_432 ? 3'h0 : hella_state;
wire [7:0] _ldq_7_bits_st_dep_mask_T = 8'h1 << stq_head;
wire [7:0] _GEN_434 = {8{~clear_store}};
wire [7:0] next_live_store_mask = (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & live_store_mask;
wire _GEN_435 = dis_ld_val & ldq_tail == 3'h0;
wire _GEN_436 = _GEN_435 | ldq_0_valid;
wire _GEN_437 = dis_ld_val & ldq_tail == 3'h1;
wire _GEN_438 = _GEN_437 | ldq_1_valid;
wire _GEN_439 = dis_ld_val & ldq_tail == 3'h2;
wire _GEN_440 = _GEN_439 | ldq_2_valid;
wire _GEN_441 = dis_ld_val & ldq_tail == 3'h3;
wire _GEN_442 = _GEN_441 | ldq_3_valid;
wire _GEN_443 = dis_ld_val & ldq_tail == 3'h4;
wire _GEN_444 = _GEN_443 | ldq_4_valid;
wire _GEN_445 = dis_ld_val & ldq_tail == 3'h5;
wire _GEN_446 = _GEN_445 | ldq_5_valid;
wire _GEN_447 = dis_ld_val & ldq_tail == 3'h6;
wire _GEN_448 = _GEN_447 | ldq_6_valid;
wire _GEN_449 = dis_ld_val & (&ldq_tail);
wire _GEN_450 = _GEN_449 | ldq_7_valid;
wire _GEN_451 = ~_GEN_435 & ldq_0_bits_order_fail;
wire _GEN_452 = ~_GEN_437 & ldq_1_bits_order_fail;
wire _GEN_453 = ~_GEN_439 & ldq_2_bits_order_fail;
wire _GEN_454 = ~_GEN_441 & ldq_3_bits_order_fail;
wire _GEN_455 = ~_GEN_443 & ldq_4_bits_order_fail;
wire _GEN_456 = ~_GEN_445 & ldq_5_bits_order_fail;
wire _GEN_457 = ~_GEN_447 & ldq_6_bits_order_fail;
wire _GEN_458 = ~_GEN_449 & ldq_7_bits_order_fail;
wire _GEN_459 = dis_st_val & stq_tail == 3'h0;
wire _GEN_460 = ~dis_ld_val & _GEN_459 | stq_0_valid;
wire _GEN_461 = dis_st_val & stq_tail == 3'h1;
wire _GEN_462 = ~dis_ld_val & _GEN_461 | stq_1_valid;
wire _GEN_463 = dis_st_val & stq_tail == 3'h2;
wire _GEN_464 = ~dis_ld_val & _GEN_463 | stq_2_valid;
wire _GEN_465 = dis_st_val & stq_tail == 3'h3;
wire _GEN_466 = ~dis_ld_val & _GEN_465 | stq_3_valid;
wire _GEN_467 = dis_st_val & stq_tail == 3'h4;
wire _GEN_468 = ~dis_ld_val & _GEN_467 | stq_4_valid;
wire _GEN_469 = dis_st_val & stq_tail == 3'h5;
wire _GEN_470 = ~dis_ld_val & _GEN_469 | stq_5_valid;
wire _GEN_471 = dis_st_val & stq_tail == 3'h6;
wire _GEN_472 = ~dis_ld_val & _GEN_471 | stq_6_valid;
wire _GEN_473 = dis_st_val & (&stq_tail);
wire _GEN_474 = ~dis_ld_val & _GEN_473 | stq_7_valid;
wire _GEN_475 = dis_ld_val | ~_GEN_459;
wire _GEN_476 = dis_ld_val | ~_GEN_461;
wire _GEN_477 = dis_ld_val | ~_GEN_463;
wire _GEN_478 = dis_ld_val | ~_GEN_465;
wire _GEN_479 = dis_ld_val | ~_GEN_467;
wire _GEN_480 = dis_ld_val | ~_GEN_469;
wire _GEN_481 = dis_ld_val | ~_GEN_471;
wire _GEN_482 = dis_ld_val | ~_GEN_473;
wire ldq_retry_idx_block = block_load_mask_0 | p1_block_load_mask_0;
wire _ldq_retry_idx_T_2 = ldq_0_bits_addr_valid & ldq_0_bits_addr_is_virtual & ~ldq_retry_idx_block;
wire ldq_retry_idx_block_1 = block_load_mask_1 | p1_block_load_mask_1;
wire _ldq_retry_idx_T_5 = ldq_1_bits_addr_valid & ldq_1_bits_addr_is_virtual & ~ldq_retry_idx_block_1;
wire ldq_retry_idx_block_2 = block_load_mask_2 | p1_block_load_mask_2;
wire _ldq_retry_idx_T_8 = ldq_2_bits_addr_valid & ldq_2_bits_addr_is_virtual & ~ldq_retry_idx_block_2;
wire ldq_retry_idx_block_3 = block_load_mask_3 | p1_block_load_mask_3;
wire _ldq_retry_idx_T_11 = ldq_3_bits_addr_valid & ldq_3_bits_addr_is_virtual & ~ldq_retry_idx_block_3;
wire ldq_retry_idx_block_4 = block_load_mask_4 | p1_block_load_mask_4;
wire _ldq_retry_idx_T_14 = ldq_4_bits_addr_valid & ldq_4_bits_addr_is_virtual & ~ldq_retry_idx_block_4;
wire ldq_retry_idx_block_5 = block_load_mask_5 | p1_block_load_mask_5;
wire _ldq_retry_idx_T_17 = ldq_5_bits_addr_valid & ldq_5_bits_addr_is_virtual & ~ldq_retry_idx_block_5;
wire ldq_retry_idx_block_6 = block_load_mask_6 | p1_block_load_mask_6;
wire _ldq_retry_idx_T_20 = ldq_6_bits_addr_valid & ldq_6_bits_addr_is_virtual & ~ldq_retry_idx_block_6;
wire ldq_retry_idx_block_7 = block_load_mask_7 | p1_block_load_mask_7;
wire _temp_bits_T = ldq_head == 3'h0;
wire _temp_bits_T_2 = ldq_head < 3'h2;
wire _temp_bits_T_4 = ldq_head < 3'h3;
wire _temp_bits_T_8 = ldq_head < 3'h5;
wire _temp_bits_T_10 = ldq_head[2:1] != 2'h3;
wire _temp_bits_T_12 = ldq_head != 3'h7;
wire _stq_retry_idx_T = stq_0_bits_addr_valid & stq_0_bits_addr_is_virtual;
wire _stq_retry_idx_T_1 = stq_1_bits_addr_valid & stq_1_bits_addr_is_virtual;
wire _stq_retry_idx_T_2 = stq_2_bits_addr_valid & stq_2_bits_addr_is_virtual;
wire _stq_retry_idx_T_3 = stq_3_bits_addr_valid & stq_3_bits_addr_is_virtual;
wire _stq_retry_idx_T_4 = stq_4_bits_addr_valid & stq_4_bits_addr_is_virtual;
wire _stq_retry_idx_T_5 = stq_5_bits_addr_valid & stq_5_bits_addr_is_virtual;
wire _stq_retry_idx_T_6 = stq_6_bits_addr_valid & stq_6_bits_addr_is_virtual;
wire _ldq_wakeup_idx_T_7 = ldq_0_bits_addr_valid & ~ldq_0_bits_executed & ~ldq_0_bits_succeeded & ~ldq_0_bits_addr_is_virtual & ~ldq_retry_idx_block;
wire _ldq_wakeup_idx_T_15 = ldq_1_bits_addr_valid & ~ldq_1_bits_executed & ~ldq_1_bits_succeeded & ~ldq_1_bits_addr_is_virtual & ~ldq_retry_idx_block_1;
wire _ldq_wakeup_idx_T_23 = ldq_2_bits_addr_valid & ~ldq_2_bits_executed & ~ldq_2_bits_succeeded & ~ldq_2_bits_addr_is_virtual & ~ldq_retry_idx_block_2;
wire _ldq_wakeup_idx_T_31 = ldq_3_bits_addr_valid & ~ldq_3_bits_executed & ~ldq_3_bits_succeeded & ~ldq_3_bits_addr_is_virtual & ~ldq_retry_idx_block_3;
wire _ldq_wakeup_idx_T_39 = ldq_4_bits_addr_valid & ~ldq_4_bits_executed & ~ldq_4_bits_succeeded & ~ldq_4_bits_addr_is_virtual & ~ldq_retry_idx_block_4;
wire _ldq_wakeup_idx_T_47 = ldq_5_bits_addr_valid & ~ldq_5_bits_executed & ~ldq_5_bits_succeeded & ~ldq_5_bits_addr_is_virtual & ~ldq_retry_idx_block_5;
wire _ldq_wakeup_idx_T_55 = ldq_6_bits_addr_valid & ~ldq_6_bits_executed & ~ldq_6_bits_succeeded & ~ldq_6_bits_addr_is_virtual & ~ldq_retry_idx_block_6;
wire ma_ld_0 = will_fire_load_incoming_0_will_fire & io_core_exe_0_req_bits_mxcpt_valid;
wire ma_st_0 = _stq_idx_T & io_core_exe_0_req_bits_mxcpt_valid;
wire pf_ld_0 = ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_pf_ld & exe_tlb_uop_0_uses_ldq;
wire pf_st_0 = ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_pf_st & exe_tlb_uop_0_uses_stq;
wire ae_ld_0 = ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_ae_ld & exe_tlb_uop_0_uses_ldq;
wire dmem_req_fire_0 = dmem_req_0_valid & io_dmem_req_ready;
wire [2:0] ldq_idx = will_fire_load_incoming_0_will_fire ? io_core_exe_0_req_bits_uop_ldq_idx : ldq_retry_idx;
wire _GEN_483 = _GEN_219 & ldq_idx == 3'h0;
wire _GEN_484 = _GEN_483 | ~_GEN_435 & ldq_0_bits_addr_valid;
wire _GEN_485 = _GEN_219 & ldq_idx == 3'h1;
wire _GEN_486 = _GEN_485 | ~_GEN_437 & ldq_1_bits_addr_valid;
wire _GEN_487 = _GEN_219 & ldq_idx == 3'h2;
wire _GEN_488 = _GEN_487 | ~_GEN_439 & ldq_2_bits_addr_valid;
wire _GEN_489 = _GEN_219 & ldq_idx == 3'h3;
wire _GEN_490 = _GEN_489 | ~_GEN_441 & ldq_3_bits_addr_valid;
wire _GEN_491 = _GEN_219 & ldq_idx == 3'h4;
wire _GEN_492 = _GEN_491 | ~_GEN_443 & ldq_4_bits_addr_valid;
wire _GEN_493 = _GEN_219 & ldq_idx == 3'h5;
wire _GEN_494 = _GEN_493 | ~_GEN_445 & ldq_5_bits_addr_valid;
wire _GEN_495 = _GEN_219 & ldq_idx == 3'h6;
wire _GEN_496 = _GEN_495 | ~_GEN_447 & ldq_6_bits_addr_valid;
wire _GEN_497 = _GEN_219 & (&ldq_idx);
wire _GEN_498 = _GEN_497 | ~_GEN_449 & ldq_7_bits_addr_valid;
wire _ldq_bits_addr_is_uncacheable_T_1 = ~_dtlb_io_resp_0_cacheable & ~exe_tlb_miss_0;
wire [2:0] stq_idx = _stq_idx_T ? io_core_exe_0_req_bits_uop_stq_idx : stq_retry_idx;
wire _GEN_499 = _GEN_221 & stq_idx == 3'h0;
wire _GEN_500 = _GEN_499 ? ~pf_st_0 : _GEN_475 & stq_0_bits_addr_valid;
wire _GEN_501 = _GEN_221 & stq_idx == 3'h1;
wire _GEN_502 = _GEN_501 ? ~pf_st_0 : _GEN_476 & stq_1_bits_addr_valid;
wire _GEN_503 = _GEN_221 & stq_idx == 3'h2;
wire _GEN_504 = _GEN_503 ? ~pf_st_0 : _GEN_477 & stq_2_bits_addr_valid;
wire _GEN_505 = _GEN_221 & stq_idx == 3'h3;
wire _GEN_506 = _GEN_505 ? ~pf_st_0 : _GEN_478 & stq_3_bits_addr_valid;
wire _GEN_507 = _GEN_221 & stq_idx == 3'h4;
wire _GEN_508 = _GEN_507 ? ~pf_st_0 : _GEN_479 & stq_4_bits_addr_valid;
wire _GEN_509 = _GEN_221 & stq_idx == 3'h5;
wire _GEN_510 = _GEN_509 ? ~pf_st_0 : _GEN_480 & stq_5_bits_addr_valid;
wire _GEN_511 = _GEN_221 & stq_idx == 3'h6;
wire _GEN_512 = _GEN_511 ? ~pf_st_0 : _GEN_481 & stq_6_bits_addr_valid;
wire _GEN_513 = _GEN_221 & (&stq_idx);
wire _GEN_514 = _GEN_513 ? ~pf_st_0 : _GEN_482 & stq_7_bits_addr_valid;
wire _GEN_515 = _GEN_222 & sidx == 3'h0;
wire _GEN_516 = _GEN_515 | _GEN_475 & stq_0_bits_data_valid;
wire _GEN_517 = _GEN_222 & sidx == 3'h1;
wire _GEN_518 = _GEN_517 | _GEN_476 & stq_1_bits_data_valid;
wire _GEN_519 = _GEN_222 & sidx == 3'h2;
wire _GEN_520 = _GEN_519 | _GEN_477 & stq_2_bits_data_valid;
wire _GEN_521 = _GEN_222 & sidx == 3'h3;
wire _GEN_522 = _GEN_521 | _GEN_478 & stq_3_bits_data_valid;
wire _GEN_523 = _GEN_222 & sidx == 3'h4;
wire _GEN_524 = _GEN_523 | _GEN_479 & stq_4_bits_data_valid;
wire _GEN_525 = _GEN_222 & sidx == 3'h5;
wire _GEN_526 = _GEN_525 | _GEN_480 & stq_5_bits_data_valid;
wire _GEN_527 = _GEN_222 & sidx == 3'h6;
wire _GEN_528 = _GEN_527 | _GEN_481 & stq_6_bits_data_valid;
wire _GEN_529 = _GEN_222 & (&sidx);
wire _GEN_530 = _GEN_529 | _GEN_482 & stq_7_bits_data_valid;
wire [63:0] _stq_bits_data_bits_T_1 = _stq_bits_data_bits_T ? io_core_exe_0_req_bits_data : io_core_fp_stdata_bits_data;
wire _fired_std_incoming_T = (io_core_brupdate_b1_mispredict_mask & io_core_exe_0_req_bits_uop_br_mask) == 8'h0;
wire [7:0] _mem_stq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask & _GEN_186;
wire [2:0] l_forward_stq_idx = l_forwarders_0 ? wb_forward_stq_idx_0 : ldq_0_bits_forward_stq_idx;
wire _GEN_531 = ~ldq_0_bits_forward_std_val | l_forward_stq_idx != lcam_stq_idx_0 & (l_forward_stq_idx < lcam_stq_idx_0 ^ l_forward_stq_idx < ldq_0_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_0_bits_youngest_stq_idx);
wire _GEN_532 = _GEN_227 & ~s1_executing_loads_0 & ldq_0_bits_observed;
wire failed_loads_0 = ~_GEN_225 & (_GEN_230 ? _GEN_531 : _GEN_231 & searcher_is_older & _GEN_532);
wire [2:0] l_forward_stq_idx_1 = l_forwarders_1_0 ? wb_forward_stq_idx_0 : ldq_1_bits_forward_stq_idx;
wire _GEN_533 = ~ldq_1_bits_forward_std_val | l_forward_stq_idx_1 != lcam_stq_idx_0 & (l_forward_stq_idx_1 < lcam_stq_idx_0 ^ l_forward_stq_idx_1 < ldq_1_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_1_bits_youngest_stq_idx);
wire _GEN_534 = _GEN_244 & ~s1_executing_loads_1 & ldq_1_bits_observed;
wire failed_loads_1 = ~_GEN_242 & (_GEN_246 ? _GEN_533 : _GEN_247 & searcher_is_older_1 & _GEN_534);
wire [2:0] l_forward_stq_idx_2 = l_forwarders_2_0 ? wb_forward_stq_idx_0 : ldq_2_bits_forward_stq_idx;
wire _GEN_535 = ~ldq_2_bits_forward_std_val | l_forward_stq_idx_2 != lcam_stq_idx_0 & (l_forward_stq_idx_2 < lcam_stq_idx_0 ^ l_forward_stq_idx_2 < ldq_2_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_2_bits_youngest_stq_idx);
wire _GEN_536 = _GEN_255 & ~s1_executing_loads_2 & ldq_2_bits_observed;
wire failed_loads_2 = ~_GEN_253 & (_GEN_257 ? _GEN_535 : _GEN_258 & searcher_is_older_2 & _GEN_536);
wire [2:0] l_forward_stq_idx_3 = l_forwarders_3_0 ? wb_forward_stq_idx_0 : ldq_3_bits_forward_stq_idx;
wire _GEN_537 = ~ldq_3_bits_forward_std_val | l_forward_stq_idx_3 != lcam_stq_idx_0 & (l_forward_stq_idx_3 < lcam_stq_idx_0 ^ l_forward_stq_idx_3 < ldq_3_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_3_bits_youngest_stq_idx);
wire _GEN_538 = _GEN_266 & ~s1_executing_loads_3 & ldq_3_bits_observed;
wire failed_loads_3 = ~_GEN_264 & (_GEN_268 ? _GEN_537 : _GEN_269 & searcher_is_older_3 & _GEN_538);
wire [2:0] l_forward_stq_idx_4 = l_forwarders_4_0 ? wb_forward_stq_idx_0 : ldq_4_bits_forward_stq_idx;
wire _GEN_539 = ~ldq_4_bits_forward_std_val | l_forward_stq_idx_4 != lcam_stq_idx_0 & (l_forward_stq_idx_4 < lcam_stq_idx_0 ^ l_forward_stq_idx_4 < ldq_4_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_4_bits_youngest_stq_idx);
wire _GEN_540 = _GEN_277 & ~s1_executing_loads_4 & ldq_4_bits_observed;
wire failed_loads_4 = ~_GEN_275 & (_GEN_279 ? _GEN_539 : _GEN_280 & searcher_is_older_4 & _GEN_540);
wire [2:0] l_forward_stq_idx_5 = l_forwarders_5_0 ? wb_forward_stq_idx_0 : ldq_5_bits_forward_stq_idx;
wire _GEN_541 = ~ldq_5_bits_forward_std_val | l_forward_stq_idx_5 != lcam_stq_idx_0 & (l_forward_stq_idx_5 < lcam_stq_idx_0 ^ l_forward_stq_idx_5 < ldq_5_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_5_bits_youngest_stq_idx);
wire _GEN_542 = _GEN_288 & ~s1_executing_loads_5 & ldq_5_bits_observed;
wire failed_loads_5 = ~_GEN_286 & (_GEN_290 ? _GEN_541 : _GEN_291 & searcher_is_older_5 & _GEN_542);
wire [2:0] l_forward_stq_idx_6 = l_forwarders_6_0 ? wb_forward_stq_idx_0 : ldq_6_bits_forward_stq_idx;
wire _GEN_543 = ~ldq_6_bits_forward_std_val | l_forward_stq_idx_6 != lcam_stq_idx_0 & (l_forward_stq_idx_6 < lcam_stq_idx_0 ^ l_forward_stq_idx_6 < ldq_6_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_6_bits_youngest_stq_idx);
wire _GEN_544 = _GEN_299 & ~s1_executing_loads_6 & ldq_6_bits_observed;
wire failed_loads_6 = ~_GEN_297 & (_GEN_301 ? _GEN_543 : _GEN_302 & searcher_is_older_6 & _GEN_544);
wire _GEN_545 = (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & (&lcam_ldq_idx_0))) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & (&lcam_ldq_idx_0))) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & (&lcam_ldq_idx_0))) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & (&lcam_ldq_idx_0))) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & (&lcam_ldq_idx_0))) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & (&lcam_ldq_idx_0))) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & (&lcam_ldq_idx_0))) & s1_executing_loads_7;
wire [2:0] l_forward_stq_idx_7 = l_forwarders_7_0 ? wb_forward_stq_idx_0 : ldq_7_bits_forward_stq_idx;
wire _GEN_546 = ~ldq_7_bits_forward_std_val | l_forward_stq_idx_7 != lcam_stq_idx_0 & (l_forward_stq_idx_7 < lcam_stq_idx_0 ^ l_forward_stq_idx_7 < ldq_7_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_7_bits_youngest_stq_idx);
wire _GEN_547 = _GEN_310 & ~s1_executing_loads_7 & ldq_7_bits_observed;
wire failed_loads_7 = ~_GEN_308 & (_GEN_312 ? _GEN_546 : _GEN_313 & searcher_is_older_7 & _GEN_547);
wire _GEN_548 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & ~(|lcam_ldq_idx_0))) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & ~(|lcam_ldq_idx_0))) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & ~(|lcam_ldq_idx_0))) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & ~(|lcam_ldq_idx_0))) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & ~(|lcam_ldq_idx_0))) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & ~(|lcam_ldq_idx_0))) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & ~(|lcam_ldq_idx_0))) & s1_executing_loads_0;
wire _GEN_549 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_234)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_234)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_234)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_234)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_234)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_234)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_234)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_234)) & s1_executing_loads_1;
wire _GEN_550 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_235)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_235)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_235)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_235)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_235)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_235)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_235)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_235)) & s1_executing_loads_2;
wire _GEN_551 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_236)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_236)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_236)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_236)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_236)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_236)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_236)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_236)) & s1_executing_loads_3;
wire _GEN_552 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_237)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_237)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_237)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_237)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_237)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_237)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_237)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_237)) & s1_executing_loads_4;
wire _GEN_553 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_238)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_238)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_238)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_238)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_238)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_238)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_238)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_238)) & s1_executing_loads_5;
wire _GEN_554 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_239)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_239)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_239)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_239)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_239)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_239)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_239)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_239)) & s1_executing_loads_6;
wire _GEN_555 = _GEN_321 | _GEN_322;
wire _GEN_556 = _GEN_319 ? (_GEN_555 ? (|lcam_ldq_idx_0) & _GEN_548 : ~(_GEN_323 & ~(|lcam_ldq_idx_0)) & _GEN_548) : _GEN_548;
wire _GEN_557 = _GEN_319 ? (_GEN_555 ? ~_GEN_234 & _GEN_549 : ~(_GEN_323 & _GEN_234) & _GEN_549) : _GEN_549;
wire _GEN_558 = _GEN_319 ? (_GEN_555 ? ~_GEN_235 & _GEN_550 : ~(_GEN_323 & _GEN_235) & _GEN_550) : _GEN_550;
wire _GEN_559 = _GEN_319 ? (_GEN_555 ? ~_GEN_236 & _GEN_551 : ~(_GEN_323 & _GEN_236) & _GEN_551) : _GEN_551;
wire _GEN_560 = _GEN_319 ? (_GEN_555 ? ~_GEN_237 & _GEN_552 : ~(_GEN_323 & _GEN_237) & _GEN_552) : _GEN_552;
wire _GEN_561 = _GEN_319 ? (_GEN_555 ? ~_GEN_238 & _GEN_553 : ~(_GEN_323 & _GEN_238) & _GEN_553) : _GEN_553;
wire _GEN_562 = _GEN_319 ? (_GEN_555 ? ~_GEN_239 & _GEN_554 : ~(_GEN_323 & _GEN_239) & _GEN_554) : _GEN_554;
wire _GEN_563 = _GEN_319 ? (_GEN_555 ? ~(&lcam_ldq_idx_0) & _GEN_545 : ~(_GEN_323 & (&lcam_ldq_idx_0)) & _GEN_545) : _GEN_545;
wire _GEN_564 = _GEN_328 | _GEN_329;
wire _GEN_565 = _GEN_326 ? (_GEN_564 ? (|lcam_ldq_idx_0) & _GEN_556 : ~(_GEN_330 & ~(|lcam_ldq_idx_0)) & _GEN_556) : _GEN_556;
wire _GEN_566 = _GEN_326 ? (_GEN_564 ? ~_GEN_234 & _GEN_557 : ~(_GEN_330 & _GEN_234) & _GEN_557) : _GEN_557;
wire _GEN_567 = _GEN_326 ? (_GEN_564 ? ~_GEN_235 & _GEN_558 : ~(_GEN_330 & _GEN_235) & _GEN_558) : _GEN_558;
wire _GEN_568 = _GEN_326 ? (_GEN_564 ? ~_GEN_236 & _GEN_559 : ~(_GEN_330 & _GEN_236) & _GEN_559) : _GEN_559;
wire _GEN_569 = _GEN_326 ? (_GEN_564 ? ~_GEN_237 & _GEN_560 : ~(_GEN_330 & _GEN_237) & _GEN_560) : _GEN_560;
wire _GEN_570 = _GEN_326 ? (_GEN_564 ? ~_GEN_238 & _GEN_561 : ~(_GEN_330 & _GEN_238) & _GEN_561) : _GEN_561;
wire _GEN_571 = _GEN_326 ? (_GEN_564 ? ~_GEN_239 & _GEN_562 : ~(_GEN_330 & _GEN_239) & _GEN_562) : _GEN_562;
wire _GEN_572 = _GEN_326 ? (_GEN_564 ? ~(&lcam_ldq_idx_0) & _GEN_563 : ~(_GEN_330 & (&lcam_ldq_idx_0)) & _GEN_563) : _GEN_563;
wire _GEN_573 = _GEN_335 | _GEN_336;
wire _GEN_574 = _GEN_333 ? (_GEN_573 ? (|lcam_ldq_idx_0) & _GEN_565 : ~(_GEN_337 & ~(|lcam_ldq_idx_0)) & _GEN_565) : _GEN_565;
wire _GEN_575 = _GEN_333 ? (_GEN_573 ? ~_GEN_234 & _GEN_566 : ~(_GEN_337 & _GEN_234) & _GEN_566) : _GEN_566;
wire _GEN_576 = _GEN_333 ? (_GEN_573 ? ~_GEN_235 & _GEN_567 : ~(_GEN_337 & _GEN_235) & _GEN_567) : _GEN_567;
wire _GEN_577 = _GEN_333 ? (_GEN_573 ? ~_GEN_236 & _GEN_568 : ~(_GEN_337 & _GEN_236) & _GEN_568) : _GEN_568;
wire _GEN_578 = _GEN_333 ? (_GEN_573 ? ~_GEN_237 & _GEN_569 : ~(_GEN_337 & _GEN_237) & _GEN_569) : _GEN_569;
wire _GEN_579 = _GEN_333 ? (_GEN_573 ? ~_GEN_238 & _GEN_570 : ~(_GEN_337 & _GEN_238) & _GEN_570) : _GEN_570;
wire _GEN_580 = _GEN_333 ? (_GEN_573 ? ~_GEN_239 & _GEN_571 : ~(_GEN_337 & _GEN_239) & _GEN_571) : _GEN_571;
wire _GEN_581 = _GEN_333 ? (_GEN_573 ? ~(&lcam_ldq_idx_0) & _GEN_572 : ~(_GEN_337 & (&lcam_ldq_idx_0)) & _GEN_572) : _GEN_572;
wire _GEN_582 = _GEN_342 | _GEN_343;
wire _GEN_583 = _GEN_340 ? (_GEN_582 ? (|lcam_ldq_idx_0) & _GEN_574 : ~(_GEN_344 & ~(|lcam_ldq_idx_0)) & _GEN_574) : _GEN_574;
wire _GEN_584 = _GEN_340 ? (_GEN_582 ? ~_GEN_234 & _GEN_575 : ~(_GEN_344 & _GEN_234) & _GEN_575) : _GEN_575;
wire _GEN_585 = _GEN_340 ? (_GEN_582 ? ~_GEN_235 & _GEN_576 : ~(_GEN_344 & _GEN_235) & _GEN_576) : _GEN_576;
wire _GEN_586 = _GEN_340 ? (_GEN_582 ? ~_GEN_236 & _GEN_577 : ~(_GEN_344 & _GEN_236) & _GEN_577) : _GEN_577;
wire _GEN_587 = _GEN_340 ? (_GEN_582 ? ~_GEN_237 & _GEN_578 : ~(_GEN_344 & _GEN_237) & _GEN_578) : _GEN_578;
wire _GEN_588 = _GEN_340 ? (_GEN_582 ? ~_GEN_238 & _GEN_579 : ~(_GEN_344 & _GEN_238) & _GEN_579) : _GEN_579;
wire _GEN_589 = _GEN_340 ? (_GEN_582 ? ~_GEN_239 & _GEN_580 : ~(_GEN_344 & _GEN_239) & _GEN_580) : _GEN_580;
wire _GEN_590 = _GEN_340 ? (_GEN_582 ? ~(&lcam_ldq_idx_0) & _GEN_581 : ~(_GEN_344 & (&lcam_ldq_idx_0)) & _GEN_581) : _GEN_581;
wire _GEN_591 = _GEN_349 | _GEN_350;
wire _GEN_592 = _GEN_347 ? (_GEN_591 ? (|lcam_ldq_idx_0) & _GEN_583 : ~(_GEN_351 & ~(|lcam_ldq_idx_0)) & _GEN_583) : _GEN_583;
wire _GEN_593 = _GEN_347 ? (_GEN_591 ? ~_GEN_234 & _GEN_584 : ~(_GEN_351 & _GEN_234) & _GEN_584) : _GEN_584;
wire _GEN_594 = _GEN_347 ? (_GEN_591 ? ~_GEN_235 & _GEN_585 : ~(_GEN_351 & _GEN_235) & _GEN_585) : _GEN_585;
wire _GEN_595 = _GEN_347 ? (_GEN_591 ? ~_GEN_236 & _GEN_586 : ~(_GEN_351 & _GEN_236) & _GEN_586) : _GEN_586;
wire _GEN_596 = _GEN_347 ? (_GEN_591 ? ~_GEN_237 & _GEN_587 : ~(_GEN_351 & _GEN_237) & _GEN_587) : _GEN_587;
wire _GEN_597 = _GEN_347 ? (_GEN_591 ? ~_GEN_238 & _GEN_588 : ~(_GEN_351 & _GEN_238) & _GEN_588) : _GEN_588;
wire _GEN_598 = _GEN_347 ? (_GEN_591 ? ~_GEN_239 & _GEN_589 : ~(_GEN_351 & _GEN_239) & _GEN_589) : _GEN_589;
wire _GEN_599 = _GEN_347 ? (_GEN_591 ? ~(&lcam_ldq_idx_0) & _GEN_590 : ~(_GEN_351 & (&lcam_ldq_idx_0)) & _GEN_590) : _GEN_590;
wire _GEN_600 = _GEN_356 | _GEN_357;
wire _GEN_601 = _GEN_354 ? (_GEN_600 ? (|lcam_ldq_idx_0) & _GEN_592 : ~(_GEN_358 & ~(|lcam_ldq_idx_0)) & _GEN_592) : _GEN_592;
wire _GEN_602 = _GEN_354 ? (_GEN_600 ? ~_GEN_234 & _GEN_593 : ~(_GEN_358 & _GEN_234) & _GEN_593) : _GEN_593;
wire _GEN_603 = _GEN_354 ? (_GEN_600 ? ~_GEN_235 & _GEN_594 : ~(_GEN_358 & _GEN_235) & _GEN_594) : _GEN_594;
wire _GEN_604 = _GEN_354 ? (_GEN_600 ? ~_GEN_236 & _GEN_595 : ~(_GEN_358 & _GEN_236) & _GEN_595) : _GEN_595;
wire _GEN_605 = _GEN_354 ? (_GEN_600 ? ~_GEN_237 & _GEN_596 : ~(_GEN_358 & _GEN_237) & _GEN_596) : _GEN_596;
wire _GEN_606 = _GEN_354 ? (_GEN_600 ? ~_GEN_238 & _GEN_597 : ~(_GEN_358 & _GEN_238) & _GEN_597) : _GEN_597;
wire _GEN_607 = _GEN_354 ? (_GEN_600 ? ~_GEN_239 & _GEN_598 : ~(_GEN_358 & _GEN_239) & _GEN_598) : _GEN_598;
wire _GEN_608 = _GEN_354 ? (_GEN_600 ? ~(&lcam_ldq_idx_0) & _GEN_599 : ~(_GEN_358 & (&lcam_ldq_idx_0)) & _GEN_599) : _GEN_599;
wire _GEN_609 = _GEN_363 | _GEN_364;
wire _GEN_610 = _GEN_361 ? (_GEN_609 ? (|lcam_ldq_idx_0) & _GEN_601 : ~(_GEN_365 & ~(|lcam_ldq_idx_0)) & _GEN_601) : _GEN_601;
wire _GEN_611 = _GEN_361 ? (_GEN_609 ? ~_GEN_234 & _GEN_602 : ~(_GEN_365 & _GEN_234) & _GEN_602) : _GEN_602;
wire _GEN_612 = _GEN_361 ? (_GEN_609 ? ~_GEN_235 & _GEN_603 : ~(_GEN_365 & _GEN_235) & _GEN_603) : _GEN_603;
wire _GEN_613 = _GEN_361 ? (_GEN_609 ? ~_GEN_236 & _GEN_604 : ~(_GEN_365 & _GEN_236) & _GEN_604) : _GEN_604;
wire _GEN_614 = _GEN_361 ? (_GEN_609 ? ~_GEN_237 & _GEN_605 : ~(_GEN_365 & _GEN_237) & _GEN_605) : _GEN_605;
wire _GEN_615 = _GEN_361 ? (_GEN_609 ? ~_GEN_238 & _GEN_606 : ~(_GEN_365 & _GEN_238) & _GEN_606) : _GEN_606;
wire _GEN_616 = _GEN_361 ? (_GEN_609 ? ~_GEN_239 & _GEN_607 : ~(_GEN_365 & _GEN_239) & _GEN_607) : _GEN_607;
wire _GEN_617 = _GEN_361 ? (_GEN_609 ? ~(&lcam_ldq_idx_0) & _GEN_608 : ~(_GEN_365 & (&lcam_ldq_idx_0)) & _GEN_608) : _GEN_608;
wire _GEN_618 = _GEN_370 | _GEN_371;
wire [7:0] _GEN_619 = {{_GEN_368 & _GEN_370}, {_GEN_361 & _GEN_363}, {_GEN_354 & _GEN_356}, {_GEN_347 & _GEN_349}, {_GEN_340 & _GEN_342}, {_GEN_333 & _GEN_335}, {_GEN_326 & _GEN_328}, {_GEN_319 & _GEN_321}};
wire mem_forward_valid_0 = _GEN_619[_forwarding_age_logic_0_io_forwarding_idx] & (io_core_brupdate_b1_mispredict_mask & (do_st_search_0 ? (_lcam_stq_idx_T ? mem_stq_incoming_e_0_bits_uop_br_mask : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_br_mask : 8'h0) : do_ld_search_0 ? (fired_load_incoming_REG ? mem_ldq_incoming_e_0_bits_uop_br_mask : fired_load_retry_REG ? mem_ldq_retry_e_bits_uop_br_mask : fired_load_wakeup_REG ? mem_ldq_wakeup_e_bits_uop_br_mask : 8'h0) : 8'h0)) == 8'h0 & ~io_core_exception & ~REG_1;
wire [2:0] l_idx = failed_loads_0 & _temp_bits_T ? 3'h0 : failed_loads_1 & _temp_bits_T_2 ? 3'h1 : failed_loads_2 & _temp_bits_T_4 ? 3'h2 : failed_loads_3 & ~(ldq_head[2]) ? 3'h3 : failed_loads_4 & _temp_bits_T_8 ? 3'h4 : failed_loads_5 & _temp_bits_T_10 ? 3'h5 : failed_loads_6 & _temp_bits_T_12 ? 3'h6 : failed_loads_7 ? 3'h7 : failed_loads_0 ? 3'h0 : failed_loads_1 ? 3'h1 : failed_loads_2 ? 3'h2 : failed_loads_3 ? 3'h3 : failed_loads_4 ? 3'h4 : failed_loads_5 ? 3'h5 : {2'h3, ~failed_loads_6};
wire ld_xcpt_valid = failed_loads_0 | failed_loads_1 | failed_loads_2 | failed_loads_3 | failed_loads_4 | failed_loads_5 | failed_loads_6 | failed_loads_7;
wire use_mem_xcpt = mem_xcpt_valids_0 & (mem_xcpt_uops_0_rob_idx < _GEN_135[l_idx] ^ mem_xcpt_uops_0_rob_idx < io_core_rob_head_idx ^ _GEN_135[l_idx] < io_core_rob_head_idx) | ~ld_xcpt_valid;
wire [7:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uops_0_br_mask : _GEN_97[l_idx];
wire _ldq_bits_succeeded_T = io_core_exe_0_iresp_valid_0 | io_core_exe_0_fresp_valid_0;
wire _GEN_620 = _GEN_396 & live;
wire _GEN_621 = _GEN_388 & _GEN_620 & ~(|wb_forward_ldq_idx_0);
wire _GEN_622 = _GEN_387 | ~_GEN_621;
wire _GEN_623 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h1;
wire _GEN_624 = _GEN_387 | ~_GEN_623;
wire _GEN_625 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h2;
wire _GEN_626 = _GEN_387 | ~_GEN_625;
wire _GEN_627 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h3;
wire _GEN_628 = _GEN_387 | ~_GEN_627;
wire _GEN_629 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h4;
wire _GEN_630 = _GEN_387 | ~_GEN_629;
wire _GEN_631 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h5;
wire _GEN_632 = _GEN_387 | ~_GEN_631;
wire _GEN_633 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h6;
wire _GEN_634 = _GEN_387 | ~_GEN_633;
wire _GEN_635 = _GEN_388 & _GEN_620 & (&wb_forward_ldq_idx_0);
wire _GEN_636 = _GEN_387 | ~_GEN_635;
wire _GEN_637 = ldq_0_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_0_bits_uop_br_mask));
wire _GEN_638 = ldq_1_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_1_bits_uop_br_mask));
wire _GEN_639 = ldq_2_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_2_bits_uop_br_mask));
wire _GEN_640 = ldq_3_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_3_bits_uop_br_mask));
wire _GEN_641 = ldq_4_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_4_bits_uop_br_mask));
wire _GEN_642 = ldq_5_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_5_bits_uop_br_mask));
wire _GEN_643 = ldq_6_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_6_bits_uop_br_mask));
wire _GEN_644 = ldq_7_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_7_bits_uop_br_mask));
wire _GEN_645 = idx == 3'h0;
wire _GEN_646 = idx == 3'h1;
wire _GEN_647 = idx == 3'h2;
wire _GEN_648 = idx == 3'h3;
wire _GEN_649 = idx == 3'h4;
wire _GEN_650 = idx == 3'h5;
wire _GEN_651 = idx == 3'h6;
wire _GEN_652 = _GEN_645 | _GEN_637;
wire _GEN_653 = commit_store | ~commit_load;
wire _GEN_654 = _GEN_646 | _GEN_638;
wire _GEN_655 = _GEN_647 | _GEN_639;
wire _GEN_656 = _GEN_648 | _GEN_640;
wire _GEN_657 = _GEN_649 | _GEN_641;
wire _GEN_658 = _GEN_650 | _GEN_642;
wire _GEN_659 = _GEN_651 | _GEN_643;
wire _GEN_660 = (&idx) | _GEN_644;
wire _GEN_661 = commit_store | ~(commit_load & _GEN_645);
wire _GEN_662 = commit_store | ~(commit_load & _GEN_646);
wire _GEN_663 = commit_store | ~(commit_load & _GEN_647);
wire _GEN_664 = commit_store | ~(commit_load & _GEN_648);
wire _GEN_665 = commit_store | ~(commit_load & _GEN_649);
wire _GEN_666 = commit_store | ~(commit_load & _GEN_650);
wire _GEN_667 = commit_store | ~(commit_load & _GEN_651);
wire _GEN_668 = commit_store | ~(commit_load & (&idx));
wire _GEN_669 = stq_head == 3'h0;
wire _GEN_670 = _GEN_669 | _GEN_402;
wire _GEN_671 = stq_head == 3'h1;
wire _GEN_672 = _GEN_671 | _GEN_404;
wire _GEN_673 = stq_head == 3'h2;
wire _GEN_674 = _GEN_673 | _GEN_406;
wire _GEN_675 = stq_head == 3'h3;
wire _GEN_676 = _GEN_675 | _GEN_408;
wire _GEN_677 = stq_head == 3'h4;
wire _GEN_678 = _GEN_677 | _GEN_410;
wire _GEN_679 = stq_head == 3'h5;
wire _GEN_680 = _GEN_679 | _GEN_412;
wire _GEN_681 = stq_head == 3'h6;
wire _GEN_682 = _GEN_681 | _GEN_414;
wire _GEN_683 = (&stq_head) | _GEN_416;
wire _GEN_684 = clear_store & _GEN_669;
wire _GEN_685 = clear_store & _GEN_671;
wire _GEN_686 = clear_store & _GEN_673;
wire _GEN_687 = clear_store & _GEN_675;
wire _GEN_688 = clear_store & _GEN_677;
wire _GEN_689 = clear_store & _GEN_679;
wire _GEN_690 = clear_store & _GEN_681;
wire _GEN_691 = clear_store & (&stq_head);
wire _GEN_692 = io_hellacache_req_ready_0 & io_hellacache_req_valid;
wire _GEN_693 = io_hellacache_req_ready_0 | ~_GEN_2;
wire _GEN_694 = reset | io_core_exception;
wire _GEN_695 = _GEN_694 & reset;
wire _GEN_696 = ~stq_0_bits_committed & ~stq_0_bits_succeeded;
wire _GEN_697 = _GEN_694 & (reset | _GEN_696);
wire _GEN_698 = ~stq_1_bits_committed & ~stq_1_bits_succeeded;
wire _GEN_699 = _GEN_694 & (reset | _GEN_698);
wire _GEN_700 = ~stq_2_bits_committed & ~stq_2_bits_succeeded;
wire _GEN_701 = _GEN_694 & (reset | _GEN_700);
wire _GEN_702 = ~stq_3_bits_committed & ~stq_3_bits_succeeded;
wire _GEN_703 = _GEN_694 & (reset | _GEN_702);
wire _GEN_704 = ~stq_4_bits_committed & ~stq_4_bits_succeeded;
wire _GEN_705 = _GEN_694 & (reset | _GEN_704);
wire _GEN_706 = ~stq_5_bits_committed & ~stq_5_bits_succeeded;
wire _GEN_707 = _GEN_694 & (reset | _GEN_706);
wire _GEN_708 = ~stq_6_bits_committed & ~stq_6_bits_succeeded;
wire _GEN_709 = _GEN_694 & (reset | _GEN_708);
wire _GEN_710 = ~stq_7_bits_committed & ~stq_7_bits_succeeded;
wire _GEN_711 = _GEN_694 & (reset | _GEN_710);
wire _GEN_712 = will_fire_hella_incoming_0_will_fire & dmem_req_fire_0;
wire [7:0][2:0] _GEN_713 = {{_GEN_433}, {_GEN_433}, {will_fire_hella_wakeup_0_will_fire & dmem_req_fire_0 ? 3'h4 : hella_state}, {_GEN_432 ? 3'h0 : _GEN_373 ? 3'h5 : hella_state}, {3'h0}, {{1'h1, |{hella_xcpt_ma_ld, hella_xcpt_ma_st, hella_xcpt_pf_ld, hella_xcpt_pf_st, hella_xcpt_gf_ld, hella_xcpt_gf_st, hella_xcpt_ae_ld, hella_xcpt_ae_st}, 1'h0}}, {io_hellacache_s1_kill ? (_GEN_712 ? 3'h6 : 3'h0) : {2'h1, ~_GEN_712}}, {_GEN_692 ? 3'h1 : hella_state}};
always @(posedge clock) begin
if (_GEN_377)
assert__assert_23: assert(_GEN_101[io_dmem_nack_0_bits_uop_ldq_idx]);
if (_GEN_417)
assert__assert_36: assert(_GEN_96[idx]);
ldq_0_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_637 & _GEN_436 : ~_GEN_652 & _GEN_436);
if (_GEN_435) begin
ldq_0_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
ldq_0_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
ldq_0_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
ldq_0_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;
ldq_0_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
ldq_0_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
ldq_0_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
ldq_0_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
ldq_0_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
ldq_0_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
ldq_0_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
ldq_0_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
ldq_0_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;
ldq_0_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
ldq_0_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;
ldq_0_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;
ldq_0_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;
ldq_0_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
ldq_0_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;
ldq_0_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;
ldq_0_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;
ldq_0_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;
ldq_0_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;
ldq_0_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;
ldq_0_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
ldq_0_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
ldq_0_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;
ldq_0_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
ldq_0_bits_uop_taken <= io_core_dis_uops_0_bits_taken;
ldq_0_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
ldq_0_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
ldq_0_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
ldq_0_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
ldq_0_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
ldq_0_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
ldq_0_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
ldq_0_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
ldq_0_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
ldq_0_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;
ldq_0_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;
ldq_0_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;
ldq_0_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
ldq_0_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
ldq_0_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;
ldq_0_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
ldq_0_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
ldq_0_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;
ldq_0_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;
ldq_0_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;
ldq_0_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;
ldq_0_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;
ldq_0_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;
ldq_0_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;
ldq_0_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;
ldq_0_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;
ldq_0_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;
ldq_0_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
ldq_0_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
ldq_0_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
ldq_0_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
ldq_0_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;
ldq_0_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
ldq_0_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
ldq_0_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
ldq_0_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;
ldq_0_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;
ldq_0_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;
ldq_0_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;
ldq_0_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;
ldq_0_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;
ldq_0_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;
ldq_0_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;
ldq_0_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
ldq_0_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
ldq_0_bits_youngest_stq_idx <= stq_tail;
end
if (ldq_0_valid)
ldq_0_bits_uop_br_mask <= ldq_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_435)
ldq_0_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_483) begin
if (_exe_tlb_uop_T_2)
ldq_0_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
ldq_0_bits_uop_pdst <= _GEN_139;
else
ldq_0_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
ldq_0_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
ldq_0_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
ldq_0_bits_addr_bits <= _GEN_180;
else
ldq_0_bits_addr_bits <= _exe_tlb_vaddr_T_3;
end
else
ldq_0_bits_addr_bits <= _GEN_217;
ldq_0_bits_addr_is_virtual <= exe_tlb_miss_0;
ldq_0_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;
end
else if (_GEN_435)
ldq_0_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
ldq_0_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h0 | (_GEN_435 ? io_core_dis_uops_0_bits_exception : ldq_0_bits_uop_exception);
ldq_0_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_637 & _GEN_484 : ~_GEN_652 & _GEN_484);
ldq_0_bits_executed <= ~_GEN_694 & _GEN_661 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_378)) & ((_GEN_368 ? (_GEN_618 ? (|lcam_ldq_idx_0) & _GEN_610 : ~(_GEN_372 & ~(|lcam_ldq_idx_0)) & _GEN_610) : _GEN_610) | ~_GEN_435 & ldq_0_bits_executed);
ldq_0_bits_succeeded <= _GEN_661 & (_GEN_622 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h0 ? _ldq_bits_succeeded_T : ~_GEN_435 & ldq_0_bits_succeeded) : _GEN_396);
ldq_0_bits_order_fail <= _GEN_661 & (_GEN_225 ? _GEN_451 : _GEN_230 ? _GEN_531 | _GEN_451 : _GEN_231 & searcher_is_older & _GEN_532 | _GEN_451);
ldq_0_bits_observed <= _GEN_225 | ~_GEN_435 & ldq_0_bits_observed;
ldq_0_bits_st_dep_mask <= _GEN_435 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_0_bits_st_dep_mask;
ldq_0_bits_forward_std_val <= _GEN_661 & (~_GEN_387 & _GEN_621 | ~_GEN_435 & ldq_0_bits_forward_std_val);
if (_GEN_622) begin
end
else
ldq_0_bits_forward_stq_idx <= wb_forward_stq_idx_0;
ldq_1_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_638 & _GEN_438 : ~_GEN_654 & _GEN_438);
if (_GEN_437) begin
ldq_1_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
ldq_1_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
ldq_1_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
ldq_1_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;
ldq_1_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
ldq_1_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
ldq_1_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
ldq_1_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
ldq_1_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
ldq_1_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
ldq_1_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
ldq_1_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
ldq_1_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;
ldq_1_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
ldq_1_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;
ldq_1_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;
ldq_1_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;
ldq_1_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
ldq_1_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;
ldq_1_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;
ldq_1_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;
ldq_1_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;
ldq_1_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;
ldq_1_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;
ldq_1_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
ldq_1_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
ldq_1_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;
ldq_1_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
ldq_1_bits_uop_taken <= io_core_dis_uops_0_bits_taken;
ldq_1_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
ldq_1_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
ldq_1_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
ldq_1_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
ldq_1_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
ldq_1_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
ldq_1_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
ldq_1_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
ldq_1_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
ldq_1_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;
ldq_1_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;
ldq_1_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;
ldq_1_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
ldq_1_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
ldq_1_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;
ldq_1_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
ldq_1_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
ldq_1_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;
ldq_1_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;
ldq_1_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;
ldq_1_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;
ldq_1_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;
ldq_1_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;
ldq_1_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;
ldq_1_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;
ldq_1_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;
ldq_1_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;
ldq_1_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
ldq_1_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
ldq_1_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
ldq_1_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
ldq_1_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;
ldq_1_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
ldq_1_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
ldq_1_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
ldq_1_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;
ldq_1_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;
ldq_1_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;
ldq_1_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;
ldq_1_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;
ldq_1_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;
ldq_1_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;
ldq_1_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;
ldq_1_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
ldq_1_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
ldq_1_bits_youngest_stq_idx <= stq_tail;
end
if (ldq_1_valid)
ldq_1_bits_uop_br_mask <= ldq_1_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_437)
ldq_1_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_485) begin
if (_exe_tlb_uop_T_2)
ldq_1_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
ldq_1_bits_uop_pdst <= _GEN_139;
else
ldq_1_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
ldq_1_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
ldq_1_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
ldq_1_bits_addr_bits <= _GEN_180;
else
ldq_1_bits_addr_bits <= _exe_tlb_vaddr_T_3;
end
else
ldq_1_bits_addr_bits <= _GEN_217;
ldq_1_bits_addr_is_virtual <= exe_tlb_miss_0;
ldq_1_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;
end
else if (_GEN_437)
ldq_1_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
ldq_1_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h1 | (_GEN_437 ? io_core_dis_uops_0_bits_exception : ldq_1_bits_uop_exception);
ldq_1_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_638 & _GEN_486 : ~_GEN_654 & _GEN_486);
ldq_1_bits_executed <= ~_GEN_694 & _GEN_662 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_379)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_234 & _GEN_611 : ~(_GEN_372 & _GEN_234) & _GEN_611) : _GEN_611) | ~_GEN_437 & ldq_1_bits_executed);
ldq_1_bits_succeeded <= _GEN_662 & (_GEN_624 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h1 ? _ldq_bits_succeeded_T : ~_GEN_437 & ldq_1_bits_succeeded) : _GEN_396);
ldq_1_bits_order_fail <= _GEN_662 & (_GEN_242 ? _GEN_452 : _GEN_246 ? _GEN_533 | _GEN_452 : _GEN_247 & searcher_is_older_1 & _GEN_534 | _GEN_452);
ldq_1_bits_observed <= _GEN_242 | ~_GEN_437 & ldq_1_bits_observed;
ldq_1_bits_st_dep_mask <= _GEN_437 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_1_bits_st_dep_mask;
ldq_1_bits_forward_std_val <= _GEN_662 & (~_GEN_387 & _GEN_623 | ~_GEN_437 & ldq_1_bits_forward_std_val);
if (_GEN_624) begin
end
else
ldq_1_bits_forward_stq_idx <= wb_forward_stq_idx_0;
ldq_2_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_639 & _GEN_440 : ~_GEN_655 & _GEN_440);
if (_GEN_439) begin
ldq_2_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
ldq_2_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
ldq_2_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
ldq_2_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;
ldq_2_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
ldq_2_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
ldq_2_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
ldq_2_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
ldq_2_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
ldq_2_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
ldq_2_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
ldq_2_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
ldq_2_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;
ldq_2_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
ldq_2_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;
ldq_2_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;
ldq_2_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;
ldq_2_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
ldq_2_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;
ldq_2_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;
ldq_2_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;
ldq_2_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;
ldq_2_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;
ldq_2_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;
ldq_2_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
ldq_2_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
ldq_2_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;
ldq_2_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
ldq_2_bits_uop_taken <= io_core_dis_uops_0_bits_taken;
ldq_2_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
ldq_2_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
ldq_2_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
ldq_2_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
ldq_2_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
ldq_2_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
ldq_2_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
ldq_2_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
ldq_2_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
ldq_2_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;
ldq_2_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;
ldq_2_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;
ldq_2_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
ldq_2_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
ldq_2_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;
ldq_2_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
ldq_2_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
ldq_2_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;
ldq_2_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;
ldq_2_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;
ldq_2_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;
ldq_2_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;
ldq_2_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;
ldq_2_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;
ldq_2_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;
ldq_2_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;
ldq_2_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;
ldq_2_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
ldq_2_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
ldq_2_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
ldq_2_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
ldq_2_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;
ldq_2_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
ldq_2_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
ldq_2_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
ldq_2_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;
ldq_2_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;
ldq_2_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;
ldq_2_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;
ldq_2_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;
ldq_2_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;
ldq_2_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;
ldq_2_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;
ldq_2_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
ldq_2_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
ldq_2_bits_youngest_stq_idx <= stq_tail;
end
if (ldq_2_valid)
ldq_2_bits_uop_br_mask <= ldq_2_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_439)
ldq_2_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_487) begin
if (_exe_tlb_uop_T_2)
ldq_2_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
ldq_2_bits_uop_pdst <= _GEN_139;
else
ldq_2_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
ldq_2_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
ldq_2_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
ldq_2_bits_addr_bits <= _GEN_180;
else
ldq_2_bits_addr_bits <= _exe_tlb_vaddr_T_3;
end
else
ldq_2_bits_addr_bits <= _GEN_217;
ldq_2_bits_addr_is_virtual <= exe_tlb_miss_0;
ldq_2_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;
end
else if (_GEN_439)
ldq_2_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
ldq_2_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h2 | (_GEN_439 ? io_core_dis_uops_0_bits_exception : ldq_2_bits_uop_exception);
ldq_2_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_639 & _GEN_488 : ~_GEN_655 & _GEN_488);
ldq_2_bits_executed <= ~_GEN_694 & _GEN_663 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_380)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_235 & _GEN_612 : ~(_GEN_372 & _GEN_235) & _GEN_612) : _GEN_612) | ~_GEN_439 & ldq_2_bits_executed);
ldq_2_bits_succeeded <= _GEN_663 & (_GEN_626 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h2 ? _ldq_bits_succeeded_T : ~_GEN_439 & ldq_2_bits_succeeded) : _GEN_396);
ldq_2_bits_order_fail <= _GEN_663 & (_GEN_253 ? _GEN_453 : _GEN_257 ? _GEN_535 | _GEN_453 : _GEN_258 & searcher_is_older_2 & _GEN_536 | _GEN_453);
ldq_2_bits_observed <= _GEN_253 | ~_GEN_439 & ldq_2_bits_observed;
ldq_2_bits_st_dep_mask <= _GEN_439 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_2_bits_st_dep_mask;
ldq_2_bits_forward_std_val <= _GEN_663 & (~_GEN_387 & _GEN_625 | ~_GEN_439 & ldq_2_bits_forward_std_val);
if (_GEN_626) begin
end
else
ldq_2_bits_forward_stq_idx <= wb_forward_stq_idx_0;
ldq_3_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_640 & _GEN_442 : ~_GEN_656 & _GEN_442);
if (_GEN_441) begin
ldq_3_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
ldq_3_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
ldq_3_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
ldq_3_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;
ldq_3_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
ldq_3_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
ldq_3_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
ldq_3_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
ldq_3_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
ldq_3_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
ldq_3_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
ldq_3_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
ldq_3_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;
ldq_3_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
ldq_3_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;
ldq_3_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;
ldq_3_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;
ldq_3_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
ldq_3_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;
ldq_3_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;
ldq_3_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;
ldq_3_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;
ldq_3_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;
ldq_3_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;
ldq_3_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
ldq_3_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
ldq_3_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;
ldq_3_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
ldq_3_bits_uop_taken <= io_core_dis_uops_0_bits_taken;
ldq_3_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
ldq_3_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
ldq_3_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
ldq_3_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
ldq_3_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
ldq_3_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
ldq_3_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
ldq_3_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
ldq_3_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
ldq_3_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;
ldq_3_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;
ldq_3_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;
ldq_3_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
ldq_3_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
ldq_3_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;
ldq_3_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
ldq_3_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
ldq_3_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;
ldq_3_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;
ldq_3_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;
ldq_3_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;
ldq_3_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;
ldq_3_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;
ldq_3_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;
ldq_3_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;
ldq_3_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;
ldq_3_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;
ldq_3_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
ldq_3_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
ldq_3_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
ldq_3_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
ldq_3_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;
ldq_3_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
ldq_3_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
ldq_3_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
ldq_3_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;
ldq_3_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;
ldq_3_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;
ldq_3_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;
ldq_3_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;
ldq_3_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;
ldq_3_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;
ldq_3_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;
ldq_3_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
ldq_3_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
ldq_3_bits_youngest_stq_idx <= stq_tail;
end
if (ldq_3_valid)
ldq_3_bits_uop_br_mask <= ldq_3_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_441)
ldq_3_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_489) begin
if (_exe_tlb_uop_T_2)
ldq_3_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
ldq_3_bits_uop_pdst <= _GEN_139;
else
ldq_3_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
ldq_3_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
ldq_3_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
ldq_3_bits_addr_bits <= _GEN_180;
else
ldq_3_bits_addr_bits <= _exe_tlb_vaddr_T_3;
end
else
ldq_3_bits_addr_bits <= _GEN_217;
ldq_3_bits_addr_is_virtual <= exe_tlb_miss_0;
ldq_3_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;
end
else if (_GEN_441)
ldq_3_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
ldq_3_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h3 | (_GEN_441 ? io_core_dis_uops_0_bits_exception : ldq_3_bits_uop_exception);
ldq_3_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_640 & _GEN_490 : ~_GEN_656 & _GEN_490);
ldq_3_bits_executed <= ~_GEN_694 & _GEN_664 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_381)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_236 & _GEN_613 : ~(_GEN_372 & _GEN_236) & _GEN_613) : _GEN_613) | ~_GEN_441 & ldq_3_bits_executed);
ldq_3_bits_succeeded <= _GEN_664 & (_GEN_628 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h3 ? _ldq_bits_succeeded_T : ~_GEN_441 & ldq_3_bits_succeeded) : _GEN_396);
ldq_3_bits_order_fail <= _GEN_664 & (_GEN_264 ? _GEN_454 : _GEN_268 ? _GEN_537 | _GEN_454 : _GEN_269 & searcher_is_older_3 & _GEN_538 | _GEN_454);
ldq_3_bits_observed <= _GEN_264 | ~_GEN_441 & ldq_3_bits_observed;
ldq_3_bits_st_dep_mask <= _GEN_441 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_3_bits_st_dep_mask;
ldq_3_bits_forward_std_val <= _GEN_664 & (~_GEN_387 & _GEN_627 | ~_GEN_441 & ldq_3_bits_forward_std_val);
if (_GEN_628) begin
end
else
ldq_3_bits_forward_stq_idx <= wb_forward_stq_idx_0;
ldq_4_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_641 & _GEN_444 : ~_GEN_657 & _GEN_444);
if (_GEN_443) begin
ldq_4_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
ldq_4_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
ldq_4_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
ldq_4_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;
ldq_4_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
ldq_4_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
ldq_4_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
ldq_4_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
ldq_4_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
ldq_4_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
ldq_4_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
ldq_4_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
ldq_4_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;
ldq_4_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
ldq_4_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;
ldq_4_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;
ldq_4_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;
ldq_4_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
ldq_4_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;
ldq_4_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;
ldq_4_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;
ldq_4_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;
ldq_4_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;
ldq_4_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;
ldq_4_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
ldq_4_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
ldq_4_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;
ldq_4_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
ldq_4_bits_uop_taken <= io_core_dis_uops_0_bits_taken;
ldq_4_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
ldq_4_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
ldq_4_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
ldq_4_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
ldq_4_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
ldq_4_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
ldq_4_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
ldq_4_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
ldq_4_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
ldq_4_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;
ldq_4_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;
ldq_4_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;
ldq_4_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
ldq_4_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
ldq_4_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;
ldq_4_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
ldq_4_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
ldq_4_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;
ldq_4_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;
ldq_4_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;
ldq_4_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;
ldq_4_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;
ldq_4_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;
ldq_4_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;
ldq_4_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;
ldq_4_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;
ldq_4_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;
ldq_4_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
ldq_4_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
ldq_4_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
ldq_4_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
ldq_4_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;
ldq_4_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
ldq_4_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
ldq_4_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
ldq_4_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;
ldq_4_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;
ldq_4_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;
ldq_4_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;
ldq_4_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;
ldq_4_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;
ldq_4_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;
ldq_4_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;
ldq_4_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
ldq_4_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
ldq_4_bits_youngest_stq_idx <= stq_tail;
end
if (ldq_4_valid)
ldq_4_bits_uop_br_mask <= ldq_4_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_443)
ldq_4_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_491) begin
if (_exe_tlb_uop_T_2)
ldq_4_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
ldq_4_bits_uop_pdst <= _GEN_139;
else
ldq_4_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
ldq_4_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
ldq_4_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
ldq_4_bits_addr_bits <= _GEN_180;
else
ldq_4_bits_addr_bits <= _exe_tlb_vaddr_T_3;
end
else
ldq_4_bits_addr_bits <= _GEN_217;
ldq_4_bits_addr_is_virtual <= exe_tlb_miss_0;
ldq_4_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;
end
else if (_GEN_443)
ldq_4_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
ldq_4_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h4 | (_GEN_443 ? io_core_dis_uops_0_bits_exception : ldq_4_bits_uop_exception);
ldq_4_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_641 & _GEN_492 : ~_GEN_657 & _GEN_492);
ldq_4_bits_executed <= ~_GEN_694 & _GEN_665 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_382)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_237 & _GEN_614 : ~(_GEN_372 & _GEN_237) & _GEN_614) : _GEN_614) | ~_GEN_443 & ldq_4_bits_executed);
ldq_4_bits_succeeded <= _GEN_665 & (_GEN_630 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h4 ? _ldq_bits_succeeded_T : ~_GEN_443 & ldq_4_bits_succeeded) : _GEN_396);
ldq_4_bits_order_fail <= _GEN_665 & (_GEN_275 ? _GEN_455 : _GEN_279 ? _GEN_539 | _GEN_455 : _GEN_280 & searcher_is_older_4 & _GEN_540 | _GEN_455);
ldq_4_bits_observed <= _GEN_275 | ~_GEN_443 & ldq_4_bits_observed;
ldq_4_bits_st_dep_mask <= _GEN_443 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_4_bits_st_dep_mask;
ldq_4_bits_forward_std_val <= _GEN_665 & (~_GEN_387 & _GEN_629 | ~_GEN_443 & ldq_4_bits_forward_std_val);
if (_GEN_630) begin
end
else
ldq_4_bits_forward_stq_idx <= wb_forward_stq_idx_0;
ldq_5_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_642 & _GEN_446 : ~_GEN_658 & _GEN_446);
if (_GEN_445) begin
ldq_5_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
ldq_5_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
ldq_5_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
ldq_5_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;
ldq_5_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
ldq_5_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
ldq_5_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
ldq_5_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
ldq_5_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
ldq_5_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
ldq_5_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
ldq_5_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
ldq_5_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;
ldq_5_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
ldq_5_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;
ldq_5_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;
ldq_5_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;
ldq_5_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
ldq_5_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;
ldq_5_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;
ldq_5_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;
ldq_5_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;
ldq_5_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;
ldq_5_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;
ldq_5_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
ldq_5_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
ldq_5_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;
ldq_5_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
ldq_5_bits_uop_taken <= io_core_dis_uops_0_bits_taken;
ldq_5_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
ldq_5_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
ldq_5_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
ldq_5_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
ldq_5_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
ldq_5_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
ldq_5_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
ldq_5_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
ldq_5_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
ldq_5_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;
ldq_5_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;
ldq_5_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;
ldq_5_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
ldq_5_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
ldq_5_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;
ldq_5_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
ldq_5_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
ldq_5_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;
ldq_5_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;
ldq_5_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;
ldq_5_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;
ldq_5_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;
ldq_5_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;
ldq_5_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;
ldq_5_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;
ldq_5_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;
ldq_5_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;
ldq_5_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
ldq_5_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
ldq_5_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
ldq_5_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
ldq_5_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;
ldq_5_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
ldq_5_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
ldq_5_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
ldq_5_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;
ldq_5_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;
ldq_5_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;
ldq_5_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;
ldq_5_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;
ldq_5_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;
ldq_5_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;
ldq_5_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;
ldq_5_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
ldq_5_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
ldq_5_bits_youngest_stq_idx <= stq_tail;
end
if (ldq_5_valid)
ldq_5_bits_uop_br_mask <= ldq_5_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_445)
ldq_5_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_493) begin
if (_exe_tlb_uop_T_2)
ldq_5_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
ldq_5_bits_uop_pdst <= _GEN_139;
else
ldq_5_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
ldq_5_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
ldq_5_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
ldq_5_bits_addr_bits <= _GEN_180;
else
ldq_5_bits_addr_bits <= _exe_tlb_vaddr_T_3;
end
else
ldq_5_bits_addr_bits <= _GEN_217;
ldq_5_bits_addr_is_virtual <= exe_tlb_miss_0;
ldq_5_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;
end
else if (_GEN_445)
ldq_5_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
ldq_5_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h5 | (_GEN_445 ? io_core_dis_uops_0_bits_exception : ldq_5_bits_uop_exception);
ldq_5_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_642 & _GEN_494 : ~_GEN_658 & _GEN_494);
ldq_5_bits_executed <= ~_GEN_694 & _GEN_666 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_383)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_238 & _GEN_615 : ~(_GEN_372 & _GEN_238) & _GEN_615) : _GEN_615) | ~_GEN_445 & ldq_5_bits_executed);
ldq_5_bits_succeeded <= _GEN_666 & (_GEN_632 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h5 ? _ldq_bits_succeeded_T : ~_GEN_445 & ldq_5_bits_succeeded) : _GEN_396);
ldq_5_bits_order_fail <= _GEN_666 & (_GEN_286 ? _GEN_456 : _GEN_290 ? _GEN_541 | _GEN_456 : _GEN_291 & searcher_is_older_5 & _GEN_542 | _GEN_456);
ldq_5_bits_observed <= _GEN_286 | ~_GEN_445 & ldq_5_bits_observed;
ldq_5_bits_st_dep_mask <= _GEN_445 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_5_bits_st_dep_mask;
ldq_5_bits_forward_std_val <= _GEN_666 & (~_GEN_387 & _GEN_631 | ~_GEN_445 & ldq_5_bits_forward_std_val);
if (_GEN_632) begin
end
else
ldq_5_bits_forward_stq_idx <= wb_forward_stq_idx_0;
ldq_6_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_643 & _GEN_448 : ~_GEN_659 & _GEN_448);
if (_GEN_447) begin
ldq_6_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
ldq_6_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
ldq_6_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
ldq_6_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;
ldq_6_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
ldq_6_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
ldq_6_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
ldq_6_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
ldq_6_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
ldq_6_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
ldq_6_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
ldq_6_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
ldq_6_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;
ldq_6_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
ldq_6_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;
ldq_6_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;
ldq_6_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;
ldq_6_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
ldq_6_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;
ldq_6_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;
ldq_6_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;
ldq_6_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;
ldq_6_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;
ldq_6_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;
ldq_6_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
ldq_6_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
ldq_6_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;
ldq_6_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
ldq_6_bits_uop_taken <= io_core_dis_uops_0_bits_taken;
ldq_6_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
ldq_6_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
ldq_6_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
ldq_6_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
ldq_6_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
ldq_6_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
ldq_6_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
ldq_6_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
ldq_6_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
ldq_6_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;
ldq_6_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;
ldq_6_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;
ldq_6_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
ldq_6_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
ldq_6_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;
ldq_6_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
ldq_6_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
ldq_6_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;
ldq_6_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;
ldq_6_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;
ldq_6_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;
ldq_6_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;
ldq_6_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;
ldq_6_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;
ldq_6_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;
ldq_6_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;
ldq_6_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;
ldq_6_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
ldq_6_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
ldq_6_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
ldq_6_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
ldq_6_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;
ldq_6_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
ldq_6_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
ldq_6_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
ldq_6_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;
ldq_6_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;
ldq_6_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;
ldq_6_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;
ldq_6_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;
ldq_6_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;
ldq_6_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;
ldq_6_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;
ldq_6_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
ldq_6_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
ldq_6_bits_youngest_stq_idx <= stq_tail;
end
if (ldq_6_valid)
ldq_6_bits_uop_br_mask <= ldq_6_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_447)
ldq_6_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_495) begin
if (_exe_tlb_uop_T_2)
ldq_6_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
ldq_6_bits_uop_pdst <= _GEN_139;
else
ldq_6_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
ldq_6_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
ldq_6_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
ldq_6_bits_addr_bits <= _GEN_180;
else
ldq_6_bits_addr_bits <= _exe_tlb_vaddr_T_3;
end
else
ldq_6_bits_addr_bits <= _GEN_217;
ldq_6_bits_addr_is_virtual <= exe_tlb_miss_0;
ldq_6_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;
end
else if (_GEN_447)
ldq_6_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
ldq_6_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h6 | (_GEN_447 ? io_core_dis_uops_0_bits_exception : ldq_6_bits_uop_exception);
ldq_6_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_643 & _GEN_496 : ~_GEN_659 & _GEN_496);
ldq_6_bits_executed <= ~_GEN_694 & _GEN_667 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_384)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_239 & _GEN_616 : ~(_GEN_372 & _GEN_239) & _GEN_616) : _GEN_616) | ~_GEN_447 & ldq_6_bits_executed);
ldq_6_bits_succeeded <= _GEN_667 & (_GEN_634 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h6 ? _ldq_bits_succeeded_T : ~_GEN_447 & ldq_6_bits_succeeded) : _GEN_396);
ldq_6_bits_order_fail <= _GEN_667 & (_GEN_297 ? _GEN_457 : _GEN_301 ? _GEN_543 | _GEN_457 : _GEN_302 & searcher_is_older_6 & _GEN_544 | _GEN_457);
ldq_6_bits_observed <= _GEN_297 | ~_GEN_447 & ldq_6_bits_observed;
ldq_6_bits_st_dep_mask <= _GEN_447 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_6_bits_st_dep_mask;
ldq_6_bits_forward_std_val <= _GEN_667 & (~_GEN_387 & _GEN_633 | ~_GEN_447 & ldq_6_bits_forward_std_val);
if (_GEN_634) begin
end
else
ldq_6_bits_forward_stq_idx <= wb_forward_stq_idx_0;
ldq_7_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_644 & _GEN_450 : ~_GEN_660 & _GEN_450);
if (_GEN_449) begin
ldq_7_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
ldq_7_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
ldq_7_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
ldq_7_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;
ldq_7_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
ldq_7_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
ldq_7_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
ldq_7_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
ldq_7_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
ldq_7_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
ldq_7_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
ldq_7_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
ldq_7_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;
ldq_7_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
ldq_7_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;
ldq_7_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;
ldq_7_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;
ldq_7_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
ldq_7_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;
ldq_7_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;
ldq_7_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;
ldq_7_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;
ldq_7_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;
ldq_7_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;
ldq_7_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
ldq_7_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
ldq_7_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;
ldq_7_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
ldq_7_bits_uop_taken <= io_core_dis_uops_0_bits_taken;
ldq_7_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
ldq_7_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
ldq_7_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
ldq_7_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
ldq_7_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
ldq_7_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
ldq_7_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
ldq_7_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
ldq_7_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
ldq_7_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;
ldq_7_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;
ldq_7_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;
ldq_7_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
ldq_7_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
ldq_7_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;
ldq_7_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
ldq_7_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
ldq_7_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;
ldq_7_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;
ldq_7_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;
ldq_7_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;
ldq_7_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;
ldq_7_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;
ldq_7_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;
ldq_7_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;
ldq_7_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;
ldq_7_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;
ldq_7_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
ldq_7_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
ldq_7_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
ldq_7_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
ldq_7_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;
ldq_7_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
ldq_7_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
ldq_7_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
ldq_7_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;
ldq_7_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;
ldq_7_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;
ldq_7_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;
ldq_7_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;
ldq_7_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;
ldq_7_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;
ldq_7_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;
ldq_7_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
ldq_7_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
ldq_7_bits_youngest_stq_idx <= stq_tail;
end
if (ldq_7_valid)
ldq_7_bits_uop_br_mask <= ldq_7_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_449)
ldq_7_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_497) begin
if (_exe_tlb_uop_T_2)
ldq_7_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
ldq_7_bits_uop_pdst <= _GEN_139;
else
ldq_7_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
ldq_7_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
ldq_7_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
ldq_7_bits_addr_bits <= _GEN_180;
else
ldq_7_bits_addr_bits <= _exe_tlb_vaddr_T_3;
end
else
ldq_7_bits_addr_bits <= _GEN_217;
ldq_7_bits_addr_is_virtual <= exe_tlb_miss_0;
ldq_7_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;
end
else if (_GEN_449)
ldq_7_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
ldq_7_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & (&mem_xcpt_uops_0_ldq_idx) | (_GEN_449 ? io_core_dis_uops_0_bits_exception : ldq_7_bits_uop_exception);
ldq_7_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_644 & _GEN_498 : ~_GEN_660 & _GEN_498);
ldq_7_bits_executed <= ~_GEN_694 & _GEN_668 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & (&io_dmem_nack_0_bits_uop_ldq_idx))) & ((_GEN_368 ? (_GEN_618 ? ~(&lcam_ldq_idx_0) & _GEN_617 : ~(_GEN_372 & (&lcam_ldq_idx_0)) & _GEN_617) : _GEN_617) | ~_GEN_449 & ldq_7_bits_executed);
ldq_7_bits_succeeded <= _GEN_668 & (_GEN_636 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & (&io_dmem_resp_0_bits_uop_ldq_idx) ? _ldq_bits_succeeded_T : ~_GEN_449 & ldq_7_bits_succeeded) : _GEN_396);
ldq_7_bits_order_fail <= _GEN_668 & (_GEN_308 ? _GEN_458 : _GEN_312 ? _GEN_546 | _GEN_458 : _GEN_313 & searcher_is_older_7 & _GEN_547 | _GEN_458);
ldq_7_bits_observed <= _GEN_308 | ~_GEN_449 & ldq_7_bits_observed;
ldq_7_bits_st_dep_mask <= _GEN_449 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_7_bits_st_dep_mask;
ldq_7_bits_forward_std_val <= _GEN_668 & (~_GEN_387 & _GEN_635 | ~_GEN_449 & ldq_7_bits_forward_std_val);
if (_GEN_636) begin
end
else
ldq_7_bits_forward_stq_idx <= wb_forward_stq_idx_0;
stq_0_valid <= ~_GEN_697 & (clear_store ? ~_GEN_670 & _GEN_460 : ~_GEN_402 & _GEN_460);
if (_GEN_695) begin
stq_0_bits_uop_uopc <= 7'h0;
stq_0_bits_uop_inst <= 32'h0;
stq_0_bits_uop_debug_inst <= 32'h0;
stq_0_bits_uop_debug_pc <= 40'h0;
stq_0_bits_uop_iq_type <= 3'h0;
stq_0_bits_uop_fu_code <= 10'h0;
stq_0_bits_uop_ctrl_br_type <= 4'h0;
stq_0_bits_uop_ctrl_op1_sel <= 2'h0;
stq_0_bits_uop_ctrl_op2_sel <= 3'h0;
stq_0_bits_uop_ctrl_imm_sel <= 3'h0;
stq_0_bits_uop_ctrl_op_fcn <= 5'h0;
stq_0_bits_uop_ctrl_csr_cmd <= 3'h0;
stq_0_bits_uop_iw_state <= 2'h0;
stq_0_bits_uop_br_mask <= 8'h0;
stq_0_bits_uop_br_tag <= 3'h0;
stq_0_bits_uop_ftq_idx <= 4'h0;
stq_0_bits_uop_pc_lob <= 6'h0;
stq_0_bits_uop_imm_packed <= 20'h0;
stq_0_bits_uop_csr_addr <= 12'h0;
stq_0_bits_uop_rob_idx <= 5'h0;
stq_0_bits_uop_ldq_idx <= 3'h0;
stq_0_bits_uop_stq_idx <= 3'h0;
stq_0_bits_uop_rxq_idx <= 2'h0;
stq_0_bits_uop_pdst <= 6'h0;
stq_0_bits_uop_prs1 <= 6'h0;
stq_0_bits_uop_prs2 <= 6'h0;
stq_0_bits_uop_prs3 <= 6'h0;
stq_0_bits_uop_stale_pdst <= 6'h0;
stq_0_bits_uop_exc_cause <= 64'h0;
stq_0_bits_uop_mem_cmd <= 5'h0;
stq_0_bits_uop_mem_size <= 2'h0;
stq_0_bits_uop_ldst <= 6'h0;
stq_0_bits_uop_lrs1 <= 6'h0;
stq_0_bits_uop_lrs2 <= 6'h0;
stq_0_bits_uop_lrs3 <= 6'h0;
stq_0_bits_uop_dst_rtype <= 2'h2;
stq_0_bits_uop_lrs1_rtype <= 2'h0;
stq_0_bits_uop_lrs2_rtype <= 2'h0;
stq_0_bits_uop_debug_fsrc <= 2'h0;
stq_0_bits_uop_debug_tsrc <= 2'h0;
stq_1_bits_uop_uopc <= 7'h0;
stq_1_bits_uop_inst <= 32'h0;
stq_1_bits_uop_debug_inst <= 32'h0;
stq_1_bits_uop_debug_pc <= 40'h0;
stq_1_bits_uop_iq_type <= 3'h0;
stq_1_bits_uop_fu_code <= 10'h0;
stq_1_bits_uop_ctrl_br_type <= 4'h0;
stq_1_bits_uop_ctrl_op1_sel <= 2'h0;
stq_1_bits_uop_ctrl_op2_sel <= 3'h0;
stq_1_bits_uop_ctrl_imm_sel <= 3'h0;
stq_1_bits_uop_ctrl_op_fcn <= 5'h0;
stq_1_bits_uop_ctrl_csr_cmd <= 3'h0;
stq_1_bits_uop_iw_state <= 2'h0;
stq_1_bits_uop_br_mask <= 8'h0;
stq_1_bits_uop_br_tag <= 3'h0;
stq_1_bits_uop_ftq_idx <= 4'h0;
stq_1_bits_uop_pc_lob <= 6'h0;
stq_1_bits_uop_imm_packed <= 20'h0;
stq_1_bits_uop_csr_addr <= 12'h0;
stq_1_bits_uop_rob_idx <= 5'h0;
stq_1_bits_uop_ldq_idx <= 3'h0;
stq_1_bits_uop_stq_idx <= 3'h0;
stq_1_bits_uop_rxq_idx <= 2'h0;
stq_1_bits_uop_pdst <= 6'h0;
stq_1_bits_uop_prs1 <= 6'h0;
stq_1_bits_uop_prs2 <= 6'h0;
stq_1_bits_uop_prs3 <= 6'h0;
stq_1_bits_uop_stale_pdst <= 6'h0;
stq_1_bits_uop_exc_cause <= 64'h0;
stq_1_bits_uop_mem_cmd <= 5'h0;
stq_1_bits_uop_mem_size <= 2'h0;
stq_1_bits_uop_ldst <= 6'h0;
stq_1_bits_uop_lrs1 <= 6'h0;
stq_1_bits_uop_lrs2 <= 6'h0;
stq_1_bits_uop_lrs3 <= 6'h0;
stq_1_bits_uop_dst_rtype <= 2'h2;
stq_1_bits_uop_lrs1_rtype <= 2'h0;
stq_1_bits_uop_lrs2_rtype <= 2'h0;
stq_1_bits_uop_debug_fsrc <= 2'h0;
stq_1_bits_uop_debug_tsrc <= 2'h0;
stq_2_bits_uop_uopc <= 7'h0;
stq_2_bits_uop_inst <= 32'h0;
stq_2_bits_uop_debug_inst <= 32'h0;
stq_2_bits_uop_debug_pc <= 40'h0;
stq_2_bits_uop_iq_type <= 3'h0;
stq_2_bits_uop_fu_code <= 10'h0;
stq_2_bits_uop_ctrl_br_type <= 4'h0;
stq_2_bits_uop_ctrl_op1_sel <= 2'h0;
stq_2_bits_uop_ctrl_op2_sel <= 3'h0;
stq_2_bits_uop_ctrl_imm_sel <= 3'h0;
stq_2_bits_uop_ctrl_op_fcn <= 5'h0;
stq_2_bits_uop_ctrl_csr_cmd <= 3'h0;
stq_2_bits_uop_iw_state <= 2'h0;
stq_2_bits_uop_br_mask <= 8'h0;
stq_2_bits_uop_br_tag <= 3'h0;
stq_2_bits_uop_ftq_idx <= 4'h0;
stq_2_bits_uop_pc_lob <= 6'h0;
stq_2_bits_uop_imm_packed <= 20'h0;
stq_2_bits_uop_csr_addr <= 12'h0;
stq_2_bits_uop_rob_idx <= 5'h0;
stq_2_bits_uop_ldq_idx <= 3'h0;
stq_2_bits_uop_stq_idx <= 3'h0;
stq_2_bits_uop_rxq_idx <= 2'h0;
stq_2_bits_uop_pdst <= 6'h0;
stq_2_bits_uop_prs1 <= 6'h0;
stq_2_bits_uop_prs2 <= 6'h0;
stq_2_bits_uop_prs3 <= 6'h0;
stq_2_bits_uop_stale_pdst <= 6'h0;
stq_2_bits_uop_exc_cause <= 64'h0;
stq_2_bits_uop_mem_cmd <= 5'h0;
stq_2_bits_uop_mem_size <= 2'h0;
stq_2_bits_uop_ldst <= 6'h0;
stq_2_bits_uop_lrs1 <= 6'h0;
stq_2_bits_uop_lrs2 <= 6'h0;
stq_2_bits_uop_lrs3 <= 6'h0;
stq_2_bits_uop_dst_rtype <= 2'h2;
stq_2_bits_uop_lrs1_rtype <= 2'h0;
stq_2_bits_uop_lrs2_rtype <= 2'h0;
stq_2_bits_uop_debug_fsrc <= 2'h0;
stq_2_bits_uop_debug_tsrc <= 2'h0;
stq_3_bits_uop_uopc <= 7'h0;
stq_3_bits_uop_inst <= 32'h0;
stq_3_bits_uop_debug_inst <= 32'h0;
stq_3_bits_uop_debug_pc <= 40'h0;
stq_3_bits_uop_iq_type <= 3'h0;
stq_3_bits_uop_fu_code <= 10'h0;
stq_3_bits_uop_ctrl_br_type <= 4'h0;
stq_3_bits_uop_ctrl_op1_sel <= 2'h0;
stq_3_bits_uop_ctrl_op2_sel <= 3'h0;
stq_3_bits_uop_ctrl_imm_sel <= 3'h0;
stq_3_bits_uop_ctrl_op_fcn <= 5'h0;
stq_3_bits_uop_ctrl_csr_cmd <= 3'h0;
stq_3_bits_uop_iw_state <= 2'h0;
stq_3_bits_uop_br_mask <= 8'h0;
stq_3_bits_uop_br_tag <= 3'h0;
stq_3_bits_uop_ftq_idx <= 4'h0;
stq_3_bits_uop_pc_lob <= 6'h0;
stq_3_bits_uop_imm_packed <= 20'h0;
stq_3_bits_uop_csr_addr <= 12'h0;
stq_3_bits_uop_rob_idx <= 5'h0;
stq_3_bits_uop_ldq_idx <= 3'h0;
stq_3_bits_uop_stq_idx <= 3'h0;
stq_3_bits_uop_rxq_idx <= 2'h0;
stq_3_bits_uop_pdst <= 6'h0;
stq_3_bits_uop_prs1 <= 6'h0;
stq_3_bits_uop_prs2 <= 6'h0;
stq_3_bits_uop_prs3 <= 6'h0;
stq_3_bits_uop_stale_pdst <= 6'h0;
stq_3_bits_uop_exc_cause <= 64'h0;
stq_3_bits_uop_mem_cmd <= 5'h0;
stq_3_bits_uop_mem_size <= 2'h0;
stq_3_bits_uop_ldst <= 6'h0;
stq_3_bits_uop_lrs1 <= 6'h0;
stq_3_bits_uop_lrs2 <= 6'h0;
stq_3_bits_uop_lrs3 <= 6'h0;
stq_3_bits_uop_dst_rtype <= 2'h2;
stq_3_bits_uop_lrs1_rtype <= 2'h0;
stq_3_bits_uop_lrs2_rtype <= 2'h0;
stq_3_bits_uop_debug_fsrc <= 2'h0;
stq_3_bits_uop_debug_tsrc <= 2'h0;
stq_4_bits_uop_uopc <= 7'h0;
stq_4_bits_uop_inst <= 32'h0;
stq_4_bits_uop_debug_inst <= 32'h0;
stq_4_bits_uop_debug_pc <= 40'h0;
stq_4_bits_uop_iq_type <= 3'h0;
stq_4_bits_uop_fu_code <= 10'h0;
stq_4_bits_uop_ctrl_br_type <= 4'h0;
stq_4_bits_uop_ctrl_op1_sel <= 2'h0;
stq_4_bits_uop_ctrl_op2_sel <= 3'h0;
stq_4_bits_uop_ctrl_imm_sel <= 3'h0;
stq_4_bits_uop_ctrl_op_fcn <= 5'h0;
stq_4_bits_uop_ctrl_csr_cmd <= 3'h0;
stq_4_bits_uop_iw_state <= 2'h0;
stq_4_bits_uop_br_mask <= 8'h0;
stq_4_bits_uop_br_tag <= 3'h0;
stq_4_bits_uop_ftq_idx <= 4'h0;
stq_4_bits_uop_pc_lob <= 6'h0;
stq_4_bits_uop_imm_packed <= 20'h0;
stq_4_bits_uop_csr_addr <= 12'h0;
stq_4_bits_uop_rob_idx <= 5'h0;
stq_4_bits_uop_ldq_idx <= 3'h0;
stq_4_bits_uop_stq_idx <= 3'h0;
stq_4_bits_uop_rxq_idx <= 2'h0;
stq_4_bits_uop_pdst <= 6'h0;
stq_4_bits_uop_prs1 <= 6'h0;
stq_4_bits_uop_prs2 <= 6'h0;
stq_4_bits_uop_prs3 <= 6'h0;
stq_4_bits_uop_stale_pdst <= 6'h0;
stq_4_bits_uop_exc_cause <= 64'h0;
stq_4_bits_uop_mem_cmd <= 5'h0;
stq_4_bits_uop_mem_size <= 2'h0;
stq_4_bits_uop_ldst <= 6'h0;
stq_4_bits_uop_lrs1 <= 6'h0;
stq_4_bits_uop_lrs2 <= 6'h0;
stq_4_bits_uop_lrs3 <= 6'h0;
stq_4_bits_uop_dst_rtype <= 2'h2;
stq_4_bits_uop_lrs1_rtype <= 2'h0;
stq_4_bits_uop_lrs2_rtype <= 2'h0;
stq_4_bits_uop_debug_fsrc <= 2'h0;
stq_4_bits_uop_debug_tsrc <= 2'h0;
stq_5_bits_uop_uopc <= 7'h0;
stq_5_bits_uop_inst <= 32'h0;
stq_5_bits_uop_debug_inst <= 32'h0;
stq_5_bits_uop_debug_pc <= 40'h0;
stq_5_bits_uop_iq_type <= 3'h0;
stq_5_bits_uop_fu_code <= 10'h0;
stq_5_bits_uop_ctrl_br_type <= 4'h0;
stq_5_bits_uop_ctrl_op1_sel <= 2'h0;
stq_5_bits_uop_ctrl_op2_sel <= 3'h0;
stq_5_bits_uop_ctrl_imm_sel <= 3'h0;
stq_5_bits_uop_ctrl_op_fcn <= 5'h0;
stq_5_bits_uop_ctrl_csr_cmd <= 3'h0;
stq_5_bits_uop_iw_state <= 2'h0;
stq_5_bits_uop_br_mask <= 8'h0;
stq_5_bits_uop_br_tag <= 3'h0;
stq_5_bits_uop_ftq_idx <= 4'h0;
stq_5_bits_uop_pc_lob <= 6'h0;
stq_5_bits_uop_imm_packed <= 20'h0;
stq_5_bits_uop_csr_addr <= 12'h0;
stq_5_bits_uop_rob_idx <= 5'h0;
stq_5_bits_uop_ldq_idx <= 3'h0;
stq_5_bits_uop_stq_idx <= 3'h0;
stq_5_bits_uop_rxq_idx <= 2'h0;
stq_5_bits_uop_pdst <= 6'h0;
stq_5_bits_uop_prs1 <= 6'h0;
stq_5_bits_uop_prs2 <= 6'h0;
stq_5_bits_uop_prs3 <= 6'h0;
stq_5_bits_uop_stale_pdst <= 6'h0;
stq_5_bits_uop_exc_cause <= 64'h0;
stq_5_bits_uop_mem_cmd <= 5'h0;
stq_5_bits_uop_mem_size <= 2'h0;
stq_5_bits_uop_ldst <= 6'h0;
stq_5_bits_uop_lrs1 <= 6'h0;
stq_5_bits_uop_lrs2 <= 6'h0;
stq_5_bits_uop_lrs3 <= 6'h0;
stq_5_bits_uop_dst_rtype <= 2'h2;
stq_5_bits_uop_lrs1_rtype <= 2'h0;
stq_5_bits_uop_lrs2_rtype <= 2'h0;
stq_5_bits_uop_debug_fsrc <= 2'h0;
stq_5_bits_uop_debug_tsrc <= 2'h0;
stq_6_bits_uop_uopc <= 7'h0;
stq_6_bits_uop_inst <= 32'h0;
stq_6_bits_uop_debug_inst <= 32'h0;
stq_6_bits_uop_debug_pc <= 40'h0;
stq_6_bits_uop_iq_type <= 3'h0;
stq_6_bits_uop_fu_code <= 10'h0;
stq_6_bits_uop_ctrl_br_type <= 4'h0;
stq_6_bits_uop_ctrl_op1_sel <= 2'h0;
stq_6_bits_uop_ctrl_op2_sel <= 3'h0;
stq_6_bits_uop_ctrl_imm_sel <= 3'h0;
stq_6_bits_uop_ctrl_op_fcn <= 5'h0;
stq_6_bits_uop_ctrl_csr_cmd <= 3'h0;
stq_6_bits_uop_iw_state <= 2'h0;
stq_6_bits_uop_br_mask <= 8'h0;
stq_6_bits_uop_br_tag <= 3'h0;
stq_6_bits_uop_ftq_idx <= 4'h0;
stq_6_bits_uop_pc_lob <= 6'h0;
stq_6_bits_uop_imm_packed <= 20'h0;
stq_6_bits_uop_csr_addr <= 12'h0;
stq_6_bits_uop_rob_idx <= 5'h0;
stq_6_bits_uop_ldq_idx <= 3'h0;
stq_6_bits_uop_stq_idx <= 3'h0;
stq_6_bits_uop_rxq_idx <= 2'h0;
stq_6_bits_uop_pdst <= 6'h0;
stq_6_bits_uop_prs1 <= 6'h0;
stq_6_bits_uop_prs2 <= 6'h0;
stq_6_bits_uop_prs3 <= 6'h0;
stq_6_bits_uop_stale_pdst <= 6'h0;
stq_6_bits_uop_exc_cause <= 64'h0;
stq_6_bits_uop_mem_cmd <= 5'h0;
stq_6_bits_uop_mem_size <= 2'h0;
stq_6_bits_uop_ldst <= 6'h0;
stq_6_bits_uop_lrs1 <= 6'h0;
stq_6_bits_uop_lrs2 <= 6'h0;
stq_6_bits_uop_lrs3 <= 6'h0;
stq_6_bits_uop_dst_rtype <= 2'h2;
stq_6_bits_uop_lrs1_rtype <= 2'h0;
stq_6_bits_uop_lrs2_rtype <= 2'h0;
stq_6_bits_uop_debug_fsrc <= 2'h0;
stq_6_bits_uop_debug_tsrc <= 2'h0;
stq_7_bits_uop_uopc <= 7'h0;
stq_7_bits_uop_inst <= 32'h0;
stq_7_bits_uop_debug_inst <= 32'h0;
stq_7_bits_uop_debug_pc <= 40'h0;
stq_7_bits_uop_iq_type <= 3'h0;
stq_7_bits_uop_fu_code <= 10'h0;
stq_7_bits_uop_ctrl_br_type <= 4'h0;
stq_7_bits_uop_ctrl_op1_sel <= 2'h0;
stq_7_bits_uop_ctrl_op2_sel <= 3'h0;
stq_7_bits_uop_ctrl_imm_sel <= 3'h0;
stq_7_bits_uop_ctrl_op_fcn <= 5'h0;
stq_7_bits_uop_ctrl_csr_cmd <= 3'h0;
stq_7_bits_uop_iw_state <= 2'h0;
stq_7_bits_uop_br_mask <= 8'h0;
stq_7_bits_uop_br_tag <= 3'h0;
stq_7_bits_uop_ftq_idx <= 4'h0;
stq_7_bits_uop_pc_lob <= 6'h0;
stq_7_bits_uop_imm_packed <= 20'h0;
stq_7_bits_uop_csr_addr <= 12'h0;
stq_7_bits_uop_rob_idx <= 5'h0;
stq_7_bits_uop_ldq_idx <= 3'h0;
stq_7_bits_uop_stq_idx <= 3'h0;
stq_7_bits_uop_rxq_idx <= 2'h0;
stq_7_bits_uop_pdst <= 6'h0;
stq_7_bits_uop_prs1 <= 6'h0;
stq_7_bits_uop_prs2 <= 6'h0;
stq_7_bits_uop_prs3 <= 6'h0;
stq_7_bits_uop_stale_pdst <= 6'h0;
stq_7_bits_uop_exc_cause <= 64'h0;
stq_7_bits_uop_mem_cmd <= 5'h0;
stq_7_bits_uop_mem_size <= 2'h0;
stq_7_bits_uop_ldst <= 6'h0;
stq_7_bits_uop_lrs1 <= 6'h0;
stq_7_bits_uop_lrs2 <= 6'h0;
stq_7_bits_uop_lrs3 <= 6'h0;
stq_7_bits_uop_dst_rtype <= 2'h2;
stq_7_bits_uop_lrs1_rtype <= 2'h0;
stq_7_bits_uop_lrs2_rtype <= 2'h0;
stq_7_bits_uop_debug_fsrc <= 2'h0;
stq_7_bits_uop_debug_tsrc <= 2'h0;
stq_head <= 3'h0;
stq_commit_head <= 3'h0;
stq_execute_head <= 3'h0;
end
else begin
if (_GEN_475) begin
end
else begin
stq_0_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
stq_0_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
stq_0_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
stq_0_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
stq_0_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
stq_0_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
stq_0_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
stq_0_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
stq_0_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
stq_0_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
stq_0_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
stq_0_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
stq_0_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
end
if (stq_0_valid)
stq_0_bits_uop_br_mask <= stq_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_475) begin
end
else
stq_0_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_475) begin
end
else begin
stq_0_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
stq_0_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
stq_0_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
stq_0_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
stq_0_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
stq_0_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
stq_0_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
stq_0_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
stq_0_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
end
if (_GEN_499) begin
if (_exe_tlb_uop_T_2)
stq_0_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
stq_0_bits_uop_pdst <= _GEN_139;
else if (will_fire_sta_retry_0_will_fire)
stq_0_bits_uop_pdst <= _GEN_187;
else
stq_0_bits_uop_pdst <= 6'h0;
end
else if (_GEN_475) begin
end
else
stq_0_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
if (_GEN_475) begin
end
else begin
stq_0_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
stq_0_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
stq_0_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
stq_0_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
stq_0_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
stq_0_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
stq_0_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
stq_0_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
stq_0_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
stq_0_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
stq_0_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
stq_0_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
stq_0_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
stq_0_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
stq_0_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
stq_0_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
end
if (_GEN_476) begin
end
else begin
stq_1_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
stq_1_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
stq_1_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
stq_1_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
stq_1_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
stq_1_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
stq_1_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
stq_1_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
stq_1_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
stq_1_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
stq_1_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
stq_1_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
stq_1_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
end
if (stq_1_valid)
stq_1_bits_uop_br_mask <= stq_1_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_476) begin
end
else
stq_1_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_476) begin
end
else begin
stq_1_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
stq_1_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
stq_1_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
stq_1_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
stq_1_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
stq_1_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
stq_1_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
stq_1_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
stq_1_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
end
if (_GEN_501) begin
if (_exe_tlb_uop_T_2)
stq_1_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
stq_1_bits_uop_pdst <= _GEN_139;
else if (will_fire_sta_retry_0_will_fire)
stq_1_bits_uop_pdst <= _GEN_187;
else
stq_1_bits_uop_pdst <= 6'h0;
end
else if (_GEN_476) begin
end
else
stq_1_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
if (_GEN_476) begin
end
else begin
stq_1_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
stq_1_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
stq_1_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
stq_1_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
stq_1_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
stq_1_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
stq_1_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
stq_1_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
stq_1_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
stq_1_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
stq_1_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
stq_1_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
stq_1_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
stq_1_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
stq_1_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
stq_1_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
end
if (_GEN_477) begin
end
else begin
stq_2_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
stq_2_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
stq_2_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
stq_2_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
stq_2_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
stq_2_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
stq_2_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
stq_2_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
stq_2_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
stq_2_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
stq_2_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
stq_2_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
stq_2_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
end
if (stq_2_valid)
stq_2_bits_uop_br_mask <= stq_2_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_477) begin
end
else
stq_2_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_477) begin
end
else begin
stq_2_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
stq_2_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
stq_2_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
stq_2_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
stq_2_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
stq_2_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
stq_2_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
stq_2_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
stq_2_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
end
if (_GEN_503) begin
if (_exe_tlb_uop_T_2)
stq_2_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
stq_2_bits_uop_pdst <= _GEN_139;
else if (will_fire_sta_retry_0_will_fire)
stq_2_bits_uop_pdst <= _GEN_187;
else
stq_2_bits_uop_pdst <= 6'h0;
end
else if (_GEN_477) begin
end
else
stq_2_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
if (_GEN_477) begin
end
else begin
stq_2_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
stq_2_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
stq_2_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
stq_2_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
stq_2_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
stq_2_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
stq_2_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
stq_2_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
stq_2_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
stq_2_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
stq_2_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
stq_2_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
stq_2_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
stq_2_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
stq_2_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
stq_2_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
end
if (_GEN_478) begin
end
else begin
stq_3_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
stq_3_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
stq_3_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
stq_3_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
stq_3_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
stq_3_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
stq_3_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
stq_3_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
stq_3_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
stq_3_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
stq_3_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
stq_3_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
stq_3_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
end
if (stq_3_valid)
stq_3_bits_uop_br_mask <= stq_3_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_478) begin
end
else
stq_3_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_478) begin
end
else begin
stq_3_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
stq_3_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
stq_3_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
stq_3_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
stq_3_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
stq_3_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
stq_3_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
stq_3_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
stq_3_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
end
if (_GEN_505) begin
if (_exe_tlb_uop_T_2)
stq_3_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
stq_3_bits_uop_pdst <= _GEN_139;
else if (will_fire_sta_retry_0_will_fire)
stq_3_bits_uop_pdst <= _GEN_187;
else
stq_3_bits_uop_pdst <= 6'h0;
end
else if (_GEN_478) begin
end
else
stq_3_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
if (_GEN_478) begin
end
else begin
stq_3_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
stq_3_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
stq_3_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
stq_3_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
stq_3_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
stq_3_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
stq_3_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
stq_3_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
stq_3_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
stq_3_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
stq_3_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
stq_3_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
stq_3_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
stq_3_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
stq_3_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
stq_3_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
end
if (_GEN_479) begin
end
else begin
stq_4_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
stq_4_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
stq_4_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
stq_4_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
stq_4_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
stq_4_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
stq_4_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
stq_4_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
stq_4_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
stq_4_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
stq_4_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
stq_4_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
stq_4_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
end
if (stq_4_valid)
stq_4_bits_uop_br_mask <= stq_4_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_479) begin
end
else
stq_4_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_479) begin
end
else begin
stq_4_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
stq_4_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
stq_4_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
stq_4_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
stq_4_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
stq_4_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
stq_4_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
stq_4_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
stq_4_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
end
if (_GEN_507) begin
if (_exe_tlb_uop_T_2)
stq_4_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
stq_4_bits_uop_pdst <= _GEN_139;
else if (will_fire_sta_retry_0_will_fire)
stq_4_bits_uop_pdst <= _GEN_187;
else
stq_4_bits_uop_pdst <= 6'h0;
end
else if (_GEN_479) begin
end
else
stq_4_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
if (_GEN_479) begin
end
else begin
stq_4_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
stq_4_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
stq_4_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
stq_4_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
stq_4_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
stq_4_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
stq_4_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
stq_4_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
stq_4_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
stq_4_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
stq_4_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
stq_4_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
stq_4_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
stq_4_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
stq_4_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
stq_4_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
end
if (_GEN_480) begin
end
else begin
stq_5_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
stq_5_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
stq_5_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
stq_5_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
stq_5_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
stq_5_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
stq_5_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
stq_5_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
stq_5_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
stq_5_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
stq_5_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
stq_5_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
stq_5_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
end
if (stq_5_valid)
stq_5_bits_uop_br_mask <= stq_5_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_480) begin
end
else
stq_5_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_480) begin
end
else begin
stq_5_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
stq_5_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
stq_5_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
stq_5_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
stq_5_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
stq_5_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
stq_5_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
stq_5_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
stq_5_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
end
if (_GEN_509) begin
if (_exe_tlb_uop_T_2)
stq_5_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
stq_5_bits_uop_pdst <= _GEN_139;
else if (will_fire_sta_retry_0_will_fire)
stq_5_bits_uop_pdst <= _GEN_187;
else
stq_5_bits_uop_pdst <= 6'h0;
end
else if (_GEN_480) begin
end
else
stq_5_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
if (_GEN_480) begin
end
else begin
stq_5_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
stq_5_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
stq_5_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
stq_5_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
stq_5_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
stq_5_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
stq_5_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
stq_5_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
stq_5_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
stq_5_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
stq_5_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
stq_5_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
stq_5_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
stq_5_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
stq_5_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
stq_5_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
end
if (_GEN_481) begin
end
else begin
stq_6_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
stq_6_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
stq_6_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
stq_6_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
stq_6_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
stq_6_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
stq_6_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
stq_6_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
stq_6_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
stq_6_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
stq_6_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
stq_6_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
stq_6_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
end
if (stq_6_valid)
stq_6_bits_uop_br_mask <= stq_6_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_481) begin
end
else
stq_6_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_481) begin
end
else begin
stq_6_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
stq_6_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
stq_6_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
stq_6_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
stq_6_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
stq_6_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
stq_6_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
stq_6_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
stq_6_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
end
if (_GEN_511) begin
if (_exe_tlb_uop_T_2)
stq_6_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
stq_6_bits_uop_pdst <= _GEN_139;
else if (will_fire_sta_retry_0_will_fire)
stq_6_bits_uop_pdst <= _GEN_187;
else
stq_6_bits_uop_pdst <= 6'h0;
end
else if (_GEN_481) begin
end
else
stq_6_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
if (_GEN_481) begin
end
else begin
stq_6_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
stq_6_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
stq_6_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
stq_6_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
stq_6_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
stq_6_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
stq_6_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
stq_6_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
stq_6_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
stq_6_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
stq_6_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
stq_6_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
stq_6_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
stq_6_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
stq_6_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
stq_6_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
end
if (_GEN_482) begin
end
else begin
stq_7_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;
stq_7_bits_uop_inst <= io_core_dis_uops_0_bits_inst;
stq_7_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;
stq_7_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;
stq_7_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;
stq_7_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;
stq_7_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;
stq_7_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;
stq_7_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;
stq_7_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;
stq_7_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;
stq_7_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;
stq_7_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;
end
if (stq_7_valid)
stq_7_bits_uop_br_mask <= stq_7_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
else if (_GEN_482) begin
end
else
stq_7_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;
if (_GEN_482) begin
end
else begin
stq_7_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;
stq_7_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;
stq_7_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;
stq_7_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;
stq_7_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;
stq_7_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;
stq_7_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;
stq_7_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;
stq_7_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;
end
if (_GEN_513) begin
if (_exe_tlb_uop_T_2)
stq_7_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;
else if (will_fire_load_retry_0_will_fire)
stq_7_bits_uop_pdst <= _GEN_139;
else if (will_fire_sta_retry_0_will_fire)
stq_7_bits_uop_pdst <= _GEN_187;
else
stq_7_bits_uop_pdst <= 6'h0;
end
else if (_GEN_482) begin
end
else
stq_7_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;
if (_GEN_482) begin
end
else begin
stq_7_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;
stq_7_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;
stq_7_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;
stq_7_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;
stq_7_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;
stq_7_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;
stq_7_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;
stq_7_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;
stq_7_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;
stq_7_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;
stq_7_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;
stq_7_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;
stq_7_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;
stq_7_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;
stq_7_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;
stq_7_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;
end
if (clear_store)
stq_head <= stq_head + 3'h1;
if (commit_store)
stq_commit_head <= stq_commit_head + 3'h1;
if (clear_store & _GEN_425)
stq_execute_head <= stq_execute_head + 3'h1;
else if (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | io_dmem_nack_0_bits_uop_uses_ldq | io_dmem_nack_0_bits_uop_stq_idx < stq_head ^ stq_execute_head < stq_head ^ io_dmem_nack_0_bits_uop_stq_idx >= stq_execute_head) begin
if (_GEN_219 | ~(will_fire_store_commit_0_will_fire & dmem_req_fire_0)) begin
end
else
stq_execute_head <= stq_execute_head + 3'h1;
end
else
stq_execute_head <= io_dmem_nack_0_bits_uop_stq_idx;
end
stq_0_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);
stq_0_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);
stq_0_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);
stq_0_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);
stq_0_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);
stq_0_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);
stq_0_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);
stq_0_bits_uop_is_br <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);
stq_0_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);
stq_0_bits_uop_is_jal <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);
stq_0_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);
stq_0_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);
stq_0_bits_uop_taken <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_taken : io_core_dis_uops_0_bits_taken);
if (_GEN_695 | ~_GEN_475)
stq_0_bits_uop_ppred <= 4'h0;
stq_0_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);
stq_0_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);
stq_0_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);
stq_0_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_475 & stq_0_bits_uop_ppred_busy;
stq_0_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h0 | (_GEN_475 ? stq_0_bits_uop_exception : io_core_dis_uops_0_bits_exception));
stq_0_bits_uop_bypassable <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);
stq_0_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);
stq_0_bits_uop_is_fence <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);
stq_0_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);
stq_0_bits_uop_is_amo <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);
stq_0_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);
stq_0_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);
stq_0_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);
stq_0_bits_uop_is_unique <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);
stq_0_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);
stq_0_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);
stq_0_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);
stq_0_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);
stq_0_bits_uop_fp_val <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);
stq_0_bits_uop_fp_single <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);
stq_0_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);
stq_0_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);
stq_0_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);
stq_0_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);
stq_0_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);
stq_0_bits_addr_valid <= ~_GEN_697 & (clear_store ? ~_GEN_670 & _GEN_500 : ~_GEN_402 & _GEN_500);
if (_GEN_499) begin
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
stq_0_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
stq_0_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
stq_0_bits_addr_bits <= _GEN_180;
else if (will_fire_sta_retry_0_will_fire)
stq_0_bits_addr_bits <= _GEN_188;
else
stq_0_bits_addr_bits <= _exe_tlb_vaddr_T_2;
end
else
stq_0_bits_addr_bits <= _GEN_217;
stq_0_bits_addr_is_virtual <= exe_tlb_miss_0;
end
stq_0_bits_data_valid <= ~_GEN_697 & (clear_store ? ~_GEN_670 & _GEN_516 : ~_GEN_402 & _GEN_516);
if (_GEN_515)
stq_0_bits_data_bits <= _stq_bits_data_bits_T_1;
stq_0_bits_committed <= ~_GEN_684 & (commit_store & _GEN_645 | _GEN_475 & stq_0_bits_committed);
stq_0_bits_succeeded <= ~_GEN_684 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h0 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h0)) & _GEN_475 & stq_0_bits_succeeded);
stq_1_valid <= ~_GEN_699 & (clear_store ? ~_GEN_672 & _GEN_462 : ~_GEN_404 & _GEN_462);
stq_1_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);
stq_1_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);
stq_1_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);
stq_1_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);
stq_1_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);
stq_1_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);
stq_1_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);
stq_1_bits_uop_is_br <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);
stq_1_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);
stq_1_bits_uop_is_jal <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);
stq_1_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);
stq_1_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);
stq_1_bits_uop_taken <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_taken : io_core_dis_uops_0_bits_taken);
if (_GEN_695 | ~_GEN_476)
stq_1_bits_uop_ppred <= 4'h0;
stq_1_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);
stq_1_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);
stq_1_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);
stq_1_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_476 & stq_1_bits_uop_ppred_busy;
stq_1_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h1 | (_GEN_476 ? stq_1_bits_uop_exception : io_core_dis_uops_0_bits_exception));
stq_1_bits_uop_bypassable <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);
stq_1_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);
stq_1_bits_uop_is_fence <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);
stq_1_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);
stq_1_bits_uop_is_amo <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);
stq_1_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);
stq_1_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);
stq_1_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);
stq_1_bits_uop_is_unique <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);
stq_1_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);
stq_1_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);
stq_1_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);
stq_1_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);
stq_1_bits_uop_fp_val <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);
stq_1_bits_uop_fp_single <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);
stq_1_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);
stq_1_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);
stq_1_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);
stq_1_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);
stq_1_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);
stq_1_bits_addr_valid <= ~_GEN_699 & (clear_store ? ~_GEN_672 & _GEN_502 : ~_GEN_404 & _GEN_502);
if (_GEN_501) begin
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
stq_1_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
stq_1_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
stq_1_bits_addr_bits <= _GEN_180;
else if (will_fire_sta_retry_0_will_fire)
stq_1_bits_addr_bits <= _GEN_188;
else
stq_1_bits_addr_bits <= _exe_tlb_vaddr_T_2;
end
else
stq_1_bits_addr_bits <= _GEN_217;
stq_1_bits_addr_is_virtual <= exe_tlb_miss_0;
end
stq_1_bits_data_valid <= ~_GEN_699 & (clear_store ? ~_GEN_672 & _GEN_518 : ~_GEN_404 & _GEN_518);
if (_GEN_517)
stq_1_bits_data_bits <= _stq_bits_data_bits_T_1;
stq_1_bits_committed <= ~_GEN_685 & (commit_store & _GEN_646 | _GEN_476 & stq_1_bits_committed);
stq_1_bits_succeeded <= ~_GEN_685 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h1 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h1)) & _GEN_476 & stq_1_bits_succeeded);
stq_2_valid <= ~_GEN_701 & (clear_store ? ~_GEN_674 & _GEN_464 : ~_GEN_406 & _GEN_464);
stq_2_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);
stq_2_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);
stq_2_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);
stq_2_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);
stq_2_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);
stq_2_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);
stq_2_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);
stq_2_bits_uop_is_br <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);
stq_2_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);
stq_2_bits_uop_is_jal <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);
stq_2_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);
stq_2_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);
stq_2_bits_uop_taken <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_taken : io_core_dis_uops_0_bits_taken);
if (_GEN_695 | ~_GEN_477)
stq_2_bits_uop_ppred <= 4'h0;
stq_2_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);
stq_2_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);
stq_2_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);
stq_2_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_477 & stq_2_bits_uop_ppred_busy;
stq_2_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h2 | (_GEN_477 ? stq_2_bits_uop_exception : io_core_dis_uops_0_bits_exception));
stq_2_bits_uop_bypassable <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);
stq_2_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);
stq_2_bits_uop_is_fence <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);
stq_2_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);
stq_2_bits_uop_is_amo <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);
stq_2_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);
stq_2_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);
stq_2_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);
stq_2_bits_uop_is_unique <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);
stq_2_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);
stq_2_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);
stq_2_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);
stq_2_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);
stq_2_bits_uop_fp_val <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);
stq_2_bits_uop_fp_single <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);
stq_2_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);
stq_2_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);
stq_2_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);
stq_2_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);
stq_2_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);
stq_2_bits_addr_valid <= ~_GEN_701 & (clear_store ? ~_GEN_674 & _GEN_504 : ~_GEN_406 & _GEN_504);
if (_GEN_503) begin
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
stq_2_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
stq_2_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
stq_2_bits_addr_bits <= _GEN_180;
else if (will_fire_sta_retry_0_will_fire)
stq_2_bits_addr_bits <= _GEN_188;
else
stq_2_bits_addr_bits <= _exe_tlb_vaddr_T_2;
end
else
stq_2_bits_addr_bits <= _GEN_217;
stq_2_bits_addr_is_virtual <= exe_tlb_miss_0;
end
stq_2_bits_data_valid <= ~_GEN_701 & (clear_store ? ~_GEN_674 & _GEN_520 : ~_GEN_406 & _GEN_520);
if (_GEN_519)
stq_2_bits_data_bits <= _stq_bits_data_bits_T_1;
stq_2_bits_committed <= ~_GEN_686 & (commit_store & _GEN_647 | _GEN_477 & stq_2_bits_committed);
stq_2_bits_succeeded <= ~_GEN_686 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h2 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h2)) & _GEN_477 & stq_2_bits_succeeded);
stq_3_valid <= ~_GEN_703 & (clear_store ? ~_GEN_676 & _GEN_466 : ~_GEN_408 & _GEN_466);
stq_3_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);
stq_3_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);
stq_3_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);
stq_3_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);
stq_3_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);
stq_3_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);
stq_3_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);
stq_3_bits_uop_is_br <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);
stq_3_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);
stq_3_bits_uop_is_jal <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);
stq_3_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);
stq_3_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);
stq_3_bits_uop_taken <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_taken : io_core_dis_uops_0_bits_taken);
if (_GEN_695 | ~_GEN_478)
stq_3_bits_uop_ppred <= 4'h0;
stq_3_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);
stq_3_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);
stq_3_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);
stq_3_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_478 & stq_3_bits_uop_ppred_busy;
stq_3_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h3 | (_GEN_478 ? stq_3_bits_uop_exception : io_core_dis_uops_0_bits_exception));
stq_3_bits_uop_bypassable <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);
stq_3_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);
stq_3_bits_uop_is_fence <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);
stq_3_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);
stq_3_bits_uop_is_amo <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);
stq_3_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);
stq_3_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);
stq_3_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);
stq_3_bits_uop_is_unique <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);
stq_3_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);
stq_3_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);
stq_3_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);
stq_3_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);
stq_3_bits_uop_fp_val <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);
stq_3_bits_uop_fp_single <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);
stq_3_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);
stq_3_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);
stq_3_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);
stq_3_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);
stq_3_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);
stq_3_bits_addr_valid <= ~_GEN_703 & (clear_store ? ~_GEN_676 & _GEN_506 : ~_GEN_408 & _GEN_506);
if (_GEN_505) begin
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
stq_3_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
stq_3_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
stq_3_bits_addr_bits <= _GEN_180;
else if (will_fire_sta_retry_0_will_fire)
stq_3_bits_addr_bits <= _GEN_188;
else
stq_3_bits_addr_bits <= _exe_tlb_vaddr_T_2;
end
else
stq_3_bits_addr_bits <= _GEN_217;
stq_3_bits_addr_is_virtual <= exe_tlb_miss_0;
end
stq_3_bits_data_valid <= ~_GEN_703 & (clear_store ? ~_GEN_676 & _GEN_522 : ~_GEN_408 & _GEN_522);
if (_GEN_521)
stq_3_bits_data_bits <= _stq_bits_data_bits_T_1;
stq_3_bits_committed <= ~_GEN_687 & (commit_store & _GEN_648 | _GEN_478 & stq_3_bits_committed);
stq_3_bits_succeeded <= ~_GEN_687 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h3 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h3)) & _GEN_478 & stq_3_bits_succeeded);
stq_4_valid <= ~_GEN_705 & (clear_store ? ~_GEN_678 & _GEN_468 : ~_GEN_410 & _GEN_468);
stq_4_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);
stq_4_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);
stq_4_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);
stq_4_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);
stq_4_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);
stq_4_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);
stq_4_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);
stq_4_bits_uop_is_br <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);
stq_4_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);
stq_4_bits_uop_is_jal <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);
stq_4_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);
stq_4_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);
stq_4_bits_uop_taken <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_taken : io_core_dis_uops_0_bits_taken);
if (_GEN_695 | ~_GEN_479)
stq_4_bits_uop_ppred <= 4'h0;
stq_4_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);
stq_4_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);
stq_4_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);
stq_4_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_479 & stq_4_bits_uop_ppred_busy;
stq_4_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h4 | (_GEN_479 ? stq_4_bits_uop_exception : io_core_dis_uops_0_bits_exception));
stq_4_bits_uop_bypassable <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);
stq_4_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);
stq_4_bits_uop_is_fence <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);
stq_4_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);
stq_4_bits_uop_is_amo <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);
stq_4_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);
stq_4_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);
stq_4_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);
stq_4_bits_uop_is_unique <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);
stq_4_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);
stq_4_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);
stq_4_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);
stq_4_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);
stq_4_bits_uop_fp_val <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);
stq_4_bits_uop_fp_single <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);
stq_4_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);
stq_4_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);
stq_4_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);
stq_4_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);
stq_4_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);
stq_4_bits_addr_valid <= ~_GEN_705 & (clear_store ? ~_GEN_678 & _GEN_508 : ~_GEN_410 & _GEN_508);
if (_GEN_507) begin
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
stq_4_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
stq_4_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
stq_4_bits_addr_bits <= _GEN_180;
else if (will_fire_sta_retry_0_will_fire)
stq_4_bits_addr_bits <= _GEN_188;
else
stq_4_bits_addr_bits <= _exe_tlb_vaddr_T_2;
end
else
stq_4_bits_addr_bits <= _GEN_217;
stq_4_bits_addr_is_virtual <= exe_tlb_miss_0;
end
stq_4_bits_data_valid <= ~_GEN_705 & (clear_store ? ~_GEN_678 & _GEN_524 : ~_GEN_410 & _GEN_524);
if (_GEN_523)
stq_4_bits_data_bits <= _stq_bits_data_bits_T_1;
stq_4_bits_committed <= ~_GEN_688 & (commit_store & _GEN_649 | _GEN_479 & stq_4_bits_committed);
stq_4_bits_succeeded <= ~_GEN_688 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h4 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h4)) & _GEN_479 & stq_4_bits_succeeded);
stq_5_valid <= ~_GEN_707 & (clear_store ? ~_GEN_680 & _GEN_470 : ~_GEN_412 & _GEN_470);
stq_5_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);
stq_5_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);
stq_5_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);
stq_5_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);
stq_5_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);
stq_5_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);
stq_5_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);
stq_5_bits_uop_is_br <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);
stq_5_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);
stq_5_bits_uop_is_jal <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);
stq_5_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);
stq_5_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);
stq_5_bits_uop_taken <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_taken : io_core_dis_uops_0_bits_taken);
if (_GEN_695 | ~_GEN_480)
stq_5_bits_uop_ppred <= 4'h0;
stq_5_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);
stq_5_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);
stq_5_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);
stq_5_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_480 & stq_5_bits_uop_ppred_busy;
stq_5_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h5 | (_GEN_480 ? stq_5_bits_uop_exception : io_core_dis_uops_0_bits_exception));
stq_5_bits_uop_bypassable <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);
stq_5_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);
stq_5_bits_uop_is_fence <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);
stq_5_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);
stq_5_bits_uop_is_amo <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);
stq_5_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);
stq_5_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);
stq_5_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);
stq_5_bits_uop_is_unique <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);
stq_5_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);
stq_5_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);
stq_5_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);
stq_5_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);
stq_5_bits_uop_fp_val <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);
stq_5_bits_uop_fp_single <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);
stq_5_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);
stq_5_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);
stq_5_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);
stq_5_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);
stq_5_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);
stq_5_bits_addr_valid <= ~_GEN_707 & (clear_store ? ~_GEN_680 & _GEN_510 : ~_GEN_412 & _GEN_510);
if (_GEN_509) begin
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
stq_5_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
stq_5_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
stq_5_bits_addr_bits <= _GEN_180;
else if (will_fire_sta_retry_0_will_fire)
stq_5_bits_addr_bits <= _GEN_188;
else
stq_5_bits_addr_bits <= _exe_tlb_vaddr_T_2;
end
else
stq_5_bits_addr_bits <= _GEN_217;
stq_5_bits_addr_is_virtual <= exe_tlb_miss_0;
end
stq_5_bits_data_valid <= ~_GEN_707 & (clear_store ? ~_GEN_680 & _GEN_526 : ~_GEN_412 & _GEN_526);
if (_GEN_525)
stq_5_bits_data_bits <= _stq_bits_data_bits_T_1;
stq_5_bits_committed <= ~_GEN_689 & (commit_store & _GEN_650 | _GEN_480 & stq_5_bits_committed);
stq_5_bits_succeeded <= ~_GEN_689 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h5 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h5)) & _GEN_480 & stq_5_bits_succeeded);
stq_6_valid <= ~_GEN_709 & (clear_store ? ~_GEN_682 & _GEN_472 : ~_GEN_414 & _GEN_472);
stq_6_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);
stq_6_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);
stq_6_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);
stq_6_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);
stq_6_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);
stq_6_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);
stq_6_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);
stq_6_bits_uop_is_br <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);
stq_6_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);
stq_6_bits_uop_is_jal <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);
stq_6_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);
stq_6_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);
stq_6_bits_uop_taken <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_taken : io_core_dis_uops_0_bits_taken);
if (_GEN_695 | ~_GEN_481)
stq_6_bits_uop_ppred <= 4'h0;
stq_6_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);
stq_6_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);
stq_6_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);
stq_6_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_481 & stq_6_bits_uop_ppred_busy;
stq_6_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h6 | (_GEN_481 ? stq_6_bits_uop_exception : io_core_dis_uops_0_bits_exception));
stq_6_bits_uop_bypassable <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);
stq_6_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);
stq_6_bits_uop_is_fence <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);
stq_6_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);
stq_6_bits_uop_is_amo <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);
stq_6_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);
stq_6_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);
stq_6_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);
stq_6_bits_uop_is_unique <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);
stq_6_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);
stq_6_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);
stq_6_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);
stq_6_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);
stq_6_bits_uop_fp_val <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);
stq_6_bits_uop_fp_single <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);
stq_6_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);
stq_6_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);
stq_6_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);
stq_6_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);
stq_6_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);
stq_6_bits_addr_valid <= ~_GEN_709 & (clear_store ? ~_GEN_682 & _GEN_512 : ~_GEN_414 & _GEN_512);
if (_GEN_511) begin
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
stq_6_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
stq_6_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
stq_6_bits_addr_bits <= _GEN_180;
else if (will_fire_sta_retry_0_will_fire)
stq_6_bits_addr_bits <= _GEN_188;
else
stq_6_bits_addr_bits <= _exe_tlb_vaddr_T_2;
end
else
stq_6_bits_addr_bits <= _GEN_217;
stq_6_bits_addr_is_virtual <= exe_tlb_miss_0;
end
stq_6_bits_data_valid <= ~_GEN_709 & (clear_store ? ~_GEN_682 & _GEN_528 : ~_GEN_414 & _GEN_528);
if (_GEN_527)
stq_6_bits_data_bits <= _stq_bits_data_bits_T_1;
stq_6_bits_committed <= ~_GEN_690 & (commit_store & _GEN_651 | _GEN_481 & stq_6_bits_committed);
stq_6_bits_succeeded <= ~_GEN_690 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h6 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h6)) & _GEN_481 & stq_6_bits_succeeded);
stq_7_valid <= ~_GEN_711 & (clear_store ? ~_GEN_683 & _GEN_474 : ~_GEN_416 & _GEN_474);
stq_7_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);
stq_7_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);
stq_7_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);
stq_7_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);
stq_7_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);
stq_7_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);
stq_7_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);
stq_7_bits_uop_is_br <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);
stq_7_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);
stq_7_bits_uop_is_jal <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);
stq_7_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);
stq_7_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);
stq_7_bits_uop_taken <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_taken : io_core_dis_uops_0_bits_taken);
if (_GEN_695 | ~_GEN_482)
stq_7_bits_uop_ppred <= 4'h0;
stq_7_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);
stq_7_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);
stq_7_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);
stq_7_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_482 & stq_7_bits_uop_ppred_busy;
stq_7_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & (&mem_xcpt_uops_0_stq_idx) | (_GEN_482 ? stq_7_bits_uop_exception : io_core_dis_uops_0_bits_exception));
stq_7_bits_uop_bypassable <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);
stq_7_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);
stq_7_bits_uop_is_fence <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);
stq_7_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);
stq_7_bits_uop_is_amo <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);
stq_7_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);
stq_7_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);
stq_7_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);
stq_7_bits_uop_is_unique <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);
stq_7_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);
stq_7_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);
stq_7_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);
stq_7_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);
stq_7_bits_uop_fp_val <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);
stq_7_bits_uop_fp_single <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);
stq_7_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);
stq_7_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);
stq_7_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);
stq_7_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);
stq_7_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);
stq_7_bits_addr_valid <= ~_GEN_711 & (clear_store ? ~_GEN_683 & _GEN_514 : ~_GEN_416 & _GEN_514);
if (_GEN_513) begin
if (exe_tlb_miss_0) begin
if (_exe_tlb_vaddr_T_1)
stq_7_bits_addr_bits <= io_core_exe_0_req_bits_addr;
else if (will_fire_sfence_0_will_fire)
stq_7_bits_addr_bits <= _GEN_216;
else if (will_fire_load_retry_0_will_fire)
stq_7_bits_addr_bits <= _GEN_180;
else if (will_fire_sta_retry_0_will_fire)
stq_7_bits_addr_bits <= _GEN_188;
else
stq_7_bits_addr_bits <= _exe_tlb_vaddr_T_2;
end
else
stq_7_bits_addr_bits <= _GEN_217;
stq_7_bits_addr_is_virtual <= exe_tlb_miss_0;
end
stq_7_bits_data_valid <= ~_GEN_711 & (clear_store ? ~_GEN_683 & _GEN_530 : ~_GEN_416 & _GEN_530);
if (_GEN_529)
stq_7_bits_data_bits <= _stq_bits_data_bits_T_1;
stq_7_bits_committed <= ~_GEN_691 & (commit_store & (&idx) | _GEN_482 & stq_7_bits_committed);
stq_7_bits_succeeded <= ~_GEN_691 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & (&io_dmem_resp_0_bits_uop_stq_idx) | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & (&stq_execute_head))) & _GEN_482 & stq_7_bits_succeeded);
if (_GEN_694) begin
ldq_head <= 3'h0;
ldq_tail <= 3'h0;
stq_tail <= reset ? 3'h0 : stq_commit_head;
end
else begin
if (commit_load)
ldq_head <= ldq_head + 3'h1;
if (io_core_brupdate_b2_mispredict & ~io_core_exception) begin
ldq_tail <= io_core_brupdate_b2_uop_ldq_idx;
stq_tail <= io_core_brupdate_b2_uop_stq_idx;
end
else begin
if (dis_ld_val)
ldq_tail <= _GEN_94;
if (dis_st_val)
stq_tail <= _GEN_95;
end
end
if (_GEN_692)
hella_req_addr <= io_hellacache_req_bits_addr;
if (_GEN_693) begin
end
else
hella_data_data <= 64'h0;
if (will_fire_load_incoming_0_will_fire | will_fire_load_retry_0_will_fire | _GEN_220 | ~will_fire_hella_incoming_0_will_fire) begin
end
else
hella_paddr <= exe_tlb_paddr_0;
if (_GEN_693) begin
end
else begin
hella_xcpt_ma_ld <= _dtlb_io_resp_0_ma_ld;
hella_xcpt_ma_st <= _dtlb_io_resp_0_ma_st;
hella_xcpt_pf_ld <= _dtlb_io_resp_0_pf_ld;
hella_xcpt_pf_st <= _dtlb_io_resp_0_pf_st;
end
hella_xcpt_gf_ld <= _GEN_693 & hella_xcpt_gf_ld;
hella_xcpt_gf_st <= _GEN_693 & hella_xcpt_gf_st;
if (_GEN_693) begin
end
else begin
hella_xcpt_ae_ld <= _dtlb_io_resp_0_ae_ld;
hella_xcpt_ae_st <= _dtlb_io_resp_0_ae_st;
end
p1_block_load_mask_0 <= block_load_mask_0;
p1_block_load_mask_1 <= block_load_mask_1;
p1_block_load_mask_2 <= block_load_mask_2;
p1_block_load_mask_3 <= block_load_mask_3;
p1_block_load_mask_4 <= block_load_mask_4;
p1_block_load_mask_5 <= block_load_mask_5;
p1_block_load_mask_6 <= block_load_mask_6;
p1_block_load_mask_7 <= block_load_mask_7;
p2_block_load_mask_0 <= p1_block_load_mask_0;
p2_block_load_mask_1 <= p1_block_load_mask_1;
p2_block_load_mask_2 <= p1_block_load_mask_2;
p2_block_load_mask_3 <= p1_block_load_mask_3;
p2_block_load_mask_4 <= p1_block_load_mask_4;
p2_block_load_mask_5 <= p1_block_load_mask_5;
p2_block_load_mask_6 <= p1_block_load_mask_6;
p2_block_load_mask_7 <= p1_block_load_mask_7;
ldq_retry_idx <= _ldq_retry_idx_T_2 & _temp_bits_T ? 3'h0 : _ldq_retry_idx_T_5 & _temp_bits_T_2 ? 3'h1 : _ldq_retry_idx_T_8 & _temp_bits_T_4 ? 3'h2 : _ldq_retry_idx_T_11 & ~(ldq_head[2]) ? 3'h3 : _ldq_retry_idx_T_14 & _temp_bits_T_8 ? 3'h4 : _ldq_retry_idx_T_17 & _temp_bits_T_10 ? 3'h5 : _ldq_retry_idx_T_20 & _temp_bits_T_12 ? 3'h6 : ldq_7_bits_addr_valid & ldq_7_bits_addr_is_virtual & ~ldq_retry_idx_block_7 ? 3'h7 : _ldq_retry_idx_T_2 ? 3'h0 : _ldq_retry_idx_T_5 ? 3'h1 : _ldq_retry_idx_T_8 ? 3'h2 : _ldq_retry_idx_T_11 ? 3'h3 : _ldq_retry_idx_T_14 ? 3'h4 : _ldq_retry_idx_T_17 ? 3'h5 : {2'h3, ~_ldq_retry_idx_T_20};
stq_retry_idx <= _stq_retry_idx_T & stq_commit_head == 3'h0 ? 3'h0 : _stq_retry_idx_T_1 & stq_commit_head < 3'h2 ? 3'h1 : _stq_retry_idx_T_2 & stq_commit_head < 3'h3 ? 3'h2 : _stq_retry_idx_T_3 & ~(stq_commit_head[2]) ? 3'h3 : _stq_retry_idx_T_4 & stq_commit_head < 3'h5 ? 3'h4 : _stq_retry_idx_T_5 & stq_commit_head[2:1] != 2'h3 ? 3'h5 : _stq_retry_idx_T_6 & stq_commit_head != 3'h7 ? 3'h6 : stq_7_bits_addr_valid & stq_7_bits_addr_is_virtual ? 3'h7 : _stq_retry_idx_T ? 3'h0 : _stq_retry_idx_T_1 ? 3'h1 : _stq_retry_idx_T_2 ? 3'h2 : _stq_retry_idx_T_3 ? 3'h3 : _stq_retry_idx_T_4 ? 3'h4 : _stq_retry_idx_T_5 ? 3'h5 : {2'h3, ~_stq_retry_idx_T_6};
ldq_wakeup_idx <= _ldq_wakeup_idx_T_7 & _temp_bits_T ? 3'h0 : _ldq_wakeup_idx_T_15 & _temp_bits_T_2 ? 3'h1 : _ldq_wakeup_idx_T_23 & _temp_bits_T_4 ? 3'h2 : _ldq_wakeup_idx_T_31 & ~(ldq_head[2]) ? 3'h3 : _ldq_wakeup_idx_T_39 & _temp_bits_T_8 ? 3'h4 : _ldq_wakeup_idx_T_47 & _temp_bits_T_10 ? 3'h5 : _ldq_wakeup_idx_T_55 & _temp_bits_T_12 ? 3'h6 : ldq_7_bits_addr_valid & ~ldq_7_bits_executed & ~ldq_7_bits_succeeded & ~ldq_7_bits_addr_is_virtual & ~ldq_retry_idx_block_7 ? 3'h7 : _ldq_wakeup_idx_T_7 ? 3'h0 : _ldq_wakeup_idx_T_15 ? 3'h1 : _ldq_wakeup_idx_T_23 ? 3'h2 : _ldq_wakeup_idx_T_31 ? 3'h3 : _ldq_wakeup_idx_T_39 ? 3'h4 : _ldq_wakeup_idx_T_47 ? 3'h5 : {2'h3, ~_ldq_wakeup_idx_T_55};
can_fire_load_retry_REG <= _dtlb_io_miss_rdy;
can_fire_sta_retry_REG <= _dtlb_io_miss_rdy;
mem_xcpt_valids_0 <= (pf_ld_0 | pf_st_0 | ae_ld_0 | ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_ae_st & exe_tlb_uop_0_uses_stq | ma_ld_0 | ma_st_0) & ~io_core_exception & (io_core_brupdate_b1_mispredict_mask & exe_tlb_uop_0_br_mask) == 8'h0;
mem_xcpt_uops_0_br_mask <= exe_tlb_uop_0_br_mask & ~io_core_brupdate_b1_resolve_mask;
mem_xcpt_uops_0_rob_idx <= exe_tlb_uop_0_rob_idx;
mem_xcpt_uops_0_ldq_idx <= exe_tlb_uop_0_ldq_idx;
mem_xcpt_uops_0_stq_idx <= exe_tlb_uop_0_stq_idx;
mem_xcpt_uops_0_uses_ldq <= exe_tlb_uop_0_uses_ldq;
mem_xcpt_uops_0_uses_stq <= exe_tlb_uop_0_uses_stq;
mem_xcpt_causes_0 <= ma_ld_0 ? 4'h4 : ma_st_0 ? 4'h6 : pf_ld_0 ? 4'hD : pf_st_0 ? 4'hF : {2'h1, ~ae_ld_0, 1'h1};
mem_xcpt_vaddrs_0 <= exe_tlb_vaddr_0;
REG <= _GEN_194 | will_fire_load_retry_0_will_fire | will_fire_sta_retry_0_will_fire;
fired_load_incoming_REG <= will_fire_load_incoming_0_will_fire & _fired_std_incoming_T;
fired_stad_incoming_REG <= will_fire_stad_incoming_0_will_fire & _fired_std_incoming_T;
fired_sta_incoming_REG <= will_fire_sta_incoming_0_will_fire & _fired_std_incoming_T;
fired_std_incoming_REG <= will_fire_std_incoming_0_will_fire & _fired_std_incoming_T;
fired_stdf_incoming <= fp_stdata_fire & (io_core_brupdate_b1_mispredict_mask & io_core_fp_stdata_bits_uop_br_mask) == 8'h0;
fired_sfence_0 <= will_fire_sfence_0_will_fire;
fired_release_0 <= will_fire_release_0_will_fire;
fired_load_retry_REG <= will_fire_load_retry_0_will_fire & (io_core_brupdate_b1_mispredict_mask & _GEN_127) == 8'h0;
fired_sta_retry_REG <= will_fire_sta_retry_0_will_fire & _mem_stq_retry_e_out_valid_T == 8'h0;
fired_load_wakeup_REG <= will_fire_load_wakeup_0_will_fire & (io_core_brupdate_b1_mispredict_mask & _GEN_189) == 8'h0;
mem_incoming_uop_0_br_mask <= io_core_exe_0_req_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
mem_incoming_uop_0_rob_idx <= io_core_exe_0_req_bits_uop_rob_idx;
mem_incoming_uop_0_ldq_idx <= io_core_exe_0_req_bits_uop_ldq_idx;
mem_incoming_uop_0_stq_idx <= io_core_exe_0_req_bits_uop_stq_idx;
mem_incoming_uop_0_pdst <= io_core_exe_0_req_bits_uop_pdst;
mem_incoming_uop_0_fp_val <= io_core_exe_0_req_bits_uop_fp_val;
mem_ldq_incoming_e_0_bits_uop_br_mask <= _GEN_97[io_core_exe_0_req_bits_uop_ldq_idx] & ~io_core_brupdate_b1_resolve_mask;
mem_ldq_incoming_e_0_bits_uop_stq_idx <= _GEN_98[io_core_exe_0_req_bits_uop_ldq_idx];
mem_ldq_incoming_e_0_bits_uop_mem_size <= _GEN_99[io_core_exe_0_req_bits_uop_ldq_idx];
mem_ldq_incoming_e_0_bits_st_dep_mask <= _GEN_102[io_core_exe_0_req_bits_uop_ldq_idx];
mem_stq_incoming_e_0_valid <= _GEN_3[io_core_exe_0_req_bits_uop_stq_idx] & (io_core_brupdate_b1_mispredict_mask & _GEN_29[io_core_exe_0_req_bits_uop_stq_idx]) == 8'h0;
mem_stq_incoming_e_0_bits_uop_br_mask <= _GEN_29[io_core_exe_0_req_bits_uop_stq_idx] & ~io_core_brupdate_b1_resolve_mask;
mem_stq_incoming_e_0_bits_uop_rob_idx <= _GEN_37[io_core_exe_0_req_bits_uop_stq_idx];
mem_stq_incoming_e_0_bits_uop_stq_idx <= _GEN_39[io_core_exe_0_req_bits_uop_stq_idx];
mem_stq_incoming_e_0_bits_uop_mem_size <= _GEN_56[io_core_exe_0_req_bits_uop_stq_idx];
mem_stq_incoming_e_0_bits_uop_is_amo <= _GEN_61[io_core_exe_0_req_bits_uop_stq_idx];
mem_stq_incoming_e_0_bits_addr_valid <= _GEN_87[io_core_exe_0_req_bits_uop_stq_idx];
mem_stq_incoming_e_0_bits_addr_is_virtual <= _GEN_89[io_core_exe_0_req_bits_uop_stq_idx];
mem_stq_incoming_e_0_bits_data_valid <= _GEN_90[io_core_exe_0_req_bits_uop_stq_idx];
mem_ldq_wakeup_e_bits_uop_br_mask <= _GEN_189 & ~io_core_brupdate_b1_resolve_mask;
mem_ldq_wakeup_e_bits_uop_stq_idx <= mem_ldq_wakeup_e_out_bits_uop_stq_idx;
mem_ldq_wakeup_e_bits_uop_mem_size <= mem_ldq_wakeup_e_out_bits_uop_mem_size;
mem_ldq_wakeup_e_bits_st_dep_mask <= mem_ldq_wakeup_e_out_bits_st_dep_mask;
mem_ldq_retry_e_bits_uop_br_mask <= _GEN_127 & ~io_core_brupdate_b1_resolve_mask;
mem_ldq_retry_e_bits_uop_stq_idx <= mem_ldq_retry_e_out_bits_uop_stq_idx;
mem_ldq_retry_e_bits_uop_mem_size <= mem_ldq_retry_e_out_bits_uop_mem_size;
mem_ldq_retry_e_bits_st_dep_mask <= _GEN_102[ldq_retry_idx];
mem_stq_retry_e_valid <= _GEN_185 & _mem_stq_retry_e_out_valid_T == 8'h0;
mem_stq_retry_e_bits_uop_br_mask <= _GEN_186 & ~io_core_brupdate_b1_resolve_mask;
mem_stq_retry_e_bits_uop_rob_idx <= mem_stq_retry_e_out_bits_uop_rob_idx;
mem_stq_retry_e_bits_uop_stq_idx <= mem_stq_retry_e_out_bits_uop_stq_idx;
mem_stq_retry_e_bits_uop_mem_size <= mem_stq_retry_e_out_bits_uop_mem_size;
mem_stq_retry_e_bits_uop_is_amo <= mem_stq_retry_e_out_bits_uop_is_amo;
mem_stq_retry_e_bits_data_valid <= _GEN_90[stq_retry_idx];
mem_stdf_uop_br_mask <= io_core_fp_stdata_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
mem_stdf_uop_rob_idx <= io_core_fp_stdata_bits_uop_rob_idx;
mem_stdf_uop_stq_idx <= io_core_fp_stdata_bits_uop_stq_idx;
mem_tlb_miss_0 <= exe_tlb_miss_0;
mem_tlb_uncacheable_0 <= ~_dtlb_io_resp_0_cacheable;
mem_paddr_0 <= dmem_req_0_bits_addr;
clr_bsy_rob_idx_0 <= fired_stad_incoming_REG | fired_sta_incoming_REG | fired_std_incoming_REG ? mem_stq_incoming_e_0_bits_uop_rob_idx : fired_sfence_0 ? mem_incoming_uop_0_rob_idx : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_rob_idx : 5'h0;
clr_bsy_brmask_0 <= fired_stad_incoming_REG ? mem_stq_incoming_e_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : fired_sta_incoming_REG ? mem_stq_incoming_e_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : fired_std_incoming_REG ? mem_stq_incoming_e_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : fired_sfence_0 ? mem_incoming_uop_0_br_mask & ~io_core_brupdate_b1_resolve_mask : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : 8'h0;
io_core_clr_bsy_0_valid_REG <= io_core_exception;
io_core_clr_bsy_0_valid_REG_1 <= io_core_exception;
io_core_clr_bsy_0_valid_REG_2 <= io_core_clr_bsy_0_valid_REG_1;
stdf_clr_bsy_rob_idx <= fired_stdf_incoming ? mem_stdf_uop_rob_idx : 5'h0;
stdf_clr_bsy_brmask <= fired_stdf_incoming ? mem_stdf_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : 8'h0;
io_core_clr_bsy_1_valid_REG <= io_core_exception;
io_core_clr_bsy_1_valid_REG_1 <= io_core_exception;
io_core_clr_bsy_1_valid_REG_2 <= io_core_clr_bsy_1_valid_REG_1;
lcam_addr_REG <= exe_tlb_paddr_0;
lcam_addr_REG_1 <= io_dmem_release_bits_address;
lcam_ldq_idx_REG <= ldq_wakeup_idx;
lcam_ldq_idx_REG_1 <= ldq_retry_idx;
lcam_stq_idx_REG <= stq_retry_idx;
s1_executing_loads_0 <= will_fire_load_incoming_0_will_fire ? _GEN_202 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_209 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_195 & dmem_req_fire_0;
s1_executing_loads_1 <= will_fire_load_incoming_0_will_fire ? _GEN_203 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_210 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_196 & dmem_req_fire_0;
s1_executing_loads_2 <= will_fire_load_incoming_0_will_fire ? _GEN_204 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_211 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_197 & dmem_req_fire_0;
s1_executing_loads_3 <= will_fire_load_incoming_0_will_fire ? _GEN_205 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_212 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_198 & dmem_req_fire_0;
s1_executing_loads_4 <= will_fire_load_incoming_0_will_fire ? _GEN_206 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_213 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_199 & dmem_req_fire_0;
s1_executing_loads_5 <= will_fire_load_incoming_0_will_fire ? _GEN_207 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_214 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_200 & dmem_req_fire_0;
s1_executing_loads_6 <= will_fire_load_incoming_0_will_fire ? _GEN_208 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_215 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_201 & dmem_req_fire_0;
s1_executing_loads_7 <= will_fire_load_incoming_0_will_fire ? (&io_core_exe_0_req_bits_uop_ldq_idx) & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? (&ldq_retry_idx) & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & (&ldq_wakeup_idx) & dmem_req_fire_0;
wb_forward_valid_0 <= mem_forward_valid_0;
wb_forward_ldq_idx_0 <= lcam_ldq_idx_0;
wb_forward_ld_addr_0 <= lcam_addr_0;
wb_forward_stq_idx_0 <= _forwarding_age_logic_0_io_forwarding_idx;
older_nacked_REG <= nacking_loads_0;
io_dmem_s1_kill_0_REG <= dmem_req_fire_0;
older_nacked_REG_1 <= nacking_loads_1;
io_dmem_s1_kill_0_REG_1 <= dmem_req_fire_0;
older_nacked_REG_2 <= nacking_loads_2;
io_dmem_s1_kill_0_REG_2 <= dmem_req_fire_0;
older_nacked_REG_3 <= nacking_loads_3;
io_dmem_s1_kill_0_REG_3 <= dmem_req_fire_0;
older_nacked_REG_4 <= nacking_loads_4;
io_dmem_s1_kill_0_REG_4 <= dmem_req_fire_0;
older_nacked_REG_5 <= nacking_loads_5;
io_dmem_s1_kill_0_REG_5 <= dmem_req_fire_0;
older_nacked_REG_6 <= nacking_loads_6;
io_dmem_s1_kill_0_REG_6 <= dmem_req_fire_0;
older_nacked_REG_7 <= nacking_loads_7;
io_dmem_s1_kill_0_REG_7 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_8 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_9 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_10 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_11 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_12 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_13 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_14 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_15 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_16 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_17 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_18 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_19 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_20 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_21 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_22 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_23 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_24 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_25 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_26 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_27 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_28 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_29 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_30 <= dmem_req_fire_0;
io_dmem_s1_kill_0_REG_31 <= dmem_req_fire_0;
REG_1 <= io_core_exception;
REG_2 <= (ldst_addr_matches_0_0 | ldst_addr_matches_0_1 | ldst_addr_matches_0_2 | ldst_addr_matches_0_3 | ldst_addr_matches_0_4 | ldst_addr_matches_0_5 | ldst_addr_matches_0_6 | ldst_addr_matches_0_7) & ~mem_forward_valid_0;
if (will_fire_store_commit_0_will_fire | ~can_fire_store_commit_0)
store_blocked_counter <= 4'h0;
else if (can_fire_store_commit_0 & ~will_fire_store_commit_0_will_fire)
store_blocked_counter <= (&store_blocked_counter) ? 4'hF : store_blocked_counter + 4'h1;
r_xcpt_uop_br_mask <= xcpt_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;
r_xcpt_uop_rob_idx <= use_mem_xcpt ? mem_xcpt_uops_0_rob_idx : _GEN_135[l_idx];
r_xcpt_cause <= use_mem_xcpt ? {1'h0, mem_xcpt_causes_0} : 5'h10;
r_xcpt_badvaddr <= mem_xcpt_vaddrs_0;
io_core_ld_miss_REG <= io_core_spec_ld_wakeup_0_valid_0;
spec_ld_succeed_REG <= io_core_spec_ld_wakeup_0_valid_0;
spec_ld_succeed_REG_1 <= mem_incoming_uop_0_ldq_idx;
if (reset) begin
hella_state <= 3'h0;
live_store_mask <= 8'h0;
clr_bsy_valid_0 <= 1'h0;
stdf_clr_bsy_valid <= 1'h0;
r_xcpt_valid <= 1'h0;
end
else begin
hella_state <= _GEN_713[hella_state];
live_store_mask <= ({8{dis_st_val}} & 8'h1 << stq_tail | next_live_store_mask) & ~{stq_7_valid & (|_GEN_415), stq_6_valid & (|_GEN_413), stq_5_valid & (|_GEN_411), stq_4_valid & (|_GEN_409), stq_3_valid & (|_GEN_407), stq_2_valid & (|_GEN_405), stq_1_valid & (|_GEN_403), stq_0_valid & (|_GEN_401)} & ~{_GEN_694 & ~reset & _GEN_710, _GEN_694 & ~reset & _GEN_708, _GEN_694 & ~reset & _GEN_706, _GEN_694 & ~reset & _GEN_704, _GEN_694 & ~reset & _GEN_702, _GEN_694 & ~reset & _GEN_700, _GEN_694 & ~reset & _GEN_698, _GEN_694 & ~reset & _GEN_696};
clr_bsy_valid_0 <= fired_stad_incoming_REG ? mem_stq_incoming_e_0_valid & ~mem_tlb_miss_0 & ~mem_stq_incoming_e_0_bits_uop_is_amo & (io_core_brupdate_b1_mispredict_mask & mem_stq_incoming_e_0_bits_uop_br_mask) == 8'h0 : fired_sta_incoming_REG ? mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_data_valid & ~mem_tlb_miss_0 & ~mem_stq_incoming_e_0_bits_uop_is_amo & (io_core_brupdate_b1_mispredict_mask & mem_stq_incoming_e_0_bits_uop_br_mask) == 8'h0 : fired_std_incoming_REG ? mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_addr_valid & ~mem_stq_incoming_e_0_bits_addr_is_virtual & ~mem_stq_incoming_e_0_bits_uop_is_amo & (io_core_brupdate_b1_mispredict_mask & mem_stq_incoming_e_0_bits_uop_br_mask) == 8'h0 : fired_sfence_0 | fired_sta_retry_REG & mem_stq_retry_e_valid & mem_stq_retry_e_bits_data_valid & ~mem_tlb_miss_0 & ~mem_stq_retry_e_bits_uop_is_amo & (io_core_brupdate_b1_mispredict_mask & mem_stq_retry_e_bits_uop_br_mask) == 8'h0;
stdf_clr_bsy_valid <= fired_stdf_incoming & _GEN_3[mem_stdf_uop_stq_idx] & _GEN_87[mem_stdf_uop_stq_idx] & ~_GEN_89[mem_stdf_uop_stq_idx] & ~_GEN_61[mem_stdf_uop_stq_idx] & (io_core_brupdate_b1_mispredict_mask & mem_stdf_uop_br_mask) == 8'h0;
r_xcpt_valid <= (ld_xcpt_valid | mem_xcpt_valids_0) & ~io_core_exception & (io_core_brupdate_b1_mispredict_mask & xcpt_uop_br_mask) == 8'h0;
end
end
NBDTLB dtlb (
.clock (clock),
.reset (reset),
.io_req_0_valid (~_will_fire_store_commit_0_T_2),
.io_req_0_bits_vaddr (exe_tlb_vaddr_0),
.io_req_0_bits_passthrough (will_fire_hella_incoming_0_will_fire),
.io_req_0_bits_size (_exe_cmd_T | will_fire_sta_incoming_0_will_fire | will_fire_sfence_0_will_fire | will_fire_load_retry_0_will_fire | will_fire_sta_retry_0_will_fire ? exe_tlb_uop_0_mem_size : {2{will_fire_hella_incoming_0_will_fire}}),
.io_req_0_bits_cmd (_exe_cmd_T | will_fire_sta_incoming_0_will_fire | will_fire_sfence_0_will_fire | will_fire_load_retry_0_will_fire | will_fire_sta_retry_0_will_fire ? exe_tlb_uop_0_mem_cmd : 5'h0),
.io_miss_rdy (_dtlb_io_miss_rdy),
.io_resp_0_miss (_dtlb_io_resp_0_miss),
.io_resp_0_paddr (_dtlb_io_resp_0_paddr),
.io_resp_0_pf_ld (_dtlb_io_resp_0_pf_ld),
.io_resp_0_pf_st (_dtlb_io_resp_0_pf_st),
.io_resp_0_ae_ld (_dtlb_io_resp_0_ae_ld),
.io_resp_0_ae_st (_dtlb_io_resp_0_ae_st),
.io_resp_0_ma_ld (_dtlb_io_resp_0_ma_ld),
.io_resp_0_ma_st (_dtlb_io_resp_0_ma_st),
.io_resp_0_cacheable (_dtlb_io_resp_0_cacheable),
.io_sfence_valid (will_fire_sfence_0_will_fire & io_core_exe_0_req_bits_sfence_valid),
.io_sfence_bits_rs1 (will_fire_sfence_0_will_fire & io_core_exe_0_req_bits_sfence_bits_rs1),
.io_sfence_bits_rs2 (will_fire_sfence_0_will_fire & io_core_exe_0_req_bits_sfence_bits_rs2),
.io_sfence_bits_addr (will_fire_sfence_0_will_fire ? io_core_exe_0_req_bits_sfence_bits_addr : 39'h0),
.io_ptw_req_ready (io_ptw_req_ready),
.io_ptw_req_valid (_dtlb_io_ptw_req_valid),
.io_ptw_req_bits_valid (io_ptw_req_bits_valid),
.io_ptw_req_bits_bits_addr (io_ptw_req_bits_bits_addr),
.io_ptw_resp_valid (io_ptw_resp_valid),
.io_ptw_resp_bits_ae_final (io_ptw_resp_bits_ae_final),
.io_ptw_resp_bits_pte_ppn (io_ptw_resp_bits_pte_ppn),
.io_ptw_resp_bits_pte_d (io_ptw_resp_bits_pte_d),
.io_ptw_resp_bits_pte_a (io_ptw_resp_bits_pte_a),
.io_ptw_resp_bits_pte_g (io_ptw_resp_bits_pte_g),
.io_ptw_resp_bits_pte_u (io_ptw_resp_bits_pte_u),
.io_ptw_resp_bits_pte_x (io_ptw_resp_bits_pte_x),
.io_ptw_resp_bits_pte_w (io_ptw_resp_bits_pte_w),
.io_ptw_resp_bits_pte_r (io_ptw_resp_bits_pte_r),
.io_ptw_resp_bits_pte_v (io_ptw_resp_bits_pte_v),
.io_ptw_resp_bits_level (io_ptw_resp_bits_level),
.io_ptw_resp_bits_homogeneous (io_ptw_resp_bits_homogeneous),
.io_ptw_ptbr_mode (io_ptw_ptbr_mode),
.io_ptw_status_dprv (io_ptw_status_dprv),
.io_ptw_status_mxr (io_ptw_status_mxr),
.io_ptw_status_sum (io_ptw_status_sum),
.io_ptw_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l),
.io_ptw_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a),
.io_ptw_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x),
.io_ptw_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w),
.io_ptw_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r),
.io_ptw_pmp_0_addr (io_ptw_pmp_0_addr),
.io_ptw_pmp_0_mask (io_ptw_pmp_0_mask),
.io_ptw_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l),
.io_ptw_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a),
.io_ptw_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x),
.io_ptw_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w),
.io_ptw_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r),
.io_ptw_pmp_1_addr (io_ptw_pmp_1_addr),
.io_ptw_pmp_1_mask (io_ptw_pmp_1_mask),
.io_ptw_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l),
.io_ptw_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a),
.io_ptw_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x),
.io_ptw_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w),
.io_ptw_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r),
.io_ptw_pmp_2_addr (io_ptw_pmp_2_addr),
.io_ptw_pmp_2_mask (io_ptw_pmp_2_mask),
.io_ptw_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l),
.io_ptw_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a),
.io_ptw_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x),
.io_ptw_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w),
.io_ptw_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r),
.io_ptw_pmp_3_addr (io_ptw_pmp_3_addr),
.io_ptw_pmp_3_mask (io_ptw_pmp_3_mask),
.io_ptw_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l),
.io_ptw_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a),
.io_ptw_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x),
.io_ptw_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w),
.io_ptw_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r),
.io_ptw_pmp_4_addr (io_ptw_pmp_4_addr),
.io_ptw_pmp_4_mask (io_ptw_pmp_4_mask),
.io_ptw_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l),
.io_ptw_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a),
.io_ptw_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x),
.io_ptw_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w),
.io_ptw_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r),
.io_ptw_pmp_5_addr (io_ptw_pmp_5_addr),
.io_ptw_pmp_5_mask (io_ptw_pmp_5_mask),
.io_ptw_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l),
.io_ptw_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a),
.io_ptw_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x),
.io_ptw_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w),
.io_ptw_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r),
.io_ptw_pmp_6_addr (io_ptw_pmp_6_addr),
.io_ptw_pmp_6_mask (io_ptw_pmp_6_mask),
.io_ptw_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l),
.io_ptw_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a),
.io_ptw_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x),
.io_ptw_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w),
.io_ptw_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r),
.io_ptw_pmp_7_addr (io_ptw_pmp_7_addr),
.io_ptw_pmp_7_mask (io_ptw_pmp_7_mask),
.io_kill (will_fire_hella_incoming_0_will_fire & io_hellacache_s1_kill)
);
ForwardingAgeLogic forwarding_age_logic_0 (
.io_addr_matches ({ldst_addr_matches_0_7, ldst_addr_matches_0_6, ldst_addr_matches_0_5, ldst_addr_matches_0_4, ldst_addr_matches_0_3, ldst_addr_matches_0_2, ldst_addr_matches_0_1, ldst_addr_matches_0_0}),
.io_youngest_st_idx (do_st_search_0 ? (_lcam_stq_idx_T ? mem_stq_incoming_e_0_bits_uop_stq_idx : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_stq_idx : 3'h0) : do_ld_search_0 ? (fired_load_incoming_REG ? mem_ldq_incoming_e_0_bits_uop_stq_idx : fired_load_retry_REG ? mem_ldq_retry_e_bits_uop_stq_idx : fired_load_wakeup_REG ? mem_ldq_wakeup_e_bits_uop_stq_idx : 3'h0) : 3'h0),
.io_forwarding_idx (_forwarding_age_logic_0_io_forwarding_idx)
);
assign io_ptw_req_valid = _dtlb_io_ptw_req_valid;
assign io_core_exe_0_iresp_valid = io_core_exe_0_iresp_valid_0;
assign io_core_exe_0_iresp_bits_uop_rob_idx = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_37[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_390;
assign io_core_exe_0_iresp_bits_uop_pdst = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_41[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_391;
assign io_core_exe_0_iresp_bits_uop_is_amo = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_61[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_393;
assign io_core_exe_0_iresp_bits_uop_uses_stq = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_64[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_394;
assign io_core_exe_0_iresp_bits_uop_dst_rtype = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_74[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_395;
assign io_core_exe_0_iresp_bits_data = _GEN_400 ? io_dmem_resp_0_bits_data : {_ldq_bits_debug_wb_data_T_17 ? {56{_GEN_392 & io_core_exe_0_iresp_bits_data_zeroed_2[7]}} : {_ldq_bits_debug_wb_data_T_9 ? {48{_GEN_392 & io_core_exe_0_iresp_bits_data_zeroed_1[15]}} : {_ldq_bits_debug_wb_data_T_1 ? {32{_GEN_392 & io_core_exe_0_iresp_bits_data_zeroed[31]}} : _GEN_399[63:32], io_core_exe_0_iresp_bits_data_zeroed[31:16]}, io_core_exe_0_iresp_bits_data_zeroed_1[15:8]}, io_core_exe_0_iresp_bits_data_zeroed_2};
assign io_core_exe_0_fresp_valid = io_core_exe_0_fresp_valid_0;
assign io_core_exe_0_fresp_bits_uop_uopc = _GEN_400 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_103[wb_forward_ldq_idx_0];
assign io_core_exe_0_fresp_bits_uop_br_mask = _GEN_400 ? _GEN_97[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_389;
assign io_core_exe_0_fresp_bits_uop_rob_idx = _GEN_400 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_390;
assign io_core_exe_0_fresp_bits_uop_stq_idx = _GEN_400 ? _GEN_98[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_98[wb_forward_ldq_idx_0];
assign io_core_exe_0_fresp_bits_uop_pdst = _GEN_400 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_391;
assign io_core_exe_0_fresp_bits_uop_mem_size = _GEN_400 ? _GEN_99[io_dmem_resp_0_bits_uop_ldq_idx] : size_1;
assign io_core_exe_0_fresp_bits_uop_is_amo = _GEN_400 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_393;
assign io_core_exe_0_fresp_bits_uop_uses_stq = _GEN_400 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_394;
assign io_core_exe_0_fresp_bits_uop_dst_rtype = _GEN_400 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_395;
assign io_core_exe_0_fresp_bits_uop_fp_val = _GEN_400 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_170[wb_forward_ldq_idx_0];
assign io_core_exe_0_fresp_bits_data = {1'h0, _GEN_400 ? io_dmem_resp_0_bits_data : {_ldq_bits_debug_wb_data_T_17 ? {56{_GEN_392 & io_core_exe_0_fresp_bits_data_zeroed_2[7]}} : {_ldq_bits_debug_wb_data_T_9 ? {48{_GEN_392 & io_core_exe_0_fresp_bits_data_zeroed_1[15]}} : {_ldq_bits_debug_wb_data_T_1 ? {32{_GEN_392 & io_core_exe_0_fresp_bits_data_zeroed[31]}} : _GEN_399[63:32], io_core_exe_0_fresp_bits_data_zeroed[31:16]}, io_core_exe_0_fresp_bits_data_zeroed_1[15:8]}, io_core_exe_0_fresp_bits_data_zeroed_2}};
assign io_core_dis_ldq_idx_0 = ldq_tail;
assign io_core_dis_stq_idx_0 = stq_tail;
assign io_core_ldq_full_0 = _GEN_94 == ldq_head;
assign io_core_stq_full_0 = _GEN_95 == stq_head;
assign io_core_fp_stdata_ready = io_core_fp_stdata_ready_0;
assign io_core_clr_bsy_0_valid = clr_bsy_valid_0 & (io_core_brupdate_b1_mispredict_mask & clr_bsy_brmask_0) == 8'h0 & ~io_core_exception & ~io_core_clr_bsy_0_valid_REG & ~io_core_clr_bsy_0_valid_REG_2;
assign io_core_clr_bsy_0_bits = clr_bsy_rob_idx_0;
assign io_core_clr_bsy_1_valid = stdf_clr_bsy_valid & (io_core_brupdate_b1_mispredict_mask & stdf_clr_bsy_brmask) == 8'h0 & ~io_core_exception & ~io_core_clr_bsy_1_valid_REG & ~io_core_clr_bsy_1_valid_REG_2;
assign io_core_clr_bsy_1_bits = stdf_clr_bsy_rob_idx;
assign io_core_spec_ld_wakeup_0_valid = io_core_spec_ld_wakeup_0_valid_0;
assign io_core_spec_ld_wakeup_0_bits = mem_incoming_uop_0_pdst;
assign io_core_ld_miss = ~(~spec_ld_succeed_REG | io_core_exe_0_iresp_valid_0 & (_GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_38[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_136[wb_forward_ldq_idx_0]) == spec_ld_succeed_REG_1) & io_core_ld_miss_REG;
assign io_core_fencei_rdy = ~(stq_0_valid | stq_1_valid | stq_2_valid | stq_3_valid | stq_4_valid | stq_5_valid | stq_6_valid | stq_7_valid) & io_dmem_ordered;
assign io_core_lxcpt_valid = r_xcpt_valid & ~io_core_exception & (io_core_brupdate_b1_mispredict_mask & r_xcpt_uop_br_mask) == 8'h0;
assign io_core_lxcpt_bits_uop_br_mask = r_xcpt_uop_br_mask;
assign io_core_lxcpt_bits_uop_rob_idx = r_xcpt_uop_rob_idx;
assign io_core_lxcpt_bits_cause = r_xcpt_cause;
assign io_core_lxcpt_bits_badvaddr = r_xcpt_badvaddr;
assign io_core_perf_acquire = io_dmem_perf_acquire;
assign io_core_perf_release = io_dmem_perf_release;
assign io_core_perf_tlbMiss = io_ptw_req_ready & _dtlb_io_ptw_req_valid;
assign io_dmem_req_valid = dmem_req_0_valid;
assign io_dmem_req_bits_0_valid = dmem_req_0_valid;
assign io_dmem_req_bits_0_bits_uop_uopc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_uopc : will_fire_load_retry_0_will_fire ? _GEN_103[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_5[stq_retry_idx] : 7'h0) : will_fire_store_commit_0_will_fire ? _GEN_5[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_103[ldq_wakeup_idx] : 7'h0;
assign io_dmem_req_bits_0_bits_uop_inst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_inst : will_fire_load_retry_0_will_fire ? _GEN_104[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_6[stq_retry_idx] : 32'h0) : will_fire_store_commit_0_will_fire ? _GEN_6[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_104[ldq_wakeup_idx] : 32'h0;
assign io_dmem_req_bits_0_bits_uop_debug_inst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_debug_inst : will_fire_load_retry_0_will_fire ? _GEN_105[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_7[stq_retry_idx] : 32'h0) : will_fire_store_commit_0_will_fire ? _GEN_7[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_105[ldq_wakeup_idx] : 32'h0;
assign io_dmem_req_bits_0_bits_uop_is_rvc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_rvc : will_fire_load_retry_0_will_fire ? _GEN_106[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_8[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_8[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_106[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_debug_pc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_debug_pc : will_fire_load_retry_0_will_fire ? _GEN_107[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_9[stq_retry_idx] : 40'h0) : will_fire_store_commit_0_will_fire ? _GEN_9[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_107[ldq_wakeup_idx] : 40'h0;
assign io_dmem_req_bits_0_bits_uop_iq_type = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_iq_type : will_fire_load_retry_0_will_fire ? _GEN_108[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_10[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_10[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_108[ldq_wakeup_idx] : 3'h0;
assign io_dmem_req_bits_0_bits_uop_fu_code = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_fu_code : will_fire_load_retry_0_will_fire ? _GEN_109[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_11[stq_retry_idx] : 10'h0) : will_fire_store_commit_0_will_fire ? _GEN_11[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_109[ldq_wakeup_idx] : 10'h0;
assign io_dmem_req_bits_0_bits_uop_ctrl_br_type = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_br_type : will_fire_load_retry_0_will_fire ? _GEN_110[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_12[stq_retry_idx] : 4'h0) : will_fire_store_commit_0_will_fire ? _GEN_12[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_110[ldq_wakeup_idx] : 4'h0;
assign io_dmem_req_bits_0_bits_uop_ctrl_op1_sel = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_op1_sel : will_fire_load_retry_0_will_fire ? _GEN_111[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_13[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_13[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_111[ldq_wakeup_idx] : 2'h0;
assign io_dmem_req_bits_0_bits_uop_ctrl_op2_sel = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_op2_sel : will_fire_load_retry_0_will_fire ? _GEN_112[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_14[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_14[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_112[ldq_wakeup_idx] : 3'h0;
assign io_dmem_req_bits_0_bits_uop_ctrl_imm_sel = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_imm_sel : will_fire_load_retry_0_will_fire ? _GEN_113[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_15[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_15[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_113[ldq_wakeup_idx] : 3'h0;
assign io_dmem_req_bits_0_bits_uop_ctrl_op_fcn = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_op_fcn : will_fire_load_retry_0_will_fire ? _GEN_114[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_16[stq_retry_idx] : 5'h0) : will_fire_store_commit_0_will_fire ? _GEN_16[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_114[ldq_wakeup_idx] : 5'h0;
assign io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_fcn_dw : will_fire_load_retry_0_will_fire ? _GEN_115[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_17[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_17[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_115[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_csr_cmd : will_fire_load_retry_0_will_fire ? _GEN_116[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_18[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_18[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_116[ldq_wakeup_idx] : 3'h0;
assign io_dmem_req_bits_0_bits_uop_ctrl_is_load = _GEN_219 ? exe_tlb_uop_0_ctrl_is_load : will_fire_store_commit_0_will_fire ? _GEN_19[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_117[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_ctrl_is_sta = _GEN_219 ? exe_tlb_uop_0_ctrl_is_sta : will_fire_store_commit_0_will_fire ? _GEN_20[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_118[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_ctrl_is_std = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_is_std : will_fire_load_retry_0_will_fire ? _GEN_119[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_21[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_21[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_119[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_iw_state = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_iw_state : will_fire_load_retry_0_will_fire ? _GEN_120[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_22[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_22[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_120[ldq_wakeup_idx] : 2'h0;
assign io_dmem_req_bits_0_bits_uop_iw_p1_poisoned = _GEN_219 ? ~_exe_tlb_uop_T_2 & (will_fire_load_retry_0_will_fire ? _GEN_121[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_23[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_23[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_121[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_iw_p2_poisoned = _GEN_219 ? ~_exe_tlb_uop_T_2 & (will_fire_load_retry_0_will_fire ? _GEN_122[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_24[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_24[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_122[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_br = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_br : will_fire_load_retry_0_will_fire ? _GEN_123[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_25[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_25[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_123[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_jalr = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_jalr : will_fire_load_retry_0_will_fire ? _GEN_124[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_26[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_26[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_124[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_jal = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_jal : will_fire_load_retry_0_will_fire ? _GEN_125[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_27[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_27[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_125[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_sfb = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_sfb : will_fire_load_retry_0_will_fire ? _GEN_126[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_28[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_28[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_126[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_br_mask = _GEN_219 ? exe_tlb_uop_0_br_mask : will_fire_store_commit_0_will_fire ? _GEN_29[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_189 : 8'h0;
assign io_dmem_req_bits_0_bits_uop_br_tag = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_br_tag : will_fire_load_retry_0_will_fire ? _GEN_128[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_30[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_30[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_128[ldq_wakeup_idx] : 3'h0;
assign io_dmem_req_bits_0_bits_uop_ftq_idx = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ftq_idx : will_fire_load_retry_0_will_fire ? _GEN_129[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_31[stq_retry_idx] : 4'h0) : will_fire_store_commit_0_will_fire ? _GEN_31[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_129[ldq_wakeup_idx] : 4'h0;
assign io_dmem_req_bits_0_bits_uop_edge_inst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_edge_inst : will_fire_load_retry_0_will_fire ? _GEN_130[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_32[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_32[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_130[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_pc_lob = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_pc_lob : will_fire_load_retry_0_will_fire ? _GEN_131[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_33[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_33[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_131[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_taken = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_taken : will_fire_load_retry_0_will_fire ? _GEN_132[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_34[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_34[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_132[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_imm_packed = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_imm_packed : will_fire_load_retry_0_will_fire ? _GEN_133[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_35[stq_retry_idx] : 20'h0) : will_fire_store_commit_0_will_fire ? _GEN_35[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_133[ldq_wakeup_idx] : 20'h0;
assign io_dmem_req_bits_0_bits_uop_csr_addr = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_csr_addr : will_fire_load_retry_0_will_fire ? _GEN_134[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_36[stq_retry_idx] : 12'h0) : will_fire_store_commit_0_will_fire ? _GEN_36[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_134[ldq_wakeup_idx] : 12'h0;
assign io_dmem_req_bits_0_bits_uop_rob_idx = _GEN_219 ? exe_tlb_uop_0_rob_idx : will_fire_store_commit_0_will_fire ? _GEN_37[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_135[ldq_wakeup_idx] : 5'h0;
assign io_dmem_req_bits_0_bits_uop_ldq_idx = _GEN_219 ? exe_tlb_uop_0_ldq_idx : will_fire_store_commit_0_will_fire ? _GEN_38[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_136[ldq_wakeup_idx] : 3'h0;
assign io_dmem_req_bits_0_bits_uop_stq_idx = _GEN_219 ? exe_tlb_uop_0_stq_idx : will_fire_store_commit_0_will_fire ? _GEN_39[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? mem_ldq_wakeup_e_out_bits_uop_stq_idx : 3'h0;
assign io_dmem_req_bits_0_bits_uop_rxq_idx = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_rxq_idx : will_fire_load_retry_0_will_fire ? _GEN_137[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_40[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_40[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_137[ldq_wakeup_idx] : 2'h0;
assign io_dmem_req_bits_0_bits_uop_pdst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_pdst : will_fire_load_retry_0_will_fire ? _GEN_139 : _exe_tlb_uop_T_4_pdst) : will_fire_store_commit_0_will_fire ? _GEN_41[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_138[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_prs1 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs1 : will_fire_load_retry_0_will_fire ? _GEN_140[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_42[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_42[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_140[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_prs2 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs2 : will_fire_load_retry_0_will_fire ? _GEN_141[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_43[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_43[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_141[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_prs3 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs3 : will_fire_load_retry_0_will_fire ? _GEN_142[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_44[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_44[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_142[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_ppred = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ppred : will_fire_load_retry_0_will_fire | ~will_fire_sta_retry_0_will_fire ? 4'h0 : _GEN_45[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_45[stq_execute_head] : 4'h0;
assign io_dmem_req_bits_0_bits_uop_prs1_busy = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs1_busy : will_fire_load_retry_0_will_fire ? _GEN_143[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_46[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_46[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_143[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_prs2_busy = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs2_busy : will_fire_load_retry_0_will_fire ? _GEN_144[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_47[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_47[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_144[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_prs3_busy = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs3_busy : will_fire_load_retry_0_will_fire ? _GEN_145[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_48[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_48[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_145[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_ppred_busy = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ppred_busy : ~will_fire_load_retry_0_will_fire & will_fire_sta_retry_0_will_fire & _GEN_49[stq_retry_idx]) : will_fire_store_commit_0_will_fire & _GEN_49[stq_execute_head];
assign io_dmem_req_bits_0_bits_uop_stale_pdst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_stale_pdst : will_fire_load_retry_0_will_fire ? _GEN_146[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_50[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_50[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_146[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_exception = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_exception : will_fire_load_retry_0_will_fire ? _GEN_147[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_51[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_52 : will_fire_load_wakeup_0_will_fire & _GEN_147[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_exc_cause = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_exc_cause : will_fire_load_retry_0_will_fire ? _GEN_148[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_53[stq_retry_idx] : 64'h0) : will_fire_store_commit_0_will_fire ? _GEN_53[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_148[ldq_wakeup_idx] : 64'h0;
assign io_dmem_req_bits_0_bits_uop_bypassable = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_bypassable : will_fire_load_retry_0_will_fire ? _GEN_149[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_54[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_54[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_149[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_mem_cmd = _GEN_219 ? exe_tlb_uop_0_mem_cmd : will_fire_store_commit_0_will_fire ? _GEN_55[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_150[ldq_wakeup_idx] : 5'h0;
assign io_dmem_req_bits_0_bits_uop_mem_size = _GEN_219 ? exe_tlb_uop_0_mem_size : will_fire_store_commit_0_will_fire ? dmem_req_0_bits_data_size : will_fire_load_wakeup_0_will_fire ? mem_ldq_wakeup_e_out_bits_uop_mem_size : {2{will_fire_hella_incoming_0_will_fire | will_fire_hella_wakeup_0_will_fire}};
assign io_dmem_req_bits_0_bits_uop_mem_signed = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_mem_signed : will_fire_load_retry_0_will_fire ? _GEN_151[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_57[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_57[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_151[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_fence = _GEN_219 ? exe_tlb_uop_0_is_fence : will_fire_store_commit_0_will_fire ? _GEN_59 : will_fire_load_wakeup_0_will_fire & _GEN_152[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_fencei = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_fencei : will_fire_load_retry_0_will_fire ? _GEN_153[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_60[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_60[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_153[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_amo = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_amo : will_fire_load_retry_0_will_fire ? _GEN_154[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & mem_stq_retry_e_out_bits_uop_is_amo) : will_fire_store_commit_0_will_fire ? _GEN_62 : will_fire_load_wakeup_0_will_fire & _GEN_154[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_uses_ldq = _GEN_219 ? exe_tlb_uop_0_uses_ldq : will_fire_store_commit_0_will_fire ? _GEN_63[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_155[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_uses_stq = _GEN_219 ? exe_tlb_uop_0_uses_stq : will_fire_store_commit_0_will_fire ? _GEN_64[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_156[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_sys_pc2epc : will_fire_load_retry_0_will_fire ? _GEN_157[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_65[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_65[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_157[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_is_unique = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_unique : will_fire_load_retry_0_will_fire ? _GEN_158[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_66[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_66[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_158[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_flush_on_commit = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_flush_on_commit : will_fire_load_retry_0_will_fire ? _GEN_159[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_67[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_67[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_159[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ldst_is_rs1 : will_fire_load_retry_0_will_fire ? _GEN_160[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_68[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_68[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_160[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_ldst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ldst : will_fire_load_retry_0_will_fire ? _GEN_161[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_69[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_69[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_161[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_lrs1 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs1 : will_fire_load_retry_0_will_fire ? _GEN_162[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_70[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_70[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_162[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_lrs2 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs2 : will_fire_load_retry_0_will_fire ? _GEN_163[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_71[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_71[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_163[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_lrs3 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs3 : will_fire_load_retry_0_will_fire ? _GEN_164[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_72[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_72[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_164[ldq_wakeup_idx] : 6'h0;
assign io_dmem_req_bits_0_bits_uop_ldst_val = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ldst_val : will_fire_load_retry_0_will_fire ? _GEN_165[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_73[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_73[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_165[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_dst_rtype = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_dst_rtype : will_fire_load_retry_0_will_fire ? _GEN_166[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_74[stq_retry_idx] : 2'h2) : will_fire_store_commit_0_will_fire ? _GEN_74[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_166[ldq_wakeup_idx] : 2'h2;
assign io_dmem_req_bits_0_bits_uop_lrs1_rtype = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs1_rtype : will_fire_load_retry_0_will_fire ? _GEN_167[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_75[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_75[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_167[ldq_wakeup_idx] : 2'h0;
assign io_dmem_req_bits_0_bits_uop_lrs2_rtype = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs2_rtype : will_fire_load_retry_0_will_fire ? _GEN_168[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_76[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_76[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_168[ldq_wakeup_idx] : 2'h0;
assign io_dmem_req_bits_0_bits_uop_frs3_en = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_frs3_en : will_fire_load_retry_0_will_fire ? _GEN_169[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_77[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_77[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_169[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_fp_val = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_fp_val : will_fire_load_retry_0_will_fire ? _GEN_170[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_78[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_78[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_170[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_fp_single = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_fp_single : will_fire_load_retry_0_will_fire ? _GEN_171[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_79[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_79[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_171[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_xcpt_pf_if : will_fire_load_retry_0_will_fire ? _GEN_172[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_80[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_80[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_172[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_xcpt_ae_if : will_fire_load_retry_0_will_fire ? _GEN_173[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_81[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_81[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_173[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_xcpt_ma_if : will_fire_load_retry_0_will_fire ? _GEN_174[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_82[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_82[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_174[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_bp_debug_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_bp_debug_if : will_fire_load_retry_0_will_fire ? _GEN_175[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_83[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_83[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_175[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_bp_xcpt_if : will_fire_load_retry_0_will_fire ? _GEN_176[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_84[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_84[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_176[ldq_wakeup_idx];
assign io_dmem_req_bits_0_bits_uop_debug_fsrc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_debug_fsrc : will_fire_load_retry_0_will_fire ? _GEN_177[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_85[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_85[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_177[ldq_wakeup_idx] : 2'h0;
assign io_dmem_req_bits_0_bits_uop_debug_tsrc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_debug_tsrc : will_fire_load_retry_0_will_fire ? _GEN_178[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_86[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_86[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_178[ldq_wakeup_idx] : 2'h0;
assign io_dmem_req_bits_0_bits_addr = dmem_req_0_bits_addr;
assign io_dmem_req_bits_0_bits_data = _GEN_219 ? 64'h0 : will_fire_store_commit_0_will_fire ? _GEN_218[dmem_req_0_bits_data_size] : will_fire_load_wakeup_0_will_fire | will_fire_hella_incoming_0_will_fire | ~will_fire_hella_wakeup_0_will_fire ? 64'h0 : hella_data_data;
assign io_dmem_req_bits_0_bits_is_hella = ~(_GEN_219 | will_fire_store_commit_0_will_fire | will_fire_load_wakeup_0_will_fire) & (will_fire_hella_incoming_0_will_fire | will_fire_hella_wakeup_0_will_fire);
assign io_dmem_s1_kill_0 = _GEN_368 ? (_GEN_370 ? io_dmem_s1_kill_0_REG_29 : _GEN_371 ? io_dmem_s1_kill_0_REG_30 : _GEN_372 ? io_dmem_s1_kill_0_REG_31 : _GEN_366) : _GEN_366;
assign io_dmem_brupdate_b1_resolve_mask = io_core_brupdate_b1_resolve_mask;
assign io_dmem_brupdate_b1_mispredict_mask = io_core_brupdate_b1_mispredict_mask;
assign io_dmem_exception = io_core_exception;
assign io_dmem_release_ready = will_fire_release_0_will_fire;
assign io_dmem_force_order = _GEN_427 & _GEN_428 | io_core_fence_dmem;
assign io_hellacache_req_ready = io_hellacache_req_ready_0;
assign io_hellacache_s2_nack = ~_GEN_430 & _GEN_429;
assign io_hellacache_resp_valid = ~(_GEN_430 | _GEN_429 | _GEN_431) & _GEN_374 & _GEN_432;
assign io_hellacache_resp_bits_data = io_dmem_resp_0_bits_data;
assign io_hellacache_s2_xcpt_ae_ld = ~(io_hellacache_req_ready_0 | _GEN_2 | _GEN_429) & _GEN_431 & hella_xcpt_ae_ld;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// If regfile bypassing is disabled, then the functional unit must do its own
// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)
//
// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import freechips.rocketchip.tile
import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}
import boom.v3.common._
import boom.v3.ifu._
import boom.v3.util._
/**t
* Functional unit constants
*/
object FUConstants
{
// bit mask, since a given execution pipeline may support multiple functional units
val FUC_SZ = 10
val FU_X = BitPat.dontCare(FUC_SZ)
val FU_ALU = 1.U(FUC_SZ.W)
val FU_JMP = 2.U(FUC_SZ.W)
val FU_MEM = 4.U(FUC_SZ.W)
val FU_MUL = 8.U(FUC_SZ.W)
val FU_DIV = 16.U(FUC_SZ.W)
val FU_CSR = 32.U(FUC_SZ.W)
val FU_FPU = 64.U(FUC_SZ.W)
val FU_FDV = 128.U(FUC_SZ.W)
val FU_I2F = 256.U(FUC_SZ.W)
val FU_F2I = 512.U(FUC_SZ.W)
// FP stores generate data through FP F2I, and generate address through MemAddrCalc
val FU_F2IMEM = 516.U(FUC_SZ.W)
}
import FUConstants._
/**
* Class to tell the FUDecoders what units it needs to support
*
* @param alu support alu unit?
* @param bru support br unit?
* @param mem support mem unit?
* @param muld support multiple div unit?
* @param fpu support FP unit?
* @param csr support csr writing unit?
* @param fdiv support FP div unit?
* @param ifpu support int to FP unit?
*/
class SupportedFuncUnits(
val alu: Boolean = false,
val jmp: Boolean = false,
val mem: Boolean = false,
val muld: Boolean = false,
val fpu: Boolean = false,
val csr: Boolean = false,
val fdiv: Boolean = false,
val ifpu: Boolean = false)
{
}
/**
* Bundle for signals sent to the functional unit
*
* @param dataWidth width of the data sent to the functional unit
*/
class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val numOperands = 3
val rs1_data = UInt(dataWidth.W)
val rs2_data = UInt(dataWidth.W)
val rs3_data = UInt(dataWidth.W) // only used for FMA units
val pred_data = Bool()
val kill = Bool() // kill everything
}
/**
* Bundle for the signals sent out of the function unit
*
* @param dataWidth data sent from the functional unit
*/
class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val predicated = Bool() // Was this response from a predicated-off instruction
val data = UInt(dataWidth.W)
val fflags = new ValidIO(new FFlagsResp)
val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU
val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU
val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc
}
/**
* Branch resolution information given from the branch unit
*/
class BrResolutionInfo(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp
val valid = Bool()
val mispredict = Bool()
val taken = Bool() // which direction did the branch go?
val cfi_type = UInt(CFI_SZ.W)
// Info for recalculating the pc for this branch
val pc_sel = UInt(2.W)
val jalr_target = UInt(vaddrBitsExtended.W)
val target_offset = SInt()
}
class BrUpdateInfo(implicit p: Parameters) extends BoomBundle
{
// On the first cycle we get masks to kill registers
val b1 = new BrUpdateMasks
// On the second cycle we get indices to reset pointers
val b2 = new BrResolutionInfo
}
class BrUpdateMasks(implicit p: Parameters) extends BoomBundle
{
val resolve_mask = UInt(maxBrCount.W)
val mispredict_mask = UInt(maxBrCount.W)
}
/**
* Abstract top level functional unit class that wraps a lower level hand made functional unit
*
* @param isPipelined is the functional unit pipelined?
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class FunctionalUnit(
val isPipelined: Boolean,
val numStages: Int,
val numBypassStages: Int,
val dataWidth: Int,
val isJmpUnit: Boolean = false,
val isAluUnit: Boolean = false,
val isMemAddrCalcUnit: Boolean = false,
val needsFcsr: Boolean = false)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))
val brupdate = Input(new BrUpdateInfo())
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
// only used by the fpu unit
val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null
// only used by branch unit
val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null
// only used by memaddr calc unit
val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null
})
io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }
io.resp.valid := false.B
io.resp.bits := DontCare
if (isJmpUnit) {
io.get_ftq_pc.ftq_idx := DontCare
}
}
/**
* Abstract top level pipelined functional unit
*
* Note: this helps track which uops get killed while in intermediate stages,
* but it is the job of the consumer to check for kills on the same cycle as consumption!!!
*
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param earliestBypassStage first stage that you can start bypassing from
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class PipelinedFunctionalUnit(
numStages: Int,
numBypassStages: Int,
earliestBypassStage: Int,
dataWidth: Int,
isJmpUnit: Boolean = false,
isAluUnit: Boolean = false,
isMemAddrCalcUnit: Boolean = false,
needsFcsr: Boolean = false
)(implicit p: Parameters) extends FunctionalUnit(
isPipelined = true,
numStages = numStages,
numBypassStages = numBypassStages,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit,
isAluUnit = isAluUnit,
isMemAddrCalcUnit = isMemAddrCalcUnit,
needsFcsr = needsFcsr)
{
// Pipelined functional unit is always ready.
io.req.ready := true.B
if (numStages > 0) {
val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_uops = Reg(Vec(numStages, new MicroOp()))
// handle incoming request
r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill
r_uops(0) := io.req.bits.uop
r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
// handle middle of the pipeline
for (i <- 1 until numStages) {
r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill
r_uops(i) := r_uops(i-1)
r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))
if (numBypassStages > 0) {
io.bypass(i-1).bits.uop := r_uops(i-1)
}
}
// handle outgoing (branch could still kill it)
// consumer must also check for pipeline flushes (kills)
io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))
io.resp.bits.predicated := false.B
io.resp.bits.uop := r_uops(numStages-1)
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))
// bypassing (TODO allow bypass vector to have a different size from numStages)
if (numBypassStages > 0 && earliestBypassStage == 0) {
io.bypass(0).bits.uop := io.req.bits.uop
for (i <- 1 until numBypassStages) {
io.bypass(i).bits.uop := r_uops(i-1)
}
}
} else {
require (numStages == 0)
// pass req straight through to response
// valid doesn't check kill signals, let consumer deal with it.
// The LSU already handles it and this hurts critical path.
io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
io.resp.bits.predicated := false.B
io.resp.bits.uop := io.req.bits.uop
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
}
}
/**
* Functional unit that wraps RocketChips ALU
*
* @param isBranchUnit is this a branch unit?
* @param numStages how many pipeline stages does the functional unit have
* @param dataWidth width of the data being operated on in the functional unit
*/
class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = numStages,
isAluUnit = true,
earliestBypassStage = 0,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit)
with boom.v3.ifu.HasBoomFrontendParameters
{
val uop = io.req.bits.uop
// immediate generation
val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)
// operand 1 select
var op1_data: UInt = null
if (isJmpUnit) {
// Get the uop PC for jumps
val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)
val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),
0.U))
} else {
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
0.U)
}
// operand 2 select
val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),
Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),
Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,
Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),
0.U))))
val alu = Module(new freechips.rocketchip.rocket.ALU())
alu.io.in1 := op1_data.asUInt
alu.io.in2 := op2_data.asUInt
alu.io.fn := uop.ctrl.op_fcn
alu.io.dw := uop.ctrl.fcn_dw
// Did I just get killed by the previous cycle's branch,
// or by a flush pipeline?
val killed = WireInit(false.B)
when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {
killed := true.B
}
val rs1 = io.req.bits.rs1_data
val rs2 = io.req.bits.rs2_data
val br_eq = (rs1 === rs2)
val br_ltu = (rs1.asUInt < rs2.asUInt)
val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |
rs1(xLen-1) & ~rs2(xLen-1)).asBool
val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(
Seq( BR_N -> PC_PLUS4,
BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),
BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),
BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),
BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),
BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),
BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),
BR_J -> PC_BRJMP,
BR_JR -> PC_JALR
))
val is_taken = io.req.valid &&
!killed &&
(uop.is_br || uop.is_jalr || uop.is_jal) &&
(pc_sel =/= PC_PLUS4)
// "mispredict" means that a branch has been resolved and it must be killed
val mispredict = WireInit(false.B)
val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb
val is_jal = io.req.valid && !killed && uop.is_jal
val is_jalr = io.req.valid && !killed && uop.is_jalr
when (is_br || is_jalr) {
if (!isJmpUnit) {
assert (pc_sel =/= PC_JALR)
}
when (pc_sel === PC_PLUS4) {
mispredict := uop.taken
}
when (pc_sel === PC_BRJMP) {
mispredict := !uop.taken
}
}
val brinfo = Wire(new BrResolutionInfo)
// note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit
brinfo.valid := is_br || is_jalr
brinfo.mispredict := mispredict
brinfo.uop := uop
brinfo.cfi_type := Mux(is_jalr, CFI_JALR,
Mux(is_br , CFI_BR, CFI_X))
brinfo.taken := is_taken
brinfo.pc_sel := pc_sel
brinfo.jalr_target := DontCare
// Branch/Jump Target Calculation
// For jumps we read the FTQ, and can calculate the target
// For branches we emit the offset for the core to redirect if necessary
val target_offset = imm_xprlen(20,0).asSInt
brinfo.jalr_target := DontCare
if (isJmpUnit) {
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {
ea
} else {
// Efficient means to compress 64-bit VA into vaddrBits+1 bits.
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
}
val jalr_target_base = io.req.bits.rs1_data.asSInt
val jalr_target_xlen = Wire(UInt(xLen.W))
jalr_target_xlen := (jalr_target_base + target_offset).asUInt
val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt
brinfo.jalr_target := jalr_target
val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)
when (pc_sel === PC_JALR) {
mispredict := !io.get_ftq_pc.next_val ||
(io.get_ftq_pc.next_pc =/= jalr_target) ||
!io.get_ftq_pc.entry.cfi_idx.valid ||
(io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)
}
}
brinfo.target_offset := target_offset
io.brinfo := brinfo
// Response
// TODO add clock gate on resp bits from functional units
// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)
// val reg_data = Reg(outType = Bits(width = xLen))
// reg_data := alu.io.out
// io.resp.bits.data := reg_data
val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_data = Reg(Vec(numStages, UInt(xLen.W)))
val r_pred = Reg(Vec(numStages, Bool()))
val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,
Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),
Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))
r_val (0) := io.req.valid
r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data
for (i <- 1 until numStages) {
r_val(i) := r_val(i-1)
r_data(i) := r_data(i-1)
r_pred(i) := r_pred(i-1)
}
io.resp.bits.data := r_data(numStages-1)
io.resp.bits.predicated := r_pred(numStages-1)
// Bypass
// for the ALU, we can bypass same cycle as compute
require (numStages >= 1)
require (numBypassStages >= 1)
io.bypass(0).valid := io.req.valid
io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
for (i <- 1 until numStages) {
io.bypass(i).valid := r_val(i-1)
io.bypass(i).bits.data := r_data(i-1)
}
// Exceptions
io.resp.bits.fflags.valid := false.B
}
/**
* Functional unit that passes in base+imm to calculate addresses, and passes store data
* to the LSU.
* For floating point, 65bit FP store-data needs to be decoded into 64bit FP form
*/
class MemAddrCalcUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = 0,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65, // TODO enable this only if FP is enabled?
isMemAddrCalcUnit = true)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
// perform address calculation
val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt
val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,
sum(63,vaddrBits) =/= 0.U)
val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt
val store_data = io.req.bits.rs2_data
io.resp.bits.addr := effective_address
io.resp.bits.data := store_data
if (dataWidth > 63) {
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&
io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.")
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),
"FP store-data should now be going through a different unit.")
}
assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=
uopLD && io.req.bits.uop.uopc =/= uopSTA),
"[maddrcalc] assert we never get store data in here.")
// Handle misaligned exceptions
val size = io.req.bits.uop.mem_size
val misaligned =
(size === 1.U && (effective_address(0) =/= 0.U)) ||
(size === 2.U && (effective_address(1,0) =/= 0.U)) ||
(size === 3.U && (effective_address(2,0) =/= 0.U))
val bkptu = Module(new BreakpointUnit(nBreakpoints))
bkptu.io.status := io.status
bkptu.io.bp := io.bp
bkptu.io.pc := DontCare
bkptu.io.ea := effective_address
bkptu.io.mcontext := io.mcontext
bkptu.io.scontext := io.scontext
val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned
val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned
val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))
val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_val, xcpt_cause) = checkExceptions(List(
(ma_ld, (Causes.misaligned_load).U),
(ma_st, (Causes.misaligned_store).U),
(dbg_bp, (CSR.debugTriggerCause).U),
(bp, (Causes.breakpoint).U)))
io.resp.bits.mxcpt.valid := xcpt_val
io.resp.bits.mxcpt.bits := xcpt_cause
assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.")
io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE
io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)
io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)
io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data
io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data
}
/**
* Functional unit to wrap lower level FPU
*
* Currently, bypassing is unsupported!
* All FP instructions are padded out to the max latency unit for easy
* write-port scheduling.
*/
class FPUUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
{
val fpu = Module(new FPU())
fpu.io.req.valid := io.req.valid
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.fcsr_rm := io.fcsr_rm
io.resp.bits.data := fpu.io.resp.bits.data
io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now
}
/**
* Int to FP conversion functional unit
*
* @param latency the amount of stages to delay by
*/
class IntToFPUnit(latency: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = latency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
with tile.HasFPUParameters
{
val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder
val io_req = io.req.bits
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, None)
req.in2 := unbox(io_req.rs2_data, tag, None)
req.in3 := DontCare
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := DontCare // FIXME: this may not be the right thing to do here
req.fmaCmd := DontCare
assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),
"[func] IntToFP integer input has 65th high-order bit set!")
assert (!(io.req.valid && !fp_ctrl.fromint),
"[func] Only support fromInt micro-ops.")
val ifpu = Module(new tile.IntToFP(intToFpLatency))
ifpu.io.in.valid := io.req.valid
ifpu.io.in.bits := req
ifpu.io.in.bits.in1 := io_req.rs1_data
val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits
//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)
io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)
io.resp.bits.fflags.valid := ifpu.io.out.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc
}
/**
* Iterative/unpipelined functional unit, can only hold a single MicroOp at a time
* assumes at least one register between request and response
*
* TODO allow up to N micro-ops simultaneously.
*
* @param dataWidth width of the data to be passed into the functional unit
*/
abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)
extends FunctionalUnit(
isPipelined = false,
numStages = 1,
numBypassStages = 0,
dataWidth = dataWidth)
{
val r_uop = Reg(new MicroOp())
val do_kill = Wire(Bool())
do_kill := io.req.bits.kill // irrelevant default
when (io.req.fire) {
// update incoming uop
do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill
r_uop := io.req.bits.uop
r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
} .otherwise {
do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill
r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)
}
// assumes at least one pipeline register between request and response
io.resp.bits.uop := r_uop
}
/**
* Divide functional unit.
*
* @param dataWidth data to be passed into the functional unit
*/
class DivUnit(dataWidth: Int)(implicit p: Parameters)
extends IterativeFunctionalUnit(dataWidth)
{
// We don't use the iterative multiply functionality here.
// Instead we use the PipelinedMultiplier
val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))
// request
div.io.req.valid := io.req.valid && !this.do_kill
div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
div.io.req.bits.in1 := io.req.bits.rs1_data
div.io.req.bits.in2 := io.req.bits.rs2_data
div.io.req.bits.tag := DontCare
io.req.ready := div.io.req.ready
// handle pipeline kills and branch misspeculations
div.io.kill := this.do_kill
// response
io.resp.valid := div.io.resp.valid && !this.do_kill
div.io.resp.ready := io.resp.ready
io.resp.bits.data := div.io.resp.bits.data
}
/**
* Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier
*
* @param numStages number of pipeline stages
* @param dataWidth size of the data being passed into the functional unit
*/
class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = dataWidth)
{
val imul = Module(new PipelinedMultiplier(xLen, numStages))
// request
imul.io.req.valid := io.req.valid
imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
imul.io.req.bits.in1 := io.req.bits.rs1_data
imul.io.req.bits.in2 := io.req.bits.rs2_data
imul.io.req.bits.tag := DontCare
// response
io.resp.bits.data := imul.io.resp.bits.data
} | module FPUUnit(
input clock,
input reset,
input io_req_valid,
input [6:0] io_req_bits_uop_uopc,
input [31:0] io_req_bits_uop_inst,
input [31:0] io_req_bits_uop_debug_inst,
input io_req_bits_uop_is_rvc,
input [39:0] io_req_bits_uop_debug_pc,
input [2:0] io_req_bits_uop_iq_type,
input [9:0] io_req_bits_uop_fu_code,
input [3:0] io_req_bits_uop_ctrl_br_type,
input [1:0] io_req_bits_uop_ctrl_op1_sel,
input [2:0] io_req_bits_uop_ctrl_op2_sel,
input [2:0] io_req_bits_uop_ctrl_imm_sel,
input [4:0] io_req_bits_uop_ctrl_op_fcn,
input io_req_bits_uop_ctrl_fcn_dw,
input [2:0] io_req_bits_uop_ctrl_csr_cmd,
input io_req_bits_uop_ctrl_is_load,
input io_req_bits_uop_ctrl_is_sta,
input io_req_bits_uop_ctrl_is_std,
input [1:0] io_req_bits_uop_iw_state,
input io_req_bits_uop_iw_p1_poisoned,
input io_req_bits_uop_iw_p2_poisoned,
input io_req_bits_uop_is_br,
input io_req_bits_uop_is_jalr,
input io_req_bits_uop_is_jal,
input io_req_bits_uop_is_sfb,
input [7:0] io_req_bits_uop_br_mask,
input [2:0] io_req_bits_uop_br_tag,
input [3:0] io_req_bits_uop_ftq_idx,
input io_req_bits_uop_edge_inst,
input [5:0] io_req_bits_uop_pc_lob,
input io_req_bits_uop_taken,
input [19:0] io_req_bits_uop_imm_packed,
input [11:0] io_req_bits_uop_csr_addr,
input [4:0] io_req_bits_uop_rob_idx,
input [2:0] io_req_bits_uop_ldq_idx,
input [2:0] io_req_bits_uop_stq_idx,
input [1:0] io_req_bits_uop_rxq_idx,
input [5:0] io_req_bits_uop_pdst,
input [5:0] io_req_bits_uop_prs1,
input [5:0] io_req_bits_uop_prs2,
input [5:0] io_req_bits_uop_prs3,
input [3:0] io_req_bits_uop_ppred,
input io_req_bits_uop_prs1_busy,
input io_req_bits_uop_prs2_busy,
input io_req_bits_uop_prs3_busy,
input io_req_bits_uop_ppred_busy,
input [5:0] io_req_bits_uop_stale_pdst,
input io_req_bits_uop_exception,
input [63:0] io_req_bits_uop_exc_cause,
input io_req_bits_uop_bypassable,
input [4:0] io_req_bits_uop_mem_cmd,
input [1:0] io_req_bits_uop_mem_size,
input io_req_bits_uop_mem_signed,
input io_req_bits_uop_is_fence,
input io_req_bits_uop_is_fencei,
input io_req_bits_uop_is_amo,
input io_req_bits_uop_uses_ldq,
input io_req_bits_uop_uses_stq,
input io_req_bits_uop_is_sys_pc2epc,
input io_req_bits_uop_is_unique,
input io_req_bits_uop_flush_on_commit,
input io_req_bits_uop_ldst_is_rs1,
input [5:0] io_req_bits_uop_ldst,
input [5:0] io_req_bits_uop_lrs1,
input [5:0] io_req_bits_uop_lrs2,
input [5:0] io_req_bits_uop_lrs3,
input io_req_bits_uop_ldst_val,
input [1:0] io_req_bits_uop_dst_rtype,
input [1:0] io_req_bits_uop_lrs1_rtype,
input [1:0] io_req_bits_uop_lrs2_rtype,
input io_req_bits_uop_frs3_en,
input io_req_bits_uop_fp_val,
input io_req_bits_uop_fp_single,
input io_req_bits_uop_xcpt_pf_if,
input io_req_bits_uop_xcpt_ae_if,
input io_req_bits_uop_xcpt_ma_if,
input io_req_bits_uop_bp_debug_if,
input io_req_bits_uop_bp_xcpt_if,
input [1:0] io_req_bits_uop_debug_fsrc,
input [1:0] io_req_bits_uop_debug_tsrc,
input [64:0] io_req_bits_rs1_data,
input [64:0] io_req_bits_rs2_data,
input [64:0] io_req_bits_rs3_data,
input io_req_bits_kill,
output io_resp_valid,
output [6:0] io_resp_bits_uop_uopc,
output [31:0] io_resp_bits_uop_inst,
output [31:0] io_resp_bits_uop_debug_inst,
output io_resp_bits_uop_is_rvc,
output [39:0] io_resp_bits_uop_debug_pc,
output [2:0] io_resp_bits_uop_iq_type,
output [9:0] io_resp_bits_uop_fu_code,
output [3:0] io_resp_bits_uop_ctrl_br_type,
output [1:0] io_resp_bits_uop_ctrl_op1_sel,
output [2:0] io_resp_bits_uop_ctrl_op2_sel,
output [2:0] io_resp_bits_uop_ctrl_imm_sel,
output [4:0] io_resp_bits_uop_ctrl_op_fcn,
output io_resp_bits_uop_ctrl_fcn_dw,
output [2:0] io_resp_bits_uop_ctrl_csr_cmd,
output io_resp_bits_uop_ctrl_is_load,
output io_resp_bits_uop_ctrl_is_sta,
output io_resp_bits_uop_ctrl_is_std,
output [1:0] io_resp_bits_uop_iw_state,
output io_resp_bits_uop_iw_p1_poisoned,
output io_resp_bits_uop_iw_p2_poisoned,
output io_resp_bits_uop_is_br,
output io_resp_bits_uop_is_jalr,
output io_resp_bits_uop_is_jal,
output io_resp_bits_uop_is_sfb,
output [7:0] io_resp_bits_uop_br_mask,
output [2:0] io_resp_bits_uop_br_tag,
output [3:0] io_resp_bits_uop_ftq_idx,
output io_resp_bits_uop_edge_inst,
output [5:0] io_resp_bits_uop_pc_lob,
output io_resp_bits_uop_taken,
output [19:0] io_resp_bits_uop_imm_packed,
output [11:0] io_resp_bits_uop_csr_addr,
output [4:0] io_resp_bits_uop_rob_idx,
output [2:0] io_resp_bits_uop_ldq_idx,
output [2:0] io_resp_bits_uop_stq_idx,
output [1:0] io_resp_bits_uop_rxq_idx,
output [5:0] io_resp_bits_uop_pdst,
output [5:0] io_resp_bits_uop_prs1,
output [5:0] io_resp_bits_uop_prs2,
output [5:0] io_resp_bits_uop_prs3,
output [3:0] io_resp_bits_uop_ppred,
output io_resp_bits_uop_prs1_busy,
output io_resp_bits_uop_prs2_busy,
output io_resp_bits_uop_prs3_busy,
output io_resp_bits_uop_ppred_busy,
output [5:0] io_resp_bits_uop_stale_pdst,
output io_resp_bits_uop_exception,
output [63:0] io_resp_bits_uop_exc_cause,
output io_resp_bits_uop_bypassable,
output [4:0] io_resp_bits_uop_mem_cmd,
output [1:0] io_resp_bits_uop_mem_size,
output io_resp_bits_uop_mem_signed,
output io_resp_bits_uop_is_fence,
output io_resp_bits_uop_is_fencei,
output io_resp_bits_uop_is_amo,
output io_resp_bits_uop_uses_ldq,
output io_resp_bits_uop_uses_stq,
output io_resp_bits_uop_is_sys_pc2epc,
output io_resp_bits_uop_is_unique,
output io_resp_bits_uop_flush_on_commit,
output io_resp_bits_uop_ldst_is_rs1,
output [5:0] io_resp_bits_uop_ldst,
output [5:0] io_resp_bits_uop_lrs1,
output [5:0] io_resp_bits_uop_lrs2,
output [5:0] io_resp_bits_uop_lrs3,
output io_resp_bits_uop_ldst_val,
output [1:0] io_resp_bits_uop_dst_rtype,
output [1:0] io_resp_bits_uop_lrs1_rtype,
output [1:0] io_resp_bits_uop_lrs2_rtype,
output io_resp_bits_uop_frs3_en,
output io_resp_bits_uop_fp_val,
output io_resp_bits_uop_fp_single,
output io_resp_bits_uop_xcpt_pf_if,
output io_resp_bits_uop_xcpt_ae_if,
output io_resp_bits_uop_xcpt_ma_if,
output io_resp_bits_uop_bp_debug_if,
output io_resp_bits_uop_bp_xcpt_if,
output [1:0] io_resp_bits_uop_debug_fsrc,
output [1:0] io_resp_bits_uop_debug_tsrc,
output [64:0] io_resp_bits_data,
output io_resp_bits_fflags_valid,
output [6:0] io_resp_bits_fflags_bits_uop_uopc,
output [31:0] io_resp_bits_fflags_bits_uop_inst,
output [31:0] io_resp_bits_fflags_bits_uop_debug_inst,
output io_resp_bits_fflags_bits_uop_is_rvc,
output [39:0] io_resp_bits_fflags_bits_uop_debug_pc,
output [2:0] io_resp_bits_fflags_bits_uop_iq_type,
output [9:0] io_resp_bits_fflags_bits_uop_fu_code,
output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type,
output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel,
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel,
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel,
output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn,
output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw,
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd,
output io_resp_bits_fflags_bits_uop_ctrl_is_load,
output io_resp_bits_fflags_bits_uop_ctrl_is_sta,
output io_resp_bits_fflags_bits_uop_ctrl_is_std,
output [1:0] io_resp_bits_fflags_bits_uop_iw_state,
output io_resp_bits_fflags_bits_uop_iw_p1_poisoned,
output io_resp_bits_fflags_bits_uop_iw_p2_poisoned,
output io_resp_bits_fflags_bits_uop_is_br,
output io_resp_bits_fflags_bits_uop_is_jalr,
output io_resp_bits_fflags_bits_uop_is_jal,
output io_resp_bits_fflags_bits_uop_is_sfb,
output [7:0] io_resp_bits_fflags_bits_uop_br_mask,
output [2:0] io_resp_bits_fflags_bits_uop_br_tag,
output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx,
output io_resp_bits_fflags_bits_uop_edge_inst,
output [5:0] io_resp_bits_fflags_bits_uop_pc_lob,
output io_resp_bits_fflags_bits_uop_taken,
output [19:0] io_resp_bits_fflags_bits_uop_imm_packed,
output [11:0] io_resp_bits_fflags_bits_uop_csr_addr,
output [4:0] io_resp_bits_fflags_bits_uop_rob_idx,
output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx,
output [2:0] io_resp_bits_fflags_bits_uop_stq_idx,
output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx,
output [5:0] io_resp_bits_fflags_bits_uop_pdst,
output [5:0] io_resp_bits_fflags_bits_uop_prs1,
output [5:0] io_resp_bits_fflags_bits_uop_prs2,
output [5:0] io_resp_bits_fflags_bits_uop_prs3,
output [3:0] io_resp_bits_fflags_bits_uop_ppred,
output io_resp_bits_fflags_bits_uop_prs1_busy,
output io_resp_bits_fflags_bits_uop_prs2_busy,
output io_resp_bits_fflags_bits_uop_prs3_busy,
output io_resp_bits_fflags_bits_uop_ppred_busy,
output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst,
output io_resp_bits_fflags_bits_uop_exception,
output [63:0] io_resp_bits_fflags_bits_uop_exc_cause,
output io_resp_bits_fflags_bits_uop_bypassable,
output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd,
output [1:0] io_resp_bits_fflags_bits_uop_mem_size,
output io_resp_bits_fflags_bits_uop_mem_signed,
output io_resp_bits_fflags_bits_uop_is_fence,
output io_resp_bits_fflags_bits_uop_is_fencei,
output io_resp_bits_fflags_bits_uop_is_amo,
output io_resp_bits_fflags_bits_uop_uses_ldq,
output io_resp_bits_fflags_bits_uop_uses_stq,
output io_resp_bits_fflags_bits_uop_is_sys_pc2epc,
output io_resp_bits_fflags_bits_uop_is_unique,
output io_resp_bits_fflags_bits_uop_flush_on_commit,
output io_resp_bits_fflags_bits_uop_ldst_is_rs1,
output [5:0] io_resp_bits_fflags_bits_uop_ldst,
output [5:0] io_resp_bits_fflags_bits_uop_lrs1,
output [5:0] io_resp_bits_fflags_bits_uop_lrs2,
output [5:0] io_resp_bits_fflags_bits_uop_lrs3,
output io_resp_bits_fflags_bits_uop_ldst_val,
output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype,
output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype,
output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype,
output io_resp_bits_fflags_bits_uop_frs3_en,
output io_resp_bits_fflags_bits_uop_fp_val,
output io_resp_bits_fflags_bits_uop_fp_single,
output io_resp_bits_fflags_bits_uop_xcpt_pf_if,
output io_resp_bits_fflags_bits_uop_xcpt_ae_if,
output io_resp_bits_fflags_bits_uop_xcpt_ma_if,
output io_resp_bits_fflags_bits_uop_bp_debug_if,
output io_resp_bits_fflags_bits_uop_bp_xcpt_if,
output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc,
output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc,
output [4:0] io_resp_bits_fflags_bits_flags,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask,
input [2:0] io_fcsr_rm
);
reg r_valids_0;
reg r_valids_1;
reg r_valids_2;
reg r_valids_3;
reg [6:0] r_uops_0_uopc;
reg [31:0] r_uops_0_inst;
reg [31:0] r_uops_0_debug_inst;
reg r_uops_0_is_rvc;
reg [39:0] r_uops_0_debug_pc;
reg [2:0] r_uops_0_iq_type;
reg [9:0] r_uops_0_fu_code;
reg [3:0] r_uops_0_ctrl_br_type;
reg [1:0] r_uops_0_ctrl_op1_sel;
reg [2:0] r_uops_0_ctrl_op2_sel;
reg [2:0] r_uops_0_ctrl_imm_sel;
reg [4:0] r_uops_0_ctrl_op_fcn;
reg r_uops_0_ctrl_fcn_dw;
reg [2:0] r_uops_0_ctrl_csr_cmd;
reg r_uops_0_ctrl_is_load;
reg r_uops_0_ctrl_is_sta;
reg r_uops_0_ctrl_is_std;
reg [1:0] r_uops_0_iw_state;
reg r_uops_0_iw_p1_poisoned;
reg r_uops_0_iw_p2_poisoned;
reg r_uops_0_is_br;
reg r_uops_0_is_jalr;
reg r_uops_0_is_jal;
reg r_uops_0_is_sfb;
reg [7:0] r_uops_0_br_mask;
reg [2:0] r_uops_0_br_tag;
reg [3:0] r_uops_0_ftq_idx;
reg r_uops_0_edge_inst;
reg [5:0] r_uops_0_pc_lob;
reg r_uops_0_taken;
reg [19:0] r_uops_0_imm_packed;
reg [11:0] r_uops_0_csr_addr;
reg [4:0] r_uops_0_rob_idx;
reg [2:0] r_uops_0_ldq_idx;
reg [2:0] r_uops_0_stq_idx;
reg [1:0] r_uops_0_rxq_idx;
reg [5:0] r_uops_0_pdst;
reg [5:0] r_uops_0_prs1;
reg [5:0] r_uops_0_prs2;
reg [5:0] r_uops_0_prs3;
reg [3:0] r_uops_0_ppred;
reg r_uops_0_prs1_busy;
reg r_uops_0_prs2_busy;
reg r_uops_0_prs3_busy;
reg r_uops_0_ppred_busy;
reg [5:0] r_uops_0_stale_pdst;
reg r_uops_0_exception;
reg [63:0] r_uops_0_exc_cause;
reg r_uops_0_bypassable;
reg [4:0] r_uops_0_mem_cmd;
reg [1:0] r_uops_0_mem_size;
reg r_uops_0_mem_signed;
reg r_uops_0_is_fence;
reg r_uops_0_is_fencei;
reg r_uops_0_is_amo;
reg r_uops_0_uses_ldq;
reg r_uops_0_uses_stq;
reg r_uops_0_is_sys_pc2epc;
reg r_uops_0_is_unique;
reg r_uops_0_flush_on_commit;
reg r_uops_0_ldst_is_rs1;
reg [5:0] r_uops_0_ldst;
reg [5:0] r_uops_0_lrs1;
reg [5:0] r_uops_0_lrs2;
reg [5:0] r_uops_0_lrs3;
reg r_uops_0_ldst_val;
reg [1:0] r_uops_0_dst_rtype;
reg [1:0] r_uops_0_lrs1_rtype;
reg [1:0] r_uops_0_lrs2_rtype;
reg r_uops_0_frs3_en;
reg r_uops_0_fp_val;
reg r_uops_0_fp_single;
reg r_uops_0_xcpt_pf_if;
reg r_uops_0_xcpt_ae_if;
reg r_uops_0_xcpt_ma_if;
reg r_uops_0_bp_debug_if;
reg r_uops_0_bp_xcpt_if;
reg [1:0] r_uops_0_debug_fsrc;
reg [1:0] r_uops_0_debug_tsrc;
reg [6:0] r_uops_1_uopc;
reg [31:0] r_uops_1_inst;
reg [31:0] r_uops_1_debug_inst;
reg r_uops_1_is_rvc;
reg [39:0] r_uops_1_debug_pc;
reg [2:0] r_uops_1_iq_type;
reg [9:0] r_uops_1_fu_code;
reg [3:0] r_uops_1_ctrl_br_type;
reg [1:0] r_uops_1_ctrl_op1_sel;
reg [2:0] r_uops_1_ctrl_op2_sel;
reg [2:0] r_uops_1_ctrl_imm_sel;
reg [4:0] r_uops_1_ctrl_op_fcn;
reg r_uops_1_ctrl_fcn_dw;
reg [2:0] r_uops_1_ctrl_csr_cmd;
reg r_uops_1_ctrl_is_load;
reg r_uops_1_ctrl_is_sta;
reg r_uops_1_ctrl_is_std;
reg [1:0] r_uops_1_iw_state;
reg r_uops_1_iw_p1_poisoned;
reg r_uops_1_iw_p2_poisoned;
reg r_uops_1_is_br;
reg r_uops_1_is_jalr;
reg r_uops_1_is_jal;
reg r_uops_1_is_sfb;
reg [7:0] r_uops_1_br_mask;
reg [2:0] r_uops_1_br_tag;
reg [3:0] r_uops_1_ftq_idx;
reg r_uops_1_edge_inst;
reg [5:0] r_uops_1_pc_lob;
reg r_uops_1_taken;
reg [19:0] r_uops_1_imm_packed;
reg [11:0] r_uops_1_csr_addr;
reg [4:0] r_uops_1_rob_idx;
reg [2:0] r_uops_1_ldq_idx;
reg [2:0] r_uops_1_stq_idx;
reg [1:0] r_uops_1_rxq_idx;
reg [5:0] r_uops_1_pdst;
reg [5:0] r_uops_1_prs1;
reg [5:0] r_uops_1_prs2;
reg [5:0] r_uops_1_prs3;
reg [3:0] r_uops_1_ppred;
reg r_uops_1_prs1_busy;
reg r_uops_1_prs2_busy;
reg r_uops_1_prs3_busy;
reg r_uops_1_ppred_busy;
reg [5:0] r_uops_1_stale_pdst;
reg r_uops_1_exception;
reg [63:0] r_uops_1_exc_cause;
reg r_uops_1_bypassable;
reg [4:0] r_uops_1_mem_cmd;
reg [1:0] r_uops_1_mem_size;
reg r_uops_1_mem_signed;
reg r_uops_1_is_fence;
reg r_uops_1_is_fencei;
reg r_uops_1_is_amo;
reg r_uops_1_uses_ldq;
reg r_uops_1_uses_stq;
reg r_uops_1_is_sys_pc2epc;
reg r_uops_1_is_unique;
reg r_uops_1_flush_on_commit;
reg r_uops_1_ldst_is_rs1;
reg [5:0] r_uops_1_ldst;
reg [5:0] r_uops_1_lrs1;
reg [5:0] r_uops_1_lrs2;
reg [5:0] r_uops_1_lrs3;
reg r_uops_1_ldst_val;
reg [1:0] r_uops_1_dst_rtype;
reg [1:0] r_uops_1_lrs1_rtype;
reg [1:0] r_uops_1_lrs2_rtype;
reg r_uops_1_frs3_en;
reg r_uops_1_fp_val;
reg r_uops_1_fp_single;
reg r_uops_1_xcpt_pf_if;
reg r_uops_1_xcpt_ae_if;
reg r_uops_1_xcpt_ma_if;
reg r_uops_1_bp_debug_if;
reg r_uops_1_bp_xcpt_if;
reg [1:0] r_uops_1_debug_fsrc;
reg [1:0] r_uops_1_debug_tsrc;
reg [6:0] r_uops_2_uopc;
reg [31:0] r_uops_2_inst;
reg [31:0] r_uops_2_debug_inst;
reg r_uops_2_is_rvc;
reg [39:0] r_uops_2_debug_pc;
reg [2:0] r_uops_2_iq_type;
reg [9:0] r_uops_2_fu_code;
reg [3:0] r_uops_2_ctrl_br_type;
reg [1:0] r_uops_2_ctrl_op1_sel;
reg [2:0] r_uops_2_ctrl_op2_sel;
reg [2:0] r_uops_2_ctrl_imm_sel;
reg [4:0] r_uops_2_ctrl_op_fcn;
reg r_uops_2_ctrl_fcn_dw;
reg [2:0] r_uops_2_ctrl_csr_cmd;
reg r_uops_2_ctrl_is_load;
reg r_uops_2_ctrl_is_sta;
reg r_uops_2_ctrl_is_std;
reg [1:0] r_uops_2_iw_state;
reg r_uops_2_iw_p1_poisoned;
reg r_uops_2_iw_p2_poisoned;
reg r_uops_2_is_br;
reg r_uops_2_is_jalr;
reg r_uops_2_is_jal;
reg r_uops_2_is_sfb;
reg [7:0] r_uops_2_br_mask;
reg [2:0] r_uops_2_br_tag;
reg [3:0] r_uops_2_ftq_idx;
reg r_uops_2_edge_inst;
reg [5:0] r_uops_2_pc_lob;
reg r_uops_2_taken;
reg [19:0] r_uops_2_imm_packed;
reg [11:0] r_uops_2_csr_addr;
reg [4:0] r_uops_2_rob_idx;
reg [2:0] r_uops_2_ldq_idx;
reg [2:0] r_uops_2_stq_idx;
reg [1:0] r_uops_2_rxq_idx;
reg [5:0] r_uops_2_pdst;
reg [5:0] r_uops_2_prs1;
reg [5:0] r_uops_2_prs2;
reg [5:0] r_uops_2_prs3;
reg [3:0] r_uops_2_ppred;
reg r_uops_2_prs1_busy;
reg r_uops_2_prs2_busy;
reg r_uops_2_prs3_busy;
reg r_uops_2_ppred_busy;
reg [5:0] r_uops_2_stale_pdst;
reg r_uops_2_exception;
reg [63:0] r_uops_2_exc_cause;
reg r_uops_2_bypassable;
reg [4:0] r_uops_2_mem_cmd;
reg [1:0] r_uops_2_mem_size;
reg r_uops_2_mem_signed;
reg r_uops_2_is_fence;
reg r_uops_2_is_fencei;
reg r_uops_2_is_amo;
reg r_uops_2_uses_ldq;
reg r_uops_2_uses_stq;
reg r_uops_2_is_sys_pc2epc;
reg r_uops_2_is_unique;
reg r_uops_2_flush_on_commit;
reg r_uops_2_ldst_is_rs1;
reg [5:0] r_uops_2_ldst;
reg [5:0] r_uops_2_lrs1;
reg [5:0] r_uops_2_lrs2;
reg [5:0] r_uops_2_lrs3;
reg r_uops_2_ldst_val;
reg [1:0] r_uops_2_dst_rtype;
reg [1:0] r_uops_2_lrs1_rtype;
reg [1:0] r_uops_2_lrs2_rtype;
reg r_uops_2_frs3_en;
reg r_uops_2_fp_val;
reg r_uops_2_fp_single;
reg r_uops_2_xcpt_pf_if;
reg r_uops_2_xcpt_ae_if;
reg r_uops_2_xcpt_ma_if;
reg r_uops_2_bp_debug_if;
reg r_uops_2_bp_xcpt_if;
reg [1:0] r_uops_2_debug_fsrc;
reg [1:0] r_uops_2_debug_tsrc;
reg [6:0] r_uops_3_uopc;
reg [31:0] r_uops_3_inst;
reg [31:0] r_uops_3_debug_inst;
reg r_uops_3_is_rvc;
reg [39:0] r_uops_3_debug_pc;
reg [2:0] r_uops_3_iq_type;
reg [9:0] r_uops_3_fu_code;
reg [3:0] r_uops_3_ctrl_br_type;
reg [1:0] r_uops_3_ctrl_op1_sel;
reg [2:0] r_uops_3_ctrl_op2_sel;
reg [2:0] r_uops_3_ctrl_imm_sel;
reg [4:0] r_uops_3_ctrl_op_fcn;
reg r_uops_3_ctrl_fcn_dw;
reg [2:0] r_uops_3_ctrl_csr_cmd;
reg r_uops_3_ctrl_is_load;
reg r_uops_3_ctrl_is_sta;
reg r_uops_3_ctrl_is_std;
reg [1:0] r_uops_3_iw_state;
reg r_uops_3_iw_p1_poisoned;
reg r_uops_3_iw_p2_poisoned;
reg r_uops_3_is_br;
reg r_uops_3_is_jalr;
reg r_uops_3_is_jal;
reg r_uops_3_is_sfb;
reg [7:0] r_uops_3_br_mask;
reg [2:0] r_uops_3_br_tag;
reg [3:0] r_uops_3_ftq_idx;
reg r_uops_3_edge_inst;
reg [5:0] r_uops_3_pc_lob;
reg r_uops_3_taken;
reg [19:0] r_uops_3_imm_packed;
reg [11:0] r_uops_3_csr_addr;
reg [4:0] r_uops_3_rob_idx;
reg [2:0] r_uops_3_ldq_idx;
reg [2:0] r_uops_3_stq_idx;
reg [1:0] r_uops_3_rxq_idx;
reg [5:0] r_uops_3_pdst;
reg [5:0] r_uops_3_prs1;
reg [5:0] r_uops_3_prs2;
reg [5:0] r_uops_3_prs3;
reg [3:0] r_uops_3_ppred;
reg r_uops_3_prs1_busy;
reg r_uops_3_prs2_busy;
reg r_uops_3_prs3_busy;
reg r_uops_3_ppred_busy;
reg [5:0] r_uops_3_stale_pdst;
reg r_uops_3_exception;
reg [63:0] r_uops_3_exc_cause;
reg r_uops_3_bypassable;
reg [4:0] r_uops_3_mem_cmd;
reg [1:0] r_uops_3_mem_size;
reg r_uops_3_mem_signed;
reg r_uops_3_is_fence;
reg r_uops_3_is_fencei;
reg r_uops_3_is_amo;
reg r_uops_3_uses_ldq;
reg r_uops_3_uses_stq;
reg r_uops_3_is_sys_pc2epc;
reg r_uops_3_is_unique;
reg r_uops_3_flush_on_commit;
reg r_uops_3_ldst_is_rs1;
reg [5:0] r_uops_3_ldst;
reg [5:0] r_uops_3_lrs1;
reg [5:0] r_uops_3_lrs2;
reg [5:0] r_uops_3_lrs3;
reg r_uops_3_ldst_val;
reg [1:0] r_uops_3_dst_rtype;
reg [1:0] r_uops_3_lrs1_rtype;
reg [1:0] r_uops_3_lrs2_rtype;
reg r_uops_3_frs3_en;
reg r_uops_3_fp_val;
reg r_uops_3_fp_single;
reg r_uops_3_xcpt_pf_if;
reg r_uops_3_xcpt_ae_if;
reg r_uops_3_xcpt_ma_if;
reg r_uops_3_bp_debug_if;
reg r_uops_3_bp_xcpt_if;
reg [1:0] r_uops_3_debug_fsrc;
reg [1:0] r_uops_3_debug_tsrc;
wire [7:0] io_resp_bits_uop_br_mask_0 = r_uops_3_br_mask & ~io_brupdate_b1_resolve_mask;
always @(posedge clock) begin
if (reset) begin
r_valids_0 <= 1'h0;
r_valids_1 <= 1'h0;
r_valids_2 <= 1'h0;
r_valids_3 <= 1'h0;
end
else begin
r_valids_0 <= io_req_valid & (io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask) == 8'h0 & ~io_req_bits_kill;
r_valids_1 <= r_valids_0 & (io_brupdate_b1_mispredict_mask & r_uops_0_br_mask) == 8'h0 & ~io_req_bits_kill;
r_valids_2 <= r_valids_1 & (io_brupdate_b1_mispredict_mask & r_uops_1_br_mask) == 8'h0 & ~io_req_bits_kill;
r_valids_3 <= r_valids_2 & (io_brupdate_b1_mispredict_mask & r_uops_2_br_mask) == 8'h0 & ~io_req_bits_kill;
end
r_uops_0_uopc <= io_req_bits_uop_uopc;
r_uops_0_inst <= io_req_bits_uop_inst;
r_uops_0_debug_inst <= io_req_bits_uop_debug_inst;
r_uops_0_is_rvc <= io_req_bits_uop_is_rvc;
r_uops_0_debug_pc <= io_req_bits_uop_debug_pc;
r_uops_0_iq_type <= io_req_bits_uop_iq_type;
r_uops_0_fu_code <= io_req_bits_uop_fu_code;
r_uops_0_ctrl_br_type <= io_req_bits_uop_ctrl_br_type;
r_uops_0_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel;
r_uops_0_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel;
r_uops_0_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel;
r_uops_0_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn;
r_uops_0_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw;
r_uops_0_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd;
r_uops_0_ctrl_is_load <= io_req_bits_uop_ctrl_is_load;
r_uops_0_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta;
r_uops_0_ctrl_is_std <= io_req_bits_uop_ctrl_is_std;
r_uops_0_iw_state <= io_req_bits_uop_iw_state;
r_uops_0_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned;
r_uops_0_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned;
r_uops_0_is_br <= io_req_bits_uop_is_br;
r_uops_0_is_jalr <= io_req_bits_uop_is_jalr;
r_uops_0_is_jal <= io_req_bits_uop_is_jal;
r_uops_0_is_sfb <= io_req_bits_uop_is_sfb;
r_uops_0_br_mask <= io_req_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;
r_uops_0_br_tag <= io_req_bits_uop_br_tag;
r_uops_0_ftq_idx <= io_req_bits_uop_ftq_idx;
r_uops_0_edge_inst <= io_req_bits_uop_edge_inst;
r_uops_0_pc_lob <= io_req_bits_uop_pc_lob;
r_uops_0_taken <= io_req_bits_uop_taken;
r_uops_0_imm_packed <= io_req_bits_uop_imm_packed;
r_uops_0_csr_addr <= io_req_bits_uop_csr_addr;
r_uops_0_rob_idx <= io_req_bits_uop_rob_idx;
r_uops_0_ldq_idx <= io_req_bits_uop_ldq_idx;
r_uops_0_stq_idx <= io_req_bits_uop_stq_idx;
r_uops_0_rxq_idx <= io_req_bits_uop_rxq_idx;
r_uops_0_pdst <= io_req_bits_uop_pdst;
r_uops_0_prs1 <= io_req_bits_uop_prs1;
r_uops_0_prs2 <= io_req_bits_uop_prs2;
r_uops_0_prs3 <= io_req_bits_uop_prs3;
r_uops_0_ppred <= io_req_bits_uop_ppred;
r_uops_0_prs1_busy <= io_req_bits_uop_prs1_busy;
r_uops_0_prs2_busy <= io_req_bits_uop_prs2_busy;
r_uops_0_prs3_busy <= io_req_bits_uop_prs3_busy;
r_uops_0_ppred_busy <= io_req_bits_uop_ppred_busy;
r_uops_0_stale_pdst <= io_req_bits_uop_stale_pdst;
r_uops_0_exception <= io_req_bits_uop_exception;
r_uops_0_exc_cause <= io_req_bits_uop_exc_cause;
r_uops_0_bypassable <= io_req_bits_uop_bypassable;
r_uops_0_mem_cmd <= io_req_bits_uop_mem_cmd;
r_uops_0_mem_size <= io_req_bits_uop_mem_size;
r_uops_0_mem_signed <= io_req_bits_uop_mem_signed;
r_uops_0_is_fence <= io_req_bits_uop_is_fence;
r_uops_0_is_fencei <= io_req_bits_uop_is_fencei;
r_uops_0_is_amo <= io_req_bits_uop_is_amo;
r_uops_0_uses_ldq <= io_req_bits_uop_uses_ldq;
r_uops_0_uses_stq <= io_req_bits_uop_uses_stq;
r_uops_0_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc;
r_uops_0_is_unique <= io_req_bits_uop_is_unique;
r_uops_0_flush_on_commit <= io_req_bits_uop_flush_on_commit;
r_uops_0_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1;
r_uops_0_ldst <= io_req_bits_uop_ldst;
r_uops_0_lrs1 <= io_req_bits_uop_lrs1;
r_uops_0_lrs2 <= io_req_bits_uop_lrs2;
r_uops_0_lrs3 <= io_req_bits_uop_lrs3;
r_uops_0_ldst_val <= io_req_bits_uop_ldst_val;
r_uops_0_dst_rtype <= io_req_bits_uop_dst_rtype;
r_uops_0_lrs1_rtype <= io_req_bits_uop_lrs1_rtype;
r_uops_0_lrs2_rtype <= io_req_bits_uop_lrs2_rtype;
r_uops_0_frs3_en <= io_req_bits_uop_frs3_en;
r_uops_0_fp_val <= io_req_bits_uop_fp_val;
r_uops_0_fp_single <= io_req_bits_uop_fp_single;
r_uops_0_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if;
r_uops_0_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if;
r_uops_0_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if;
r_uops_0_bp_debug_if <= io_req_bits_uop_bp_debug_if;
r_uops_0_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if;
r_uops_0_debug_fsrc <= io_req_bits_uop_debug_fsrc;
r_uops_0_debug_tsrc <= io_req_bits_uop_debug_tsrc;
r_uops_1_uopc <= r_uops_0_uopc;
r_uops_1_inst <= r_uops_0_inst;
r_uops_1_debug_inst <= r_uops_0_debug_inst;
r_uops_1_is_rvc <= r_uops_0_is_rvc;
r_uops_1_debug_pc <= r_uops_0_debug_pc;
r_uops_1_iq_type <= r_uops_0_iq_type;
r_uops_1_fu_code <= r_uops_0_fu_code;
r_uops_1_ctrl_br_type <= r_uops_0_ctrl_br_type;
r_uops_1_ctrl_op1_sel <= r_uops_0_ctrl_op1_sel;
r_uops_1_ctrl_op2_sel <= r_uops_0_ctrl_op2_sel;
r_uops_1_ctrl_imm_sel <= r_uops_0_ctrl_imm_sel;
r_uops_1_ctrl_op_fcn <= r_uops_0_ctrl_op_fcn;
r_uops_1_ctrl_fcn_dw <= r_uops_0_ctrl_fcn_dw;
r_uops_1_ctrl_csr_cmd <= r_uops_0_ctrl_csr_cmd;
r_uops_1_ctrl_is_load <= r_uops_0_ctrl_is_load;
r_uops_1_ctrl_is_sta <= r_uops_0_ctrl_is_sta;
r_uops_1_ctrl_is_std <= r_uops_0_ctrl_is_std;
r_uops_1_iw_state <= r_uops_0_iw_state;
r_uops_1_iw_p1_poisoned <= r_uops_0_iw_p1_poisoned;
r_uops_1_iw_p2_poisoned <= r_uops_0_iw_p2_poisoned;
r_uops_1_is_br <= r_uops_0_is_br;
r_uops_1_is_jalr <= r_uops_0_is_jalr;
r_uops_1_is_jal <= r_uops_0_is_jal;
r_uops_1_is_sfb <= r_uops_0_is_sfb;
r_uops_1_br_mask <= r_uops_0_br_mask & ~io_brupdate_b1_resolve_mask;
r_uops_1_br_tag <= r_uops_0_br_tag;
r_uops_1_ftq_idx <= r_uops_0_ftq_idx;
r_uops_1_edge_inst <= r_uops_0_edge_inst;
r_uops_1_pc_lob <= r_uops_0_pc_lob;
r_uops_1_taken <= r_uops_0_taken;
r_uops_1_imm_packed <= r_uops_0_imm_packed;
r_uops_1_csr_addr <= r_uops_0_csr_addr;
r_uops_1_rob_idx <= r_uops_0_rob_idx;
r_uops_1_ldq_idx <= r_uops_0_ldq_idx;
r_uops_1_stq_idx <= r_uops_0_stq_idx;
r_uops_1_rxq_idx <= r_uops_0_rxq_idx;
r_uops_1_pdst <= r_uops_0_pdst;
r_uops_1_prs1 <= r_uops_0_prs1;
r_uops_1_prs2 <= r_uops_0_prs2;
r_uops_1_prs3 <= r_uops_0_prs3;
r_uops_1_ppred <= r_uops_0_ppred;
r_uops_1_prs1_busy <= r_uops_0_prs1_busy;
r_uops_1_prs2_busy <= r_uops_0_prs2_busy;
r_uops_1_prs3_busy <= r_uops_0_prs3_busy;
r_uops_1_ppred_busy <= r_uops_0_ppred_busy;
r_uops_1_stale_pdst <= r_uops_0_stale_pdst;
r_uops_1_exception <= r_uops_0_exception;
r_uops_1_exc_cause <= r_uops_0_exc_cause;
r_uops_1_bypassable <= r_uops_0_bypassable;
r_uops_1_mem_cmd <= r_uops_0_mem_cmd;
r_uops_1_mem_size <= r_uops_0_mem_size;
r_uops_1_mem_signed <= r_uops_0_mem_signed;
r_uops_1_is_fence <= r_uops_0_is_fence;
r_uops_1_is_fencei <= r_uops_0_is_fencei;
r_uops_1_is_amo <= r_uops_0_is_amo;
r_uops_1_uses_ldq <= r_uops_0_uses_ldq;
r_uops_1_uses_stq <= r_uops_0_uses_stq;
r_uops_1_is_sys_pc2epc <= r_uops_0_is_sys_pc2epc;
r_uops_1_is_unique <= r_uops_0_is_unique;
r_uops_1_flush_on_commit <= r_uops_0_flush_on_commit;
r_uops_1_ldst_is_rs1 <= r_uops_0_ldst_is_rs1;
r_uops_1_ldst <= r_uops_0_ldst;
r_uops_1_lrs1 <= r_uops_0_lrs1;
r_uops_1_lrs2 <= r_uops_0_lrs2;
r_uops_1_lrs3 <= r_uops_0_lrs3;
r_uops_1_ldst_val <= r_uops_0_ldst_val;
r_uops_1_dst_rtype <= r_uops_0_dst_rtype;
r_uops_1_lrs1_rtype <= r_uops_0_lrs1_rtype;
r_uops_1_lrs2_rtype <= r_uops_0_lrs2_rtype;
r_uops_1_frs3_en <= r_uops_0_frs3_en;
r_uops_1_fp_val <= r_uops_0_fp_val;
r_uops_1_fp_single <= r_uops_0_fp_single;
r_uops_1_xcpt_pf_if <= r_uops_0_xcpt_pf_if;
r_uops_1_xcpt_ae_if <= r_uops_0_xcpt_ae_if;
r_uops_1_xcpt_ma_if <= r_uops_0_xcpt_ma_if;
r_uops_1_bp_debug_if <= r_uops_0_bp_debug_if;
r_uops_1_bp_xcpt_if <= r_uops_0_bp_xcpt_if;
r_uops_1_debug_fsrc <= r_uops_0_debug_fsrc;
r_uops_1_debug_tsrc <= r_uops_0_debug_tsrc;
r_uops_2_uopc <= r_uops_1_uopc;
r_uops_2_inst <= r_uops_1_inst;
r_uops_2_debug_inst <= r_uops_1_debug_inst;
r_uops_2_is_rvc <= r_uops_1_is_rvc;
r_uops_2_debug_pc <= r_uops_1_debug_pc;
r_uops_2_iq_type <= r_uops_1_iq_type;
r_uops_2_fu_code <= r_uops_1_fu_code;
r_uops_2_ctrl_br_type <= r_uops_1_ctrl_br_type;
r_uops_2_ctrl_op1_sel <= r_uops_1_ctrl_op1_sel;
r_uops_2_ctrl_op2_sel <= r_uops_1_ctrl_op2_sel;
r_uops_2_ctrl_imm_sel <= r_uops_1_ctrl_imm_sel;
r_uops_2_ctrl_op_fcn <= r_uops_1_ctrl_op_fcn;
r_uops_2_ctrl_fcn_dw <= r_uops_1_ctrl_fcn_dw;
r_uops_2_ctrl_csr_cmd <= r_uops_1_ctrl_csr_cmd;
r_uops_2_ctrl_is_load <= r_uops_1_ctrl_is_load;
r_uops_2_ctrl_is_sta <= r_uops_1_ctrl_is_sta;
r_uops_2_ctrl_is_std <= r_uops_1_ctrl_is_std;
r_uops_2_iw_state <= r_uops_1_iw_state;
r_uops_2_iw_p1_poisoned <= r_uops_1_iw_p1_poisoned;
r_uops_2_iw_p2_poisoned <= r_uops_1_iw_p2_poisoned;
r_uops_2_is_br <= r_uops_1_is_br;
r_uops_2_is_jalr <= r_uops_1_is_jalr;
r_uops_2_is_jal <= r_uops_1_is_jal;
r_uops_2_is_sfb <= r_uops_1_is_sfb;
r_uops_2_br_mask <= r_uops_1_br_mask & ~io_brupdate_b1_resolve_mask;
r_uops_2_br_tag <= r_uops_1_br_tag;
r_uops_2_ftq_idx <= r_uops_1_ftq_idx;
r_uops_2_edge_inst <= r_uops_1_edge_inst;
r_uops_2_pc_lob <= r_uops_1_pc_lob;
r_uops_2_taken <= r_uops_1_taken;
r_uops_2_imm_packed <= r_uops_1_imm_packed;
r_uops_2_csr_addr <= r_uops_1_csr_addr;
r_uops_2_rob_idx <= r_uops_1_rob_idx;
r_uops_2_ldq_idx <= r_uops_1_ldq_idx;
r_uops_2_stq_idx <= r_uops_1_stq_idx;
r_uops_2_rxq_idx <= r_uops_1_rxq_idx;
r_uops_2_pdst <= r_uops_1_pdst;
r_uops_2_prs1 <= r_uops_1_prs1;
r_uops_2_prs2 <= r_uops_1_prs2;
r_uops_2_prs3 <= r_uops_1_prs3;
r_uops_2_ppred <= r_uops_1_ppred;
r_uops_2_prs1_busy <= r_uops_1_prs1_busy;
r_uops_2_prs2_busy <= r_uops_1_prs2_busy;
r_uops_2_prs3_busy <= r_uops_1_prs3_busy;
r_uops_2_ppred_busy <= r_uops_1_ppred_busy;
r_uops_2_stale_pdst <= r_uops_1_stale_pdst;
r_uops_2_exception <= r_uops_1_exception;
r_uops_2_exc_cause <= r_uops_1_exc_cause;
r_uops_2_bypassable <= r_uops_1_bypassable;
r_uops_2_mem_cmd <= r_uops_1_mem_cmd;
r_uops_2_mem_size <= r_uops_1_mem_size;
r_uops_2_mem_signed <= r_uops_1_mem_signed;
r_uops_2_is_fence <= r_uops_1_is_fence;
r_uops_2_is_fencei <= r_uops_1_is_fencei;
r_uops_2_is_amo <= r_uops_1_is_amo;
r_uops_2_uses_ldq <= r_uops_1_uses_ldq;
r_uops_2_uses_stq <= r_uops_1_uses_stq;
r_uops_2_is_sys_pc2epc <= r_uops_1_is_sys_pc2epc;
r_uops_2_is_unique <= r_uops_1_is_unique;
r_uops_2_flush_on_commit <= r_uops_1_flush_on_commit;
r_uops_2_ldst_is_rs1 <= r_uops_1_ldst_is_rs1;
r_uops_2_ldst <= r_uops_1_ldst;
r_uops_2_lrs1 <= r_uops_1_lrs1;
r_uops_2_lrs2 <= r_uops_1_lrs2;
r_uops_2_lrs3 <= r_uops_1_lrs3;
r_uops_2_ldst_val <= r_uops_1_ldst_val;
r_uops_2_dst_rtype <= r_uops_1_dst_rtype;
r_uops_2_lrs1_rtype <= r_uops_1_lrs1_rtype;
r_uops_2_lrs2_rtype <= r_uops_1_lrs2_rtype;
r_uops_2_frs3_en <= r_uops_1_frs3_en;
r_uops_2_fp_val <= r_uops_1_fp_val;
r_uops_2_fp_single <= r_uops_1_fp_single;
r_uops_2_xcpt_pf_if <= r_uops_1_xcpt_pf_if;
r_uops_2_xcpt_ae_if <= r_uops_1_xcpt_ae_if;
r_uops_2_xcpt_ma_if <= r_uops_1_xcpt_ma_if;
r_uops_2_bp_debug_if <= r_uops_1_bp_debug_if;
r_uops_2_bp_xcpt_if <= r_uops_1_bp_xcpt_if;
r_uops_2_debug_fsrc <= r_uops_1_debug_fsrc;
r_uops_2_debug_tsrc <= r_uops_1_debug_tsrc;
r_uops_3_uopc <= r_uops_2_uopc;
r_uops_3_inst <= r_uops_2_inst;
r_uops_3_debug_inst <= r_uops_2_debug_inst;
r_uops_3_is_rvc <= r_uops_2_is_rvc;
r_uops_3_debug_pc <= r_uops_2_debug_pc;
r_uops_3_iq_type <= r_uops_2_iq_type;
r_uops_3_fu_code <= r_uops_2_fu_code;
r_uops_3_ctrl_br_type <= r_uops_2_ctrl_br_type;
r_uops_3_ctrl_op1_sel <= r_uops_2_ctrl_op1_sel;
r_uops_3_ctrl_op2_sel <= r_uops_2_ctrl_op2_sel;
r_uops_3_ctrl_imm_sel <= r_uops_2_ctrl_imm_sel;
r_uops_3_ctrl_op_fcn <= r_uops_2_ctrl_op_fcn;
r_uops_3_ctrl_fcn_dw <= r_uops_2_ctrl_fcn_dw;
r_uops_3_ctrl_csr_cmd <= r_uops_2_ctrl_csr_cmd;
r_uops_3_ctrl_is_load <= r_uops_2_ctrl_is_load;
r_uops_3_ctrl_is_sta <= r_uops_2_ctrl_is_sta;
r_uops_3_ctrl_is_std <= r_uops_2_ctrl_is_std;
r_uops_3_iw_state <= r_uops_2_iw_state;
r_uops_3_iw_p1_poisoned <= r_uops_2_iw_p1_poisoned;
r_uops_3_iw_p2_poisoned <= r_uops_2_iw_p2_poisoned;
r_uops_3_is_br <= r_uops_2_is_br;
r_uops_3_is_jalr <= r_uops_2_is_jalr;
r_uops_3_is_jal <= r_uops_2_is_jal;
r_uops_3_is_sfb <= r_uops_2_is_sfb;
r_uops_3_br_mask <= r_uops_2_br_mask & ~io_brupdate_b1_resolve_mask;
r_uops_3_br_tag <= r_uops_2_br_tag;
r_uops_3_ftq_idx <= r_uops_2_ftq_idx;
r_uops_3_edge_inst <= r_uops_2_edge_inst;
r_uops_3_pc_lob <= r_uops_2_pc_lob;
r_uops_3_taken <= r_uops_2_taken;
r_uops_3_imm_packed <= r_uops_2_imm_packed;
r_uops_3_csr_addr <= r_uops_2_csr_addr;
r_uops_3_rob_idx <= r_uops_2_rob_idx;
r_uops_3_ldq_idx <= r_uops_2_ldq_idx;
r_uops_3_stq_idx <= r_uops_2_stq_idx;
r_uops_3_rxq_idx <= r_uops_2_rxq_idx;
r_uops_3_pdst <= r_uops_2_pdst;
r_uops_3_prs1 <= r_uops_2_prs1;
r_uops_3_prs2 <= r_uops_2_prs2;
r_uops_3_prs3 <= r_uops_2_prs3;
r_uops_3_ppred <= r_uops_2_ppred;
r_uops_3_prs1_busy <= r_uops_2_prs1_busy;
r_uops_3_prs2_busy <= r_uops_2_prs2_busy;
r_uops_3_prs3_busy <= r_uops_2_prs3_busy;
r_uops_3_ppred_busy <= r_uops_2_ppred_busy;
r_uops_3_stale_pdst <= r_uops_2_stale_pdst;
r_uops_3_exception <= r_uops_2_exception;
r_uops_3_exc_cause <= r_uops_2_exc_cause;
r_uops_3_bypassable <= r_uops_2_bypassable;
r_uops_3_mem_cmd <= r_uops_2_mem_cmd;
r_uops_3_mem_size <= r_uops_2_mem_size;
r_uops_3_mem_signed <= r_uops_2_mem_signed;
r_uops_3_is_fence <= r_uops_2_is_fence;
r_uops_3_is_fencei <= r_uops_2_is_fencei;
r_uops_3_is_amo <= r_uops_2_is_amo;
r_uops_3_uses_ldq <= r_uops_2_uses_ldq;
r_uops_3_uses_stq <= r_uops_2_uses_stq;
r_uops_3_is_sys_pc2epc <= r_uops_2_is_sys_pc2epc;
r_uops_3_is_unique <= r_uops_2_is_unique;
r_uops_3_flush_on_commit <= r_uops_2_flush_on_commit;
r_uops_3_ldst_is_rs1 <= r_uops_2_ldst_is_rs1;
r_uops_3_ldst <= r_uops_2_ldst;
r_uops_3_lrs1 <= r_uops_2_lrs1;
r_uops_3_lrs2 <= r_uops_2_lrs2;
r_uops_3_lrs3 <= r_uops_2_lrs3;
r_uops_3_ldst_val <= r_uops_2_ldst_val;
r_uops_3_dst_rtype <= r_uops_2_dst_rtype;
r_uops_3_lrs1_rtype <= r_uops_2_lrs1_rtype;
r_uops_3_lrs2_rtype <= r_uops_2_lrs2_rtype;
r_uops_3_frs3_en <= r_uops_2_frs3_en;
r_uops_3_fp_val <= r_uops_2_fp_val;
r_uops_3_fp_single <= r_uops_2_fp_single;
r_uops_3_xcpt_pf_if <= r_uops_2_xcpt_pf_if;
r_uops_3_xcpt_ae_if <= r_uops_2_xcpt_ae_if;
r_uops_3_xcpt_ma_if <= r_uops_2_xcpt_ma_if;
r_uops_3_bp_debug_if <= r_uops_2_bp_debug_if;
r_uops_3_bp_xcpt_if <= r_uops_2_bp_xcpt_if;
r_uops_3_debug_fsrc <= r_uops_2_debug_fsrc;
r_uops_3_debug_tsrc <= r_uops_2_debug_tsrc;
end
FPU fpu (
.clock (clock),
.reset (reset),
.io_req_valid (io_req_valid),
.io_req_bits_uop_uopc (io_req_bits_uop_uopc),
.io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),
.io_req_bits_rs1_data (io_req_bits_rs1_data),
.io_req_bits_rs2_data (io_req_bits_rs2_data),
.io_req_bits_rs3_data (io_req_bits_rs3_data),
.io_req_bits_fcsr_rm (io_fcsr_rm),
.io_resp_bits_data (io_resp_bits_data),
.io_resp_bits_fflags_valid (io_resp_bits_fflags_valid),
.io_resp_bits_fflags_bits_flags (io_resp_bits_fflags_bits_flags)
);
assign io_resp_valid = r_valids_3 & (io_brupdate_b1_mispredict_mask & r_uops_3_br_mask) == 8'h0;
assign io_resp_bits_uop_uopc = r_uops_3_uopc;
assign io_resp_bits_uop_inst = r_uops_3_inst;
assign io_resp_bits_uop_debug_inst = r_uops_3_debug_inst;
assign io_resp_bits_uop_is_rvc = r_uops_3_is_rvc;
assign io_resp_bits_uop_debug_pc = r_uops_3_debug_pc;
assign io_resp_bits_uop_iq_type = r_uops_3_iq_type;
assign io_resp_bits_uop_fu_code = r_uops_3_fu_code;
assign io_resp_bits_uop_ctrl_br_type = r_uops_3_ctrl_br_type;
assign io_resp_bits_uop_ctrl_op1_sel = r_uops_3_ctrl_op1_sel;
assign io_resp_bits_uop_ctrl_op2_sel = r_uops_3_ctrl_op2_sel;
assign io_resp_bits_uop_ctrl_imm_sel = r_uops_3_ctrl_imm_sel;
assign io_resp_bits_uop_ctrl_op_fcn = r_uops_3_ctrl_op_fcn;
assign io_resp_bits_uop_ctrl_fcn_dw = r_uops_3_ctrl_fcn_dw;
assign io_resp_bits_uop_ctrl_csr_cmd = r_uops_3_ctrl_csr_cmd;
assign io_resp_bits_uop_ctrl_is_load = r_uops_3_ctrl_is_load;
assign io_resp_bits_uop_ctrl_is_sta = r_uops_3_ctrl_is_sta;
assign io_resp_bits_uop_ctrl_is_std = r_uops_3_ctrl_is_std;
assign io_resp_bits_uop_iw_state = r_uops_3_iw_state;
assign io_resp_bits_uop_iw_p1_poisoned = r_uops_3_iw_p1_poisoned;
assign io_resp_bits_uop_iw_p2_poisoned = r_uops_3_iw_p2_poisoned;
assign io_resp_bits_uop_is_br = r_uops_3_is_br;
assign io_resp_bits_uop_is_jalr = r_uops_3_is_jalr;
assign io_resp_bits_uop_is_jal = r_uops_3_is_jal;
assign io_resp_bits_uop_is_sfb = r_uops_3_is_sfb;
assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0;
assign io_resp_bits_uop_br_tag = r_uops_3_br_tag;
assign io_resp_bits_uop_ftq_idx = r_uops_3_ftq_idx;
assign io_resp_bits_uop_edge_inst = r_uops_3_edge_inst;
assign io_resp_bits_uop_pc_lob = r_uops_3_pc_lob;
assign io_resp_bits_uop_taken = r_uops_3_taken;
assign io_resp_bits_uop_imm_packed = r_uops_3_imm_packed;
assign io_resp_bits_uop_csr_addr = r_uops_3_csr_addr;
assign io_resp_bits_uop_rob_idx = r_uops_3_rob_idx;
assign io_resp_bits_uop_ldq_idx = r_uops_3_ldq_idx;
assign io_resp_bits_uop_stq_idx = r_uops_3_stq_idx;
assign io_resp_bits_uop_rxq_idx = r_uops_3_rxq_idx;
assign io_resp_bits_uop_pdst = r_uops_3_pdst;
assign io_resp_bits_uop_prs1 = r_uops_3_prs1;
assign io_resp_bits_uop_prs2 = r_uops_3_prs2;
assign io_resp_bits_uop_prs3 = r_uops_3_prs3;
assign io_resp_bits_uop_ppred = r_uops_3_ppred;
assign io_resp_bits_uop_prs1_busy = r_uops_3_prs1_busy;
assign io_resp_bits_uop_prs2_busy = r_uops_3_prs2_busy;
assign io_resp_bits_uop_prs3_busy = r_uops_3_prs3_busy;
assign io_resp_bits_uop_ppred_busy = r_uops_3_ppred_busy;
assign io_resp_bits_uop_stale_pdst = r_uops_3_stale_pdst;
assign io_resp_bits_uop_exception = r_uops_3_exception;
assign io_resp_bits_uop_exc_cause = r_uops_3_exc_cause;
assign io_resp_bits_uop_bypassable = r_uops_3_bypassable;
assign io_resp_bits_uop_mem_cmd = r_uops_3_mem_cmd;
assign io_resp_bits_uop_mem_size = r_uops_3_mem_size;
assign io_resp_bits_uop_mem_signed = r_uops_3_mem_signed;
assign io_resp_bits_uop_is_fence = r_uops_3_is_fence;
assign io_resp_bits_uop_is_fencei = r_uops_3_is_fencei;
assign io_resp_bits_uop_is_amo = r_uops_3_is_amo;
assign io_resp_bits_uop_uses_ldq = r_uops_3_uses_ldq;
assign io_resp_bits_uop_uses_stq = r_uops_3_uses_stq;
assign io_resp_bits_uop_is_sys_pc2epc = r_uops_3_is_sys_pc2epc;
assign io_resp_bits_uop_is_unique = r_uops_3_is_unique;
assign io_resp_bits_uop_flush_on_commit = r_uops_3_flush_on_commit;
assign io_resp_bits_uop_ldst_is_rs1 = r_uops_3_ldst_is_rs1;
assign io_resp_bits_uop_ldst = r_uops_3_ldst;
assign io_resp_bits_uop_lrs1 = r_uops_3_lrs1;
assign io_resp_bits_uop_lrs2 = r_uops_3_lrs2;
assign io_resp_bits_uop_lrs3 = r_uops_3_lrs3;
assign io_resp_bits_uop_ldst_val = r_uops_3_ldst_val;
assign io_resp_bits_uop_dst_rtype = r_uops_3_dst_rtype;
assign io_resp_bits_uop_lrs1_rtype = r_uops_3_lrs1_rtype;
assign io_resp_bits_uop_lrs2_rtype = r_uops_3_lrs2_rtype;
assign io_resp_bits_uop_frs3_en = r_uops_3_frs3_en;
assign io_resp_bits_uop_fp_val = r_uops_3_fp_val;
assign io_resp_bits_uop_fp_single = r_uops_3_fp_single;
assign io_resp_bits_uop_xcpt_pf_if = r_uops_3_xcpt_pf_if;
assign io_resp_bits_uop_xcpt_ae_if = r_uops_3_xcpt_ae_if;
assign io_resp_bits_uop_xcpt_ma_if = r_uops_3_xcpt_ma_if;
assign io_resp_bits_uop_bp_debug_if = r_uops_3_bp_debug_if;
assign io_resp_bits_uop_bp_xcpt_if = r_uops_3_bp_xcpt_if;
assign io_resp_bits_uop_debug_fsrc = r_uops_3_debug_fsrc;
assign io_resp_bits_uop_debug_tsrc = r_uops_3_debug_tsrc;
assign io_resp_bits_fflags_bits_uop_uopc = r_uops_3_uopc;
assign io_resp_bits_fflags_bits_uop_inst = r_uops_3_inst;
assign io_resp_bits_fflags_bits_uop_debug_inst = r_uops_3_debug_inst;
assign io_resp_bits_fflags_bits_uop_is_rvc = r_uops_3_is_rvc;
assign io_resp_bits_fflags_bits_uop_debug_pc = r_uops_3_debug_pc;
assign io_resp_bits_fflags_bits_uop_iq_type = r_uops_3_iq_type;
assign io_resp_bits_fflags_bits_uop_fu_code = r_uops_3_fu_code;
assign io_resp_bits_fflags_bits_uop_ctrl_br_type = r_uops_3_ctrl_br_type;
assign io_resp_bits_fflags_bits_uop_ctrl_op1_sel = r_uops_3_ctrl_op1_sel;
assign io_resp_bits_fflags_bits_uop_ctrl_op2_sel = r_uops_3_ctrl_op2_sel;
assign io_resp_bits_fflags_bits_uop_ctrl_imm_sel = r_uops_3_ctrl_imm_sel;
assign io_resp_bits_fflags_bits_uop_ctrl_op_fcn = r_uops_3_ctrl_op_fcn;
assign io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = r_uops_3_ctrl_fcn_dw;
assign io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = r_uops_3_ctrl_csr_cmd;
assign io_resp_bits_fflags_bits_uop_ctrl_is_load = r_uops_3_ctrl_is_load;
assign io_resp_bits_fflags_bits_uop_ctrl_is_sta = r_uops_3_ctrl_is_sta;
assign io_resp_bits_fflags_bits_uop_ctrl_is_std = r_uops_3_ctrl_is_std;
assign io_resp_bits_fflags_bits_uop_iw_state = r_uops_3_iw_state;
assign io_resp_bits_fflags_bits_uop_iw_p1_poisoned = r_uops_3_iw_p1_poisoned;
assign io_resp_bits_fflags_bits_uop_iw_p2_poisoned = r_uops_3_iw_p2_poisoned;
assign io_resp_bits_fflags_bits_uop_is_br = r_uops_3_is_br;
assign io_resp_bits_fflags_bits_uop_is_jalr = r_uops_3_is_jalr;
assign io_resp_bits_fflags_bits_uop_is_jal = r_uops_3_is_jal;
assign io_resp_bits_fflags_bits_uop_is_sfb = r_uops_3_is_sfb;
assign io_resp_bits_fflags_bits_uop_br_mask = io_resp_bits_uop_br_mask_0;
assign io_resp_bits_fflags_bits_uop_br_tag = r_uops_3_br_tag;
assign io_resp_bits_fflags_bits_uop_ftq_idx = r_uops_3_ftq_idx;
assign io_resp_bits_fflags_bits_uop_edge_inst = r_uops_3_edge_inst;
assign io_resp_bits_fflags_bits_uop_pc_lob = r_uops_3_pc_lob;
assign io_resp_bits_fflags_bits_uop_taken = r_uops_3_taken;
assign io_resp_bits_fflags_bits_uop_imm_packed = r_uops_3_imm_packed;
assign io_resp_bits_fflags_bits_uop_csr_addr = r_uops_3_csr_addr;
assign io_resp_bits_fflags_bits_uop_rob_idx = r_uops_3_rob_idx;
assign io_resp_bits_fflags_bits_uop_ldq_idx = r_uops_3_ldq_idx;
assign io_resp_bits_fflags_bits_uop_stq_idx = r_uops_3_stq_idx;
assign io_resp_bits_fflags_bits_uop_rxq_idx = r_uops_3_rxq_idx;
assign io_resp_bits_fflags_bits_uop_pdst = r_uops_3_pdst;
assign io_resp_bits_fflags_bits_uop_prs1 = r_uops_3_prs1;
assign io_resp_bits_fflags_bits_uop_prs2 = r_uops_3_prs2;
assign io_resp_bits_fflags_bits_uop_prs3 = r_uops_3_prs3;
assign io_resp_bits_fflags_bits_uop_ppred = r_uops_3_ppred;
assign io_resp_bits_fflags_bits_uop_prs1_busy = r_uops_3_prs1_busy;
assign io_resp_bits_fflags_bits_uop_prs2_busy = r_uops_3_prs2_busy;
assign io_resp_bits_fflags_bits_uop_prs3_busy = r_uops_3_prs3_busy;
assign io_resp_bits_fflags_bits_uop_ppred_busy = r_uops_3_ppred_busy;
assign io_resp_bits_fflags_bits_uop_stale_pdst = r_uops_3_stale_pdst;
assign io_resp_bits_fflags_bits_uop_exception = r_uops_3_exception;
assign io_resp_bits_fflags_bits_uop_exc_cause = r_uops_3_exc_cause;
assign io_resp_bits_fflags_bits_uop_bypassable = r_uops_3_bypassable;
assign io_resp_bits_fflags_bits_uop_mem_cmd = r_uops_3_mem_cmd;
assign io_resp_bits_fflags_bits_uop_mem_size = r_uops_3_mem_size;
assign io_resp_bits_fflags_bits_uop_mem_signed = r_uops_3_mem_signed;
assign io_resp_bits_fflags_bits_uop_is_fence = r_uops_3_is_fence;
assign io_resp_bits_fflags_bits_uop_is_fencei = r_uops_3_is_fencei;
assign io_resp_bits_fflags_bits_uop_is_amo = r_uops_3_is_amo;
assign io_resp_bits_fflags_bits_uop_uses_ldq = r_uops_3_uses_ldq;
assign io_resp_bits_fflags_bits_uop_uses_stq = r_uops_3_uses_stq;
assign io_resp_bits_fflags_bits_uop_is_sys_pc2epc = r_uops_3_is_sys_pc2epc;
assign io_resp_bits_fflags_bits_uop_is_unique = r_uops_3_is_unique;
assign io_resp_bits_fflags_bits_uop_flush_on_commit = r_uops_3_flush_on_commit;
assign io_resp_bits_fflags_bits_uop_ldst_is_rs1 = r_uops_3_ldst_is_rs1;
assign io_resp_bits_fflags_bits_uop_ldst = r_uops_3_ldst;
assign io_resp_bits_fflags_bits_uop_lrs1 = r_uops_3_lrs1;
assign io_resp_bits_fflags_bits_uop_lrs2 = r_uops_3_lrs2;
assign io_resp_bits_fflags_bits_uop_lrs3 = r_uops_3_lrs3;
assign io_resp_bits_fflags_bits_uop_ldst_val = r_uops_3_ldst_val;
assign io_resp_bits_fflags_bits_uop_dst_rtype = r_uops_3_dst_rtype;
assign io_resp_bits_fflags_bits_uop_lrs1_rtype = r_uops_3_lrs1_rtype;
assign io_resp_bits_fflags_bits_uop_lrs2_rtype = r_uops_3_lrs2_rtype;
assign io_resp_bits_fflags_bits_uop_frs3_en = r_uops_3_frs3_en;
assign io_resp_bits_fflags_bits_uop_fp_val = r_uops_3_fp_val;
assign io_resp_bits_fflags_bits_uop_fp_single = r_uops_3_fp_single;
assign io_resp_bits_fflags_bits_uop_xcpt_pf_if = r_uops_3_xcpt_pf_if;
assign io_resp_bits_fflags_bits_uop_xcpt_ae_if = r_uops_3_xcpt_ae_if;
assign io_resp_bits_fflags_bits_uop_xcpt_ma_if = r_uops_3_xcpt_ma_if;
assign io_resp_bits_fflags_bits_uop_bp_debug_if = r_uops_3_bp_debug_if;
assign io_resp_bits_fflags_bits_uop_bp_xcpt_if = r_uops_3_bp_xcpt_if;
assign io_resp_bits_fflags_bits_uop_debug_fsrc = r_uops_3_debug_fsrc;
assign io_resp_bits_fflags_bits_uop_debug_tsrc = r_uops_3_debug_tsrc;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.experimental.SourceInfo
import chisel3.util._
import freechips.rocketchip.diplomacy.AddressDecoder
import freechips.rocketchip.util.{BundleFieldBase, BundleMap, MuxSeq, ReduceOthers, property}
// A bus agnostic register interface to a register-based device
case class RegMapperParams(indexBits: Int, maskBits: Int, extraFields: Seq[BundleFieldBase] = Nil)
class RegMapperInput(val params: RegMapperParams) extends Bundle
{
val read = Bool()
val index = UInt((params.indexBits).W)
val data = UInt((params.maskBits*8).W)
val mask = UInt((params.maskBits).W)
val extra = BundleMap(params.extraFields)
}
class RegMapperOutput(val params: RegMapperParams) extends Bundle
{
val read = Bool()
val data = UInt((params.maskBits*8).W)
val extra = BundleMap(params.extraFields)
}
object RegMapper
{
// Create a generic register-based device
def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*)(implicit sourceInfo: SourceInfo) = {
// Filter out zero-width fields
val bytemap = mapping.toList.map { case (offset, fields) => (offset, fields.filter(_.width != 0)) }
// Negative addresses are bad
bytemap.foreach { byte => require (byte._1 >= 0) }
// Transform all fields into bit offsets Seq[(bit, field)]
val bitmap = bytemap.map { case (byte, fields) =>
val bits = fields.scanLeft(byte * 8)(_ + _.width).init
bits zip fields
}.flatten.sortBy(_._1)
// Detect overlaps
(bitmap.init zip bitmap.tail) foreach { case ((lbit, lfield), (rbit, rfield)) =>
require (lbit + lfield.width <= rbit, s"Register map overlaps at bit ${rbit}.")
}
// Group those fields into bus words Map[word, List[(bit, field)]]
val wordmap = bitmap.groupBy(_._1 / (8*bytes))
// Make sure registers fit
val inParams = in.bits.params
val inBits = inParams.indexBits
assert (wordmap.keySet.max < (1 << inBits), "Register map does not fit in device")
val out = Wire(Decoupled(new RegMapperOutput(inParams)))
val front = Wire(Decoupled(new RegMapperInput(inParams)))
front.bits := in.bits
// Must this device pipeline the control channel?
val pipelined = wordmap.values.map(_.map(_._2.pipelined)).flatten.reduce(_ || _)
val depth = concurrency
require (depth >= 0)
require (!pipelined || depth > 0, "Register-based device with request/response handshaking needs concurrency > 0")
val back = if (depth > 0) {
val front_q = Module(new Queue(new RegMapperInput(inParams), depth) {
override def desiredName = s"Queue${depth}_${front.bits.typeName}_i${inParams.indexBits}_m${inParams.maskBits}"
})
front_q.io.enq <> front
front_q.io.deq
} else front
// Convert to and from Bits
def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =
if (x == 0) tail.reverse else toBits(x >> 1, ((x & 1) == 1) :: tail)
def ofBits(bits: List[Boolean]) = bits.foldRight(0){ case (x,y) => (if (x) 1 else 0) | y << 1 }
// Find the minimal mask that can decide the register map
val mask = AddressDecoder(wordmap.keySet.toList)
val maskMatch = ~mask.U(inBits.W)
val maskFilter = toBits(mask)
val maskBits = maskFilter.filter(x => x).size
// Calculate size and indexes into the register map
val regSize = 1 << maskBits
def regIndexI(x: Int) = ofBits((maskFilter zip toBits(x)).filter(_._1).map(_._2))
def regIndexU(x: UInt) = if (maskBits == 0) 0.U else
Cat((maskFilter zip x.asBools).filter(_._1).map(_._2).reverse)
val findex = front.bits.index & maskMatch
val bindex = back .bits.index & maskMatch
// Protection flag for undefined registers
val iRightReg = Array.fill(regSize) { true.B }
val oRightReg = Array.fill(regSize) { true.B }
// Transform the wordmap into minimal decoded indexes, Seq[(index, bit, field)]
val flat = wordmap.toList.map { case (word, fields) =>
val index = regIndexI(word)
if (undefZero) {
val uint = (word & ~mask).U(inBits.W)
iRightReg(index) = findex === uint
oRightReg(index) = bindex === uint
}
// Confirm that no field spans a word boundary
fields foreach { case (bit, field) =>
val off = bit - 8*bytes*word
// println(s"Reg ${word}: [${off}, ${off+field.width})")
require (off + field.width <= bytes * 8, s"Field at word ${word}*(${bytes}B) has bits [${off}, ${off+field.width}), which exceeds word limit.")
}
// println("mapping 0x%x -> 0x%x for 0x%x/%d".format(word, index, mask, maskBits))
fields.map { case (bit, field) => (index, bit-8*bytes*word, field) }
}.flatten
// Forward declaration of all flow control signals
val rivalid = Wire(Vec(flat.size, Bool()))
val wivalid = Wire(Vec(flat.size, Bool()))
val roready = Wire(Vec(flat.size, Bool()))
val woready = Wire(Vec(flat.size, Bool()))
// Per-register list of all control signals needed for data to flow
val rifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val wifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val rofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val wofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
// The output values for each register
val dataOut = Array.fill(regSize) { 0.U }
// Which bits are touched?
val frontMask = FillInterleaved(8, front.bits.mask)
val backMask = FillInterleaved(8, back .bits.mask)
// Connect the fields
for (i <- 0 until flat.size) {
val (reg, low, field) = flat(i)
val high = low + field.width - 1
// Confirm that no register is too big
require (high < 8*bytes)
val rimask = frontMask(high, low).orR
val wimask = frontMask(high, low).andR
val romask = backMask(high, low).orR
val womask = backMask(high, low).andR
val data = if (field.write.combinational) back.bits.data else front.bits.data
val f_rivalid = rivalid(i) && rimask
val f_roready = roready(i) && romask
val f_wivalid = wivalid(i) && wimask
val f_woready = woready(i) && womask
val (f_riready, f_rovalid, f_data) = field.read.fn(f_rivalid, f_roready)
val (f_wiready, f_wovalid) = field.write.fn(f_wivalid, f_woready, data(high, low))
// cover reads and writes to register
val fname = field.desc.map{_.name}.getOrElse("")
val fdesc = field.desc.map{_.desc + ":"}.getOrElse("")
val facct = field.desc.map{_.access}.getOrElse("")
if((facct == RegFieldAccessType.R) || (facct == RegFieldAccessType.RW)) {
property.cover(f_rivalid && f_riready, fname + "_Reg_read_start", fdesc + " RegField Read Request Initiate")
property.cover(f_rovalid && f_roready, fname + "_Reg_read_out", fdesc + " RegField Read Request Complete")
}
if((facct == RegFieldAccessType.W) || (facct == RegFieldAccessType.RW)) {
property.cover(f_wivalid && f_wiready, fname + "_Reg_write_start", fdesc + " RegField Write Request Initiate")
property.cover(f_wovalid && f_woready, fname + "_Reg_write_out", fdesc + " RegField Write Request Complete")
}
def litOR(x: Bool, y: Bool) = if (x.isLit && x.litValue == 1) true.B else x || y
// Add this field to the ready-valid signals for the register
rifire(reg) = (rivalid(i), litOR(f_riready, !rimask)) +: rifire(reg)
wifire(reg) = (wivalid(i), litOR(f_wiready, !wimask)) +: wifire(reg)
rofire(reg) = (roready(i), litOR(f_rovalid, !romask)) +: rofire(reg)
wofire(reg) = (woready(i), litOR(f_wovalid, !womask)) +: wofire(reg)
// ... this loop iterates from smallest to largest bit offset
val prepend = if (low == 0) { f_data } else { Cat(f_data, dataOut(reg) | 0.U(low.W)) }
dataOut(reg) = (prepend | 0.U((high+1).W))(high, 0)
}
// Which register is touched?
val iindex = regIndexU(front.bits.index)
val oindex = regIndexU(back .bits.index)
val frontSel = UIntToOH(iindex).asBools
val backSel = UIntToOH(oindex).asBools
// Compute: is the selected register ready? ... and cross-connect all ready-valids
def mux(index: UInt, valid: Bool, select: Seq[Bool], guard: Seq[Bool], flow: Seq[Seq[(Bool, Bool)]]): Bool =
MuxSeq(index, true.B, ((select zip guard) zip flow).map { case ((s, g), f) =>
val out = Wire(Bool())
ReduceOthers((out, valid && s && g) +: f)
out || !g
})
// Include the per-register one-hot selected criteria
val rifireMux = mux(iindex, in.valid && front.ready && front.bits.read, frontSel, iRightReg, rifire)
val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg, wifire)
val rofireMux = mux(oindex, back.valid && out.ready && back .bits.read, backSel, oRightReg, rofire)
val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel, oRightReg, wofire)
val iready = Mux(front.bits.read, rifireMux, wifireMux)
val oready = Mux(back .bits.read, rofireMux, wofireMux)
// Connect the pipeline
in.ready := front.ready && iready
front.valid := in.valid && iready
back.ready := out.ready && oready
out.valid := back.valid && oready
out.bits.read := back.bits.read
out.bits.data := Mux(MuxSeq(oindex, true.B, oRightReg),
MuxSeq(oindex, 0.U, dataOut),
0.U)
out.bits.extra := back.bits.extra
out
}
} | module Queue1_RegMapperInput_i23_m8(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input io_enq_bits_read,
input [22:0] io_enq_bits_index,
input [63:0] io_enq_bits_data,
input [7:0] io_enq_bits_mask,
input [10:0] io_enq_bits_extra_tlrr_extra_source,
input [1:0] io_enq_bits_extra_tlrr_extra_size,
input io_deq_ready,
output io_deq_valid,
output io_deq_bits_read,
output [22:0] io_deq_bits_index,
output [63:0] io_deq_bits_data,
output [7:0] io_deq_bits_mask,
output [10:0] io_deq_bits_extra_tlrr_extra_source,
output [1:0] io_deq_bits_extra_tlrr_extra_size
);
reg [108:0] ram;
reg full;
wire do_enq = ~full & io_enq_valid;
always @(posedge clock) begin
if (do_enq)
ram <= {io_enq_bits_extra_tlrr_extra_size, io_enq_bits_extra_tlrr_extra_source, io_enq_bits_mask, io_enq_bits_data, io_enq_bits_index, io_enq_bits_read};
if (reset)
full <= 1'h0;
else if (~(do_enq == (io_deq_ready & full)))
full <= do_enq;
end
assign io_enq_ready = ~full;
assign io_deq_valid = full;
assign io_deq_bits_read = ram[0];
assign io_deq_bits_index = ram[23:1];
assign io_deq_bits_data = ram[87:24];
assign io_deq_bits_mask = ram[95:88];
assign io_deq_bits_extra_tlrr_extra_source = ram[106:96];
assign io_deq_bits_extra_tlrr_extra_size = ram[108:107];
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
} | module Repeater_TLBundleA_a13d64s7k1z3u(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [6:0] io_enq_bits_source,
input [12:0] io_enq_bits_address,
input [7:0] io_enq_bits_mask,
input io_enq_bits_corrupt,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [6:0] io_deq_bits_source,
output [12:0] io_deq_bits_address,
output [7:0] io_deq_bits_mask,
output io_deq_bits_corrupt
);
reg full;
reg [2:0] saved_opcode;
reg [2:0] saved_param;
reg [2:0] saved_size;
reg [6:0] saved_source;
reg [12:0] saved_address;
reg [7:0] saved_mask;
reg saved_corrupt;
wire io_deq_valid_0 = io_enq_valid | full;
wire io_enq_ready_0 = io_deq_ready & ~full;
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;
always @(posedge clock) begin
if (reset)
full <= 1'h0;
else
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);
if (_GEN) begin
saved_opcode <= io_enq_bits_opcode;
saved_param <= io_enq_bits_param;
saved_size <= io_enq_bits_size;
saved_source <= io_enq_bits_source;
saved_address <= io_enq_bits_address;
saved_mask <= io_enq_bits_mask;
saved_corrupt <= io_enq_bits_corrupt;
end
end
assign io_full = full;
assign io_enq_ready = io_enq_ready_0;
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericDeserializer_TLBeatw87_f32_TestHarness_UNIQUIFIED(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output io_out_bits_head,
output io_out_bits_tail
);
reg [31:0] data_0;
reg [31:0] data_1;
reg [1:0] beat;
wire io_in_ready_0 = io_out_ready | beat != 2'h2;
wire _beat_T = beat == 2'h2;
wire _GEN = io_in_ready_0 & io_in_valid;
wire _GEN_0 = beat == 2'h2;
always @(posedge clock) begin
if (~_GEN | _GEN_0 | beat[0]) begin
end
else
data_0 <= io_in_bits_flit;
if (~_GEN | _GEN_0 | ~(beat[0])) begin
end
else
data_1 <= io_in_bits_flit;
if (reset)
beat <= 2'h0;
else if (_GEN)
beat <= _beat_T ? 2'h0 : beat + 2'h1;
end
assign io_in_ready = io_in_ready_0;
assign io_out_valid = io_in_valid & _beat_T;
assign io_out_bits_head = data_0[1];
assign io_out_bits_tail = data_0[0];
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// If regfile bypassing is disabled, then the functional unit must do its own
// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)
//
// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import freechips.rocketchip.tile
import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}
import boom.v3.common._
import boom.v3.ifu._
import boom.v3.util._
/**t
* Functional unit constants
*/
object FUConstants
{
// bit mask, since a given execution pipeline may support multiple functional units
val FUC_SZ = 10
val FU_X = BitPat.dontCare(FUC_SZ)
val FU_ALU = 1.U(FUC_SZ.W)
val FU_JMP = 2.U(FUC_SZ.W)
val FU_MEM = 4.U(FUC_SZ.W)
val FU_MUL = 8.U(FUC_SZ.W)
val FU_DIV = 16.U(FUC_SZ.W)
val FU_CSR = 32.U(FUC_SZ.W)
val FU_FPU = 64.U(FUC_SZ.W)
val FU_FDV = 128.U(FUC_SZ.W)
val FU_I2F = 256.U(FUC_SZ.W)
val FU_F2I = 512.U(FUC_SZ.W)
// FP stores generate data through FP F2I, and generate address through MemAddrCalc
val FU_F2IMEM = 516.U(FUC_SZ.W)
}
import FUConstants._
/**
* Class to tell the FUDecoders what units it needs to support
*
* @param alu support alu unit?
* @param bru support br unit?
* @param mem support mem unit?
* @param muld support multiple div unit?
* @param fpu support FP unit?
* @param csr support csr writing unit?
* @param fdiv support FP div unit?
* @param ifpu support int to FP unit?
*/
class SupportedFuncUnits(
val alu: Boolean = false,
val jmp: Boolean = false,
val mem: Boolean = false,
val muld: Boolean = false,
val fpu: Boolean = false,
val csr: Boolean = false,
val fdiv: Boolean = false,
val ifpu: Boolean = false)
{
}
/**
* Bundle for signals sent to the functional unit
*
* @param dataWidth width of the data sent to the functional unit
*/
class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val numOperands = 3
val rs1_data = UInt(dataWidth.W)
val rs2_data = UInt(dataWidth.W)
val rs3_data = UInt(dataWidth.W) // only used for FMA units
val pred_data = Bool()
val kill = Bool() // kill everything
}
/**
* Bundle for the signals sent out of the function unit
*
* @param dataWidth data sent from the functional unit
*/
class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val predicated = Bool() // Was this response from a predicated-off instruction
val data = UInt(dataWidth.W)
val fflags = new ValidIO(new FFlagsResp)
val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU
val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU
val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc
}
/**
* Branch resolution information given from the branch unit
*/
class BrResolutionInfo(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp
val valid = Bool()
val mispredict = Bool()
val taken = Bool() // which direction did the branch go?
val cfi_type = UInt(CFI_SZ.W)
// Info for recalculating the pc for this branch
val pc_sel = UInt(2.W)
val jalr_target = UInt(vaddrBitsExtended.W)
val target_offset = SInt()
}
class BrUpdateInfo(implicit p: Parameters) extends BoomBundle
{
// On the first cycle we get masks to kill registers
val b1 = new BrUpdateMasks
// On the second cycle we get indices to reset pointers
val b2 = new BrResolutionInfo
}
class BrUpdateMasks(implicit p: Parameters) extends BoomBundle
{
val resolve_mask = UInt(maxBrCount.W)
val mispredict_mask = UInt(maxBrCount.W)
}
/**
* Abstract top level functional unit class that wraps a lower level hand made functional unit
*
* @param isPipelined is the functional unit pipelined?
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class FunctionalUnit(
val isPipelined: Boolean,
val numStages: Int,
val numBypassStages: Int,
val dataWidth: Int,
val isJmpUnit: Boolean = false,
val isAluUnit: Boolean = false,
val isMemAddrCalcUnit: Boolean = false,
val needsFcsr: Boolean = false)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))
val brupdate = Input(new BrUpdateInfo())
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
// only used by the fpu unit
val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null
// only used by branch unit
val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null
// only used by memaddr calc unit
val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null
})
io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }
io.resp.valid := false.B
io.resp.bits := DontCare
if (isJmpUnit) {
io.get_ftq_pc.ftq_idx := DontCare
}
}
/**
* Abstract top level pipelined functional unit
*
* Note: this helps track which uops get killed while in intermediate stages,
* but it is the job of the consumer to check for kills on the same cycle as consumption!!!
*
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param earliestBypassStage first stage that you can start bypassing from
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class PipelinedFunctionalUnit(
numStages: Int,
numBypassStages: Int,
earliestBypassStage: Int,
dataWidth: Int,
isJmpUnit: Boolean = false,
isAluUnit: Boolean = false,
isMemAddrCalcUnit: Boolean = false,
needsFcsr: Boolean = false
)(implicit p: Parameters) extends FunctionalUnit(
isPipelined = true,
numStages = numStages,
numBypassStages = numBypassStages,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit,
isAluUnit = isAluUnit,
isMemAddrCalcUnit = isMemAddrCalcUnit,
needsFcsr = needsFcsr)
{
// Pipelined functional unit is always ready.
io.req.ready := true.B
if (numStages > 0) {
val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_uops = Reg(Vec(numStages, new MicroOp()))
// handle incoming request
r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill
r_uops(0) := io.req.bits.uop
r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
// handle middle of the pipeline
for (i <- 1 until numStages) {
r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill
r_uops(i) := r_uops(i-1)
r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))
if (numBypassStages > 0) {
io.bypass(i-1).bits.uop := r_uops(i-1)
}
}
// handle outgoing (branch could still kill it)
// consumer must also check for pipeline flushes (kills)
io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))
io.resp.bits.predicated := false.B
io.resp.bits.uop := r_uops(numStages-1)
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))
// bypassing (TODO allow bypass vector to have a different size from numStages)
if (numBypassStages > 0 && earliestBypassStage == 0) {
io.bypass(0).bits.uop := io.req.bits.uop
for (i <- 1 until numBypassStages) {
io.bypass(i).bits.uop := r_uops(i-1)
}
}
} else {
require (numStages == 0)
// pass req straight through to response
// valid doesn't check kill signals, let consumer deal with it.
// The LSU already handles it and this hurts critical path.
io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
io.resp.bits.predicated := false.B
io.resp.bits.uop := io.req.bits.uop
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
}
}
/**
* Functional unit that wraps RocketChips ALU
*
* @param isBranchUnit is this a branch unit?
* @param numStages how many pipeline stages does the functional unit have
* @param dataWidth width of the data being operated on in the functional unit
*/
class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = numStages,
isAluUnit = true,
earliestBypassStage = 0,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit)
with boom.v3.ifu.HasBoomFrontendParameters
{
val uop = io.req.bits.uop
// immediate generation
val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)
// operand 1 select
var op1_data: UInt = null
if (isJmpUnit) {
// Get the uop PC for jumps
val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)
val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),
0.U))
} else {
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
0.U)
}
// operand 2 select
val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),
Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),
Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,
Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),
0.U))))
val alu = Module(new freechips.rocketchip.rocket.ALU())
alu.io.in1 := op1_data.asUInt
alu.io.in2 := op2_data.asUInt
alu.io.fn := uop.ctrl.op_fcn
alu.io.dw := uop.ctrl.fcn_dw
// Did I just get killed by the previous cycle's branch,
// or by a flush pipeline?
val killed = WireInit(false.B)
when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {
killed := true.B
}
val rs1 = io.req.bits.rs1_data
val rs2 = io.req.bits.rs2_data
val br_eq = (rs1 === rs2)
val br_ltu = (rs1.asUInt < rs2.asUInt)
val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |
rs1(xLen-1) & ~rs2(xLen-1)).asBool
val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(
Seq( BR_N -> PC_PLUS4,
BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),
BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),
BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),
BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),
BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),
BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),
BR_J -> PC_BRJMP,
BR_JR -> PC_JALR
))
val is_taken = io.req.valid &&
!killed &&
(uop.is_br || uop.is_jalr || uop.is_jal) &&
(pc_sel =/= PC_PLUS4)
// "mispredict" means that a branch has been resolved and it must be killed
val mispredict = WireInit(false.B)
val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb
val is_jal = io.req.valid && !killed && uop.is_jal
val is_jalr = io.req.valid && !killed && uop.is_jalr
when (is_br || is_jalr) {
if (!isJmpUnit) {
assert (pc_sel =/= PC_JALR)
}
when (pc_sel === PC_PLUS4) {
mispredict := uop.taken
}
when (pc_sel === PC_BRJMP) {
mispredict := !uop.taken
}
}
val brinfo = Wire(new BrResolutionInfo)
// note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit
brinfo.valid := is_br || is_jalr
brinfo.mispredict := mispredict
brinfo.uop := uop
brinfo.cfi_type := Mux(is_jalr, CFI_JALR,
Mux(is_br , CFI_BR, CFI_X))
brinfo.taken := is_taken
brinfo.pc_sel := pc_sel
brinfo.jalr_target := DontCare
// Branch/Jump Target Calculation
// For jumps we read the FTQ, and can calculate the target
// For branches we emit the offset for the core to redirect if necessary
val target_offset = imm_xprlen(20,0).asSInt
brinfo.jalr_target := DontCare
if (isJmpUnit) {
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {
ea
} else {
// Efficient means to compress 64-bit VA into vaddrBits+1 bits.
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
}
val jalr_target_base = io.req.bits.rs1_data.asSInt
val jalr_target_xlen = Wire(UInt(xLen.W))
jalr_target_xlen := (jalr_target_base + target_offset).asUInt
val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt
brinfo.jalr_target := jalr_target
val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)
when (pc_sel === PC_JALR) {
mispredict := !io.get_ftq_pc.next_val ||
(io.get_ftq_pc.next_pc =/= jalr_target) ||
!io.get_ftq_pc.entry.cfi_idx.valid ||
(io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)
}
}
brinfo.target_offset := target_offset
io.brinfo := brinfo
// Response
// TODO add clock gate on resp bits from functional units
// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)
// val reg_data = Reg(outType = Bits(width = xLen))
// reg_data := alu.io.out
// io.resp.bits.data := reg_data
val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_data = Reg(Vec(numStages, UInt(xLen.W)))
val r_pred = Reg(Vec(numStages, Bool()))
val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,
Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),
Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))
r_val (0) := io.req.valid
r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data
for (i <- 1 until numStages) {
r_val(i) := r_val(i-1)
r_data(i) := r_data(i-1)
r_pred(i) := r_pred(i-1)
}
io.resp.bits.data := r_data(numStages-1)
io.resp.bits.predicated := r_pred(numStages-1)
// Bypass
// for the ALU, we can bypass same cycle as compute
require (numStages >= 1)
require (numBypassStages >= 1)
io.bypass(0).valid := io.req.valid
io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
for (i <- 1 until numStages) {
io.bypass(i).valid := r_val(i-1)
io.bypass(i).bits.data := r_data(i-1)
}
// Exceptions
io.resp.bits.fflags.valid := false.B
}
/**
* Functional unit that passes in base+imm to calculate addresses, and passes store data
* to the LSU.
* For floating point, 65bit FP store-data needs to be decoded into 64bit FP form
*/
class MemAddrCalcUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = 0,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65, // TODO enable this only if FP is enabled?
isMemAddrCalcUnit = true)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
// perform address calculation
val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt
val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,
sum(63,vaddrBits) =/= 0.U)
val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt
val store_data = io.req.bits.rs2_data
io.resp.bits.addr := effective_address
io.resp.bits.data := store_data
if (dataWidth > 63) {
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&
io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.")
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),
"FP store-data should now be going through a different unit.")
}
assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=
uopLD && io.req.bits.uop.uopc =/= uopSTA),
"[maddrcalc] assert we never get store data in here.")
// Handle misaligned exceptions
val size = io.req.bits.uop.mem_size
val misaligned =
(size === 1.U && (effective_address(0) =/= 0.U)) ||
(size === 2.U && (effective_address(1,0) =/= 0.U)) ||
(size === 3.U && (effective_address(2,0) =/= 0.U))
val bkptu = Module(new BreakpointUnit(nBreakpoints))
bkptu.io.status := io.status
bkptu.io.bp := io.bp
bkptu.io.pc := DontCare
bkptu.io.ea := effective_address
bkptu.io.mcontext := io.mcontext
bkptu.io.scontext := io.scontext
val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned
val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned
val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))
val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_val, xcpt_cause) = checkExceptions(List(
(ma_ld, (Causes.misaligned_load).U),
(ma_st, (Causes.misaligned_store).U),
(dbg_bp, (CSR.debugTriggerCause).U),
(bp, (Causes.breakpoint).U)))
io.resp.bits.mxcpt.valid := xcpt_val
io.resp.bits.mxcpt.bits := xcpt_cause
assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.")
io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE
io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)
io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)
io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data
io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data
}
/**
* Functional unit to wrap lower level FPU
*
* Currently, bypassing is unsupported!
* All FP instructions are padded out to the max latency unit for easy
* write-port scheduling.
*/
class FPUUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
{
val fpu = Module(new FPU())
fpu.io.req.valid := io.req.valid
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.fcsr_rm := io.fcsr_rm
io.resp.bits.data := fpu.io.resp.bits.data
io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now
}
/**
* Int to FP conversion functional unit
*
* @param latency the amount of stages to delay by
*/
class IntToFPUnit(latency: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = latency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
with tile.HasFPUParameters
{
val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder
val io_req = io.req.bits
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, None)
req.in2 := unbox(io_req.rs2_data, tag, None)
req.in3 := DontCare
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := DontCare // FIXME: this may not be the right thing to do here
req.fmaCmd := DontCare
assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),
"[func] IntToFP integer input has 65th high-order bit set!")
assert (!(io.req.valid && !fp_ctrl.fromint),
"[func] Only support fromInt micro-ops.")
val ifpu = Module(new tile.IntToFP(intToFpLatency))
ifpu.io.in.valid := io.req.valid
ifpu.io.in.bits := req
ifpu.io.in.bits.in1 := io_req.rs1_data
val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits
//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)
io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)
io.resp.bits.fflags.valid := ifpu.io.out.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc
}
/**
* Iterative/unpipelined functional unit, can only hold a single MicroOp at a time
* assumes at least one register between request and response
*
* TODO allow up to N micro-ops simultaneously.
*
* @param dataWidth width of the data to be passed into the functional unit
*/
abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)
extends FunctionalUnit(
isPipelined = false,
numStages = 1,
numBypassStages = 0,
dataWidth = dataWidth)
{
val r_uop = Reg(new MicroOp())
val do_kill = Wire(Bool())
do_kill := io.req.bits.kill // irrelevant default
when (io.req.fire) {
// update incoming uop
do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill
r_uop := io.req.bits.uop
r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
} .otherwise {
do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill
r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)
}
// assumes at least one pipeline register between request and response
io.resp.bits.uop := r_uop
}
/**
* Divide functional unit.
*
* @param dataWidth data to be passed into the functional unit
*/
class DivUnit(dataWidth: Int)(implicit p: Parameters)
extends IterativeFunctionalUnit(dataWidth)
{
// We don't use the iterative multiply functionality here.
// Instead we use the PipelinedMultiplier
val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))
// request
div.io.req.valid := io.req.valid && !this.do_kill
div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
div.io.req.bits.in1 := io.req.bits.rs1_data
div.io.req.bits.in2 := io.req.bits.rs2_data
div.io.req.bits.tag := DontCare
io.req.ready := div.io.req.ready
// handle pipeline kills and branch misspeculations
div.io.kill := this.do_kill
// response
io.resp.valid := div.io.resp.valid && !this.do_kill
div.io.resp.ready := io.resp.ready
io.resp.bits.data := div.io.resp.bits.data
}
/**
* Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier
*
* @param numStages number of pipeline stages
* @param dataWidth size of the data being passed into the functional unit
*/
class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = dataWidth)
{
val imul = Module(new PipelinedMultiplier(xLen, numStages))
// request
imul.io.req.valid := io.req.valid
imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
imul.io.req.bits.in1 := io.req.bits.rs1_data
imul.io.req.bits.in2 := io.req.bits.rs2_data
imul.io.req.bits.tag := DontCare
// response
io.resp.bits.data := imul.io.resp.bits.data
} | module MemAddrCalcUnit(
input clock,
input reset,
input io_req_valid,
input [6:0] io_req_bits_uop_uopc,
input [31:0] io_req_bits_uop_inst,
input [31:0] io_req_bits_uop_debug_inst,
input io_req_bits_uop_is_rvc,
input [39:0] io_req_bits_uop_debug_pc,
input [2:0] io_req_bits_uop_iq_type,
input [9:0] io_req_bits_uop_fu_code,
input [3:0] io_req_bits_uop_ctrl_br_type,
input [1:0] io_req_bits_uop_ctrl_op1_sel,
input [2:0] io_req_bits_uop_ctrl_op2_sel,
input [2:0] io_req_bits_uop_ctrl_imm_sel,
input [4:0] io_req_bits_uop_ctrl_op_fcn,
input io_req_bits_uop_ctrl_fcn_dw,
input [2:0] io_req_bits_uop_ctrl_csr_cmd,
input io_req_bits_uop_ctrl_is_load,
input io_req_bits_uop_ctrl_is_sta,
input io_req_bits_uop_ctrl_is_std,
input [1:0] io_req_bits_uop_iw_state,
input io_req_bits_uop_is_br,
input io_req_bits_uop_is_jalr,
input io_req_bits_uop_is_jal,
input io_req_bits_uop_is_sfb,
input [7:0] io_req_bits_uop_br_mask,
input [2:0] io_req_bits_uop_br_tag,
input [3:0] io_req_bits_uop_ftq_idx,
input io_req_bits_uop_edge_inst,
input [5:0] io_req_bits_uop_pc_lob,
input io_req_bits_uop_taken,
input [19:0] io_req_bits_uop_imm_packed,
input [11:0] io_req_bits_uop_csr_addr,
input [4:0] io_req_bits_uop_rob_idx,
input [2:0] io_req_bits_uop_ldq_idx,
input [2:0] io_req_bits_uop_stq_idx,
input [1:0] io_req_bits_uop_rxq_idx,
input [5:0] io_req_bits_uop_pdst,
input [5:0] io_req_bits_uop_prs1,
input [5:0] io_req_bits_uop_prs2,
input [5:0] io_req_bits_uop_prs3,
input [3:0] io_req_bits_uop_ppred,
input io_req_bits_uop_prs1_busy,
input io_req_bits_uop_prs2_busy,
input io_req_bits_uop_prs3_busy,
input io_req_bits_uop_ppred_busy,
input [5:0] io_req_bits_uop_stale_pdst,
input io_req_bits_uop_exception,
input [63:0] io_req_bits_uop_exc_cause,
input io_req_bits_uop_bypassable,
input [4:0] io_req_bits_uop_mem_cmd,
input [1:0] io_req_bits_uop_mem_size,
input io_req_bits_uop_mem_signed,
input io_req_bits_uop_is_fence,
input io_req_bits_uop_is_fencei,
input io_req_bits_uop_is_amo,
input io_req_bits_uop_uses_ldq,
input io_req_bits_uop_uses_stq,
input io_req_bits_uop_is_sys_pc2epc,
input io_req_bits_uop_is_unique,
input io_req_bits_uop_flush_on_commit,
input io_req_bits_uop_ldst_is_rs1,
input [5:0] io_req_bits_uop_ldst,
input [5:0] io_req_bits_uop_lrs1,
input [5:0] io_req_bits_uop_lrs2,
input [5:0] io_req_bits_uop_lrs3,
input io_req_bits_uop_ldst_val,
input [1:0] io_req_bits_uop_dst_rtype,
input [1:0] io_req_bits_uop_lrs1_rtype,
input [1:0] io_req_bits_uop_lrs2_rtype,
input io_req_bits_uop_frs3_en,
input io_req_bits_uop_fp_val,
input io_req_bits_uop_fp_single,
input io_req_bits_uop_xcpt_pf_if,
input io_req_bits_uop_xcpt_ae_if,
input io_req_bits_uop_xcpt_ma_if,
input io_req_bits_uop_bp_debug_if,
input io_req_bits_uop_bp_xcpt_if,
input [1:0] io_req_bits_uop_debug_fsrc,
input [1:0] io_req_bits_uop_debug_tsrc,
input [64:0] io_req_bits_rs1_data,
input [64:0] io_req_bits_rs2_data,
output io_resp_valid,
output [6:0] io_resp_bits_uop_uopc,
output [31:0] io_resp_bits_uop_inst,
output [31:0] io_resp_bits_uop_debug_inst,
output io_resp_bits_uop_is_rvc,
output [39:0] io_resp_bits_uop_debug_pc,
output [2:0] io_resp_bits_uop_iq_type,
output [9:0] io_resp_bits_uop_fu_code,
output [3:0] io_resp_bits_uop_ctrl_br_type,
output [1:0] io_resp_bits_uop_ctrl_op1_sel,
output [2:0] io_resp_bits_uop_ctrl_op2_sel,
output [2:0] io_resp_bits_uop_ctrl_imm_sel,
output [4:0] io_resp_bits_uop_ctrl_op_fcn,
output io_resp_bits_uop_ctrl_fcn_dw,
output [2:0] io_resp_bits_uop_ctrl_csr_cmd,
output io_resp_bits_uop_ctrl_is_load,
output io_resp_bits_uop_ctrl_is_sta,
output io_resp_bits_uop_ctrl_is_std,
output [1:0] io_resp_bits_uop_iw_state,
output io_resp_bits_uop_is_br,
output io_resp_bits_uop_is_jalr,
output io_resp_bits_uop_is_jal,
output io_resp_bits_uop_is_sfb,
output [7:0] io_resp_bits_uop_br_mask,
output [2:0] io_resp_bits_uop_br_tag,
output [3:0] io_resp_bits_uop_ftq_idx,
output io_resp_bits_uop_edge_inst,
output [5:0] io_resp_bits_uop_pc_lob,
output io_resp_bits_uop_taken,
output [19:0] io_resp_bits_uop_imm_packed,
output [11:0] io_resp_bits_uop_csr_addr,
output [4:0] io_resp_bits_uop_rob_idx,
output [2:0] io_resp_bits_uop_ldq_idx,
output [2:0] io_resp_bits_uop_stq_idx,
output [1:0] io_resp_bits_uop_rxq_idx,
output [5:0] io_resp_bits_uop_pdst,
output [5:0] io_resp_bits_uop_prs1,
output [5:0] io_resp_bits_uop_prs2,
output [5:0] io_resp_bits_uop_prs3,
output [3:0] io_resp_bits_uop_ppred,
output io_resp_bits_uop_prs1_busy,
output io_resp_bits_uop_prs2_busy,
output io_resp_bits_uop_prs3_busy,
output io_resp_bits_uop_ppred_busy,
output [5:0] io_resp_bits_uop_stale_pdst,
output io_resp_bits_uop_exception,
output [63:0] io_resp_bits_uop_exc_cause,
output io_resp_bits_uop_bypassable,
output [4:0] io_resp_bits_uop_mem_cmd,
output [1:0] io_resp_bits_uop_mem_size,
output io_resp_bits_uop_mem_signed,
output io_resp_bits_uop_is_fence,
output io_resp_bits_uop_is_fencei,
output io_resp_bits_uop_is_amo,
output io_resp_bits_uop_uses_ldq,
output io_resp_bits_uop_uses_stq,
output io_resp_bits_uop_is_sys_pc2epc,
output io_resp_bits_uop_is_unique,
output io_resp_bits_uop_flush_on_commit,
output io_resp_bits_uop_ldst_is_rs1,
output [5:0] io_resp_bits_uop_ldst,
output [5:0] io_resp_bits_uop_lrs1,
output [5:0] io_resp_bits_uop_lrs2,
output [5:0] io_resp_bits_uop_lrs3,
output io_resp_bits_uop_ldst_val,
output [1:0] io_resp_bits_uop_dst_rtype,
output [1:0] io_resp_bits_uop_lrs1_rtype,
output [1:0] io_resp_bits_uop_lrs2_rtype,
output io_resp_bits_uop_frs3_en,
output io_resp_bits_uop_fp_val,
output io_resp_bits_uop_fp_single,
output io_resp_bits_uop_xcpt_pf_if,
output io_resp_bits_uop_xcpt_ae_if,
output io_resp_bits_uop_xcpt_ma_if,
output io_resp_bits_uop_bp_debug_if,
output io_resp_bits_uop_bp_xcpt_if,
output [1:0] io_resp_bits_uop_debug_fsrc,
output [1:0] io_resp_bits_uop_debug_tsrc,
output [64:0] io_resp_bits_data,
output [39:0] io_resp_bits_addr,
output io_resp_bits_mxcpt_valid,
output io_resp_bits_sfence_valid,
output io_resp_bits_sfence_bits_rs1,
output io_resp_bits_sfence_bits_rs2,
output [38:0] io_resp_bits_sfence_bits_addr,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask
);
wire [63:0] _sum_T_3 = io_req_bits_rs1_data[63:0] + {{52{io_req_bits_uop_imm_packed[19]}}, io_req_bits_uop_imm_packed[19:8]};
wire misaligned = io_req_bits_uop_mem_size == 2'h1 & _sum_T_3[0] | io_req_bits_uop_mem_size == 2'h2 & (|(_sum_T_3[1:0])) | (&io_req_bits_uop_mem_size) & (|(_sum_T_3[2:0]));
wire ma_ld = io_req_valid & io_req_bits_uop_uopc == 7'h1 & misaligned;
wire ma_st = io_req_valid & (io_req_bits_uop_uopc == 7'h2 | io_req_bits_uop_uopc == 7'h43) & misaligned;
assign io_resp_valid = io_req_valid & (io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask) == 8'h0;
assign io_resp_bits_uop_uopc = io_req_bits_uop_uopc;
assign io_resp_bits_uop_inst = io_req_bits_uop_inst;
assign io_resp_bits_uop_debug_inst = io_req_bits_uop_debug_inst;
assign io_resp_bits_uop_is_rvc = io_req_bits_uop_is_rvc;
assign io_resp_bits_uop_debug_pc = io_req_bits_uop_debug_pc;
assign io_resp_bits_uop_iq_type = io_req_bits_uop_iq_type;
assign io_resp_bits_uop_fu_code = io_req_bits_uop_fu_code;
assign io_resp_bits_uop_ctrl_br_type = io_req_bits_uop_ctrl_br_type;
assign io_resp_bits_uop_ctrl_op1_sel = io_req_bits_uop_ctrl_op1_sel;
assign io_resp_bits_uop_ctrl_op2_sel = io_req_bits_uop_ctrl_op2_sel;
assign io_resp_bits_uop_ctrl_imm_sel = io_req_bits_uop_ctrl_imm_sel;
assign io_resp_bits_uop_ctrl_op_fcn = io_req_bits_uop_ctrl_op_fcn;
assign io_resp_bits_uop_ctrl_fcn_dw = io_req_bits_uop_ctrl_fcn_dw;
assign io_resp_bits_uop_ctrl_csr_cmd = io_req_bits_uop_ctrl_csr_cmd;
assign io_resp_bits_uop_ctrl_is_load = io_req_bits_uop_ctrl_is_load;
assign io_resp_bits_uop_ctrl_is_sta = io_req_bits_uop_ctrl_is_sta;
assign io_resp_bits_uop_ctrl_is_std = io_req_bits_uop_ctrl_is_std;
assign io_resp_bits_uop_iw_state = io_req_bits_uop_iw_state;
assign io_resp_bits_uop_is_br = io_req_bits_uop_is_br;
assign io_resp_bits_uop_is_jalr = io_req_bits_uop_is_jalr;
assign io_resp_bits_uop_is_jal = io_req_bits_uop_is_jal;
assign io_resp_bits_uop_is_sfb = io_req_bits_uop_is_sfb;
assign io_resp_bits_uop_br_mask = io_req_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;
assign io_resp_bits_uop_br_tag = io_req_bits_uop_br_tag;
assign io_resp_bits_uop_ftq_idx = io_req_bits_uop_ftq_idx;
assign io_resp_bits_uop_edge_inst = io_req_bits_uop_edge_inst;
assign io_resp_bits_uop_pc_lob = io_req_bits_uop_pc_lob;
assign io_resp_bits_uop_taken = io_req_bits_uop_taken;
assign io_resp_bits_uop_imm_packed = io_req_bits_uop_imm_packed;
assign io_resp_bits_uop_csr_addr = io_req_bits_uop_csr_addr;
assign io_resp_bits_uop_rob_idx = io_req_bits_uop_rob_idx;
assign io_resp_bits_uop_ldq_idx = io_req_bits_uop_ldq_idx;
assign io_resp_bits_uop_stq_idx = io_req_bits_uop_stq_idx;
assign io_resp_bits_uop_rxq_idx = io_req_bits_uop_rxq_idx;
assign io_resp_bits_uop_pdst = io_req_bits_uop_pdst;
assign io_resp_bits_uop_prs1 = io_req_bits_uop_prs1;
assign io_resp_bits_uop_prs2 = io_req_bits_uop_prs2;
assign io_resp_bits_uop_prs3 = io_req_bits_uop_prs3;
assign io_resp_bits_uop_ppred = io_req_bits_uop_ppred;
assign io_resp_bits_uop_prs1_busy = io_req_bits_uop_prs1_busy;
assign io_resp_bits_uop_prs2_busy = io_req_bits_uop_prs2_busy;
assign io_resp_bits_uop_prs3_busy = io_req_bits_uop_prs3_busy;
assign io_resp_bits_uop_ppred_busy = io_req_bits_uop_ppred_busy;
assign io_resp_bits_uop_stale_pdst = io_req_bits_uop_stale_pdst;
assign io_resp_bits_uop_exception = io_req_bits_uop_exception;
assign io_resp_bits_uop_exc_cause = io_req_bits_uop_exc_cause;
assign io_resp_bits_uop_bypassable = io_req_bits_uop_bypassable;
assign io_resp_bits_uop_mem_cmd = io_req_bits_uop_mem_cmd;
assign io_resp_bits_uop_mem_size = io_req_bits_uop_mem_size;
assign io_resp_bits_uop_mem_signed = io_req_bits_uop_mem_signed;
assign io_resp_bits_uop_is_fence = io_req_bits_uop_is_fence;
assign io_resp_bits_uop_is_fencei = io_req_bits_uop_is_fencei;
assign io_resp_bits_uop_is_amo = io_req_bits_uop_is_amo;
assign io_resp_bits_uop_uses_ldq = io_req_bits_uop_uses_ldq;
assign io_resp_bits_uop_uses_stq = io_req_bits_uop_uses_stq;
assign io_resp_bits_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc;
assign io_resp_bits_uop_is_unique = io_req_bits_uop_is_unique;
assign io_resp_bits_uop_flush_on_commit = io_req_bits_uop_flush_on_commit;
assign io_resp_bits_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1;
assign io_resp_bits_uop_ldst = io_req_bits_uop_ldst;
assign io_resp_bits_uop_lrs1 = io_req_bits_uop_lrs1;
assign io_resp_bits_uop_lrs2 = io_req_bits_uop_lrs2;
assign io_resp_bits_uop_lrs3 = io_req_bits_uop_lrs3;
assign io_resp_bits_uop_ldst_val = io_req_bits_uop_ldst_val;
assign io_resp_bits_uop_dst_rtype = io_req_bits_uop_dst_rtype;
assign io_resp_bits_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype;
assign io_resp_bits_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype;
assign io_resp_bits_uop_frs3_en = io_req_bits_uop_frs3_en;
assign io_resp_bits_uop_fp_val = io_req_bits_uop_fp_val;
assign io_resp_bits_uop_fp_single = io_req_bits_uop_fp_single;
assign io_resp_bits_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if;
assign io_resp_bits_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if;
assign io_resp_bits_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if;
assign io_resp_bits_uop_bp_debug_if = io_req_bits_uop_bp_debug_if;
assign io_resp_bits_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if;
assign io_resp_bits_uop_debug_fsrc = io_req_bits_uop_debug_fsrc;
assign io_resp_bits_uop_debug_tsrc = io_req_bits_uop_debug_tsrc;
assign io_resp_bits_data = io_req_bits_rs2_data;
assign io_resp_bits_addr = {_sum_T_3[38] ? (&(_sum_T_3[63:39])) : (|(_sum_T_3[63:39])), _sum_T_3[38:0]};
assign io_resp_bits_mxcpt_valid = ma_ld | ma_st;
assign io_resp_bits_sfence_valid = io_req_valid & io_req_bits_uop_mem_cmd == 5'h14;
assign io_resp_bits_sfence_bits_rs1 = io_req_bits_uop_mem_size[0];
assign io_resp_bits_sfence_bits_rs2 = io_req_bits_uop_mem_size[1];
assign io_resp_bits_sfence_bits_addr = io_req_bits_rs1_data[38:0];
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.internal.firrtl.KnownWidth
import chisel3.util.{Cat, Valid}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.property
/** Base JTAG shifter IO, viewed from input to shift register chain.
* Can be chained together.
*/
class ShifterIO extends Bundle {
val shift = Bool() // advance the scan chain on clock high
val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB
val capture = Bool() // high in the CaptureIR/DR state when this chain is selected
val update = Bool() // high in the UpdateIR/DR state when this chain is selected
/** Sets a output shifter IO's control signals from a input shifter IO's control signals.
*/
def chainControlFrom(in: ShifterIO): Unit = {
shift := in.shift
capture := in.capture
update := in.update
}
}
trait ChainIO extends Bundle {
val chainIn = Input(new ShifterIO)
val chainOut = Output(new ShifterIO)
}
class Capture[+T <: Data](gen: T) extends Bundle {
val bits = Input(gen) // data to capture, should be always valid
val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge
}
object Capture {
def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)
}
/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain
* IO.
*/
trait Chain extends Module {
val io: ChainIO
}
/** One-element shift register, data register for bypass mode.
*
* Implements Clause 10.
*/
class JtagBypassChain(implicit val p: Parameters) extends Chain {
class ModIO extends ChainIO
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val reg = Reg(Bool()) // 10.1.1a single shift register stage
io.chainOut.data := reg
property.cover(io.chainIn.capture, "bypass_chain_capture", "JTAG; bypass_chain_capture; This Bypass Chain captured data")
when (io.chainIn.capture) {
reg := false.B // 10.1.1b capture logic 0 on TCK rising
} .elsewhen (io.chainIn.shift) {
reg := io.chainIn.data
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object JtagBypassChain {
def apply()(implicit p: Parameters) = new JtagBypassChain
}
/** Simple shift register with parallel capture only, for read-only data registers.
*
* Number of stages is the number of bits in gen, which must have a known width.
*
* Useful notes:
* 7.2.1c shifter shifts on TCK rising edge
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
*/
class CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {
override def desiredName = s"CaptureChain_${gen.typeName}"
class ModIO extends ChainIO {
val capture = Capture(gen)
}
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val n = DataMirror.widthOf(gen) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $gen"); -1 // TODO: remove -1 type hack
}
val regs = (0 until n) map (x => Reg(Bool()))
io.chainOut.data := regs(0)
property.cover(io.chainIn.capture, "chain_capture", "JTAG; chain_capture; This Chain captured data")
when (io.chainIn.capture) {
(0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))
io.capture.capture := true.B
} .elsewhen (io.chainIn.shift) {
regs(n-1) := io.chainIn.data
(0 until n-1) map (x => regs(x) := regs(x+1))
io.capture.capture := false.B
} .otherwise {
io.capture.capture := false.B
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object CaptureChain {
def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)
}
/** Simple shift register with parallel capture and update. Useful for general instruction and data
* scan registers.
*
* Number of stages is the max number of bits in genCapture and genUpdate, both of which must have
* known widths. If there is a width mismatch, the unused most significant bits will be zero.
*
* Useful notes:
* 7.2.1c shifter shifts on TCK rising edge
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
*/
class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {
override def desiredName = s"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}"
class ModIO extends ChainIO {
val capture = Capture(genCapture)
val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after
}
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val captureWidth = DataMirror.widthOf(genCapture) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $genCapture"); -1 // TODO: remove -1 type hack
}
val updateWidth = DataMirror.widthOf(genUpdate) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $genUpdate"); -1 // TODO: remove -1 type hack
}
val n = math.max(captureWidth, updateWidth)
val regs = (0 until n) map (x => Reg(Bool()))
io.chainOut.data := regs(0)
val updateBits = Cat(regs.reverse)(updateWidth-1, 0)
io.update.bits := updateBits.asTypeOf(io.update.bits)
val captureBits = io.capture.bits.asUInt
property.cover(io.chainIn.capture, "chain_capture", "JTAG;chain_capture; This Chain captured data")
property.cover(io.chainIn.capture, "chain_update", "JTAG;chain_update; This Chain updated data")
when (io.chainIn.capture) {
(0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))
(captureWidth until n) map (x => regs(x) := 0.U)
io.capture.capture := true.B
io.update.valid := false.B
} .elsewhen (io.chainIn.update) {
io.capture.capture := false.B
io.update.valid := true.B
} .elsewhen (io.chainIn.shift) {
regs(n-1) := io.chainIn.data
(0 until n-1) map (x => regs(x) := regs(x+1))
io.capture.capture := false.B
io.update.valid := false.B
} .otherwise {
io.capture.capture := false.B
io.update.valid := false.B
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object CaptureUpdateChain {
/** Capture-update chain with matching capture and update types.
*/
def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)
def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =
new CaptureUpdateChain(genCapture, genUpdate)
} | module JtagBypassChain(
input clock,
input reset,
input io_chainIn_shift,
input io_chainIn_data,
input io_chainIn_capture,
input io_chainIn_update,
output io_chainOut_data
);
reg reg_0;
always @(posedge clock) begin
if (io_chainIn_capture)
reg_0 <= 1'h0;
else if (io_chainIn_shift)
reg_0 <= io_chainIn_data;
end
assign io_chainOut_data = reg_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module table_0_0(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [43:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [43:0] W0_data,
input [3:0] W0_mask
);
table_ext table_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Fetch Target Queue (FTQ)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Each entry in the FTQ holds the fetch address and branch prediction snapshot state.
//
// TODO:
// * reduce port counts.
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util.{Str}
import boom.v3.common._
import boom.v3.exu._
import boom.v3.util._
/**
* FTQ Parameters used in configurations
*
* @param nEntries # of entries in the FTQ
*/
case class FtqParameters(
nEntries: Int = 16
)
/**
* Bundle to add to the FTQ RAM and to be used as the pass in IO
*/
class FTQBundle(implicit p: Parameters) extends BoomBundle
with HasBoomFrontendParameters
{
// // TODO compress out high-order bits
// val fetch_pc = UInt(vaddrBitsExtended.W)
// IDX of instruction that was predicted taken, if any
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
// Was the CFI in this bundle found to be taken? or not
val cfi_taken = Bool()
// Was this CFI mispredicted by the branch prediction pipeline?
val cfi_mispredicted = Bool()
// What type of CFI was taken out of this bundle
val cfi_type = UInt(CFI_SZ.W)
// mask of branches which were visible in this fetch bundle
val br_mask = UInt(fetchWidth.W)
// This CFI is likely a CALL
val cfi_is_call = Bool()
// This CFI is likely a RET
val cfi_is_ret = Bool()
// Is the NPC after the CFI +4 or +2
val cfi_npc_plus4 = Bool()
// What was the top of the RAS that this bundle saw?
val ras_top = UInt(vaddrBitsExtended.W)
val ras_idx = UInt(log2Ceil(nRasEntries).W)
// Which bank did this start from?
val start_bank = UInt(1.W)
// // Metadata for the branch predictor
// val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))
}
/**
* IO to provide a port for a FunctionalUnit to get the PC of an instruction.
* And for JALRs, the PC of the next instruction.
*/
class GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = Input(UInt(log2Ceil(ftqSz).W))
val entry = Output(new FTQBundle)
val ghist = Output(new GlobalHistory)
val pc = Output(UInt(vaddrBitsExtended.W))
val com_pc = Output(UInt(vaddrBitsExtended.W))
// the next_pc may not be valid (stalled or still being fetched)
val next_val = Output(Bool())
val next_pc = Output(UInt(vaddrBitsExtended.W))
}
/**
* Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the
* processor.
*
* @param num_entries # of entries in the FTQ
*/
class FetchTargetQueue(implicit p: Parameters) extends BoomModule
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val num_entries = ftqSz
private val idx_sz = log2Ceil(num_entries)
val io = IO(new BoomBundle {
// Enqueue one entry for every fetch cycle.
val enq = Flipped(Decoupled(new FetchBundle()))
// Pass to FetchBuffer (newly fetched instructions).
val enq_idx = Output(UInt(idx_sz.W))
// ROB tells us the youngest committed ftq_idx to remove from FTQ.
val deq = Flipped(Valid(UInt(idx_sz.W)))
// Give PC info to BranchUnit.
val get_ftq_pc = Vec(2, new GetPCFromFtqIO())
// Used to regenerate PC for trace port stuff in FireSim
// Don't tape this out, this blows up the FTQ
val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))
val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W)))
val redirect = Input(Valid(UInt(idx_sz.W)))
val brupdate = Input(new BrUpdateInfo)
val bpdupdate = Output(Valid(new BranchPredictionUpdate))
val ras_update = Output(Bool())
val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W))
val ras_update_pc = Output(UInt(vaddrBitsExtended.W))
})
val bpd_ptr = RegInit(0.U(idx_sz.W))
val deq_ptr = RegInit(0.U(idx_sz.W))
val enq_ptr = RegInit(1.U(idx_sz.W))
val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) ||
(WrapInc(enq_ptr, num_entries) === bpd_ptr))
val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W)))
val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W)))
val ram = Reg(Vec(num_entries, new FTQBundle))
val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) }
val lhist = if (useLHist) {
Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W))))
} else {
None
}
val do_enq = io.enq.fire
// This register lets us initialize the ghist to 0
val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory))
val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle))
val prev_pc = RegInit(0.U(vaddrBitsExtended.W))
when (do_enq) {
pcs(enq_ptr) := io.enq.bits.pc
val new_entry = Wire(new FTQBundle)
new_entry.cfi_idx := io.enq.bits.cfi_idx
// Initially, if we see a CFI, it is assumed to be taken.
// Branch resolutions may change this
new_entry.cfi_taken := io.enq.bits.cfi_idx.valid
new_entry.cfi_mispredicted := false.B
new_entry.cfi_type := io.enq.bits.cfi_type
new_entry.cfi_is_call := io.enq.bits.cfi_is_call
new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret
new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4
new_entry.ras_top := io.enq.bits.ras_top
new_entry.ras_idx := io.enq.bits.ghist.ras_idx
new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask
new_entry.start_bank := bank(io.enq.bits.pc)
val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken,
io.enq.bits.ghist,
prev_ghist.update(
prev_entry.br_mask,
prev_entry.cfi_taken,
prev_entry.br_mask(prev_entry.cfi_idx.bits),
prev_entry.cfi_idx.bits,
prev_entry.cfi_idx.valid,
prev_pc,
prev_entry.cfi_is_call,
prev_entry.cfi_is_ret
)
)
lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist))
ghist.map( g => g.write(enq_ptr, new_ghist))
meta.write(enq_ptr, io.enq.bits.bpd_meta)
ram(enq_ptr) := new_entry
prev_pc := io.enq.bits.pc
prev_entry := new_entry
prev_ghist := new_ghist
enq_ptr := WrapInc(enq_ptr, num_entries)
}
io.enq_idx := enq_ptr
io.bpdupdate.valid := false.B
io.bpdupdate.bits := DontCare
when (io.deq.valid) {
deq_ptr := io.deq.bits
}
// This register avoids a spurious bpd update on the first fetch packet
val first_empty = RegInit(true.B)
// We can update the branch predictors when we know the target of the
// CFI in this fetch bundle
val ras_update = WireInit(false.B)
val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W))
val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W))
io.ras_update := RegNext(ras_update)
io.ras_update_pc := RegNext(ras_update_pc)
io.ras_update_idx := RegNext(ras_update_idx)
val bpd_update_mispredict = RegInit(false.B)
val bpd_update_repair = RegInit(false.B)
val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W))
val bpd_idx = Mux(io.redirect.valid, io.redirect.bits,
Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr))
val bpd_entry = RegNext(ram(bpd_idx))
val bpd_ghist = ghist(0).read(bpd_idx, true.B)
val bpd_lhist = if (useLHist) {
lhist.get.read(bpd_idx, true.B)
} else {
VecInit(Seq.fill(nBanks) { 0.U })
}
val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs
val bpd_pc = RegNext(pcs(bpd_idx))
val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries)))
when (io.redirect.valid) {
bpd_update_mispredict := false.B
bpd_update_repair := false.B
} .elsewhen (RegNext(io.brupdate.b2.mispredict)) {
bpd_update_mispredict := true.B
bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx)
bpd_end_idx := RegNext(enq_ptr)
} .elsewhen (bpd_update_mispredict) {
bpd_update_mispredict := false.B
bpd_update_repair := true.B
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {
bpd_repair_pc := bpd_pc
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair) {
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||
bpd_pc === bpd_repair_pc) {
bpd_update_repair := false.B
}
}
val do_commit_update = (!bpd_update_mispredict &&
!bpd_update_repair &&
bpd_ptr =/= deq_ptr &&
enq_ptr =/= WrapInc(bpd_ptr, num_entries) &&
!io.brupdate.b2.mispredict &&
!io.redirect.valid && !RegNext(io.redirect.valid))
val do_mispredict_update = bpd_update_mispredict
val do_repair_update = bpd_update_repair
when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) {
val cfi_idx = bpd_entry.cfi_idx.bits
val valid_repair = bpd_pc =/= bpd_repair_pc
io.bpdupdate.valid := (!first_empty &&
(bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) &&
!(RegNext(do_repair_update) && !valid_repair))
io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update)
io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update)
io.bpdupdate.bits.pc := bpd_pc
io.bpdupdate.bits.btb_mispredicts := 0.U
io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid,
MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask)
io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx
io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted
io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken
io.bpdupdate.bits.target := bpd_target
io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx)
io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR
io.bpdupdate.bits.ghist := bpd_ghist
io.bpdupdate.bits.lhist := bpd_lhist
io.bpdupdate.bits.meta := bpd_meta
first_empty := false.B
}
when (do_commit_update) {
bpd_ptr := WrapInc(bpd_ptr, num_entries)
}
io.enq.ready := RegNext(!full || do_commit_update)
val redirect_idx = io.redirect.bits
val redirect_entry = ram(redirect_idx)
val redirect_new_entry = WireInit(redirect_entry)
when (io.redirect.valid) {
enq_ptr := WrapInc(io.redirect.bits, num_entries)
when (io.brupdate.b2.mispredict) {
val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^
Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
redirect_new_entry.cfi_idx.valid := true.B
redirect_new_entry.cfi_idx.bits := new_cfi_idx
redirect_new_entry.cfi_mispredicted := true.B
redirect_new_entry.cfi_taken := io.brupdate.b2.taken
redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx
redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx
}
ras_update := true.B
ras_update_pc := redirect_entry.ras_top
ras_update_idx := redirect_entry.ras_idx
} .elsewhen (RegNext(io.redirect.valid)) {
prev_entry := RegNext(redirect_new_entry)
prev_ghist := bpd_ghist
prev_pc := bpd_pc
ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)
}
//-------------------------------------------------------------
// **** Core Read PCs ****
//-------------------------------------------------------------
for (i <- 0 until 2) {
val idx = io.get_ftq_pc(i).ftq_idx
val next_idx = WrapInc(idx, num_entries)
val next_is_enq = (next_idx === enq_ptr) && io.enq.fire
val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))
val get_entry = ram(idx)
val next_entry = ram(next_idx)
io.get_ftq_pc(i).entry := RegNext(get_entry)
if (i == 1)
io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B)
else
io.get_ftq_pc(i).ghist := DontCare
io.get_ftq_pc(i).pc := RegNext(pcs(idx))
io.get_ftq_pc(i).next_pc := RegNext(next_pc)
io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq)
io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))
}
for (w <- 0 until coreWidth) {
io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w)))
}
} | module ghist_0(
input [3:0] R0_addr,
input R0_clk,
output [71:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [71:0] W0_data
);
ghist_0_ext ghist_0_ext (
.R0_addr (R0_addr),
.R0_en (1'h1),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.property
object JtagState {
sealed abstract class State(val id: Int) {
def U: UInt = id.U(State.width.W)
}
object State {
import scala.language.implicitConversions
implicit def toInt(x: State) = x.id
implicit def toBigInt(x: State):BigInt = x.id
// TODO: this could be automatically generated with macros and stuff
val all: Set[State] = Set(
TestLogicReset,
RunTestIdle,
SelectDRScan,
CaptureDR,
ShiftDR,
Exit1DR,
PauseDR,
Exit2DR,
UpdateDR,
SelectIRScan,
CaptureIR,
ShiftIR,
Exit1IR,
PauseIR,
Exit2IR,
UpdateIR
)
val width = log2Ceil(all.size)
def chiselType() = UInt(width.W)
}
// States as described in 6.1.1.2, numeric assignments from example in Table 6-3
case object TestLogicReset extends State(15) // no effect on system logic, entered when TMS high for 5 TCK rising edges
case object RunTestIdle extends State(12) // runs active instruction (which can be idle)
case object SelectDRScan extends State(7)
case object CaptureDR extends State(6) // parallel-load DR shifter when exiting this state (if required)
case object ShiftDR extends State(2) // shifts DR shifter from TDI towards TDO, last shift occurs on rising edge transition out of this state
case object Exit1DR extends State(1)
case object PauseDR extends State(3) // pause DR shifting
case object Exit2DR extends State(0)
case object UpdateDR extends State(5) // parallel-load output from DR shifter on TCK falling edge while in this state (not a rule?)
case object SelectIRScan extends State(4)
case object CaptureIR extends State(14) // parallel-load IR shifter with fixed logic values and design-specific when exiting this state (if required)
case object ShiftIR extends State(10) // shifts IR shifter from TDI towards TDO, last shift occurs on rising edge transition out of this state
case object Exit1IR extends State(9)
case object PauseIR extends State(11) // pause IR shifting
case object Exit2IR extends State(8)
case object UpdateIR extends State(13) // latch IR shifter into IR (changes to IR may only occur while in this state, latch on TCK falling edge)
}
/** The JTAG state machine, implements spec 6.1.1.1a (Figure 6.1)
*
* Usage notes:
* - 6.1.1.1b state transitions occur on TCK rising edge
* - 6.1.1.1c actions can occur on the following TCK falling or rising edge
*
*/
class JtagStateMachine(implicit val p: Parameters) extends Module() {
class StateMachineIO extends Bundle {
val tms = Input(Bool())
val currState = Output(JtagState.State.chiselType())
}
val io = IO(new StateMachineIO)
val nextState = WireInit(JtagState.TestLogicReset.U)
val currState = RegNext(next=nextState, init=JtagState.TestLogicReset.U)
switch (currState) {
is (JtagState.TestLogicReset.U) {
nextState := Mux(io.tms, JtagState.TestLogicReset.U, JtagState.RunTestIdle.U)
}
is (JtagState.RunTestIdle.U) {
nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)
}
is (JtagState.SelectDRScan.U) {
nextState := Mux(io.tms, JtagState.SelectIRScan.U, JtagState.CaptureDR.U)
}
is (JtagState.CaptureDR.U) {
nextState := Mux(io.tms, JtagState.Exit1DR.U, JtagState.ShiftDR.U)
}
is (JtagState.ShiftDR.U) {
nextState := Mux(io.tms, JtagState.Exit1DR.U, JtagState.ShiftDR.U)
}
is (JtagState.Exit1DR.U) {
nextState := Mux(io.tms, JtagState.UpdateDR.U, JtagState.PauseDR.U)
}
is (JtagState.PauseDR.U) {
nextState := Mux(io.tms, JtagState.Exit2DR.U, JtagState.PauseDR.U)
}
is (JtagState.Exit2DR.U) {
nextState := Mux(io.tms, JtagState.UpdateDR.U, JtagState.ShiftDR.U)
}
is (JtagState.UpdateDR.U) {
nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)
}
is (JtagState.SelectIRScan.U) {
nextState := Mux(io.tms, JtagState.TestLogicReset.U, JtagState.CaptureIR.U)
}
is (JtagState.CaptureIR.U) {
nextState := Mux(io.tms, JtagState.Exit1IR.U, JtagState.ShiftIR.U)
}
is (JtagState.ShiftIR.U) {
nextState := Mux(io.tms, JtagState.Exit1IR.U, JtagState.ShiftIR.U)
}
is (JtagState.Exit1IR.U) {
nextState := Mux(io.tms, JtagState.UpdateIR.U, JtagState.PauseIR.U)
}
is (JtagState.PauseIR.U) {
nextState := Mux(io.tms, JtagState.Exit2IR.U, JtagState.PauseIR.U)
}
is (JtagState.Exit2IR.U) {
nextState := Mux(io.tms, JtagState.UpdateIR.U, JtagState.ShiftIR.U)
}
is (JtagState.UpdateIR.U) {
nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)
}
}
io.currState := currState
// Generate Coverate Points
JtagState.State.all.foreach { s =>
property.cover (currState === s.U && io.tms === true.B, s"${s.toString}_tms_1", s"JTAG; ${s.toString} with TMS = 1; State Transition from ${s.toString} with TMS = 1")
property.cover (currState === s.U && io.tms === false.B, s"${s.toString}_tms_0", s"JTAG; ${s.toString} with TMS = 0; State Transition from ${s.toString} with TMS = 0")
property.cover (currState === s.U && reset.asBool === true.B, s"${s.toString}_reset", s"JTAG; ${s.toString} with reset; JTAG Reset asserted during ${s.toString}")
}
} | module JtagStateMachine(
input clock,
input reset,
input io_tms,
output [3:0] io_currState
);
reg [3:0] currState;
wire [15:0][3:0] _GEN = {{io_tms ? 4'hF : 4'hC}, {io_tms ? 4'h9 : 4'hA}, {io_tms ? 4'h7 : 4'hC}, {io_tms ? 4'h7 : 4'hC}, {io_tms ? 4'h8 : 4'hB}, {io_tms ? 4'h9 : 4'hA}, {io_tms ? 4'hD : 4'hB}, {io_tms ? 4'hD : 4'hA}, {{2'h1, ~io_tms, 1'h0}}, {io_tms ? 4'h1 : 4'h2}, {io_tms ? 4'h7 : 4'hC}, {{3'h7, io_tms}}, {io_tms ? 4'h0 : 4'h3}, {io_tms ? 4'h1 : 4'h2}, {io_tms ? 4'h5 : 4'h3}, {io_tms ? 4'h5 : 4'h2}};
always @(posedge clock or posedge reset) begin
if (reset)
currState <= 4'hF;
else
currState <= _GEN[currState];
end
assign io_currState = currState;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.experimental.SourceInfo
import chisel3.util._
import freechips.rocketchip.diplomacy.AddressDecoder
import freechips.rocketchip.util.{BundleFieldBase, BundleMap, MuxSeq, ReduceOthers, property}
// A bus agnostic register interface to a register-based device
case class RegMapperParams(indexBits: Int, maskBits: Int, extraFields: Seq[BundleFieldBase] = Nil)
class RegMapperInput(val params: RegMapperParams) extends Bundle
{
val read = Bool()
val index = UInt((params.indexBits).W)
val data = UInt((params.maskBits*8).W)
val mask = UInt((params.maskBits).W)
val extra = BundleMap(params.extraFields)
}
class RegMapperOutput(val params: RegMapperParams) extends Bundle
{
val read = Bool()
val data = UInt((params.maskBits*8).W)
val extra = BundleMap(params.extraFields)
}
object RegMapper
{
// Create a generic register-based device
def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*)(implicit sourceInfo: SourceInfo) = {
// Filter out zero-width fields
val bytemap = mapping.toList.map { case (offset, fields) => (offset, fields.filter(_.width != 0)) }
// Negative addresses are bad
bytemap.foreach { byte => require (byte._1 >= 0) }
// Transform all fields into bit offsets Seq[(bit, field)]
val bitmap = bytemap.map { case (byte, fields) =>
val bits = fields.scanLeft(byte * 8)(_ + _.width).init
bits zip fields
}.flatten.sortBy(_._1)
// Detect overlaps
(bitmap.init zip bitmap.tail) foreach { case ((lbit, lfield), (rbit, rfield)) =>
require (lbit + lfield.width <= rbit, s"Register map overlaps at bit ${rbit}.")
}
// Group those fields into bus words Map[word, List[(bit, field)]]
val wordmap = bitmap.groupBy(_._1 / (8*bytes))
// Make sure registers fit
val inParams = in.bits.params
val inBits = inParams.indexBits
assert (wordmap.keySet.max < (1 << inBits), "Register map does not fit in device")
val out = Wire(Decoupled(new RegMapperOutput(inParams)))
val front = Wire(Decoupled(new RegMapperInput(inParams)))
front.bits := in.bits
// Must this device pipeline the control channel?
val pipelined = wordmap.values.map(_.map(_._2.pipelined)).flatten.reduce(_ || _)
val depth = concurrency
require (depth >= 0)
require (!pipelined || depth > 0, "Register-based device with request/response handshaking needs concurrency > 0")
val back = if (depth > 0) {
val front_q = Module(new Queue(new RegMapperInput(inParams), depth) {
override def desiredName = s"Queue${depth}_${front.bits.typeName}_i${inParams.indexBits}_m${inParams.maskBits}"
})
front_q.io.enq <> front
front_q.io.deq
} else front
// Convert to and from Bits
def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =
if (x == 0) tail.reverse else toBits(x >> 1, ((x & 1) == 1) :: tail)
def ofBits(bits: List[Boolean]) = bits.foldRight(0){ case (x,y) => (if (x) 1 else 0) | y << 1 }
// Find the minimal mask that can decide the register map
val mask = AddressDecoder(wordmap.keySet.toList)
val maskMatch = ~mask.U(inBits.W)
val maskFilter = toBits(mask)
val maskBits = maskFilter.filter(x => x).size
// Calculate size and indexes into the register map
val regSize = 1 << maskBits
def regIndexI(x: Int) = ofBits((maskFilter zip toBits(x)).filter(_._1).map(_._2))
def regIndexU(x: UInt) = if (maskBits == 0) 0.U else
Cat((maskFilter zip x.asBools).filter(_._1).map(_._2).reverse)
val findex = front.bits.index & maskMatch
val bindex = back .bits.index & maskMatch
// Protection flag for undefined registers
val iRightReg = Array.fill(regSize) { true.B }
val oRightReg = Array.fill(regSize) { true.B }
// Transform the wordmap into minimal decoded indexes, Seq[(index, bit, field)]
val flat = wordmap.toList.map { case (word, fields) =>
val index = regIndexI(word)
if (undefZero) {
val uint = (word & ~mask).U(inBits.W)
iRightReg(index) = findex === uint
oRightReg(index) = bindex === uint
}
// Confirm that no field spans a word boundary
fields foreach { case (bit, field) =>
val off = bit - 8*bytes*word
// println(s"Reg ${word}: [${off}, ${off+field.width})")
require (off + field.width <= bytes * 8, s"Field at word ${word}*(${bytes}B) has bits [${off}, ${off+field.width}), which exceeds word limit.")
}
// println("mapping 0x%x -> 0x%x for 0x%x/%d".format(word, index, mask, maskBits))
fields.map { case (bit, field) => (index, bit-8*bytes*word, field) }
}.flatten
// Forward declaration of all flow control signals
val rivalid = Wire(Vec(flat.size, Bool()))
val wivalid = Wire(Vec(flat.size, Bool()))
val roready = Wire(Vec(flat.size, Bool()))
val woready = Wire(Vec(flat.size, Bool()))
// Per-register list of all control signals needed for data to flow
val rifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val wifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val rofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val wofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
// The output values for each register
val dataOut = Array.fill(regSize) { 0.U }
// Which bits are touched?
val frontMask = FillInterleaved(8, front.bits.mask)
val backMask = FillInterleaved(8, back .bits.mask)
// Connect the fields
for (i <- 0 until flat.size) {
val (reg, low, field) = flat(i)
val high = low + field.width - 1
// Confirm that no register is too big
require (high < 8*bytes)
val rimask = frontMask(high, low).orR
val wimask = frontMask(high, low).andR
val romask = backMask(high, low).orR
val womask = backMask(high, low).andR
val data = if (field.write.combinational) back.bits.data else front.bits.data
val f_rivalid = rivalid(i) && rimask
val f_roready = roready(i) && romask
val f_wivalid = wivalid(i) && wimask
val f_woready = woready(i) && womask
val (f_riready, f_rovalid, f_data) = field.read.fn(f_rivalid, f_roready)
val (f_wiready, f_wovalid) = field.write.fn(f_wivalid, f_woready, data(high, low))
// cover reads and writes to register
val fname = field.desc.map{_.name}.getOrElse("")
val fdesc = field.desc.map{_.desc + ":"}.getOrElse("")
val facct = field.desc.map{_.access}.getOrElse("")
if((facct == RegFieldAccessType.R) || (facct == RegFieldAccessType.RW)) {
property.cover(f_rivalid && f_riready, fname + "_Reg_read_start", fdesc + " RegField Read Request Initiate")
property.cover(f_rovalid && f_roready, fname + "_Reg_read_out", fdesc + " RegField Read Request Complete")
}
if((facct == RegFieldAccessType.W) || (facct == RegFieldAccessType.RW)) {
property.cover(f_wivalid && f_wiready, fname + "_Reg_write_start", fdesc + " RegField Write Request Initiate")
property.cover(f_wovalid && f_woready, fname + "_Reg_write_out", fdesc + " RegField Write Request Complete")
}
def litOR(x: Bool, y: Bool) = if (x.isLit && x.litValue == 1) true.B else x || y
// Add this field to the ready-valid signals for the register
rifire(reg) = (rivalid(i), litOR(f_riready, !rimask)) +: rifire(reg)
wifire(reg) = (wivalid(i), litOR(f_wiready, !wimask)) +: wifire(reg)
rofire(reg) = (roready(i), litOR(f_rovalid, !romask)) +: rofire(reg)
wofire(reg) = (woready(i), litOR(f_wovalid, !womask)) +: wofire(reg)
// ... this loop iterates from smallest to largest bit offset
val prepend = if (low == 0) { f_data } else { Cat(f_data, dataOut(reg) | 0.U(low.W)) }
dataOut(reg) = (prepend | 0.U((high+1).W))(high, 0)
}
// Which register is touched?
val iindex = regIndexU(front.bits.index)
val oindex = regIndexU(back .bits.index)
val frontSel = UIntToOH(iindex).asBools
val backSel = UIntToOH(oindex).asBools
// Compute: is the selected register ready? ... and cross-connect all ready-valids
def mux(index: UInt, valid: Bool, select: Seq[Bool], guard: Seq[Bool], flow: Seq[Seq[(Bool, Bool)]]): Bool =
MuxSeq(index, true.B, ((select zip guard) zip flow).map { case ((s, g), f) =>
val out = Wire(Bool())
ReduceOthers((out, valid && s && g) +: f)
out || !g
})
// Include the per-register one-hot selected criteria
val rifireMux = mux(iindex, in.valid && front.ready && front.bits.read, frontSel, iRightReg, rifire)
val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg, wifire)
val rofireMux = mux(oindex, back.valid && out.ready && back .bits.read, backSel, oRightReg, rofire)
val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel, oRightReg, wofire)
val iready = Mux(front.bits.read, rifireMux, wifireMux)
val oready = Mux(back .bits.read, rofireMux, wofireMux)
// Connect the pipeline
in.ready := front.ready && iready
front.valid := in.valid && iready
back.ready := out.ready && oready
out.valid := back.valid && oready
out.bits.read := back.bits.read
out.bits.data := Mux(MuxSeq(oindex, true.B, oRightReg),
MuxSeq(oindex, 0.U, dataOut),
0.U)
out.bits.extra := back.bits.extra
out
}
} | module Queue1_RegMapperInput_i9_m8(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input io_enq_bits_read,
input [8:0] io_enq_bits_index,
input [63:0] io_enq_bits_data,
input [7:0] io_enq_bits_mask,
input [10:0] io_enq_bits_extra_tlrr_extra_source,
input [1:0] io_enq_bits_extra_tlrr_extra_size,
input io_deq_ready,
output io_deq_valid,
output io_deq_bits_read,
output [8:0] io_deq_bits_index,
output [7:0] io_deq_bits_mask,
output [10:0] io_deq_bits_extra_tlrr_extra_source,
output [1:0] io_deq_bits_extra_tlrr_extra_size
);
reg [94:0] ram;
reg full;
wire do_enq = ~full & io_enq_valid;
always @(posedge clock) begin
if (do_enq)
ram <= {io_enq_bits_extra_tlrr_extra_size, io_enq_bits_extra_tlrr_extra_source, io_enq_bits_mask, io_enq_bits_data, io_enq_bits_index, io_enq_bits_read};
if (reset)
full <= 1'h0;
else if (~(do_enq == (io_deq_ready & full)))
full <= do_enq;
end
assign io_enq_ready = ~full;
assign io_deq_valid = full;
assign io_deq_bits_read = ram[0];
assign io_deq_bits_index = ram[9:1];
assign io_deq_bits_mask = ram[81:74];
assign io_deq_bits_extra_tlrr_extra_source = ram[92:82];
assign io_deq_bits_extra_tlrr_extra_size = ram[94:93];
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2017 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import boom.v3.common._
import boom.v3.exu.{CommitExceptionSignals, BranchDecode, BrUpdateInfo}
import boom.v3.util._
class BoomRAS(implicit p: Parameters) extends BoomModule()(p)
{
val io = IO(new Bundle {
val read_idx = Input(UInt(log2Ceil(nRasEntries).W))
val read_addr = Output(UInt(vaddrBitsExtended.W))
val write_valid = Input(Bool())
val write_idx = Input(UInt(log2Ceil(nRasEntries).W))
val write_addr = Input(UInt(vaddrBitsExtended.W))
})
val ras = Reg(Vec(nRasEntries, UInt(vaddrBitsExtended.W)))
io.read_addr := Mux(RegNext(io.write_valid && io.write_idx === io.read_idx),
RegNext(io.write_addr),
RegNext(ras(io.read_idx)))
when (io.write_valid) {
ras(io.write_idx) := io.write_addr
}
} | module BoomRAS(
input clock,
input [4:0] io_read_idx,
output [39:0] io_read_addr,
input io_write_valid,
input [4:0] io_write_idx,
input [39:0] io_write_addr
);
reg [39:0] ras_0;
reg [39:0] ras_1;
reg [39:0] ras_2;
reg [39:0] ras_3;
reg [39:0] ras_4;
reg [39:0] ras_5;
reg [39:0] ras_6;
reg [39:0] ras_7;
reg [39:0] ras_8;
reg [39:0] ras_9;
reg [39:0] ras_10;
reg [39:0] ras_11;
reg [39:0] ras_12;
reg [39:0] ras_13;
reg [39:0] ras_14;
reg [39:0] ras_15;
reg [39:0] ras_16;
reg [39:0] ras_17;
reg [39:0] ras_18;
reg [39:0] ras_19;
reg [39:0] ras_20;
reg [39:0] ras_21;
reg [39:0] ras_22;
reg [39:0] ras_23;
reg [39:0] ras_24;
reg [39:0] ras_25;
reg [39:0] ras_26;
reg [39:0] ras_27;
reg [39:0] ras_28;
reg [39:0] ras_29;
reg [39:0] ras_30;
reg [39:0] ras_31;
reg io_read_addr_REG;
reg [39:0] io_read_addr_REG_1;
reg [39:0] io_read_addr_REG_2;
wire [31:0][39:0] _GEN = {{ras_31}, {ras_30}, {ras_29}, {ras_28}, {ras_27}, {ras_26}, {ras_25}, {ras_24}, {ras_23}, {ras_22}, {ras_21}, {ras_20}, {ras_19}, {ras_18}, {ras_17}, {ras_16}, {ras_15}, {ras_14}, {ras_13}, {ras_12}, {ras_11}, {ras_10}, {ras_9}, {ras_8}, {ras_7}, {ras_6}, {ras_5}, {ras_4}, {ras_3}, {ras_2}, {ras_1}, {ras_0}};
always @(posedge clock) begin
if (io_write_valid & io_write_idx == 5'h0)
ras_0 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h1)
ras_1 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h2)
ras_2 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h3)
ras_3 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h4)
ras_4 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h5)
ras_5 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h6)
ras_6 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h7)
ras_7 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h8)
ras_8 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h9)
ras_9 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'hA)
ras_10 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'hB)
ras_11 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'hC)
ras_12 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'hD)
ras_13 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'hE)
ras_14 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'hF)
ras_15 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h10)
ras_16 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h11)
ras_17 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h12)
ras_18 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h13)
ras_19 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h14)
ras_20 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h15)
ras_21 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h16)
ras_22 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h17)
ras_23 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h18)
ras_24 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h19)
ras_25 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h1A)
ras_26 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h1B)
ras_27 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h1C)
ras_28 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h1D)
ras_29 <= io_write_addr;
if (io_write_valid & io_write_idx == 5'h1E)
ras_30 <= io_write_addr;
if (io_write_valid & (&io_write_idx))
ras_31 <= io_write_addr;
io_read_addr_REG <= io_write_valid & io_write_idx == io_read_idx;
io_read_addr_REG_1 <= io_write_addr;
io_read_addr_REG_2 <= _GEN[io_read_idx];
end
assign io_read_addr = io_read_addr_REG ? io_read_addr_REG_1 : io_read_addr_REG_2;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module PhitDemux_p32_f32_n5_TestHarness_UNIQUIFIED(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_phit,
input io_out_0_ready,
output io_out_0_valid,
output [31:0] io_out_0_bits_phit,
input io_out_1_ready,
output io_out_1_valid,
output [31:0] io_out_1_bits_phit,
input io_out_2_ready,
output io_out_2_valid,
output [31:0] io_out_2_bits_phit,
input io_out_3_ready,
output io_out_3_valid,
output [31:0] io_out_3_bits_phit,
input io_out_4_ready,
output io_out_4_valid,
output [31:0] io_out_4_bits_phit
);
reg beat;
reg [31:0] channel_vec_0;
wire [7:0] _GEN = {{io_out_0_ready}, {io_out_0_ready}, {io_out_0_ready}, {io_out_4_ready}, {io_out_3_ready}, {io_out_2_ready}, {io_out_1_ready}, {io_out_0_ready}};
wire io_in_ready_0 = ~beat | _GEN[channel_vec_0[2:0]];
wire _GEN_0 = io_in_ready_0 & io_in_valid;
always @(posedge clock) begin
if (reset)
beat <= 1'h0;
else if (_GEN_0)
beat <= ~beat & beat - 1'h1;
if (_GEN_0 & ~beat)
channel_vec_0 <= io_in_bits_phit;
end
assign io_in_ready = io_in_ready_0;
assign io_out_0_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h0;
assign io_out_0_bits_phit = io_in_bits_phit;
assign io_out_1_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h1;
assign io_out_1_bits_phit = io_in_bits_phit;
assign io_out_2_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h2;
assign io_out_2_bits_phit = io_in_bits_phit;
assign io_out_3_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h3;
assign io_out_3_bits_phit = io_in_bits_phit;
assign io_out_4_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h4;
assign io_out_4_bits_phit = io_in_bits_phit;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module FlitToPhit_f32_p32(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_phit
);
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign io_out_bits_phit = io_in_bits_flit;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
} | module MulAddRecFNPipe_l2_e8_s24(
input clock,
input reset,
input io_validin,
input [1:0] io_op,
input [32:0] io_a,
input [32:0] io_b,
input [32:0] io_c,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags,
output io_validout
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA;
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB;
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;
reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;
reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;
reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;
reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;
reg [2:0] roundingMode_stage0_pipe_b;
reg valid_stage0_pipe_v;
reg roundRawFNToRecFN_io_invalidExc_pipe_b;
reg roundRawFNToRecFN_io_in_pipe_b_isNaN;
reg roundRawFNToRecFN_io_in_pipe_b_isInf;
reg roundRawFNToRecFN_io_in_pipe_b_isZero;
reg roundRawFNToRecFN_io_in_pipe_b_sign;
reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp;
reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig;
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;
reg io_validout_pipe_v;
always @(posedge clock) begin
if (io_validin) begin
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= {1'h0, {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode;
roundingMode_stage0_pipe_b <= io_roundingMode;
end
if (valid_stage0_pipe_v) begin
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_b;
end
if (reset) begin
valid_stage0_pipe_v <= 1'h0;
io_validout_pipe_v <= 1'h0;
end
else begin
valid_stage0_pipe_v <= io_validin;
io_validout_pipe_v <= valid_stage0_pipe_v;
end
end
MulAddRecFNToRaw_preMul_e8_s24 mulAddRecFNToRaw_preMul (
.io_op (io_op),
.io_a (io_a),
.io_b (io_b),
.io_c (io_c),
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
);
MulAddRecFNToRaw_postMul_e8_s24 mulAddRecFNToRaw_postMul (
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny),
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB),
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA),
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA),
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB),
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB),
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd),
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC),
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC),
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC),
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum),
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags),
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant),
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist),
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC),
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC),
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b),
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b),
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
);
RoundRawFNToRecFN_e8_s24 roundRawFNToRecFN (
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b),
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN),
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf),
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero),
.io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign),
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp),
.io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig),
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
assign io_validout = io_validout_pipe_v;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.{Cat, Fill}
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for standard 64-bit floating-point in
| recoded form, using a separate integer multiplier-adder. Multiple clock
| cycles are needed for each division or square-root operation. See
| "docs/DivSqrtRecF64_mulAddZ31.txt" for more details.
*----------------------------------------------------------------------------*/
class DivSqrtRecF64ToRaw_mulAddZ31 extends Module
{
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady_div = Output(Bool())
val inReady_sqrt = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(Bits(65.W))
val b = Input(Bits(65.W))
val roundingMode = Input(UInt(3.W))
//*** OPTIONALLY PROPAGATE:
// val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val usingMulAdd = Output(Bits(4.W))
val latchMulAddA_0 = Output(Bool())
val mulAddA_0 = Output(UInt(54.W))
val latchMulAddB_0 = Output(Bool())
val mulAddB_0 = Output(UInt(54.W))
val mulAddC_2 = Output(UInt(105.W))
val mulAddResult_3 = Input(UInt(105.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(11, 55))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum_A = RegInit(0.U(3.W))
val cycleNum_B = RegInit(0.U(4.W))
val cycleNum_C = RegInit(0.U(3.W))
val cycleNum_E = RegInit(0.U(3.W))
val valid_PA = RegInit(false.B)
val sqrtOp_PA = Reg(Bool())
val majorExc_PA = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PA = Reg(Bool())
val isInf_PA = Reg(Bool())
val isZero_PA = Reg(Bool())
val sign_PA = Reg(Bool())
val sExp_PA = Reg(SInt(13.W))
val fractB_PA = Reg(UInt(52.W))
val fractA_PA = Reg(UInt(52.W))
val roundingMode_PA = Reg(UInt(3.W))
val valid_PB = RegInit(false.B)
val sqrtOp_PB = Reg(Bool())
val majorExc_PB = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PB = Reg(Bool())
val isInf_PB = Reg(Bool())
val isZero_PB = Reg(Bool())
val sign_PB = Reg(Bool())
val sExp_PB = Reg(SInt(13.W))
val bit0FractA_PB = Reg(UInt(1.W))
val fractB_PB = Reg(UInt(52.W))
val roundingMode_PB = Reg(UInt(3.W))
val valid_PC = RegInit(false.B)
val sqrtOp_PC = Reg(Bool())
val majorExc_PC = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PC = Reg(Bool())
val isInf_PC = Reg(Bool())
val isZero_PC = Reg(Bool())
val sign_PC = Reg(Bool())
val sExp_PC = Reg(SInt(13.W))
val bit0FractA_PC = Reg(UInt(1.W))
val fractB_PC = Reg(UInt(52.W))
val roundingMode_PC = Reg(UInt(3.W))
val fractR0_A = Reg(UInt(9.W))
//*** COMBINE 'hiSqrR0_A_sqrt' AND 'partNegSigma0_A'?
val hiSqrR0_A_sqrt = Reg(UInt(10.W))
val partNegSigma0_A = Reg(UInt(21.W))
val nextMulAdd9A_A = Reg(UInt(9.W))
val nextMulAdd9B_A = Reg(UInt(9.W))
val ER1_B_sqrt = Reg(UInt(17.W))
val ESqrR1_B_sqrt = Reg(UInt(32.W))
val sigX1_B = Reg(UInt(58.W))
val sqrSigma1_C = Reg(UInt(33.W))
val sigXN_C = Reg(UInt(58.W))
val u_C_sqrt = Reg(UInt(31.W))
val E_E_div = Reg(Bool())
val sigT_E = Reg(UInt(54.W))
val isNegRemT_E = Reg(Bool())
val isZeroRemT_E = Reg(Bool())
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val ready_PA = Wire(Bool())
val ready_PB = Wire(Bool())
val ready_PC = Wire(Bool())
val leaving_PA = Wire(Bool())
val leaving_PB = Wire(Bool())
val leaving_PC = Wire(Bool())
val zSigma1_B4 = Wire(UInt())
val sigXNU_B3_CX = Wire(UInt())
val zComplSigT_C1_sqrt = Wire(UInt())
val zComplSigT_C1 = Wire(UInt())
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cyc_S_div = io.inReady_div && io.inValid && ! io.sqrtOp
val cyc_S_sqrt = io.inReady_sqrt && io.inValid && io.sqrtOp
val cyc_S = cyc_S_div || cyc_S_sqrt
val rawA_S = rawFloatFromRecFN(11, 53, io.a)
val rawB_S = rawFloatFromRecFN(11, 53, io.b)
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawB_S.isNaN && ! rawB_S.isZero && rawB_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawB_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawB_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawB_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawB_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = (! io.sqrtOp && rawA_S.sign) ^ rawB_S.sign
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseB_S && ! rawB_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +& (rawB_S.sExp(11) ## ~rawB_S.sExp(10, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
(Mux(((7<<9).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(12, 9)
) ##
sExpQuot_S_div(8, 0)
).asSInt
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PA_normalCase_div = cyc_S_div && normalCase_S_div
val entering_PA_normalCase_sqrt = cyc_S_sqrt && normalCase_S_sqrt
val entering_PA_normalCase =
entering_PA_normalCase_div || entering_PA_normalCase_sqrt
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering_PA_normalCase || (cycleNum_A =/= 0.U)) {
cycleNum_A :=
Mux(entering_PA_normalCase_div, 3.U, 0.U) |
Mux(entering_PA_normalCase_sqrt, 6.U, 0.U) |
Mux(! entering_PA_normalCase, cycleNum_A - 1.U, 0.U)
}
val cyc_A7_sqrt = entering_PA_normalCase_sqrt
val cyc_A6_sqrt = (cycleNum_A === 6.U)
val cyc_A5_sqrt = (cycleNum_A === 5.U)
val cyc_A4_sqrt = (cycleNum_A === 4.U)
val cyc_A4_div = entering_PA_normalCase_div
val cyc_A4 = cyc_A4_sqrt || cyc_A4_div
val cyc_A3 = (cycleNum_A === 3.U)
val cyc_A2 = (cycleNum_A === 2.U)
val cyc_A1 = (cycleNum_A === 1.U)
val cyc_A3_div = cyc_A3 && ! sqrtOp_PA
val cyc_A2_div = cyc_A2 && ! sqrtOp_PA
val cyc_A1_div = cyc_A1 && ! sqrtOp_PA
val cyc_A3_sqrt = cyc_A3 && sqrtOp_PA
val cyc_A2_sqrt = cyc_A2 && sqrtOp_PA
val cyc_A1_sqrt = cyc_A1 && sqrtOp_PA
when (cyc_A1 || (cycleNum_B =/= 0.U)) {
cycleNum_B :=
Mux(cyc_A1,
Mux(sqrtOp_PA, 10.U, 6.U),
cycleNum_B - 1.U
)
}
val cyc_B10_sqrt = (cycleNum_B === 10.U)
val cyc_B9_sqrt = (cycleNum_B === 9.U)
val cyc_B8_sqrt = (cycleNum_B === 8.U)
val cyc_B7_sqrt = (cycleNum_B === 7.U)
val cyc_B6 = (cycleNum_B === 6.U)
val cyc_B5 = (cycleNum_B === 5.U)
val cyc_B4 = (cycleNum_B === 4.U)
val cyc_B3 = (cycleNum_B === 3.U)
val cyc_B2 = (cycleNum_B === 2.U)
val cyc_B1 = (cycleNum_B === 1.U)
val cyc_B6_div = cyc_B6 && valid_PA && ! sqrtOp_PA
val cyc_B5_div = cyc_B5 && valid_PA && ! sqrtOp_PA
val cyc_B4_div = cyc_B4 && valid_PA && ! sqrtOp_PA
val cyc_B3_div = cyc_B3 && ! sqrtOp_PB
val cyc_B2_div = cyc_B2 && ! sqrtOp_PB
val cyc_B1_div = cyc_B1 && ! sqrtOp_PB
val cyc_B6_sqrt = cyc_B6 && valid_PB && sqrtOp_PB
val cyc_B5_sqrt = cyc_B5 && valid_PB && sqrtOp_PB
val cyc_B4_sqrt = cyc_B4 && valid_PB && sqrtOp_PB
val cyc_B3_sqrt = cyc_B3 && sqrtOp_PB
val cyc_B2_sqrt = cyc_B2 && sqrtOp_PB
val cyc_B1_sqrt = cyc_B1 && sqrtOp_PB
when (cyc_B1 || (cycleNum_C =/= 0.U)) {
cycleNum_C :=
Mux(cyc_B1, Mux(sqrtOp_PB, 6.U, 5.U), cycleNum_C - 1.U)
}
val cyc_C6_sqrt = (cycleNum_C === 6.U)
val cyc_C5 = (cycleNum_C === 5.U)
val cyc_C4 = (cycleNum_C === 4.U)
val cyc_C3 = (cycleNum_C === 3.U)
val cyc_C2 = (cycleNum_C === 2.U)
val cyc_C1 = (cycleNum_C === 1.U)
val cyc_C5_div = cyc_C5 && ! sqrtOp_PB
val cyc_C4_div = cyc_C4 && ! sqrtOp_PB
val cyc_C3_div = cyc_C3 && ! sqrtOp_PB
val cyc_C2_div = cyc_C2 && ! sqrtOp_PC
val cyc_C1_div = cyc_C1 && ! sqrtOp_PC
val cyc_C5_sqrt = cyc_C5 && sqrtOp_PB
val cyc_C4_sqrt = cyc_C4 && sqrtOp_PB
val cyc_C3_sqrt = cyc_C3 && sqrtOp_PB
val cyc_C2_sqrt = cyc_C2 && sqrtOp_PC
val cyc_C1_sqrt = cyc_C1 && sqrtOp_PC
when (cyc_C1 || (cycleNum_E =/= 0.U)) {
cycleNum_E := Mux(cyc_C1, 4.U, cycleNum_E - 1.U)
}
val cyc_E4 = (cycleNum_E === 4.U)
val cyc_E3 = (cycleNum_E === 3.U)
val cyc_E2 = (cycleNum_E === 2.U)
val cyc_E1 = (cycleNum_E === 1.U)
val cyc_E4_div = cyc_E4 && ! sqrtOp_PC
val cyc_E3_div = cyc_E3 && ! sqrtOp_PC
val cyc_E2_div = cyc_E2 && ! sqrtOp_PC
val cyc_E1_div = cyc_E1 && ! sqrtOp_PC
val cyc_E4_sqrt = cyc_E4 && sqrtOp_PC
val cyc_E3_sqrt = cyc_E3 && sqrtOp_PC
val cyc_E2_sqrt = cyc_E2 && sqrtOp_PC
val cyc_E1_sqrt = cyc_E1 && sqrtOp_PC
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PA =
entering_PA_normalCase || (cyc_S && (valid_PA || ! ready_PB))
when (entering_PA || leaving_PA) {
valid_PA := entering_PA
}
when (entering_PA) {
sqrtOp_PA := io.sqrtOp
majorExc_PA := majorExc_S
isNaN_PA := isNaN_S
isInf_PA := isInf_S
isZero_PA := isZero_S
sign_PA := sign_S
}
when (entering_PA_normalCase) {
sExp_PA := Mux(io.sqrtOp, rawB_S.sExp, sSatExpQuot_S_div)
fractB_PA := rawB_S.sig(51, 0)
roundingMode_PA := io.roundingMode
}
when (entering_PA_normalCase_div) {
fractA_PA := rawA_S.sig(51, 0)
}
val normalCase_PA = ! isNaN_PA && ! isInf_PA && ! isZero_PA
val sigA_PA = 1.U(1.W) ## fractA_PA
val sigB_PA = 1.U(1.W) ## fractB_PA
val valid_normalCase_leaving_PA = cyc_B4_div || cyc_B7_sqrt
val valid_leaving_PA =
Mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB)
leaving_PA := valid_PA && valid_leaving_PA
ready_PA := ! valid_PA || valid_leaving_PA
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PB_S =
cyc_S && ! normalCase_S && ! valid_PA &&
(leaving_PB || (! valid_PB && ! ready_PC))
val entering_PB_normalCase =
valid_PA && normalCase_PA && valid_normalCase_leaving_PA
val entering_PB = entering_PB_S || leaving_PA
when (entering_PB || leaving_PB) {
valid_PB := entering_PB
}
when (entering_PB) {
sqrtOp_PB := Mux(valid_PA, sqrtOp_PA, io.sqrtOp )
majorExc_PB := Mux(valid_PA, majorExc_PA, majorExc_S)
isNaN_PB := Mux(valid_PA, isNaN_PA, isNaN_S )
isInf_PB := Mux(valid_PA, isInf_PA, isInf_S )
isZero_PB := Mux(valid_PA, isZero_PA, isZero_S )
sign_PB := Mux(valid_PA, sign_PA, sign_S )
}
when (entering_PB_normalCase) {
sExp_PB := sExp_PA
bit0FractA_PB := fractA_PA(0)
fractB_PB := fractB_PA
roundingMode_PB := Mux(valid_PA, roundingMode_PA, io.roundingMode)
}
val normalCase_PB = ! isNaN_PB && ! isInf_PB && ! isZero_PB
val valid_normalCase_leaving_PB = cyc_C3
val valid_leaving_PB =
Mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC)
leaving_PB := valid_PB && valid_leaving_PB
ready_PB := ! valid_PB || valid_leaving_PB
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PC_S =
cyc_S && ! normalCase_S && ! valid_PA && ! valid_PB && ready_PC
val entering_PC_normalCase =
valid_PB && normalCase_PB && valid_normalCase_leaving_PB
val entering_PC = entering_PC_S || leaving_PB
when (entering_PC || leaving_PC) {
valid_PC := entering_PC
}
when (entering_PC) {
sqrtOp_PC := Mux(valid_PB, sqrtOp_PB, io.sqrtOp )
majorExc_PC := Mux(valid_PB, majorExc_PB, majorExc_S)
isNaN_PC := Mux(valid_PB, isNaN_PB, isNaN_S )
isInf_PC := Mux(valid_PB, isInf_PB, isInf_S )
isZero_PC := Mux(valid_PB, isZero_PB, isZero_S )
sign_PC := Mux(valid_PB, sign_PB, sign_S )
}
when (entering_PC_normalCase) {
sExp_PC := sExp_PB
bit0FractA_PC := bit0FractA_PB
fractB_PC := fractB_PB
roundingMode_PC := Mux(valid_PB, roundingMode_PB, io.roundingMode)
}
val normalCase_PC = ! isNaN_PC && ! isInf_PC && ! isZero_PC
val sigB_PC = 1.U(1.W) ## fractB_PC
val valid_leaving_PC = ! normalCase_PC || cyc_E1
leaving_PC := valid_PC && valid_leaving_PC
ready_PC := ! valid_PC || valid_leaving_PC
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
//*** NEED TO COMPUTE AS MUCH AS POSSIBLE IN PREVIOUS CYCLE?:
io.inReady_div :=
//*** REPLACE ALL OF '! cyc_B*_sqrt' BY '! (valid_PB && sqrtOp_PB)'?:
ready_PA && ! cyc_B7_sqrt && ! cyc_B6_sqrt && ! cyc_B5_sqrt &&
! cyc_B4_sqrt && ! cyc_B3 && ! cyc_B2 && ! cyc_B1_sqrt &&
! cyc_C5 && ! cyc_C4
io.inReady_sqrt :=
ready_PA && ! cyc_B6_sqrt && ! cyc_B5_sqrt && ! cyc_B4_sqrt &&
! cyc_B2_div && ! cyc_B1_sqrt
/*------------------------------------------------------------------------
| Macrostage A, built around a 9x9-bit multiplier-adder.
*------------------------------------------------------------------------*/
val zFractB_A4_div = Mux(cyc_A4_div, rawB_S.sig(51, 0), 0.U)
val zLinPiece_0_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 0.U)
val zLinPiece_1_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 1.U)
val zLinPiece_2_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 2.U)
val zLinPiece_3_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 3.U)
val zLinPiece_4_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 4.U)
val zLinPiece_5_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 5.U)
val zLinPiece_6_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 6.U)
val zLinPiece_7_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 7.U)
val zK1_A4_div =
Mux(zLinPiece_0_A4_div, "h1C7".U, 0.U) |
Mux(zLinPiece_1_A4_div, "h16C".U, 0.U) |
Mux(zLinPiece_2_A4_div, "h12A".U, 0.U) |
Mux(zLinPiece_3_A4_div, "h0F8".U, 0.U) |
Mux(zLinPiece_4_A4_div, "h0D2".U, 0.U) |
Mux(zLinPiece_5_A4_div, "h0B4".U, 0.U) |
Mux(zLinPiece_6_A4_div, "h09C".U, 0.U) |
Mux(zLinPiece_7_A4_div, "h089".U, 0.U)
val zComplFractK0_A4_div =
Mux(zLinPiece_0_A4_div, ~"hFE3".U(12.W), 0.U) |
Mux(zLinPiece_1_A4_div, ~"hC5D".U(12.W), 0.U) |
Mux(zLinPiece_2_A4_div, ~"h98A".U(12.W), 0.U) |
Mux(zLinPiece_3_A4_div, ~"h739".U(12.W), 0.U) |
Mux(zLinPiece_4_A4_div, ~"h54B".U(12.W), 0.U) |
Mux(zLinPiece_5_A4_div, ~"h3A9".U(12.W), 0.U) |
Mux(zLinPiece_6_A4_div, ~"h242".U(12.W), 0.U) |
Mux(zLinPiece_7_A4_div, ~"h10B".U(12.W), 0.U)
val zFractB_A7_sqrt = Mux(cyc_A7_sqrt, rawB_S.sig(51, 0), 0.U)
val zQuadPiece_0_A7_sqrt =
cyc_A7_sqrt && ! rawB_S.sExp(0) && ! rawB_S.sig(51)
val zQuadPiece_1_A7_sqrt =
cyc_A7_sqrt && ! rawB_S.sExp(0) && rawB_S.sig(51)
val zQuadPiece_2_A7_sqrt =
cyc_A7_sqrt && rawB_S.sExp(0) && ! rawB_S.sig(51)
val zQuadPiece_3_A7_sqrt = cyc_A7_sqrt && rawB_S.sExp(0) && rawB_S.sig(51)
val zK2_A7_sqrt =
Mux(zQuadPiece_0_A7_sqrt, "h1C8".U, 0.U) |
Mux(zQuadPiece_1_A7_sqrt, "h0C1".U, 0.U) |
Mux(zQuadPiece_2_A7_sqrt, "h143".U, 0.U) |
Mux(zQuadPiece_3_A7_sqrt, "h089".U, 0.U)
val zComplK1_A7_sqrt =
Mux(zQuadPiece_0_A7_sqrt, ~"h3D0".U(10.W), 0.U) |
Mux(zQuadPiece_1_A7_sqrt, ~"h220".U(10.W), 0.U) |
Mux(zQuadPiece_2_A7_sqrt, ~"h2B2".U(10.W), 0.U) |
Mux(zQuadPiece_3_A7_sqrt, ~"h181".U(10.W), 0.U)
val zQuadPiece_0_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && ! sigB_PA(51)
val zQuadPiece_1_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && sigB_PA(51)
val zQuadPiece_2_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && ! sigB_PA(51)
val zQuadPiece_3_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && sigB_PA(51)
val zComplFractK0_A6_sqrt =
Mux(zQuadPiece_0_A6_sqrt, ~"h1FE5".U(13.W), 0.U) |
Mux(zQuadPiece_1_A6_sqrt, ~"h1435".U(13.W), 0.U) |
Mux(zQuadPiece_2_A6_sqrt, ~"h0D2C".U(13.W), 0.U) |
Mux(zQuadPiece_3_A6_sqrt, ~"h04E8".U(13.W), 0.U)
val mulAdd9A_A =
zFractB_A4_div(48, 40) | zK2_A7_sqrt |
Mux(! cyc_S, nextMulAdd9A_A, 0.U)
val mulAdd9B_A =
zK1_A4_div | zFractB_A7_sqrt(50, 42) |
Mux(! cyc_S, nextMulAdd9B_A, 0.U)
val mulAdd9C_A =
//*** ADJUST CONSTANTS SO 'Fill'S AREN'T NEEDED:
zComplK1_A7_sqrt ## Fill(10, cyc_A7_sqrt) |
Cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt, Fill(6, cyc_A6_sqrt)) |
Cat(cyc_A4_div, zComplFractK0_A4_div, Fill(8, cyc_A4_div )) |
Mux(cyc_A5_sqrt, (1<<18).U +& (fractR0_A<<10), 0.U) |
Mux(cyc_A4_sqrt && ! hiSqrR0_A_sqrt(9), (1<<10).U, 0.U) |
Mux((cyc_A4_sqrt && hiSqrR0_A_sqrt(9)) || cyc_A3_div,
sigB_PA(46, 26) + (1<<10).U,
0.U
) |
Mux(cyc_A3_sqrt || cyc_A2, partNegSigma0_A, 0.U) |
Mux(cyc_A1_sqrt, fractR0_A<<16, 0.U) |
Mux(cyc_A1_div, fractR0_A<<15, 0.U)
val loMulAdd9Out_A = mulAdd9A_A * mulAdd9B_A +& mulAdd9C_A(17, 0)
val mulAdd9Out_A =
Cat(Mux(loMulAdd9Out_A(18),
mulAdd9C_A(24, 18) + 1.U,
mulAdd9C_A(24, 18)
),
loMulAdd9Out_A(17, 0)
)
val zFractR0_A6_sqrt =
Mux(cyc_A6_sqrt && mulAdd9Out_A(19), ~(mulAdd9Out_A>>10), 0.U)
/*------------------------------------------------------------------------
| ('sqrR0_A5_sqrt' is usually >= 1, but not always.)
*------------------------------------------------------------------------*/
val sqrR0_A5_sqrt = Mux(sExp_PA(0), mulAdd9Out_A<<1, mulAdd9Out_A)
val zFractR0_A4_div =
Mux(cyc_A4_div && mulAdd9Out_A(20), ~(mulAdd9Out_A>>11), 0.U)
val zSigma0_A2 =
Mux(cyc_A2 && mulAdd9Out_A(11), ~(mulAdd9Out_A>>2), 0.U)
val r1_A1 = (1<<15).U | Mux(sqrtOp_PA, mulAdd9Out_A>>10, mulAdd9Out_A>>9)
val ER1_A1_sqrt = Mux(sExp_PA(0), r1_A1<<1, r1_A1)
when (cyc_A6_sqrt || cyc_A4_div) {
fractR0_A := zFractR0_A6_sqrt | zFractR0_A4_div
}
when (cyc_A5_sqrt) {
hiSqrR0_A_sqrt := sqrR0_A5_sqrt>>10
}
when (cyc_A4_sqrt || cyc_A3) {
partNegSigma0_A := Mux(cyc_A4_sqrt, mulAdd9Out_A, mulAdd9Out_A>>9)
}
when (
cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A3 || cyc_A2
) {
nextMulAdd9A_A :=
Mux(cyc_A7_sqrt, ~mulAdd9Out_A>>11, 0.U) |
zFractR0_A6_sqrt |
Mux(cyc_A4_sqrt, sigB_PA(43, 35), 0.U) |
zFractB_A4_div(43, 35) |
Mux(cyc_A5_sqrt || cyc_A3, sigB_PA(52, 44), 0.U) |
zSigma0_A2
}
when (cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A2) {
nextMulAdd9B_A :=
zFractB_A7_sqrt(50, 42) |
zFractR0_A6_sqrt |
Mux(cyc_A5_sqrt, sqrR0_A5_sqrt(9, 1), 0.U) |
zFractR0_A4_div |
Mux(cyc_A4_sqrt, hiSqrR0_A_sqrt(8, 0), 0.U) |
Mux(cyc_A2, Cat(1.U(1.W), fractR0_A(8, 1)), 0.U)
}
when (cyc_A1_sqrt) {
ER1_B_sqrt := ER1_A1_sqrt
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.latchMulAddA_0 :=
cyc_A1 || cyc_B7_sqrt || cyc_B6_div || cyc_B4 || cyc_B3 ||
cyc_C6_sqrt || cyc_C4 || cyc_C1
io.mulAddA_0 :=
Mux(cyc_A1_sqrt, ER1_A1_sqrt<<36, 0.U) | // 52:36
Mux(cyc_B7_sqrt || cyc_A1_div, sigB_PA, 0.U) | // 52:0
Mux(cyc_B6_div, sigA_PA, 0.U) | // 52:0
zSigma1_B4(45, 12) | // 33:0
//*** ONLY 30 BITS NEEDED IN CYCLE C6:
Mux(cyc_B3 || cyc_C6_sqrt, sigXNU_B3_CX(57, 12), 0.U) | // 45:0
Mux(cyc_C4_div, sigXN_C(57, 25)<<13, 0.U) | // 45:13
Mux(cyc_C4_sqrt, u_C_sqrt<<15, 0.U) | // 45:15
Mux(cyc_C1_div, sigB_PC, 0.U) | // 52:0
zComplSigT_C1_sqrt // 53:0
io.latchMulAddB_0 :=
cyc_A1 || cyc_B7_sqrt || cyc_B6_sqrt || cyc_B4 ||
cyc_C6_sqrt || cyc_C4 || cyc_C1
io.mulAddB_0 :=
Mux(cyc_A1, r1_A1<<36, 0.U) | // 51:36
Mux(cyc_B7_sqrt, ESqrR1_B_sqrt<<19, 0.U) | // 50:19
Mux(cyc_B6_sqrt, ER1_B_sqrt<<36, 0.U) | // 52:36
zSigma1_B4 | // 45:0
Mux(cyc_C6_sqrt, sqrSigma1_C(30, 1), 0.U) | // 29:0
Mux(cyc_C4, sqrSigma1_C, 0.U) | // 32:0
zComplSigT_C1 // 53:0
io.usingMulAdd :=
Cat(cyc_A4 || cyc_A3_div || cyc_A1_div ||
cyc_B10_sqrt || cyc_B9_sqrt || cyc_B7_sqrt || cyc_B6 ||
cyc_B5_sqrt || cyc_B3_sqrt || cyc_B2_div || cyc_B1_sqrt ||
cyc_C4,
cyc_A3 || cyc_A2_div ||
cyc_B9_sqrt || cyc_B8_sqrt || cyc_B6 || cyc_B5 ||
cyc_B4_sqrt || cyc_B2_sqrt || cyc_B1_div || cyc_C6_sqrt ||
cyc_C3,
cyc_A2 || cyc_A1_div ||
cyc_B8_sqrt || cyc_B7_sqrt || cyc_B5 || cyc_B4 ||
cyc_B3_sqrt || cyc_B1_sqrt || cyc_C5 ||
cyc_C2,
io.latchMulAddA_0 || cyc_B6 || cyc_B2_sqrt
)
io.mulAddC_2 :=
Mux(cyc_B1, sigX1_B<<47, 0.U) |
Mux(cyc_C6_sqrt, sigX1_B<<46, 0.U) |
Mux(cyc_C4_sqrt || cyc_C2, sigXN_C<<47, 0.U) |
Mux(cyc_E3_div && ! E_E_div, bit0FractA_PC<<53, 0.U) |
Mux(cyc_E3_sqrt,
(Mux(sExp_PC(0),
sigB_PC(0)<<1,
(sigB_PC(1) ^ sigB_PC(0)) ## sigB_PC(0)
) ^ ((~ sigT_E(0))<<1)
)<<54,
0.U
)
val ESqrR1_B8_sqrt = io.mulAddResult_3(103, 72)
zSigma1_B4 := Mux(cyc_B4, ~io.mulAddResult_3(90, 45), 0.U)
val sqrSigma1_B1 = io.mulAddResult_3(79, 47)
sigXNU_B3_CX := io.mulAddResult_3(104, 47) // x1, x2, u (sqrt), xT'
val E_C1_div = ! io.mulAddResult_3(104)
zComplSigT_C1 :=
Mux((cyc_C1_div && ! E_C1_div) || cyc_C1_sqrt,
~io.mulAddResult_3(104, 51),
0.U
) |
Mux(cyc_C1_div && E_C1_div, ~io.mulAddResult_3(102, 50), 0.U)
zComplSigT_C1_sqrt :=
Mux(cyc_C1_sqrt, ~io.mulAddResult_3(104, 51), 0.U)
/*------------------------------------------------------------------------
| (For square root, 'sigT_C1' will usually be >= 1, but not always.)
*------------------------------------------------------------------------*/
val sigT_C1 = ~zComplSigT_C1
val remT_E2 = io.mulAddResult_3(55, 0)
when (cyc_B8_sqrt) {
ESqrR1_B_sqrt := ESqrR1_B8_sqrt
}
when (cyc_B3) {
sigX1_B := sigXNU_B3_CX
}
when (cyc_B1) {
sqrSigma1_C := sqrSigma1_B1
}
when (cyc_C6_sqrt || cyc_C5_div || cyc_C3_sqrt) {
sigXN_C := sigXNU_B3_CX
}
when (cyc_C5_sqrt) {
u_C_sqrt := sigXNU_B3_CX(56, 26)
}
when (cyc_C1) {
E_E_div := E_C1_div
sigT_E := sigT_C1
}
when (cyc_E2) {
isNegRemT_E := Mux(sqrtOp_PC, remT_E2(55), remT_E2(53))
isZeroRemT_E :=
(remT_E2(53, 0) === 0.U) &&
(! sqrtOp_PC || (remT_E2(55, 54) === 0.U))
}
/*------------------------------------------------------------------------
| T is the lower-bound "trial" result value, with 54 bits of precision.
| It is known that the true unrounded result is within the range of
| (T, T + (2 ulps of 54 bits)). X is defined as the best estimate,
| = T + (1 ulp), which is exactly in the middle of the possible range.
*------------------------------------------------------------------------*/
val trueLtX_E1 =
Mux(sqrtOp_PC, ! isNegRemT_E && ! isZeroRemT_E, isNegRemT_E)
val trueEqX_E1 = isZeroRemT_E
/*------------------------------------------------------------------------
| The inputs to these two values are stable for several clock cycles in
| advance, so the circuitry can be minimized at the expense of speed.
*** ANY WAY TO TELL THIS TO THE TOOLS?
*------------------------------------------------------------------------*/
val sExpP1_PC = sExp_PC + 1.S
val sigTP1_E = sigT_E +& 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := leaving_PC && ! sqrtOp_PC
io.rawOutValid_sqrt := leaving_PC && sqrtOp_PC
io.roundingModeOut := roundingMode_PC
io.invalidExc := majorExc_PC && isNaN_PC
io.infiniteExc := majorExc_PC && ! isNaN_PC
io.rawOut.isNaN := isNaN_PC
io.rawOut.isInf := isInf_PC
io.rawOut.isZero := isZero_PC
io.rawOut.sign := sign_PC
io.rawOut.sExp :=
Mux(! sqrtOp_PC && E_E_div, sExp_PC, 0.S) |
Mux(! sqrtOp_PC && ! E_E_div, sExpP1_PC, 0.S) |
Mux( sqrtOp_PC, (sExp_PC>>1) +& 1024.S, 0.S)
io.rawOut.sig := Mux(trueLtX_E1, sigT_E, sigTP1_E) ## ! trueEqX_E1
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class DivSqrtRecF64_mulAddZ31(options: Int) extends Module
{
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady_div = Output(Bool())
val inReady_sqrt = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(Bits(65.W))
val b = Input(Bits(65.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val usingMulAdd = Output(Bits(4.W))
val latchMulAddA_0 = Output(Bool())
val mulAddA_0 = Output(UInt(54.W))
val latchMulAddB_0 = Output(Bool())
val mulAddB_0 = Output(UInt(54.W))
val mulAddC_2 = Output(UInt(105.W))
val mulAddResult_3 = Input(UInt(105.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(Bits(65.W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecF64ToRaw = Module(new DivSqrtRecF64ToRaw_mulAddZ31)
io.inReady_div := divSqrtRecF64ToRaw.io.inReady_div
io.inReady_sqrt := divSqrtRecF64ToRaw.io.inReady_sqrt
divSqrtRecF64ToRaw.io.inValid := io.inValid
divSqrtRecF64ToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecF64ToRaw.io.a := io.a
divSqrtRecF64ToRaw.io.b := io.b
divSqrtRecF64ToRaw.io.roundingMode := io.roundingMode
io.usingMulAdd := divSqrtRecF64ToRaw.io.usingMulAdd
io.latchMulAddA_0 := divSqrtRecF64ToRaw.io.latchMulAddA_0
io.mulAddA_0 := divSqrtRecF64ToRaw.io.mulAddA_0
io.latchMulAddB_0 := divSqrtRecF64ToRaw.io.latchMulAddB_0
io.mulAddB_0 := divSqrtRecF64ToRaw.io.mulAddB_0
io.mulAddC_2 := divSqrtRecF64ToRaw.io.mulAddC_2
divSqrtRecF64ToRaw.io.mulAddResult_3 := io.mulAddResult_3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecF64ToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecF64ToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(11, 53, flRoundOpt_sigMSBitAlwaysZero))
roundRawFNToRecFN.io.invalidExc := divSqrtRecF64ToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecF64ToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecF64ToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecF64ToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module DivSqrtRecF64ToRaw_mulAddZ31(
input clock,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [2:0] io_roundingMode,
output [3:0] io_usingMulAdd,
output io_latchMulAddA_0,
output [53:0] io_mulAddA_0,
output io_latchMulAddB_0,
output [53:0] io_mulAddB_0,
output [104:0] io_mulAddC_2,
input [104:0] io_mulAddResult_3,
output io_rawOutValid_div,
output io_rawOutValid_sqrt,
output [2:0] io_roundingModeOut,
output io_invalidExc,
output io_infiniteExc,
output io_rawOut_isNaN,
output io_rawOut_isInf,
output io_rawOut_isZero,
output io_rawOut_sign,
output [12:0] io_rawOut_sExp,
output [55:0] io_rawOut_sig
);
wire [53:0] zComplSigT_C1_sqrt;
wire [52:0] _GEN;
wire _zComplSigT_C1_T_5_53;
wire [45:0] zSigma1_B4;
wire io_inReady_sqrt_0;
wire io_inReady_div_0;
wire ready_PC;
wire ready_PB;
reg [2:0] cycleNum_A;
reg [3:0] cycleNum_B;
reg [2:0] cycleNum_C;
reg [2:0] cycleNum_E;
reg valid_PA;
reg sqrtOp_PA;
reg majorExc_PA;
reg isNaN_PA;
reg isInf_PA;
reg isZero_PA;
reg sign_PA;
reg [12:0] sExp_PA;
reg [51:0] fractB_PA;
reg [51:0] fractA_PA;
reg [2:0] roundingMode_PA;
reg valid_PB;
reg sqrtOp_PB;
reg majorExc_PB;
reg isNaN_PB;
reg isInf_PB;
reg isZero_PB;
reg sign_PB;
reg [12:0] sExp_PB;
reg bit0FractA_PB;
reg [51:0] fractB_PB;
reg [2:0] roundingMode_PB;
reg valid_PC;
reg sqrtOp_PC;
reg majorExc_PC;
reg isNaN_PC;
reg isInf_PC;
reg isZero_PC;
reg sign_PC;
reg [12:0] sExp_PC;
reg bit0FractA_PC;
reg [51:0] fractB_PC;
reg [2:0] roundingMode_PC;
reg [8:0] fractR0_A;
reg [9:0] hiSqrR0_A_sqrt;
reg [20:0] partNegSigma0_A;
reg [8:0] nextMulAdd9A_A;
reg [8:0] nextMulAdd9B_A;
reg [16:0] ER1_B_sqrt;
reg [31:0] ESqrR1_B_sqrt;
reg [57:0] sigX1_B;
reg [32:0] sqrSigma1_C;
reg [57:0] sigXN_C;
reg [30:0] u_C_sqrt;
reg E_E_div;
reg [53:0] sigT_E;
reg isNegRemT_E;
reg isZeroRemT_E;
wire cyc_S_div = io_inReady_div_0 & io_inValid & ~io_sqrtOp;
wire cyc_S_sqrt = io_inReady_sqrt_0 & io_inValid & io_sqrtOp;
wire cyc_S = cyc_S_div | cyc_S_sqrt;
wire rawA_S_isZero = io_a[63:61] == 3'h0;
wire rawA_S_isNaN = (&(io_a[63:62])) & io_a[61];
wire rawA_S_isInf = (&(io_a[63:62])) & ~(io_a[61]);
wire rawB_S_isNaN = (&(io_b[63:62])) & io_b[61];
wire rawB_S_isInf = (&(io_b[63:62])) & ~(io_b[61]);
wire specialCaseB_S = rawB_S_isNaN | rawB_S_isInf | ~(|(io_b[63:61]));
wire normalCase_S_div = ~(rawA_S_isNaN | rawA_S_isInf | rawA_S_isZero) & ~specialCaseB_S;
wire normalCase_S_sqrt = ~specialCaseB_S & ~(io_b[64]);
wire entering_PA_normalCase_div = cyc_S_div & normalCase_S_div;
wire entering_PA_normalCase_sqrt = cyc_S_sqrt & normalCase_S_sqrt;
wire cyc_A6_sqrt = cycleNum_A == 3'h6;
wire cyc_A5_sqrt = cycleNum_A == 3'h5;
wire cyc_A4_sqrt = cycleNum_A == 3'h4;
wire cyc_A4 = cyc_A4_sqrt | entering_PA_normalCase_div;
wire cyc_A3 = cycleNum_A == 3'h3;
wire cyc_A2 = cycleNum_A == 3'h2;
wire cyc_A1 = cycleNum_A == 3'h1;
wire cyc_A3_div = cyc_A3 & ~sqrtOp_PA;
wire cyc_A1_div = cyc_A1 & ~sqrtOp_PA;
wire cyc_A1_sqrt = cyc_A1 & sqrtOp_PA;
wire cyc_B9_sqrt = cycleNum_B == 4'h9;
wire cyc_B8_sqrt = cycleNum_B == 4'h8;
wire cyc_B7_sqrt = cycleNum_B == 4'h7;
wire cyc_B6 = cycleNum_B == 4'h6;
wire cyc_B5 = cycleNum_B == 4'h5;
wire cyc_B4 = cycleNum_B == 4'h4;
wire cyc_B3 = cycleNum_B == 4'h3;
wire cyc_B2 = cycleNum_B == 4'h2;
wire cyc_B1 = cycleNum_B == 4'h1;
wire cyc_B6_div = cyc_B6 & valid_PA & ~sqrtOp_PA;
wire cyc_B2_div = cyc_B2 & ~sqrtOp_PB;
wire cyc_B6_sqrt = cyc_B6 & valid_PB & sqrtOp_PB;
wire cyc_B5_sqrt = cyc_B5 & valid_PB & sqrtOp_PB;
wire cyc_B4_sqrt = cyc_B4 & valid_PB & sqrtOp_PB;
wire cyc_B3_sqrt = cyc_B3 & sqrtOp_PB;
wire cyc_B2_sqrt = cyc_B2 & sqrtOp_PB;
wire cyc_B1_sqrt = cyc_B1 & sqrtOp_PB;
wire cyc_C6_sqrt = cycleNum_C == 3'h6;
wire cyc_C5 = cycleNum_C == 3'h5;
wire cyc_C4 = cycleNum_C == 3'h4;
wire cyc_C3 = cycleNum_C == 3'h3;
wire cyc_C2 = cycleNum_C == 3'h2;
wire cyc_C1 = cycleNum_C == 3'h1;
wire cyc_C1_div = cyc_C1 & ~sqrtOp_PC;
wire cyc_C4_sqrt = cyc_C4 & sqrtOp_PB;
wire cyc_C1_sqrt = cyc_C1 & sqrtOp_PC;
wire cyc_E3 = cycleNum_E == 3'h3;
wire normalCase_PA = ~isNaN_PA & ~isInf_PA & ~isZero_PA;
wire valid_normalCase_leaving_PA = cyc_B4 & valid_PA & ~sqrtOp_PA | cyc_B7_sqrt;
wire valid_leaving_PA = normalCase_PA ? valid_normalCase_leaving_PA : ready_PB;
wire leaving_PA = valid_PA & valid_leaving_PA;
wire ready_PA = ~valid_PA | valid_leaving_PA;
wire normalCase_PB = ~isNaN_PB & ~isInf_PB & ~isZero_PB;
wire valid_leaving_PB = normalCase_PB ? cyc_C3 : ready_PC;
wire leaving_PB = valid_PB & valid_leaving_PB;
assign ready_PB = ~valid_PB | valid_leaving_PB;
wire valid_leaving_PC = ~(~isNaN_PC & ~isInf_PC & ~isZero_PC) | cycleNum_E == 3'h1;
wire leaving_PC = valid_PC & valid_leaving_PC;
assign ready_PC = ~valid_PC | valid_leaving_PC;
assign io_inReady_div_0 = ready_PA & cycleNum_B != 4'h7 & ~cyc_B6_sqrt & ~cyc_B5_sqrt & ~cyc_B4_sqrt & cycleNum_B != 4'h3 & cycleNum_B != 4'h2 & ~cyc_B1_sqrt & cycleNum_C != 3'h5 & cycleNum_C != 3'h4;
assign io_inReady_sqrt_0 = ready_PA & ~cyc_B6_sqrt & ~cyc_B5_sqrt & ~cyc_B4_sqrt & ~cyc_B2_div & ~cyc_B1_sqrt;
wire [13:0] zFractB_A4_div = entering_PA_normalCase_div ? io_b[48:35] : 14'h0;
wire zLinPiece_0_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h0;
wire zLinPiece_1_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h1;
wire zLinPiece_2_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h2;
wire zLinPiece_3_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h3;
wire zLinPiece_4_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h4;
wire zLinPiece_5_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h5;
wire zLinPiece_6_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h6;
wire zLinPiece_7_A4_div = entering_PA_normalCase_div & (&(io_b[51:49]));
wire [8:0] _zK1_A4_div_T_4 = (zLinPiece_0_A4_div ? 9'h1C7 : 9'h0) | (zLinPiece_1_A4_div ? 9'h16C : 9'h0) | (zLinPiece_2_A4_div ? 9'h12A : 9'h0);
wire [8:0] zFractB_A7_sqrt = entering_PA_normalCase_sqrt ? io_b[50:42] : 9'h0;
wire zQuadPiece_0_A7_sqrt = entering_PA_normalCase_sqrt & ~(io_b[52]) & ~(io_b[51]);
wire zQuadPiece_1_A7_sqrt = entering_PA_normalCase_sqrt & ~(io_b[52]) & io_b[51];
wire zQuadPiece_2_A7_sqrt = entering_PA_normalCase_sqrt & io_b[52] & ~(io_b[51]);
wire zQuadPiece_3_A7_sqrt = entering_PA_normalCase_sqrt & io_b[52] & io_b[51];
wire [8:0] _zK2_A7_sqrt_T_4 = {zQuadPiece_0_A7_sqrt, (zQuadPiece_0_A7_sqrt ? 8'hC8 : 8'h0) | (zQuadPiece_1_A7_sqrt ? 8'hC1 : 8'h0)} | (zQuadPiece_2_A7_sqrt ? 9'h143 : 9'h0);
wire [19:0] _mulAdd9C_A_T_4 = {(zQuadPiece_0_A7_sqrt ? 10'h2F : 10'h0) | (zQuadPiece_1_A7_sqrt ? 10'h1DF : 10'h0) | (zQuadPiece_2_A7_sqrt ? 10'h14D : 10'h0) | (zQuadPiece_3_A7_sqrt ? 10'h27E : 10'h0), {10{entering_PA_normalCase_sqrt}}} | {cyc_A6_sqrt, (cyc_A6_sqrt & ~(sExp_PA[0]) & ~(fractB_PA[51]) ? 13'h1A : 13'h0) | (cyc_A6_sqrt & ~(sExp_PA[0]) & fractB_PA[51] ? 13'hBCA : 13'h0) | (cyc_A6_sqrt & sExp_PA[0] & ~(fractB_PA[51]) ? 13'h12D3 : 13'h0) | (cyc_A6_sqrt & sExp_PA[0] & fractB_PA[51] ? 13'h1B17 : 13'h0), {6{cyc_A6_sqrt}}};
wire [19:0] _GEN_0 = {_mulAdd9C_A_T_4[19:8] | (zLinPiece_0_A4_div ? 12'h1C : 12'h0) | (zLinPiece_1_A4_div ? 12'h3A2 : 12'h0) | (zLinPiece_2_A4_div ? 12'h675 : 12'h0) | (zLinPiece_3_A4_div ? 12'h8C6 : 12'h0) | (zLinPiece_4_A4_div ? 12'hAB4 : 12'h0) | (zLinPiece_5_A4_div ? 12'hC56 : 12'h0) | (zLinPiece_6_A4_div ? 12'hDBD : 12'h0) | (zLinPiece_7_A4_div ? 12'hEF4 : 12'h0), _mulAdd9C_A_T_4[7:0] | {8{entering_PA_normalCase_div}}} | (cyc_A5_sqrt ? {1'h0, fractR0_A, 10'h0} + 20'h40000 : 20'h0);
wire [24:0] _mulAdd9C_A_T_30 = {4'h0, {entering_PA_normalCase_div, _GEN_0[19:11], _GEN_0[10:0] | {cyc_A4_sqrt & ~(hiSqrR0_A_sqrt[9]), 10'h0}} | (cyc_A4_sqrt & hiSqrR0_A_sqrt[9] | cyc_A3_div ? fractB_PA[46:26] + 21'h400 : 21'h0) | (cyc_A3 & sqrtOp_PA | cyc_A2 ? partNegSigma0_A : 21'h0)} | (cyc_A1_sqrt ? {fractR0_A, 16'h0} : 25'h0);
wire [23:0] _GEN_1 = _mulAdd9C_A_T_30[23:0] | (cyc_A1_div ? {fractR0_A, 15'h0} : 24'h0);
wire [18:0] loMulAdd9Out_A = {1'h0, {9'h0, zFractB_A4_div[13:5] | {_zK2_A7_sqrt_T_4[8], _zK2_A7_sqrt_T_4[7:0] | (zQuadPiece_3_A7_sqrt ? 8'h89 : 8'h0)} | (cyc_S ? 9'h0 : nextMulAdd9A_A)} * {9'h0, {_zK1_A4_div_T_4[8], _zK1_A4_div_T_4[7:0] | (zLinPiece_3_A4_div ? 8'hF8 : 8'h0) | (zLinPiece_4_A4_div ? 8'hD2 : 8'h0) | (zLinPiece_5_A4_div ? 8'hB4 : 8'h0) | (zLinPiece_6_A4_div ? 8'h9C : 8'h0) | (zLinPiece_7_A4_div ? 8'h89 : 8'h0)} | zFractB_A7_sqrt | (cyc_S ? 9'h0 : nextMulAdd9B_A)}} + {1'h0, _GEN_1[17:0]};
wire [6:0] _mulAdd9Out_A_T_5 = loMulAdd9Out_A[18] ? {_mulAdd9C_A_T_30[24], _GEN_1[23:18]} + 7'h1 : {_mulAdd9C_A_T_30[24], _GEN_1[23:18]};
wire [15:0] r1_A1 = (sqrtOp_PA ? {1'h0, _mulAdd9Out_A_T_5, loMulAdd9Out_A[17:10]} : {_mulAdd9Out_A_T_5, loMulAdd9Out_A[17:9]}) | 16'h8000;
wire [16:0] ER1_A1_sqrt = sExp_PA[0] ? {r1_A1, 1'h0} : {1'h0, r1_A1};
wire _io_latchMulAddB_0_T = cyc_A1 | cyc_B7_sqrt;
wire io_latchMulAddA_0_0 = _io_latchMulAddB_0_T | cyc_B6_div | cyc_B4 | cyc_B3 | cyc_C6_sqrt | cyc_C4 | cyc_C1;
wire [52:0] _io_mulAddA_0_T_6 = (cyc_A1_sqrt ? {ER1_A1_sqrt, 36'h0} : 53'h0) | (cyc_B7_sqrt | cyc_A1_div ? {1'h1, fractB_PA} : 53'h0) | (cyc_B6_div ? {1'h1, fractA_PA} : 53'h0);
wire [51:0] _io_mulAddB_0_T_1 = cyc_A1 ? {r1_A1, 36'h0} : 52'h0;
wire [52:0] _io_mulAddB_0_T_7 = {1'h0, _io_mulAddB_0_T_1[51], _io_mulAddB_0_T_1[50:0] | (cyc_B7_sqrt ? {ESqrR1_B_sqrt, 19'h0} : 51'h0)} | (cyc_B6_sqrt ? {ER1_B_sqrt, 36'h0} : 53'h0);
wire [45:0] _GEN_2 = _io_mulAddB_0_T_7[45:0] | zSigma1_B4;
wire [104:0] _io_mulAddC_2_T_1 = cyc_B1 ? {sigX1_B, 47'h0} : 105'h0;
wire [104:0] _io_mulAddC_2_T_8 = {_io_mulAddC_2_T_1[104], _io_mulAddC_2_T_1[103:0] | (cyc_C6_sqrt ? {sigX1_B, 46'h0} : 104'h0)} | (cyc_C4_sqrt | cyc_C2 ? {sigXN_C, 47'h0} : 105'h0);
assign zSigma1_B4 = cyc_B4 ? ~(io_mulAddResult_3[90:45]) : 46'h0;
wire [53:0] _zComplSigT_C1_T_5 = cyc_C1_div & io_mulAddResult_3[104] | cyc_C1_sqrt ? ~(io_mulAddResult_3[104:51]) : 54'h0;
assign _zComplSigT_C1_T_5_53 = _zComplSigT_C1_T_5[53];
assign _GEN = _zComplSigT_C1_T_5[52:0] | (cyc_C1_div & ~(io_mulAddResult_3[104]) ? ~(io_mulAddResult_3[102:50]) : 53'h0);
assign zComplSigT_C1_sqrt = cyc_C1_sqrt ? ~(io_mulAddResult_3[104:51]) : 54'h0;
wire [54:0] _GEN_3 = {1'h0, sigT_E};
wire [13:0] sExpQuot_S_div = {2'h0, io_a[63:52]} + {{3{io_b[63]}}, ~(io_b[62:52])};
wire notSigNaNIn_invalidExc_S_div = rawA_S_isZero & ~(|(io_b[63:61])) | rawA_S_isInf & rawB_S_isInf;
wire notSigNaNIn_invalidExc_S_sqrt = ~rawB_S_isNaN & (|(io_b[63:61])) & io_b[64];
wire majorExc_S = io_sqrtOp ? rawB_S_isNaN & ~(io_b[51]) | notSigNaNIn_invalidExc_S_sqrt : rawA_S_isNaN & ~(io_a[51]) | rawB_S_isNaN & ~(io_b[51]) | notSigNaNIn_invalidExc_S_div | ~rawA_S_isNaN & ~rawA_S_isInf & ~(|(io_b[63:61]));
wire isNaN_S = io_sqrtOp ? rawB_S_isNaN | notSigNaNIn_invalidExc_S_sqrt : rawA_S_isNaN | rawB_S_isNaN | notSigNaNIn_invalidExc_S_div;
wire isInf_S = io_sqrtOp ? rawB_S_isInf : rawA_S_isInf | ~(|(io_b[63:61]));
wire isZero_S = io_sqrtOp ? ~(|(io_b[63:61])) : rawA_S_isZero | rawB_S_isInf;
wire sign_S = ~io_sqrtOp & io_a[64] ^ io_b[64];
wire normalCase_S = io_sqrtOp ? normalCase_S_sqrt : normalCase_S_div;
wire entering_PA_normalCase = entering_PA_normalCase_div | entering_PA_normalCase_sqrt;
wire entering_PA = entering_PA_normalCase | cyc_S & (valid_PA | ~ready_PB);
wire entering_PB = cyc_S & ~normalCase_S & ~valid_PA & (leaving_PB | ~valid_PB & ~ready_PC) | leaving_PA;
wire entering_PC = cyc_S & ~normalCase_S & ~valid_PA & ~valid_PB & ready_PC | leaving_PB;
wire [8:0] zFractR0_A6_sqrt = cyc_A6_sqrt & _mulAdd9Out_A_T_5[1] ? ~{_mulAdd9Out_A_T_5[0], loMulAdd9Out_A[17:10]} : 9'h0;
wire [18:0] sqrR0_A5_sqrt = sExp_PA[0] ? {_mulAdd9Out_A_T_5[0], loMulAdd9Out_A[17:0]} : {_mulAdd9Out_A_T_5[1:0], loMulAdd9Out_A[17:1]};
wire [8:0] _GEN_4 = {_mulAdd9Out_A_T_5[1:0], loMulAdd9Out_A[17:11]};
wire [8:0] zFractR0_A4_div = entering_PA_normalCase_div & _mulAdd9Out_A_T_5[2] ? ~_GEN_4 : 9'h0;
wire _GEN_5 = entering_PA_normalCase_sqrt | cyc_A6_sqrt | cyc_A5_sqrt | cyc_A4;
always @(posedge clock) begin
if (reset) begin
cycleNum_A <= 3'h0;
cycleNum_B <= 4'h0;
cycleNum_C <= 3'h0;
cycleNum_E <= 3'h0;
valid_PA <= 1'h0;
valid_PB <= 1'h0;
valid_PC <= 1'h0;
end
else begin
if (|{entering_PA_normalCase, cycleNum_A})
cycleNum_A <= {1'h0, {2{entering_PA_normalCase_div}}} | (entering_PA_normalCase_sqrt ? 3'h6 : 3'h0) | (entering_PA_normalCase ? 3'h0 : cycleNum_A - 3'h1);
if (|{cyc_A1, cycleNum_B})
cycleNum_B <= cyc_A1 ? (sqrtOp_PA ? 4'hA : 4'h6) : cycleNum_B - 4'h1;
if (|{cyc_B1, cycleNum_C})
cycleNum_C <= cyc_B1 ? (sqrtOp_PB ? 3'h6 : 3'h5) : cycleNum_C - 3'h1;
if (|{cyc_C1, cycleNum_E})
cycleNum_E <= cyc_C1 ? 3'h4 : cycleNum_E - 3'h1;
if (entering_PA | leaving_PA)
valid_PA <= entering_PA;
if (entering_PB | leaving_PB)
valid_PB <= entering_PB;
if (entering_PC | leaving_PC)
valid_PC <= entering_PC;
end
if (entering_PA) begin
sqrtOp_PA <= io_sqrtOp;
majorExc_PA <= majorExc_S;
isNaN_PA <= isNaN_S;
isInf_PA <= isInf_S;
isZero_PA <= isZero_S;
sign_PA <= sign_S;
end
if (entering_PA_normalCase) begin
sExp_PA <= io_sqrtOp ? {1'h0, io_b[63:52]} : {$signed(sExpQuot_S_div) > 14'shDFF ? 4'h6 : sExpQuot_S_div[12:9], sExpQuot_S_div[8:0]};
fractB_PA <= io_b[51:0];
roundingMode_PA <= io_roundingMode;
end
if (entering_PA_normalCase_div)
fractA_PA <= io_a[51:0];
if (entering_PB) begin
sqrtOp_PB <= valid_PA ? sqrtOp_PA : io_sqrtOp;
majorExc_PB <= valid_PA ? majorExc_PA : majorExc_S;
isNaN_PB <= valid_PA ? isNaN_PA : isNaN_S;
isInf_PB <= valid_PA ? isInf_PA : isInf_S;
isZero_PB <= valid_PA ? isZero_PA : isZero_S;
sign_PB <= valid_PA ? sign_PA : sign_S;
end
if (valid_PA & normalCase_PA & valid_normalCase_leaving_PA) begin
sExp_PB <= sExp_PA;
bit0FractA_PB <= fractA_PA[0];
fractB_PB <= fractB_PA;
roundingMode_PB <= valid_PA ? roundingMode_PA : io_roundingMode;
end
if (entering_PC) begin
sqrtOp_PC <= valid_PB ? sqrtOp_PB : io_sqrtOp;
majorExc_PC <= valid_PB ? majorExc_PB : majorExc_S;
isNaN_PC <= valid_PB ? isNaN_PB : isNaN_S;
isInf_PC <= valid_PB ? isInf_PB : isInf_S;
isZero_PC <= valid_PB ? isZero_PB : isZero_S;
sign_PC <= valid_PB ? sign_PB : sign_S;
end
if (valid_PB & normalCase_PB & cyc_C3) begin
sExp_PC <= sExp_PB;
bit0FractA_PC <= bit0FractA_PB;
fractB_PC <= fractB_PB;
roundingMode_PC <= valid_PB ? roundingMode_PB : io_roundingMode;
end
if (cyc_A6_sqrt | entering_PA_normalCase_div)
fractR0_A <= zFractR0_A6_sqrt | zFractR0_A4_div;
if (cyc_A5_sqrt)
hiSqrR0_A_sqrt <= sqrR0_A5_sqrt[18:9];
if (cyc_A4_sqrt | cyc_A3)
partNegSigma0_A <= cyc_A4_sqrt ? {_mulAdd9Out_A_T_5[2:0], loMulAdd9Out_A[17:0]} : {5'h0, _mulAdd9Out_A_T_5, loMulAdd9Out_A[17:9]};
if (_GEN_5 | cyc_A3 | cyc_A2)
nextMulAdd9A_A <= (entering_PA_normalCase_sqrt ? ~_GEN_4 : 9'h0) | zFractR0_A6_sqrt | (cyc_A4_sqrt ? fractB_PA[43:35] : 9'h0) | zFractB_A4_div[8:0] | (cyc_A5_sqrt | cyc_A3 ? {1'h1, fractB_PA[51:44]} : 9'h0) | (cyc_A2 & loMulAdd9Out_A[11] ? ~(loMulAdd9Out_A[10:2]) : 9'h0);
if (_GEN_5 | cyc_A2)
nextMulAdd9B_A <= zFractB_A7_sqrt | zFractR0_A6_sqrt | (cyc_A5_sqrt ? sqrR0_A5_sqrt[8:0] : 9'h0) | zFractR0_A4_div | (cyc_A4_sqrt ? hiSqrR0_A_sqrt[8:0] : 9'h0) | (cyc_A2 ? {1'h1, fractR0_A[8:1]} : 9'h0);
if (cyc_A1_sqrt)
ER1_B_sqrt <= ER1_A1_sqrt;
if (cyc_B8_sqrt)
ESqrR1_B_sqrt <= io_mulAddResult_3[103:72];
if (cyc_B3)
sigX1_B <= io_mulAddResult_3[104:47];
if (cyc_B1)
sqrSigma1_C <= io_mulAddResult_3[79:47];
if (cyc_C6_sqrt | cyc_C5 & ~sqrtOp_PB | cyc_C3 & sqrtOp_PB)
sigXN_C <= io_mulAddResult_3[104:47];
if (cyc_C5 & sqrtOp_PB)
u_C_sqrt <= io_mulAddResult_3[103:73];
if (cyc_C1) begin
E_E_div <= ~(io_mulAddResult_3[104]);
sigT_E <= ~{_zComplSigT_C1_T_5_53, _GEN};
end
if (cycleNum_E == 3'h2) begin
isNegRemT_E <= sqrtOp_PC ? io_mulAddResult_3[55] : io_mulAddResult_3[53];
isZeroRemT_E <= io_mulAddResult_3[53:0] == 54'h0 & (~sqrtOp_PC | io_mulAddResult_3[55:54] == 2'h0);
end
end
assign io_inReady_div = io_inReady_div_0;
assign io_inReady_sqrt = io_inReady_sqrt_0;
assign io_usingMulAdd = {cyc_A4 | cyc_A3_div | cyc_A1_div | cycleNum_B == 4'hA | cyc_B9_sqrt | cyc_B7_sqrt | cyc_B6 | cyc_B5_sqrt | cyc_B3_sqrt | cyc_B2_div | cyc_B1_sqrt | cyc_C4, cyc_A3 | cyc_A2 & ~sqrtOp_PA | cyc_B9_sqrt | cyc_B8_sqrt | cyc_B6 | cyc_B5 | cyc_B4_sqrt | cyc_B2_sqrt | cyc_B1 & ~sqrtOp_PB | cyc_C6_sqrt | cyc_C3, cyc_A2 | cyc_A1_div | cyc_B8_sqrt | cyc_B7_sqrt | cyc_B5 | cyc_B4 | cyc_B3_sqrt | cyc_B1_sqrt | cyc_C5 | cyc_C2, io_latchMulAddA_0_0 | cyc_B6 | cyc_B2_sqrt};
assign io_latchMulAddA_0 = io_latchMulAddA_0_0;
assign io_mulAddA_0 = {1'h0, {_io_mulAddA_0_T_6[52:46], {_io_mulAddA_0_T_6[45:34], _io_mulAddA_0_T_6[33:0] | zSigma1_B4[45:12]} | (cyc_B3 | cyc_C6_sqrt ? io_mulAddResult_3[104:59] : 46'h0) | (cyc_C4 & ~sqrtOp_PB ? {sigXN_C[57:25], 13'h0} : 46'h0) | (cyc_C4_sqrt ? {u_C_sqrt, 15'h0} : 46'h0)} | (cyc_C1_div ? {1'h1, fractB_PC} : 53'h0)} | zComplSigT_C1_sqrt;
assign io_latchMulAddB_0 = _io_latchMulAddB_0_T | cyc_B6_sqrt | cyc_B4 | cyc_C6_sqrt | cyc_C4 | cyc_C1;
assign io_mulAddB_0 = {_zComplSigT_C1_T_5_53, _io_mulAddB_0_T_7[52:46] | _GEN[52:46], _GEN_2[45:33] | _GEN[45:33], {_GEN_2[32:30], _GEN_2[29:0] | (cyc_C6_sqrt ? sqrSigma1_C[30:1] : 30'h0)} | (cyc_C4 ? sqrSigma1_C : 33'h0) | _GEN[32:0]};
assign io_mulAddC_2 = {_io_mulAddC_2_T_8[104:56], {_io_mulAddC_2_T_8[55:54], _io_mulAddC_2_T_8[53:0] | (cyc_E3 & ~sqrtOp_PC & ~E_E_div ? {bit0FractA_PC, 53'h0} : 54'h0)} | (cyc_E3 & sqrtOp_PC ? {(sExp_PC[0] ? {fractB_PC[0], 1'h0} : {fractB_PC[1] ^ fractB_PC[0], fractB_PC[0]}) ^ {~(sigT_E[0]), 1'h0}, 54'h0} : 56'h0)};
assign io_rawOutValid_div = leaving_PC & ~sqrtOp_PC;
assign io_rawOutValid_sqrt = leaving_PC & sqrtOp_PC;
assign io_roundingModeOut = roundingMode_PC;
assign io_invalidExc = majorExc_PC & isNaN_PC;
assign io_infiniteExc = majorExc_PC & ~isNaN_PC;
assign io_rawOut_isNaN = isNaN_PC;
assign io_rawOut_isInf = isInf_PC;
assign io_rawOut_isZero = isZero_PC;
assign io_rawOut_sign = sign_PC;
assign io_rawOut_sExp = (~sqrtOp_PC & E_E_div ? sExp_PC : 13'h0) | (sqrtOp_PC | E_E_div ? 13'h0 : sExp_PC + 13'h1) | (sqrtOp_PC ? {sExp_PC[12], sExp_PC[12:1]} + 13'h400 : 13'h0);
assign io_rawOut_sig = {(sqrtOp_PC ? ~isNegRemT_E & ~isZeroRemT_E : isNegRemT_E) ? _GEN_3 : _GEN_3 + 55'h1, ~isZeroRemT_E};
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.{Annotated, MuxT, property}
import scala.math.min
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.SeqToAugmentedSeq
class GatewayPLICIO extends Bundle {
val valid = Output(Bool())
val ready = Input(Bool())
val complete = Input(Bool())
}
class LevelGateway extends Module {
val io = IO(new Bundle {
val interrupt = Input(Bool())
val plic = new GatewayPLICIO
})
val inFlight = RegInit(false.B)
when (io.interrupt && io.plic.ready) { inFlight := true.B }
when (io.plic.complete) { inFlight := false.B }
io.plic.valid := io.interrupt && !inFlight
}
object PLICConsts
{
def maxDevices = 1023
def maxMaxHarts = 15872
def priorityBase = 0x0
def pendingBase = 0x1000
def enableBase = 0x2000
def hartBase = 0x200000
def claimOffset = 4
def priorityBytes = 4
def enableOffset(i: Int) = i * ((maxDevices+7)/8)
def hartOffset(i: Int) = i * 0x1000
def enableBase(i: Int):Int = enableOffset(i) + enableBase
def hartBase(i: Int):Int = hartOffset(i) + hartBase
def size(maxHarts: Int): Int = {
require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}")
1 << log2Ceil(hartBase(maxHarts))
}
require(hartBase >= enableBase(maxMaxHarts))
}
case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts)
{
require (maxPriorities >= 0)
def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1)
}
case object PLICKey extends Field[Option[PLICParams]](None)
case class PLICAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object PLICAttachKey extends Field(PLICAttachParams())
/** Platform-Level Interrupt Controller */
class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// plic0 => max devices 1023
val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val extra = Map(
"interrupt-controller" -> Nil,
"riscv,ndev" -> Seq(ResourceInt(nDevices)),
"riscv,max-priority" -> Seq(ResourceInt(nPriorities)),
"#interrupt-cells" -> Seq(ResourceInt(1)))
Description(name, mapping ++ extra)
}
}
val node : TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes,
undefZero = true,
concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
val intnode: IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false)
/* Negotiated sizes */
def nDevices: Int = intnode.edges.in.map(_.source.num).sum
def minPriorities = min(params.maxPriorities, nDevices)
def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1
def nHarts = intnode.edges.out.map(_.source.num).sum
// Assign all the devices unique ranges
lazy val sources = intnode.edges.in.map(_.source)
lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten
ResourceBinding {
flatSources.foreach { s => s.resources.foreach { r =>
// +1 because interrupt 0 is reserved
(s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }
} }
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
val (io_devices, edgesIn) = intnode.in.unzip
val (io_harts, _) = intnode.out.unzip
// Compact the interrupt vector the same way
val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
val harts = io_harts.flatten
def getNInterrupts = interrupts.size
println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
flatSources.foreach { s =>
// +1 because 0 is reserved, +1-1 because the range is half-open
println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
}
println("")
require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}")
require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}")
require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}")
require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}")
// For now, use LevelGateways for all TL2 interrupts
val gateways = interrupts.map { case i =>
val gateway = Module(new LevelGateway)
gateway.io.interrupt := i
gateway.io.plic
}
val prioBits = log2Ceil(nPriorities+1)
val priority =
if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nDevices max 1)(1.U))
val threshold =
if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nHarts)(0.U))
val pending = RegInit(VecInit.fill(nDevices max 1){false.B})
/* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */
val firstEnable = nDevices min 7
val fullEnables = (nDevices - firstEnable) / 8
val tailEnable = nDevices - firstEnable - 8*fullEnables
def enableRegs = (Reg(UInt(firstEnable.W)) +:
Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++
(if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None)
val enables = Seq.fill(nHarts) { enableRegs }
val enableVec = VecInit(enables.map(x => Cat(x.reverse)))
val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W))))
val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))
val pendingUInt = Cat(pending.reverse)
if(nDevices > 0) {
for (hart <- 0 until nHarts) {
val fanin = Module(new PLICFanIn(nDevices, prioBits))
fanin.io.prio := priority
fanin.io.ip := enableVec(hart) & pendingUInt
maxDevs(hart) := fanin.io.dev
harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)
}
}
// Priority registers are 32-bit aligned so treat each as its own group.
// Otherwise, the off-by-one nature of the priority registers gets confusing.
require(PLICConsts.priorityBytes == 4,
s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}")
def priorityRegDesc(i: Int) =
RegFieldDesc(
name = s"priority_$i",
desc = s"Acting priority of interrupt source $i",
group = Some(s"priority_${i}"),
groupDesc = Some(s"Acting priority of interrupt source ${i}"),
reset = if (nPriorities > 0) None else Some(1))
def pendingRegDesc(i: Int) =
RegFieldDesc(
name = s"pending_$i",
desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
group = Some("pending"),
groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."),
volatile = true)
def enableRegDesc(i: Int, j: Int, wide: Int) = {
val low = if (j == 0) 1 else j*8
val high = low + wide - 1
RegFieldDesc(
name = s"enables_${j}",
desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.",
group = Some(s"enables_${i}"),
groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source."))
}
def priorityRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, priorityRegDesc(i))
} else {
RegField.r(prioBits, x, priorityRegDesc(i))
}
val priorityRegFields = priority.zipWithIndex.map { case (p, i) =>
PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) ->
Seq(priorityRegField(p, i+1)) }
val pendingRegFields = Seq(PLICConsts.pendingBase ->
(RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))}))
val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) =>
RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) }
// When a hart reads a claim/complete register, then the
// device which is currently its highest priority is no longer pending.
// This code exploits the fact that, practically, only one claim/complete
// register can be read at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note: PLIC doesn't care which hart reads the register.
val claimer = Wire(Vec(nHarts, Bool()))
assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot
val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_)
val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools)
((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) =>
g.ready := !p
when (c || g.valid) { p := !c }
}
// When a hart writes a claim/complete register, then
// the written device (as long as it is actually enabled for that
// hart) is marked complete.
// This code exploits the fact that, practically, only one claim/complete register
// can be written at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note -- PLIC doesn't care which hart writes the register.
val completer = Wire(Vec(nHarts, Bool()))
assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot
val completerDev = Wire(UInt(log2Up(nDevices + 1).W))
val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U)
(gateways zip completedDevs.asBools.tail) foreach { case (g, c) =>
g.complete := c
}
def thresholdRegDesc(i: Int) =
RegFieldDesc(
name = s"threshold_$i",
desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.",
reset = if (nPriorities > 0) None else Some(1))
def thresholdRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, thresholdRegDesc(i))
} else {
RegField.r(prioBits, x, thresholdRegDesc(i))
}
val hartRegFields = Seq.tabulate(nHarts) { i =>
PLICConsts.hartBase(i) -> Seq(
thresholdRegField(threshold(i), i),
RegField(32-prioBits),
RegField(32,
RegReadFn { valid =>
claimer(i) := valid
(true.B, maxDevs(i))
},
RegWriteFn { (valid, data) =>
assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),
"completerDev should be consistent for all harts")
completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
completer(i) := valid && enableVec0(i)(completerDev)
true.B
},
Some(RegFieldDesc(s"claim_complete_$i",
s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
s"Writing the interrupt number back completes the interrupt.",
reset = None,
wrType = Some(RegFieldWrType.MODIFY),
rdAction = Some(RegFieldRdAction.MODIFY),
volatile = true))
)
)
}
node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
if (nDevices >= 2) {
val claimed = claimer(0) && maxDevs(0) > 0.U
val completed = completer(0)
property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete")
property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim")
val ep = enables(0).asUInt & pending.asUInt
val ep2 = RegNext(ep)
val diff = ep & ~ep2
property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle")
if (nPriorities > 0)
ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)),
"THRESHOLD", "interrupt pending but less than threshold")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc)
}
}
class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
val io = IO(new Bundle {
val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
val ip = Flipped(UInt(nDevices.W))
val dev = UInt(log2Ceil(nDevices+1).W)
val max = UInt(prioBits.W)
})
def findMax(x: Seq[UInt]): (UInt, UInt) = {
if (x.length > 1) {
val half = 1 << (log2Ceil(x.length) - 1)
val left = findMax(x take half)
val right = findMax(x drop half)
MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
} else (x.head, 0.U)
}
val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }
val (maxPri, maxDev) = findMax(effectivePriority)
io.max := maxPri // strips the always-constant high '1' bit
io.dev := maxDev
}
/** Trait that will connect a PLIC to a subsystem */
trait CanHavePeripheryPLIC { this: BaseSubsystem =>
val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>
val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)
val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain")
val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } }
plicDomainWrapper { plic.intnode :=* ibus.toPLIC }
(plic, plicDomainWrapper)
}.unzip
} | module PLICFanIn(
input io_prio_0,
input io_ip,
output io_dev,
output io_max
);
wire [1:0] effectivePriority_1 = {io_ip, io_prio_0};
assign io_dev = &effectivePriority_1;
assign io_max = (&effectivePriority_1) & io_prio_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module lo_us(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLEToBeat_SerialRAM_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_bits_head
);
assign io_beat_bits_head = 1'h1;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module next_35x6(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0:34];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.{Annotated, MuxT, property}
import scala.math.min
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.SeqToAugmentedSeq
class GatewayPLICIO extends Bundle {
val valid = Output(Bool())
val ready = Input(Bool())
val complete = Input(Bool())
}
class LevelGateway extends Module {
val io = IO(new Bundle {
val interrupt = Input(Bool())
val plic = new GatewayPLICIO
})
val inFlight = RegInit(false.B)
when (io.interrupt && io.plic.ready) { inFlight := true.B }
when (io.plic.complete) { inFlight := false.B }
io.plic.valid := io.interrupt && !inFlight
}
object PLICConsts
{
def maxDevices = 1023
def maxMaxHarts = 15872
def priorityBase = 0x0
def pendingBase = 0x1000
def enableBase = 0x2000
def hartBase = 0x200000
def claimOffset = 4
def priorityBytes = 4
def enableOffset(i: Int) = i * ((maxDevices+7)/8)
def hartOffset(i: Int) = i * 0x1000
def enableBase(i: Int):Int = enableOffset(i) + enableBase
def hartBase(i: Int):Int = hartOffset(i) + hartBase
def size(maxHarts: Int): Int = {
require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}")
1 << log2Ceil(hartBase(maxHarts))
}
require(hartBase >= enableBase(maxMaxHarts))
}
case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts)
{
require (maxPriorities >= 0)
def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1)
}
case object PLICKey extends Field[Option[PLICParams]](None)
case class PLICAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object PLICAttachKey extends Field(PLICAttachParams())
/** Platform-Level Interrupt Controller */
class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// plic0 => max devices 1023
val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val extra = Map(
"interrupt-controller" -> Nil,
"riscv,ndev" -> Seq(ResourceInt(nDevices)),
"riscv,max-priority" -> Seq(ResourceInt(nPriorities)),
"#interrupt-cells" -> Seq(ResourceInt(1)))
Description(name, mapping ++ extra)
}
}
val node : TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes,
undefZero = true,
concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
val intnode: IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false)
/* Negotiated sizes */
def nDevices: Int = intnode.edges.in.map(_.source.num).sum
def minPriorities = min(params.maxPriorities, nDevices)
def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1
def nHarts = intnode.edges.out.map(_.source.num).sum
// Assign all the devices unique ranges
lazy val sources = intnode.edges.in.map(_.source)
lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten
ResourceBinding {
flatSources.foreach { s => s.resources.foreach { r =>
// +1 because interrupt 0 is reserved
(s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }
} }
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
val (io_devices, edgesIn) = intnode.in.unzip
val (io_harts, _) = intnode.out.unzip
// Compact the interrupt vector the same way
val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
val harts = io_harts.flatten
def getNInterrupts = interrupts.size
println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
flatSources.foreach { s =>
// +1 because 0 is reserved, +1-1 because the range is half-open
println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
}
println("")
require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}")
require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}")
require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}")
require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}")
// For now, use LevelGateways for all TL2 interrupts
val gateways = interrupts.map { case i =>
val gateway = Module(new LevelGateway)
gateway.io.interrupt := i
gateway.io.plic
}
val prioBits = log2Ceil(nPriorities+1)
val priority =
if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nDevices max 1)(1.U))
val threshold =
if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nHarts)(0.U))
val pending = RegInit(VecInit.fill(nDevices max 1){false.B})
/* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */
val firstEnable = nDevices min 7
val fullEnables = (nDevices - firstEnable) / 8
val tailEnable = nDevices - firstEnable - 8*fullEnables
def enableRegs = (Reg(UInt(firstEnable.W)) +:
Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++
(if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None)
val enables = Seq.fill(nHarts) { enableRegs }
val enableVec = VecInit(enables.map(x => Cat(x.reverse)))
val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W))))
val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))
val pendingUInt = Cat(pending.reverse)
if(nDevices > 0) {
for (hart <- 0 until nHarts) {
val fanin = Module(new PLICFanIn(nDevices, prioBits))
fanin.io.prio := priority
fanin.io.ip := enableVec(hart) & pendingUInt
maxDevs(hart) := fanin.io.dev
harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)
}
}
// Priority registers are 32-bit aligned so treat each as its own group.
// Otherwise, the off-by-one nature of the priority registers gets confusing.
require(PLICConsts.priorityBytes == 4,
s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}")
def priorityRegDesc(i: Int) =
RegFieldDesc(
name = s"priority_$i",
desc = s"Acting priority of interrupt source $i",
group = Some(s"priority_${i}"),
groupDesc = Some(s"Acting priority of interrupt source ${i}"),
reset = if (nPriorities > 0) None else Some(1))
def pendingRegDesc(i: Int) =
RegFieldDesc(
name = s"pending_$i",
desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
group = Some("pending"),
groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."),
volatile = true)
def enableRegDesc(i: Int, j: Int, wide: Int) = {
val low = if (j == 0) 1 else j*8
val high = low + wide - 1
RegFieldDesc(
name = s"enables_${j}",
desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.",
group = Some(s"enables_${i}"),
groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source."))
}
def priorityRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, priorityRegDesc(i))
} else {
RegField.r(prioBits, x, priorityRegDesc(i))
}
val priorityRegFields = priority.zipWithIndex.map { case (p, i) =>
PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) ->
Seq(priorityRegField(p, i+1)) }
val pendingRegFields = Seq(PLICConsts.pendingBase ->
(RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))}))
val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) =>
RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) }
// When a hart reads a claim/complete register, then the
// device which is currently its highest priority is no longer pending.
// This code exploits the fact that, practically, only one claim/complete
// register can be read at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note: PLIC doesn't care which hart reads the register.
val claimer = Wire(Vec(nHarts, Bool()))
assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot
val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_)
val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools)
((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) =>
g.ready := !p
when (c || g.valid) { p := !c }
}
// When a hart writes a claim/complete register, then
// the written device (as long as it is actually enabled for that
// hart) is marked complete.
// This code exploits the fact that, practically, only one claim/complete register
// can be written at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note -- PLIC doesn't care which hart writes the register.
val completer = Wire(Vec(nHarts, Bool()))
assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot
val completerDev = Wire(UInt(log2Up(nDevices + 1).W))
val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U)
(gateways zip completedDevs.asBools.tail) foreach { case (g, c) =>
g.complete := c
}
def thresholdRegDesc(i: Int) =
RegFieldDesc(
name = s"threshold_$i",
desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.",
reset = if (nPriorities > 0) None else Some(1))
def thresholdRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, thresholdRegDesc(i))
} else {
RegField.r(prioBits, x, thresholdRegDesc(i))
}
val hartRegFields = Seq.tabulate(nHarts) { i =>
PLICConsts.hartBase(i) -> Seq(
thresholdRegField(threshold(i), i),
RegField(32-prioBits),
RegField(32,
RegReadFn { valid =>
claimer(i) := valid
(true.B, maxDevs(i))
},
RegWriteFn { (valid, data) =>
assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),
"completerDev should be consistent for all harts")
completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
completer(i) := valid && enableVec0(i)(completerDev)
true.B
},
Some(RegFieldDesc(s"claim_complete_$i",
s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
s"Writing the interrupt number back completes the interrupt.",
reset = None,
wrType = Some(RegFieldWrType.MODIFY),
rdAction = Some(RegFieldRdAction.MODIFY),
volatile = true))
)
)
}
node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
if (nDevices >= 2) {
val claimed = claimer(0) && maxDevs(0) > 0.U
val completed = completer(0)
property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete")
property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim")
val ep = enables(0).asUInt & pending.asUInt
val ep2 = RegNext(ep)
val diff = ep & ~ep2
property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle")
if (nPriorities > 0)
ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)),
"THRESHOLD", "interrupt pending but less than threshold")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc)
}
}
class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
val io = IO(new Bundle {
val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
val ip = Flipped(UInt(nDevices.W))
val dev = UInt(log2Ceil(nDevices+1).W)
val max = UInt(prioBits.W)
})
def findMax(x: Seq[UInt]): (UInt, UInt) = {
if (x.length > 1) {
val half = 1 << (log2Ceil(x.length) - 1)
val left = findMax(x take half)
val right = findMax(x drop half)
MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
} else (x.head, 0.U)
}
val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }
val (maxPri, maxDev) = findMax(effectivePriority)
io.max := maxPri // strips the always-constant high '1' bit
io.dev := maxDev
}
/** Trait that will connect a PLIC to a subsystem */
trait CanHavePeripheryPLIC { this: BaseSubsystem =>
val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>
val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)
val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain")
val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } }
plicDomainWrapper { plic.intnode :=* ibus.toPLIC }
(plic, plicDomainWrapper)
}.unzip
} | module LevelGateway(
input clock,
input reset,
input io_interrupt,
output io_plic_valid,
input io_plic_ready,
input io_plic_complete
);
reg inFlight;
always @(posedge clock) begin
if (reset)
inFlight <= 1'h0;
else
inFlight <= ~io_plic_complete & (io_interrupt & io_plic_ready | inFlight);
end
assign io_plic_valid = io_interrupt & ~inFlight;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W))
size := typ
val dat_padded = dat.pad(maxSize*8)
def misaligned: Bool =
(addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR
def mask = {
var res = 1.U
for (i <- 0 until log2Up(maxSize)) {
val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U)
val lower = Mux(addr(i), 0.U, res)
res = Cat(upper, lower)
}
res
}
protected def genData(i: Int): UInt =
if (i >= log2Up(maxSize)) dat_padded
else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1))
def data = genData(0)
def wordData = genData(2)
}
class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
private val size = new StoreGen(typ, addr, dat, maxSize).size
private def genData(logMinSize: Int): UInt = {
var res = dat
for (i <- log2Up(maxSize)-1 to logMinSize by -1) {
val pos = 8 << i
val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
val doZero = (i == 0).B && zero
val zeroed = Mux(doZero, 0.U, shifted)
res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
}
res
}
def wordData = genData(2)
def data = genData(0)
}
class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module {
val minXLen = 32
val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _)
val io = IO(new Bundle {
val mask = Input(UInt((operandBits / 8).W))
val cmd = Input(UInt(M_SZ.W))
val lhs = Input(UInt(operandBits.W))
val rhs = Input(UInt(operandBits.W))
val out = Output(UInt(operandBits.W))
val out_unmasked = Output(UInt(operandBits.W))
})
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
val add = io.cmd === M_XA_ADD
val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND
val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR
val adder_out = {
// partition the carry chain to support sub-xLen addition
val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_)
(io.lhs & mask) + (io.rhs & mask)
}
val less = {
// break up the comparator so the lower parts will be CSE'd
def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = {
if (n == minXLen) x(n-1, 0) < y(n-1, 0)
else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2)
}
def isLess(x: UInt, y: UInt, n: Int): Bool = {
val signed = {
val mask = M_XA_MIN ^ M_XA_MINU
(io.cmd & mask) === (M_XA_MIN & mask)
}
Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1)))
}
PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w))))
}
val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs)
val logic =
Mux(logic_and, io.lhs & io.rhs, 0.U) |
Mux(logic_xor, io.lhs ^ io.rhs, 0.U)
val out =
Mux(add, adder_out,
Mux(logic_and || logic_xor, logic,
minmax))
val wmask = FillInterleaved(8, io.mask)
io.out := wmask & out | ~wmask & io.lhs
io.out_unmasked := out
} | module AMOALU(
input [7:0] io_mask,
input [4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire _logic_xor_T_1 = io_cmd == 5'hA;
wire logic_and = _logic_xor_T_1 | io_cmd == 5'hB;
wire logic_xor = io_cmd == 5'h9 | _logic_xor_T_1;
wire [63:0] adder_out_mask = {32'hFFFFFFFF, io_mask[3], 31'h7FFFFFFF};
wire [63:0] wmask = {{8{io_mask[7]}}, {8{io_mask[6]}}, {8{io_mask[5]}}, {8{io_mask[4]}}, {8{io_mask[3]}}, {8{io_mask[2]}}, {8{io_mask[1]}}, {8{io_mask[0]}}};
assign io_out = wmask & (io_cmd == 5'h8 ? (io_lhs & adder_out_mask) + (io_rhs & adder_out_mask) : logic_and | logic_xor ? (logic_and ? io_lhs & io_rhs : 64'h0) | (logic_xor ? io_lhs ^ io_rhs : 64'h0) : ((io_mask[4] ? (io_lhs[63] == io_rhs[63] ? io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32] & io_lhs[31:0] < io_rhs[31:0] : io_cmd[1] ? io_rhs[63] : io_lhs[63]) : io_lhs[31] == io_rhs[31] ? io_lhs[31:0] < io_rhs[31:0] : io_cmd[1] ? io_rhs[31] : io_lhs[31]) ? io_cmd == 5'hC | io_cmd == 5'hE : io_cmd == 5'hD | io_cmd == 5'hF) ? io_lhs : io_rhs) | ~wmask & io_lhs;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
} | module PlusArgTimeout(
input clock,
input reset,
input [31:0] io_count
);
wire [31:0] _plusarg_reader_out;
plusarg_reader #(
.DEFAULT(0),
.FORMAT("max_core_cycles=%d"),
.WIDTH(32)
) plusarg_reader (
.out (_plusarg_reader_out)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2017 SiFive, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of SiFive nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*
s = sigWidth
c_i = newBit
Division:
width of a is (s+2)
Normal
------
(qi + ci * 2^(-i))*b <= a
q0 = 0
r0 = a
q(i+1) = qi + ci*2^(-i)
ri = a - qi*b
r(i+1) = a - q(i+1)*b
= a - qi*b - ci*2^(-i)*b
r(i+1) = ri - ci*2^(-i)*b
ci = ri >= 2^(-i)*b
summary_i = ri != 0
i = 0 to s+1
(s+1)th bit plus summary_(i+1) gives enough information for rounding
If (a < b), then we need to calculate (s+2)th bit and summary_(i+1)
because we need s bits ignoring the leading zero. (This is skipCycle2
part of Hauser's code.)
Hauser
------
sig_i = qi
rem_i = 2^(i-2)*ri
cycle_i = s+3-i
sig_0 = 0
rem_0 = a/4
cycle_0 = s+3
bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)
sig(i+1) = sig(i) + ci*bit_i
rem(i+1) = 2rem_i - ci*b/2
ci = 2rem_i >= b/2
bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)
cycle(i+1) = cycle_i-1
summary_1 = a <> b
summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0
Proof:
2^i*r(i+1) = 2^i*ri - ci*b. Qed
ci = 2^i*ri >= b. Qed
summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0
Now, note that all of ck's cannot be 0, since that means
a is 0. So when you traverse through a chain of 0 ck's,
from the end,
eventually, you reach a non-zero cj. That is exactly the
value of ri as the reminder remains the same. When all ck's
are 0 except c0 (which must be 1) then summary_1 is set
correctly according
to r1 = a-b != 0. So summary(i+1) is always set correctly
according to r(i+1)
Square root:
width of a is (s+1)
Normal
------
(xi + ci*2^(-i))^2 <= a
xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a
x0 = 0
x(i+1) = xi + ci*2^(-i)
ri = a - xi^2
r(i+1) = a - x(i+1)^2
= a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))
= ri - ci*2^(-i)*(2xi+ci*2^(-i))
= ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1
ci = ri >= 2^(-i)*(2xi + 2^(-i))
summary_i = ri != 0
i = 0 to s+1
For odd expression, do 2 steps initially.
(s+1)th bit plus summary_(i+1) gives enough information for rounding.
Hauser
------
sig_i = xi
rem_i = ri*2^(i-1)
cycle_i = s+2-i
bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)
sig_0 = 0
rem_0 = a/2
cycle_0 = s+2
bit_0 = 1 (= 2^s in terms of bit representation)
sig(i+1) = sig_i + ci * bit_i
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
ci = 2*sig_i + bit_i <= 2*rem_i
bit_i = 2^(cycle_i-2) (in terms of bit representation)
cycle(i+1) = cycle_i-1
summary_1 = a - (2^s) (in terms of bit representation)
summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0
Proof:
ci = 2*sig_i + bit_i <= 2*rem_i
ci = 2xi + 2^(-i) <= ri*2^i. Qed
sig(i+1) = sig_i + ci * bit_i
x(i+1) = xi + ci*2^(-i). Qed
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))
r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed
Same argument as before for summary.
------------------------------
Note that all registers are updated normally until cycle == 2.
At cycle == 2, rem is not updated, but all other registers are updated normally.
But, cycle == 1 does not read rem to calculate anything (note that final summary
is calculated using the values at cycle = 2).
*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))
val inReady = RegInit(true.B) // <-> (cycleNum <= 1)
val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)
val sqrtOp_Z = Reg(Bool())
val majorExc_Z = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_Z = Reg(Bool())
val isInf_Z = Reg(Bool())
val isZero_Z = Reg(Bool())
val sign_Z = Reg(Bool())
val sExp_Z = Reg(SInt((expWidth + 2).W))
val fractB_Z = Reg(UInt(sigWidth.W))
val roundingMode_Z = Reg(UInt(3.W))
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
val rem_Z = Reg(UInt((sigWidth + 2).W))
val notZeroRem_Z = Reg(Bool())
val sigX_Z = Reg(UInt((sigWidth + 2).W))
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rawA_S = io.a
val rawB_S = io.b
//*** IMPROVE THESE:
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +&
Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(expWidth + 1, expWidth - 2)
),
sExpQuot_S_div(expWidth - 3, 0)
).asSInt
val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)
val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val idle = cycleNum === 0.U
val entering = inReady && io.inValid
val entering_normalCase = entering && normalCase_S
val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B
val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B
when (! idle || entering) {
def computeCycleNum(f: UInt => UInt): UInt = {
Mux(entering & ! normalCase_S, f(1.U), 0.U) |
Mux(entering_normalCase,
Mux(io.sqrtOp,
Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),
f((sigWidth + 2).U)
),
0.U
) |
Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |
Mux(skipCycle2, f(1.U), 0.U)
}
inReady := computeCycleNum(_ <= 1.U).asBool
rawOutValid := computeCycleNum(_ === 1.U).asBool
cycleNum := computeCycleNum(x => x)
}
io.inReady := inReady
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering) {
sqrtOp_Z := io.sqrtOp
majorExc_Z := majorExc_S
isNaN_Z := isNaN_S
isInf_Z := isInf_S
isZero_Z := isZero_S
sign_Z := sign_S
sExp_Z :=
Mux(io.sqrtOp,
(rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,
sSatExpQuot_S_div
)
roundingMode_Z := io.roundingMode
}
when (entering || ! inReady && sqrtOp_Z) {
fractB_Z :=
Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |
Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |
Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rem =
Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |
Mux(inReady && oddSqrt_S,
Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,
rawA_S.sig(sigWidth - 3, 0)<<3
),
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady, fractB_Z, 0.U) |
Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) |
Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U)
val trialRem = rem.zext -& trialTerm.zext
val newBit = (0.S <= trialRem)
val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0)
val rem2 = nextRem_Z<<1
val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))
val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)
val trialRem2 =
Mux(newBit,
(trialRem<<1) - trialTerm2_newBit1.zext,
(rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)
val newBit2 = (0.S <= trialRem2)
val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)
val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)
processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||
processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||
!(processTwoBits && newBit2) && nextNotZeroRem_Z
val nextRem_Z_2 =
Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |
Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |
Mux(!processTwoBits, nextRem_Z, 0.U)
when (entering || ! inReady) {
notZeroRem_Z := nextNotZeroRem_Z_2
rem_Z := nextRem_Z_2
sigX_Z :=
Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |
Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) |
Mux(! inReady, sigX_Z, 0.U) |
Mux(! inReady && newBit, bitMask, 0.U) |
Mux(processTwoBits && newBit2, bitMask>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := rawOutValid && ! sqrtOp_Z
io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z
io.roundingModeOut := roundingMode_Z
io.invalidExc := majorExc_Z && isNaN_Z
io.infiniteExc := majorExc_Z && ! isNaN_Z
io.rawOut.isNaN := isNaN_Z
io.rawOut.isInf := isInf_Z
io.rawOut.isZero := isZero_Z
io.rawOut.sign := sign_Z
io.rawOut.sExp := sExp_Z
io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val divSqrtRawFN =
Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))
io.inReady := divSqrtRawFN.io.inReady
divSqrtRawFN.io.inValid := io.inValid
divSqrtRawFN.io.sqrtOp := io.sqrtOp
divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
divSqrtRawFN.io.roundingMode := io.roundingMode
io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div
io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt
io.roundingModeOut := divSqrtRawFN.io.roundingModeOut
io.invalidExc := divSqrtRawFN.io.invalidExc
io.infiniteExc := divSqrtRawFN.io.infiniteExc
io.rawOut := divSqrtRawFN.io.rawOut
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecFNToRaw =
Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))
io.inReady := divSqrtRecFNToRaw.io.inReady
divSqrtRecFNToRaw.io.inValid := io.inValid
divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecFNToRaw.io.a := io.a
divSqrtRecFNToRaw.io.b := io.b
divSqrtRecFNToRaw.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module DivSqrtRawFN_small_e5_s11(
input clock,
input reset,
output io_inReady,
input io_inValid,
input io_sqrtOp,
input io_a_isNaN,
input io_a_isInf,
input io_a_isZero,
input io_a_sign,
input [6:0] io_a_sExp,
input [11:0] io_a_sig,
input io_b_isNaN,
input io_b_isInf,
input io_b_isZero,
input io_b_sign,
input [6:0] io_b_sExp,
input [11:0] io_b_sig,
input [2:0] io_roundingMode,
output io_rawOutValid_div,
output io_rawOutValid_sqrt,
output [2:0] io_roundingModeOut,
output io_invalidExc,
output io_infiniteExc,
output io_rawOut_isNaN,
output io_rawOut_isInf,
output io_rawOut_isZero,
output io_rawOut_sign,
output [6:0] io_rawOut_sExp,
output [13:0] io_rawOut_sig
);
reg [3:0] cycleNum;
reg inReady;
reg rawOutValid;
reg sqrtOp_Z;
reg majorExc_Z;
reg isNaN_Z;
reg isInf_Z;
reg isZero_Z;
reg sign_Z;
reg [6:0] sExp_Z;
reg [10:0] fractB_Z;
reg [2:0] roundingMode_Z;
reg [12:0] rem_Z;
reg notZeroRem_Z;
reg [12:0] sigX_Z;
wire specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero;
wire normalCase_S = io_sqrtOp ? ~specialCaseA_S & ~io_a_sign : ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero);
wire skipCycle2 = cycleNum == 4'h3 & sigX_Z[12];
wire notSigNaNIn_invalidExc_S_div = io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf;
wire notSigNaNIn_invalidExc_S_sqrt = ~io_a_isNaN & ~io_a_isZero & io_a_sign;
wire [7:0] sExpQuot_S_div = {io_a_sExp[6], io_a_sExp} + {{3{io_b_sExp[5]}}, ~(io_b_sExp[4:0])};
wire [10:0] _fractB_Z_T_4 = inReady & ~io_sqrtOp ? {io_b_sig[9:0], 1'h0} : 11'h0;
wire _fractB_Z_T_10 = inReady & io_sqrtOp;
wire [15:0] _bitMask_T = 16'h1 << cycleNum;
wire oddSqrt_S = io_sqrtOp & io_a_sExp[0];
wire entering = inReady & io_inValid;
wire _sigX_Z_T_7 = inReady & oddSqrt_S;
wire [13:0] rem = {1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 13'h0} | (_sigX_Z_T_7 ? {io_a_sig[10:9] - 2'h1, io_a_sig[8:0], 3'h0} : 14'h0) | (inReady ? 14'h0 : {rem_Z, 1'h0});
wire [12:0] _trialTerm_T_3 = inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 13'h0;
wire [12:0] _trialTerm_T_9 = {_trialTerm_T_3[12], _trialTerm_T_3[11:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 11'h0}} | (_sigX_Z_T_7 ? 13'h1400 : 13'h0);
wire [15:0] trialRem = {2'h0, rem} - {2'h0, {1'h0, _trialTerm_T_9[12], _trialTerm_T_9[11] | ~inReady & ~sqrtOp_Z, _trialTerm_T_9[10:0] | (inReady ? 11'h0 : fractB_Z)} | (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 14'h0)};
wire newBit = $signed(trialRem) > -16'sh1;
wire _GEN = entering | ~inReady;
wire [3:0] _cycleNum_T_15 = {3'h0, entering & ~normalCase_S} | (entering & normalCase_S ? (io_sqrtOp ? (io_a_sExp[0] ? 4'hB : 4'hC) : 4'hD) : 4'h0) | (entering | skipCycle2 ? 4'h0 : cycleNum - 4'h1);
wire [12:0] _sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 12'h0} : 13'h0;
wire [11:0] _GEN_0 = _sigX_Z_T_3[11:0] | {inReady & io_sqrtOp, 11'h0};
always @(posedge clock) begin
if (reset) begin
cycleNum <= 4'h0;
inReady <= 1'h1;
rawOutValid <= 1'h0;
end
else if ((|cycleNum) | entering) begin
cycleNum <= {_cycleNum_T_15[3:1], _cycleNum_T_15[0] | skipCycle2};
inReady <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 4'h1 < 4'h2 | skipCycle2;
rawOutValid <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 4'h1 == 4'h1 | skipCycle2;
end
if (entering) begin
sqrtOp_Z <= io_sqrtOp;
majorExc_Z <= io_sqrtOp ? io_a_isNaN & ~(io_a_sig[9]) | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN & ~(io_a_sig[9]) | io_b_isNaN & ~(io_b_sig[9]) | notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero;
isNaN_Z <= io_sqrtOp ? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div;
isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf;
isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero;
sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign;
sExp_Z <= io_sqrtOp ? {io_a_sExp[6], io_a_sExp[6:1]} + 7'h10 : {$signed(sExpQuot_S_div) > 8'sh37 ? 4'h6 : sExpQuot_S_div[6:3], sExpQuot_S_div[2:0]};
roundingMode_Z <= io_roundingMode;
end
if (entering | ~inReady & sqrtOp_Z)
fractB_Z <= {_fractB_Z_T_4[10] | _fractB_Z_T_10 & ~(io_a_sExp[0]), _fractB_Z_T_4[9:0] | {_fractB_Z_T_10 & io_a_sExp[0], 9'h0} | (inReady ? 10'h0 : fractB_Z[10:1])};
if (_GEN) begin
rem_Z <= newBit ? trialRem[12:0] : rem[12:0];
sigX_Z <= {_sigX_Z_T_3[12], _GEN_0[11], _GEN_0[10:0] | (_sigX_Z_T_7 ? {newBit, 10'h0} : 11'h0)} | (inReady ? 13'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[14:2] : 13'h0);
end
if (_GEN & (inReady | newBit))
notZeroRem_Z <= |trialRem;
end
assign io_inReady = inReady;
assign io_rawOutValid_div = rawOutValid & ~sqrtOp_Z;
assign io_rawOutValid_sqrt = rawOutValid & sqrtOp_Z;
assign io_roundingModeOut = roundingMode_Z;
assign io_invalidExc = majorExc_Z & isNaN_Z;
assign io_infiniteExc = majorExc_Z & ~isNaN_Z;
assign io_rawOut_isNaN = isNaN_Z;
assign io_rawOut_isInf = isInf_Z;
assign io_rawOut_isZero = isZero_Z;
assign io_rawOut_sign = sign_Z;
assign io_rawOut_sExp = sExp_Z;
assign io_rawOut_sig = {sigX_Z, notZeroRem_Z};
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundRawFNToRecFN_e11_s53(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 roundAnyRawFNToRecFN (
.io_invalidExc (io_invalidExc),
.io_in_isNaN (io_in_isNaN),
.io_in_isInf (io_in_isInf),
.io_in_isZero (io_in_isZero),
.io_in_sign (io_in_sign),
.io_in_sExp (io_in_sExp),
.io_in_sig (io_in_sig),
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module cc_banks_0(
input [13:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
class SourceCRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val opcode = UInt(3.W)
val param = UInt(3.W)
val source = UInt(params.outer.bundle.sourceBits.W)
val tag = UInt(params.tagBits.W)
val set = UInt(params.setBits.W)
val way = UInt(params.wayBits.W)
val dirty = Bool()
}
class SourceC(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new SourceCRequest(params)))
val c = Decoupled(new TLBundleC(params.outer.bundle))
// BankedStore port
val bs_adr = Decoupled(new BankedStoreOuterAddress(params))
val bs_dat = Flipped(new BankedStoreOuterDecoded(params))
// RaW hazard
val evict_req = new SourceDHazard(params)
val evict_safe = Flipped(Bool())
})
// We ignore the depth and pipe is useless here (we have to provision for worst-case=stall)
require (!params.micro.outerBuf.c.pipe)
val beatBytes = params.outer.manager.beatBytes
val beats = params.cache.blockBytes / beatBytes
val flow = params.micro.outerBuf.c.flow
val queue = Module(new Queue(chiselTypeOf(io.c.bits), beats + 3 + (if (flow) 0 else 1), flow = flow))
// queue.io.count is far too slow
val fillBits = log2Up(beats + 4)
val fill = RegInit(0.U(fillBits.W))
val room = RegInit(true.B)
when (queue.io.enq.fire =/= queue.io.deq.fire) {
fill := fill + Mux(queue.io.enq.fire, 1.U, ~0.U(fillBits.W))
room := fill === 0.U || ((fill === 1.U || fill === 2.U) && !queue.io.enq.fire)
}
assert (room === queue.io.count <= 1.U)
val busy = RegInit(false.B)
val beat = RegInit(0.U(params.outerBeatBits.W))
val last = if (params.cache.blockBytes == params.outer.manager.beatBytes) true.B else (beat === ~(0.U(params.outerBeatBits.W)))
val req = Mux(!busy, io.req.bits, RegEnable(io.req.bits, !busy && io.req.valid))
val want_data = busy || (io.req.valid && room && io.req.bits.dirty)
io.req.ready := !busy && room
io.evict_req.set := req.set
io.evict_req.way := req.way
io.bs_adr.valid := (beat.orR || io.evict_safe) && want_data
io.bs_adr.bits.noop := false.B
io.bs_adr.bits.way := req.way
io.bs_adr.bits.set := req.set
io.bs_adr.bits.beat := beat
io.bs_adr.bits.mask := ~0.U(params.outerMaskBits.W)
params.ccover(io.req.valid && io.req.bits.dirty && room && !io.evict_safe, "SOURCEC_HAZARD", "Prevented Eviction data hazard with backpressure")
params.ccover(io.bs_adr.valid && !io.bs_adr.ready, "SOURCEC_SRAM_STALL", "Data SRAM busy")
when (io.req.valid && room && io.req.bits.dirty) { busy := true.B }
when (io.bs_adr.fire) {
beat := beat + 1.U
when (last) {
busy := false.B
beat := 0.U
}
}
val s2_latch = Mux(want_data, io.bs_adr.fire, io.req.fire)
val s2_valid = RegNext(s2_latch)
val s2_req = RegEnable(req, s2_latch)
val s2_beat = RegEnable(beat, s2_latch)
val s2_last = RegEnable(last, s2_latch)
val s3_latch = s2_valid
val s3_valid = RegNext(s3_latch)
val s3_req = RegEnable(s2_req, s3_latch)
val s3_beat = RegEnable(s2_beat, s3_latch)
val s3_last = RegEnable(s2_last, s3_latch)
val c = Wire(chiselTypeOf(io.c))
c.valid := s3_valid
c.bits.opcode := s3_req.opcode
c.bits.param := s3_req.param
c.bits.size := params.offsetBits.U
c.bits.source := s3_req.source
c.bits.address := params.expandAddress(s3_req.tag, s3_req.set, 0.U)
c.bits.data := io.bs_dat.data
c.bits.corrupt := false.B
// We never accept at the front-end unless we're sure things will fit
assert(!c.valid || c.ready)
params.ccover(!c.ready, "SOURCEC_QUEUE_FULL", "Eviction queue fully utilized")
queue.io.enq <> c
io.c <> queue.io.deq
} | module SourceC(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [2:0] io_req_bits_opcode,
input [2:0] io_req_bits_param,
input [1:0] io_req_bits_source,
input [12:0] io_req_bits_tag,
input [9:0] io_req_bits_set,
input [2:0] io_req_bits_way,
input io_req_bits_dirty,
input io_c_ready,
output io_c_valid,
output [2:0] io_c_bits_opcode,
output [2:0] io_c_bits_param,
output [2:0] io_c_bits_size,
output [1:0] io_c_bits_source,
output [31:0] io_c_bits_address,
output [63:0] io_c_bits_data,
output io_c_bits_corrupt,
input io_bs_adr_ready,
output io_bs_adr_valid,
output [2:0] io_bs_adr_bits_way,
output [9:0] io_bs_adr_bits_set,
output [2:0] io_bs_adr_bits_beat,
input [63:0] io_bs_dat_data,
output [9:0] io_evict_req_set,
output [2:0] io_evict_req_way,
input io_evict_safe
);
wire _queue_io_enq_ready;
wire _queue_io_deq_valid;
wire [3:0] _queue_io_count;
reg [3:0] fill;
reg room;
reg busy;
reg [2:0] beat;
reg [2:0] req_r_opcode;
reg [2:0] req_r_param;
reg [1:0] req_r_source;
reg [12:0] req_r_tag;
reg [9:0] req_r_set;
reg [2:0] req_r_way;
wire [9:0] req_set = busy ? req_r_set : io_req_bits_set;
wire [2:0] req_way = busy ? req_r_way : io_req_bits_way;
wire _want_data_T = io_req_valid & room;
wire want_data = busy | _want_data_T & io_req_bits_dirty;
wire io_req_ready_0 = ~busy & room;
wire io_bs_adr_valid_0 = ((|beat) | io_evict_safe) & want_data;
reg s2_valid;
reg [2:0] s2_req_opcode;
reg [2:0] s2_req_param;
reg [1:0] s2_req_source;
reg [12:0] s2_req_tag;
reg [9:0] s2_req_set;
reg s3_valid;
reg [2:0] s3_req_opcode;
reg [2:0] s3_req_param;
reg [1:0] s3_req_source;
reg [12:0] s3_req_tag;
reg [9:0] s3_req_set;
wire _room_T_4 = _queue_io_enq_ready & s3_valid;
wire _s2_latch_T = io_bs_adr_ready & io_bs_adr_valid_0;
wire s2_latch = want_data ? _s2_latch_T : io_req_ready_0 & io_req_valid;
always @(posedge clock) begin
if (reset) begin
fill <= 4'h0;
room <= 1'h1;
busy <= 1'h0;
beat <= 3'h0;
end
else begin
if (~(_room_T_4 == (io_c_ready & _queue_io_deq_valid))) begin
fill <= fill + (_room_T_4 ? 4'h1 : 4'hF);
room <= fill == 4'h0 | (fill == 4'h1 | fill == 4'h2) & ~_room_T_4;
end
busy <= ~(_s2_latch_T & (&beat)) & (_want_data_T & io_req_bits_dirty | busy);
if (_s2_latch_T)
beat <= (&beat) ? 3'h0 : beat + 3'h1;
end
if (~busy & io_req_valid) begin
req_r_opcode <= io_req_bits_opcode;
req_r_param <= io_req_bits_param;
req_r_source <= io_req_bits_source;
req_r_tag <= io_req_bits_tag;
req_r_set <= io_req_bits_set;
req_r_way <= io_req_bits_way;
end
s2_valid <= s2_latch;
if (s2_latch) begin
s2_req_opcode <= busy ? req_r_opcode : io_req_bits_opcode;
s2_req_param <= busy ? req_r_param : io_req_bits_param;
s2_req_source <= busy ? req_r_source : io_req_bits_source;
s2_req_tag <= busy ? req_r_tag : io_req_bits_tag;
s2_req_set <= req_set;
end
s3_valid <= s2_valid;
if (s2_valid) begin
s3_req_opcode <= s2_req_opcode;
s3_req_param <= s2_req_param;
s3_req_source <= s2_req_source;
s3_req_tag <= s2_req_tag;
s3_req_set <= s2_req_set;
end
end
Queue12_TLBundleC_a32d64s2k3z3c queue (
.clock (clock),
.reset (reset),
.io_enq_ready (_queue_io_enq_ready),
.io_enq_valid (s3_valid),
.io_enq_bits_opcode (s3_req_opcode),
.io_enq_bits_param (s3_req_param),
.io_enq_bits_source (s3_req_source),
.io_enq_bits_address ({s3_req_tag[12], 3'h0, s3_req_tag[11:0], s3_req_set, 6'h0}),
.io_enq_bits_data (io_bs_dat_data),
.io_deq_ready (io_c_ready),
.io_deq_valid (_queue_io_deq_valid),
.io_deq_bits_opcode (io_c_bits_opcode),
.io_deq_bits_param (io_c_bits_param),
.io_deq_bits_size (io_c_bits_size),
.io_deq_bits_source (io_c_bits_source),
.io_deq_bits_address (io_c_bits_address),
.io_deq_bits_data (io_c_bits_data),
.io_deq_bits_corrupt (io_c_bits_corrupt),
.io_count (_queue_io_count)
);
assign io_req_ready = io_req_ready_0;
assign io_c_valid = _queue_io_deq_valid;
assign io_bs_adr_valid = io_bs_adr_valid_0;
assign io_bs_adr_bits_way = req_way;
assign io_bs_adr_bits_set = req_set;
assign io_bs_adr_bits_beat = beat;
assign io_evict_req_set = req_set;
assign io_evict_req_way = req_way;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
class SourceARequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val tag = UInt(params.tagBits.W)
val set = UInt(params.setBits.W)
val param = UInt(3.W)
val source = UInt(params.outer.bundle.sourceBits.W)
val block = Bool()
}
class SourceA(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new SourceARequest(params)))
val a = Decoupled(new TLBundleA(params.outer.bundle))
})
// ready must be a register, because we derive valid from ready
require (!params.micro.outerBuf.a.pipe && params.micro.outerBuf.a.isDefined)
val a = Wire(chiselTypeOf(io.a))
io.a <> params.micro.outerBuf.a(a)
io.req.ready := a.ready
a.valid := io.req.valid
params.ccover(a.valid && !a.ready, "SOURCEA_STALL", "Backpressured when issuing an Acquire")
a.bits.opcode := Mux(io.req.bits.block, TLMessages.AcquireBlock, TLMessages.AcquirePerm)
a.bits.param := io.req.bits.param
a.bits.size := params.offsetBits.U
a.bits.source := io.req.bits.source
a.bits.address := params.expandAddress(io.req.bits.tag, io.req.bits.set, 0.U)
a.bits.mask := ~0.U(params.outer.manager.beatBytes.W)
a.bits.data := 0.U
a.bits.corrupt := false.B
} | module SourceA(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [12:0] io_req_bits_tag,
input [9:0] io_req_bits_set,
input [2:0] io_req_bits_param,
input [1:0] io_req_bits_source,
input io_req_bits_block,
input io_a_ready,
output io_a_valid,
output [2:0] io_a_bits_opcode,
output [2:0] io_a_bits_param,
output [2:0] io_a_bits_size,
output [1:0] io_a_bits_source,
output [31:0] io_a_bits_address,
output [7:0] io_a_bits_mask,
output [63:0] io_a_bits_data,
output io_a_bits_corrupt
);
Queue2_TLBundleA_a32d64s2k3z3c io_a_q (
.clock (clock),
.reset (reset),
.io_enq_ready (io_req_ready),
.io_enq_valid (io_req_valid),
.io_enq_bits_opcode ({2'h3, ~io_req_bits_block}),
.io_enq_bits_param (io_req_bits_param),
.io_enq_bits_source (io_req_bits_source),
.io_enq_bits_address ({io_req_bits_tag[12], 3'h0, io_req_bits_tag[11:0], io_req_bits_set, 6'h0}),
.io_deq_ready (io_a_ready),
.io_deq_valid (io_a_valid),
.io_deq_bits_opcode (io_a_bits_opcode),
.io_deq_bits_param (io_a_bits_param),
.io_deq_bits_size (io_a_bits_size),
.io_deq_bits_source (io_a_bits_source),
.io_deq_bits_address (io_a_bits_address),
.io_deq_bits_mask (io_a_bits_mask),
.io_deq_bits_data (io_a_bits_data),
.io_deq_bits_corrupt (io_a_bits_corrupt)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
} | module Repeater_TLBundleA_a32d64s5k3z4u(
input clock,
input reset,
input io_repeat,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [3:0] io_enq_bits_size,
input [4:0] io_enq_bits_source,
input [31:0] io_enq_bits_address,
input [7:0] io_enq_bits_mask,
input [63:0] io_enq_bits_data,
input io_enq_bits_corrupt,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [3:0] io_deq_bits_size,
output [4:0] io_deq_bits_source,
output [31:0] io_deq_bits_address,
output [7:0] io_deq_bits_mask,
output [63:0] io_deq_bits_data,
output io_deq_bits_corrupt
);
reg full;
reg [2:0] saved_opcode;
reg [2:0] saved_param;
reg [3:0] saved_size;
reg [4:0] saved_source;
reg [31:0] saved_address;
reg [7:0] saved_mask;
reg [63:0] saved_data;
reg saved_corrupt;
wire io_deq_valid_0 = io_enq_valid | full;
wire io_enq_ready_0 = io_deq_ready & ~full;
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;
always @(posedge clock) begin
if (reset)
full <= 1'h0;
else
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);
if (_GEN) begin
saved_opcode <= io_enq_bits_opcode;
saved_param <= io_enq_bits_param;
saved_size <= io_enq_bits_size;
saved_source <= io_enq_bits_source;
saved_address <= io_enq_bits_address;
saved_mask <= io_enq_bits_mask;
saved_data <= io_enq_bits_data;
saved_corrupt <= io_enq_bits_corrupt;
end
end
assign io_enq_ready = io_enq_ready_0;
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;
assign io_deq_bits_data = full ? saved_data : io_enq_bits_data;
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
} | module BranchKillableQueue(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [6:0] io_enq_bits_uop_uopc,
input [31:0] io_enq_bits_uop_inst,
input [31:0] io_enq_bits_uop_debug_inst,
input io_enq_bits_uop_is_rvc,
input [39:0] io_enq_bits_uop_debug_pc,
input [2:0] io_enq_bits_uop_iq_type,
input [9:0] io_enq_bits_uop_fu_code,
input [3:0] io_enq_bits_uop_ctrl_br_type,
input [1:0] io_enq_bits_uop_ctrl_op1_sel,
input [2:0] io_enq_bits_uop_ctrl_op2_sel,
input [2:0] io_enq_bits_uop_ctrl_imm_sel,
input [4:0] io_enq_bits_uop_ctrl_op_fcn,
input io_enq_bits_uop_ctrl_fcn_dw,
input [2:0] io_enq_bits_uop_ctrl_csr_cmd,
input io_enq_bits_uop_ctrl_is_load,
input io_enq_bits_uop_ctrl_is_sta,
input io_enq_bits_uop_ctrl_is_std,
input [1:0] io_enq_bits_uop_iw_state,
input io_enq_bits_uop_iw_p1_poisoned,
input io_enq_bits_uop_iw_p2_poisoned,
input io_enq_bits_uop_is_br,
input io_enq_bits_uop_is_jalr,
input io_enq_bits_uop_is_jal,
input io_enq_bits_uop_is_sfb,
input [7:0] io_enq_bits_uop_br_mask,
input [2:0] io_enq_bits_uop_br_tag,
input [3:0] io_enq_bits_uop_ftq_idx,
input io_enq_bits_uop_edge_inst,
input [5:0] io_enq_bits_uop_pc_lob,
input io_enq_bits_uop_taken,
input [19:0] io_enq_bits_uop_imm_packed,
input [11:0] io_enq_bits_uop_csr_addr,
input [4:0] io_enq_bits_uop_rob_idx,
input [2:0] io_enq_bits_uop_ldq_idx,
input [2:0] io_enq_bits_uop_stq_idx,
input [1:0] io_enq_bits_uop_rxq_idx,
input [5:0] io_enq_bits_uop_pdst,
input [5:0] io_enq_bits_uop_prs1,
input [5:0] io_enq_bits_uop_prs2,
input [5:0] io_enq_bits_uop_prs3,
input [3:0] io_enq_bits_uop_ppred,
input io_enq_bits_uop_prs1_busy,
input io_enq_bits_uop_prs2_busy,
input io_enq_bits_uop_prs3_busy,
input io_enq_bits_uop_ppred_busy,
input [5:0] io_enq_bits_uop_stale_pdst,
input io_enq_bits_uop_exception,
input [63:0] io_enq_bits_uop_exc_cause,
input io_enq_bits_uop_bypassable,
input [4:0] io_enq_bits_uop_mem_cmd,
input [1:0] io_enq_bits_uop_mem_size,
input io_enq_bits_uop_mem_signed,
input io_enq_bits_uop_is_fence,
input io_enq_bits_uop_is_fencei,
input io_enq_bits_uop_is_amo,
input io_enq_bits_uop_uses_ldq,
input io_enq_bits_uop_uses_stq,
input io_enq_bits_uop_is_sys_pc2epc,
input io_enq_bits_uop_is_unique,
input io_enq_bits_uop_flush_on_commit,
input io_enq_bits_uop_ldst_is_rs1,
input [5:0] io_enq_bits_uop_ldst,
input [5:0] io_enq_bits_uop_lrs1,
input [5:0] io_enq_bits_uop_lrs2,
input [5:0] io_enq_bits_uop_lrs3,
input io_enq_bits_uop_ldst_val,
input [1:0] io_enq_bits_uop_dst_rtype,
input [1:0] io_enq_bits_uop_lrs1_rtype,
input [1:0] io_enq_bits_uop_lrs2_rtype,
input io_enq_bits_uop_frs3_en,
input io_enq_bits_uop_fp_val,
input io_enq_bits_uop_fp_single,
input io_enq_bits_uop_xcpt_pf_if,
input io_enq_bits_uop_xcpt_ae_if,
input io_enq_bits_uop_xcpt_ma_if,
input io_enq_bits_uop_bp_debug_if,
input io_enq_bits_uop_bp_xcpt_if,
input [1:0] io_enq_bits_uop_debug_fsrc,
input [1:0] io_enq_bits_uop_debug_tsrc,
input [39:0] io_enq_bits_addr,
input [63:0] io_enq_bits_data,
input io_enq_bits_is_hella,
input io_enq_bits_tag_match,
input [1:0] io_enq_bits_old_meta_coh_state,
input [19:0] io_enq_bits_old_meta_tag,
input [3:0] io_enq_bits_way_en,
input [4:0] io_enq_bits_sdq_id,
input io_deq_ready,
output io_deq_valid,
output [6:0] io_deq_bits_uop_uopc,
output [31:0] io_deq_bits_uop_inst,
output [31:0] io_deq_bits_uop_debug_inst,
output io_deq_bits_uop_is_rvc,
output [39:0] io_deq_bits_uop_debug_pc,
output [2:0] io_deq_bits_uop_iq_type,
output [9:0] io_deq_bits_uop_fu_code,
output [3:0] io_deq_bits_uop_ctrl_br_type,
output [1:0] io_deq_bits_uop_ctrl_op1_sel,
output [2:0] io_deq_bits_uop_ctrl_op2_sel,
output [2:0] io_deq_bits_uop_ctrl_imm_sel,
output [4:0] io_deq_bits_uop_ctrl_op_fcn,
output io_deq_bits_uop_ctrl_fcn_dw,
output [2:0] io_deq_bits_uop_ctrl_csr_cmd,
output io_deq_bits_uop_ctrl_is_load,
output io_deq_bits_uop_ctrl_is_sta,
output io_deq_bits_uop_ctrl_is_std,
output [1:0] io_deq_bits_uop_iw_state,
output io_deq_bits_uop_iw_p1_poisoned,
output io_deq_bits_uop_iw_p2_poisoned,
output io_deq_bits_uop_is_br,
output io_deq_bits_uop_is_jalr,
output io_deq_bits_uop_is_jal,
output io_deq_bits_uop_is_sfb,
output [7:0] io_deq_bits_uop_br_mask,
output [2:0] io_deq_bits_uop_br_tag,
output [3:0] io_deq_bits_uop_ftq_idx,
output io_deq_bits_uop_edge_inst,
output [5:0] io_deq_bits_uop_pc_lob,
output io_deq_bits_uop_taken,
output [19:0] io_deq_bits_uop_imm_packed,
output [11:0] io_deq_bits_uop_csr_addr,
output [4:0] io_deq_bits_uop_rob_idx,
output [2:0] io_deq_bits_uop_ldq_idx,
output [2:0] io_deq_bits_uop_stq_idx,
output [1:0] io_deq_bits_uop_rxq_idx,
output [5:0] io_deq_bits_uop_pdst,
output [5:0] io_deq_bits_uop_prs1,
output [5:0] io_deq_bits_uop_prs2,
output [5:0] io_deq_bits_uop_prs3,
output [3:0] io_deq_bits_uop_ppred,
output io_deq_bits_uop_prs1_busy,
output io_deq_bits_uop_prs2_busy,
output io_deq_bits_uop_prs3_busy,
output io_deq_bits_uop_ppred_busy,
output [5:0] io_deq_bits_uop_stale_pdst,
output io_deq_bits_uop_exception,
output [63:0] io_deq_bits_uop_exc_cause,
output io_deq_bits_uop_bypassable,
output [4:0] io_deq_bits_uop_mem_cmd,
output [1:0] io_deq_bits_uop_mem_size,
output io_deq_bits_uop_mem_signed,
output io_deq_bits_uop_is_fence,
output io_deq_bits_uop_is_fencei,
output io_deq_bits_uop_is_amo,
output io_deq_bits_uop_uses_ldq,
output io_deq_bits_uop_uses_stq,
output io_deq_bits_uop_is_sys_pc2epc,
output io_deq_bits_uop_is_unique,
output io_deq_bits_uop_flush_on_commit,
output io_deq_bits_uop_ldst_is_rs1,
output [5:0] io_deq_bits_uop_ldst,
output [5:0] io_deq_bits_uop_lrs1,
output [5:0] io_deq_bits_uop_lrs2,
output [5:0] io_deq_bits_uop_lrs3,
output io_deq_bits_uop_ldst_val,
output [1:0] io_deq_bits_uop_dst_rtype,
output [1:0] io_deq_bits_uop_lrs1_rtype,
output [1:0] io_deq_bits_uop_lrs2_rtype,
output io_deq_bits_uop_frs3_en,
output io_deq_bits_uop_fp_val,
output io_deq_bits_uop_fp_single,
output io_deq_bits_uop_xcpt_pf_if,
output io_deq_bits_uop_xcpt_ae_if,
output io_deq_bits_uop_xcpt_ma_if,
output io_deq_bits_uop_bp_debug_if,
output io_deq_bits_uop_bp_xcpt_if,
output [1:0] io_deq_bits_uop_debug_fsrc,
output [1:0] io_deq_bits_uop_debug_tsrc,
output [39:0] io_deq_bits_addr,
output io_deq_bits_is_hella,
output [4:0] io_deq_bits_sdq_id,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask,
input io_flush,
output io_empty
);
wire [45:0] _ram_ext_R0_data;
reg valids_0;
reg valids_1;
reg valids_2;
reg valids_3;
reg valids_4;
reg valids_5;
reg valids_6;
reg valids_7;
reg valids_8;
reg valids_9;
reg valids_10;
reg valids_11;
reg valids_12;
reg valids_13;
reg valids_14;
reg valids_15;
reg [6:0] uops_0_uopc;
reg [31:0] uops_0_inst;
reg [31:0] uops_0_debug_inst;
reg uops_0_is_rvc;
reg [39:0] uops_0_debug_pc;
reg [2:0] uops_0_iq_type;
reg [9:0] uops_0_fu_code;
reg [3:0] uops_0_ctrl_br_type;
reg [1:0] uops_0_ctrl_op1_sel;
reg [2:0] uops_0_ctrl_op2_sel;
reg [2:0] uops_0_ctrl_imm_sel;
reg [4:0] uops_0_ctrl_op_fcn;
reg uops_0_ctrl_fcn_dw;
reg [2:0] uops_0_ctrl_csr_cmd;
reg uops_0_ctrl_is_load;
reg uops_0_ctrl_is_sta;
reg uops_0_ctrl_is_std;
reg [1:0] uops_0_iw_state;
reg uops_0_iw_p1_poisoned;
reg uops_0_iw_p2_poisoned;
reg uops_0_is_br;
reg uops_0_is_jalr;
reg uops_0_is_jal;
reg uops_0_is_sfb;
reg [7:0] uops_0_br_mask;
reg [2:0] uops_0_br_tag;
reg [3:0] uops_0_ftq_idx;
reg uops_0_edge_inst;
reg [5:0] uops_0_pc_lob;
reg uops_0_taken;
reg [19:0] uops_0_imm_packed;
reg [11:0] uops_0_csr_addr;
reg [4:0] uops_0_rob_idx;
reg [2:0] uops_0_ldq_idx;
reg [2:0] uops_0_stq_idx;
reg [1:0] uops_0_rxq_idx;
reg [5:0] uops_0_pdst;
reg [5:0] uops_0_prs1;
reg [5:0] uops_0_prs2;
reg [5:0] uops_0_prs3;
reg [3:0] uops_0_ppred;
reg uops_0_prs1_busy;
reg uops_0_prs2_busy;
reg uops_0_prs3_busy;
reg uops_0_ppred_busy;
reg [5:0] uops_0_stale_pdst;
reg uops_0_exception;
reg [63:0] uops_0_exc_cause;
reg uops_0_bypassable;
reg [4:0] uops_0_mem_cmd;
reg [1:0] uops_0_mem_size;
reg uops_0_mem_signed;
reg uops_0_is_fence;
reg uops_0_is_fencei;
reg uops_0_is_amo;
reg uops_0_uses_ldq;
reg uops_0_uses_stq;
reg uops_0_is_sys_pc2epc;
reg uops_0_is_unique;
reg uops_0_flush_on_commit;
reg uops_0_ldst_is_rs1;
reg [5:0] uops_0_ldst;
reg [5:0] uops_0_lrs1;
reg [5:0] uops_0_lrs2;
reg [5:0] uops_0_lrs3;
reg uops_0_ldst_val;
reg [1:0] uops_0_dst_rtype;
reg [1:0] uops_0_lrs1_rtype;
reg [1:0] uops_0_lrs2_rtype;
reg uops_0_frs3_en;
reg uops_0_fp_val;
reg uops_0_fp_single;
reg uops_0_xcpt_pf_if;
reg uops_0_xcpt_ae_if;
reg uops_0_xcpt_ma_if;
reg uops_0_bp_debug_if;
reg uops_0_bp_xcpt_if;
reg [1:0] uops_0_debug_fsrc;
reg [1:0] uops_0_debug_tsrc;
reg [6:0] uops_1_uopc;
reg [31:0] uops_1_inst;
reg [31:0] uops_1_debug_inst;
reg uops_1_is_rvc;
reg [39:0] uops_1_debug_pc;
reg [2:0] uops_1_iq_type;
reg [9:0] uops_1_fu_code;
reg [3:0] uops_1_ctrl_br_type;
reg [1:0] uops_1_ctrl_op1_sel;
reg [2:0] uops_1_ctrl_op2_sel;
reg [2:0] uops_1_ctrl_imm_sel;
reg [4:0] uops_1_ctrl_op_fcn;
reg uops_1_ctrl_fcn_dw;
reg [2:0] uops_1_ctrl_csr_cmd;
reg uops_1_ctrl_is_load;
reg uops_1_ctrl_is_sta;
reg uops_1_ctrl_is_std;
reg [1:0] uops_1_iw_state;
reg uops_1_iw_p1_poisoned;
reg uops_1_iw_p2_poisoned;
reg uops_1_is_br;
reg uops_1_is_jalr;
reg uops_1_is_jal;
reg uops_1_is_sfb;
reg [7:0] uops_1_br_mask;
reg [2:0] uops_1_br_tag;
reg [3:0] uops_1_ftq_idx;
reg uops_1_edge_inst;
reg [5:0] uops_1_pc_lob;
reg uops_1_taken;
reg [19:0] uops_1_imm_packed;
reg [11:0] uops_1_csr_addr;
reg [4:0] uops_1_rob_idx;
reg [2:0] uops_1_ldq_idx;
reg [2:0] uops_1_stq_idx;
reg [1:0] uops_1_rxq_idx;
reg [5:0] uops_1_pdst;
reg [5:0] uops_1_prs1;
reg [5:0] uops_1_prs2;
reg [5:0] uops_1_prs3;
reg [3:0] uops_1_ppred;
reg uops_1_prs1_busy;
reg uops_1_prs2_busy;
reg uops_1_prs3_busy;
reg uops_1_ppred_busy;
reg [5:0] uops_1_stale_pdst;
reg uops_1_exception;
reg [63:0] uops_1_exc_cause;
reg uops_1_bypassable;
reg [4:0] uops_1_mem_cmd;
reg [1:0] uops_1_mem_size;
reg uops_1_mem_signed;
reg uops_1_is_fence;
reg uops_1_is_fencei;
reg uops_1_is_amo;
reg uops_1_uses_ldq;
reg uops_1_uses_stq;
reg uops_1_is_sys_pc2epc;
reg uops_1_is_unique;
reg uops_1_flush_on_commit;
reg uops_1_ldst_is_rs1;
reg [5:0] uops_1_ldst;
reg [5:0] uops_1_lrs1;
reg [5:0] uops_1_lrs2;
reg [5:0] uops_1_lrs3;
reg uops_1_ldst_val;
reg [1:0] uops_1_dst_rtype;
reg [1:0] uops_1_lrs1_rtype;
reg [1:0] uops_1_lrs2_rtype;
reg uops_1_frs3_en;
reg uops_1_fp_val;
reg uops_1_fp_single;
reg uops_1_xcpt_pf_if;
reg uops_1_xcpt_ae_if;
reg uops_1_xcpt_ma_if;
reg uops_1_bp_debug_if;
reg uops_1_bp_xcpt_if;
reg [1:0] uops_1_debug_fsrc;
reg [1:0] uops_1_debug_tsrc;
reg [6:0] uops_2_uopc;
reg [31:0] uops_2_inst;
reg [31:0] uops_2_debug_inst;
reg uops_2_is_rvc;
reg [39:0] uops_2_debug_pc;
reg [2:0] uops_2_iq_type;
reg [9:0] uops_2_fu_code;
reg [3:0] uops_2_ctrl_br_type;
reg [1:0] uops_2_ctrl_op1_sel;
reg [2:0] uops_2_ctrl_op2_sel;
reg [2:0] uops_2_ctrl_imm_sel;
reg [4:0] uops_2_ctrl_op_fcn;
reg uops_2_ctrl_fcn_dw;
reg [2:0] uops_2_ctrl_csr_cmd;
reg uops_2_ctrl_is_load;
reg uops_2_ctrl_is_sta;
reg uops_2_ctrl_is_std;
reg [1:0] uops_2_iw_state;
reg uops_2_iw_p1_poisoned;
reg uops_2_iw_p2_poisoned;
reg uops_2_is_br;
reg uops_2_is_jalr;
reg uops_2_is_jal;
reg uops_2_is_sfb;
reg [7:0] uops_2_br_mask;
reg [2:0] uops_2_br_tag;
reg [3:0] uops_2_ftq_idx;
reg uops_2_edge_inst;
reg [5:0] uops_2_pc_lob;
reg uops_2_taken;
reg [19:0] uops_2_imm_packed;
reg [11:0] uops_2_csr_addr;
reg [4:0] uops_2_rob_idx;
reg [2:0] uops_2_ldq_idx;
reg [2:0] uops_2_stq_idx;
reg [1:0] uops_2_rxq_idx;
reg [5:0] uops_2_pdst;
reg [5:0] uops_2_prs1;
reg [5:0] uops_2_prs2;
reg [5:0] uops_2_prs3;
reg [3:0] uops_2_ppred;
reg uops_2_prs1_busy;
reg uops_2_prs2_busy;
reg uops_2_prs3_busy;
reg uops_2_ppred_busy;
reg [5:0] uops_2_stale_pdst;
reg uops_2_exception;
reg [63:0] uops_2_exc_cause;
reg uops_2_bypassable;
reg [4:0] uops_2_mem_cmd;
reg [1:0] uops_2_mem_size;
reg uops_2_mem_signed;
reg uops_2_is_fence;
reg uops_2_is_fencei;
reg uops_2_is_amo;
reg uops_2_uses_ldq;
reg uops_2_uses_stq;
reg uops_2_is_sys_pc2epc;
reg uops_2_is_unique;
reg uops_2_flush_on_commit;
reg uops_2_ldst_is_rs1;
reg [5:0] uops_2_ldst;
reg [5:0] uops_2_lrs1;
reg [5:0] uops_2_lrs2;
reg [5:0] uops_2_lrs3;
reg uops_2_ldst_val;
reg [1:0] uops_2_dst_rtype;
reg [1:0] uops_2_lrs1_rtype;
reg [1:0] uops_2_lrs2_rtype;
reg uops_2_frs3_en;
reg uops_2_fp_val;
reg uops_2_fp_single;
reg uops_2_xcpt_pf_if;
reg uops_2_xcpt_ae_if;
reg uops_2_xcpt_ma_if;
reg uops_2_bp_debug_if;
reg uops_2_bp_xcpt_if;
reg [1:0] uops_2_debug_fsrc;
reg [1:0] uops_2_debug_tsrc;
reg [6:0] uops_3_uopc;
reg [31:0] uops_3_inst;
reg [31:0] uops_3_debug_inst;
reg uops_3_is_rvc;
reg [39:0] uops_3_debug_pc;
reg [2:0] uops_3_iq_type;
reg [9:0] uops_3_fu_code;
reg [3:0] uops_3_ctrl_br_type;
reg [1:0] uops_3_ctrl_op1_sel;
reg [2:0] uops_3_ctrl_op2_sel;
reg [2:0] uops_3_ctrl_imm_sel;
reg [4:0] uops_3_ctrl_op_fcn;
reg uops_3_ctrl_fcn_dw;
reg [2:0] uops_3_ctrl_csr_cmd;
reg uops_3_ctrl_is_load;
reg uops_3_ctrl_is_sta;
reg uops_3_ctrl_is_std;
reg [1:0] uops_3_iw_state;
reg uops_3_iw_p1_poisoned;
reg uops_3_iw_p2_poisoned;
reg uops_3_is_br;
reg uops_3_is_jalr;
reg uops_3_is_jal;
reg uops_3_is_sfb;
reg [7:0] uops_3_br_mask;
reg [2:0] uops_3_br_tag;
reg [3:0] uops_3_ftq_idx;
reg uops_3_edge_inst;
reg [5:0] uops_3_pc_lob;
reg uops_3_taken;
reg [19:0] uops_3_imm_packed;
reg [11:0] uops_3_csr_addr;
reg [4:0] uops_3_rob_idx;
reg [2:0] uops_3_ldq_idx;
reg [2:0] uops_3_stq_idx;
reg [1:0] uops_3_rxq_idx;
reg [5:0] uops_3_pdst;
reg [5:0] uops_3_prs1;
reg [5:0] uops_3_prs2;
reg [5:0] uops_3_prs3;
reg [3:0] uops_3_ppred;
reg uops_3_prs1_busy;
reg uops_3_prs2_busy;
reg uops_3_prs3_busy;
reg uops_3_ppred_busy;
reg [5:0] uops_3_stale_pdst;
reg uops_3_exception;
reg [63:0] uops_3_exc_cause;
reg uops_3_bypassable;
reg [4:0] uops_3_mem_cmd;
reg [1:0] uops_3_mem_size;
reg uops_3_mem_signed;
reg uops_3_is_fence;
reg uops_3_is_fencei;
reg uops_3_is_amo;
reg uops_3_uses_ldq;
reg uops_3_uses_stq;
reg uops_3_is_sys_pc2epc;
reg uops_3_is_unique;
reg uops_3_flush_on_commit;
reg uops_3_ldst_is_rs1;
reg [5:0] uops_3_ldst;
reg [5:0] uops_3_lrs1;
reg [5:0] uops_3_lrs2;
reg [5:0] uops_3_lrs3;
reg uops_3_ldst_val;
reg [1:0] uops_3_dst_rtype;
reg [1:0] uops_3_lrs1_rtype;
reg [1:0] uops_3_lrs2_rtype;
reg uops_3_frs3_en;
reg uops_3_fp_val;
reg uops_3_fp_single;
reg uops_3_xcpt_pf_if;
reg uops_3_xcpt_ae_if;
reg uops_3_xcpt_ma_if;
reg uops_3_bp_debug_if;
reg uops_3_bp_xcpt_if;
reg [1:0] uops_3_debug_fsrc;
reg [1:0] uops_3_debug_tsrc;
reg [6:0] uops_4_uopc;
reg [31:0] uops_4_inst;
reg [31:0] uops_4_debug_inst;
reg uops_4_is_rvc;
reg [39:0] uops_4_debug_pc;
reg [2:0] uops_4_iq_type;
reg [9:0] uops_4_fu_code;
reg [3:0] uops_4_ctrl_br_type;
reg [1:0] uops_4_ctrl_op1_sel;
reg [2:0] uops_4_ctrl_op2_sel;
reg [2:0] uops_4_ctrl_imm_sel;
reg [4:0] uops_4_ctrl_op_fcn;
reg uops_4_ctrl_fcn_dw;
reg [2:0] uops_4_ctrl_csr_cmd;
reg uops_4_ctrl_is_load;
reg uops_4_ctrl_is_sta;
reg uops_4_ctrl_is_std;
reg [1:0] uops_4_iw_state;
reg uops_4_iw_p1_poisoned;
reg uops_4_iw_p2_poisoned;
reg uops_4_is_br;
reg uops_4_is_jalr;
reg uops_4_is_jal;
reg uops_4_is_sfb;
reg [7:0] uops_4_br_mask;
reg [2:0] uops_4_br_tag;
reg [3:0] uops_4_ftq_idx;
reg uops_4_edge_inst;
reg [5:0] uops_4_pc_lob;
reg uops_4_taken;
reg [19:0] uops_4_imm_packed;
reg [11:0] uops_4_csr_addr;
reg [4:0] uops_4_rob_idx;
reg [2:0] uops_4_ldq_idx;
reg [2:0] uops_4_stq_idx;
reg [1:0] uops_4_rxq_idx;
reg [5:0] uops_4_pdst;
reg [5:0] uops_4_prs1;
reg [5:0] uops_4_prs2;
reg [5:0] uops_4_prs3;
reg [3:0] uops_4_ppred;
reg uops_4_prs1_busy;
reg uops_4_prs2_busy;
reg uops_4_prs3_busy;
reg uops_4_ppred_busy;
reg [5:0] uops_4_stale_pdst;
reg uops_4_exception;
reg [63:0] uops_4_exc_cause;
reg uops_4_bypassable;
reg [4:0] uops_4_mem_cmd;
reg [1:0] uops_4_mem_size;
reg uops_4_mem_signed;
reg uops_4_is_fence;
reg uops_4_is_fencei;
reg uops_4_is_amo;
reg uops_4_uses_ldq;
reg uops_4_uses_stq;
reg uops_4_is_sys_pc2epc;
reg uops_4_is_unique;
reg uops_4_flush_on_commit;
reg uops_4_ldst_is_rs1;
reg [5:0] uops_4_ldst;
reg [5:0] uops_4_lrs1;
reg [5:0] uops_4_lrs2;
reg [5:0] uops_4_lrs3;
reg uops_4_ldst_val;
reg [1:0] uops_4_dst_rtype;
reg [1:0] uops_4_lrs1_rtype;
reg [1:0] uops_4_lrs2_rtype;
reg uops_4_frs3_en;
reg uops_4_fp_val;
reg uops_4_fp_single;
reg uops_4_xcpt_pf_if;
reg uops_4_xcpt_ae_if;
reg uops_4_xcpt_ma_if;
reg uops_4_bp_debug_if;
reg uops_4_bp_xcpt_if;
reg [1:0] uops_4_debug_fsrc;
reg [1:0] uops_4_debug_tsrc;
reg [6:0] uops_5_uopc;
reg [31:0] uops_5_inst;
reg [31:0] uops_5_debug_inst;
reg uops_5_is_rvc;
reg [39:0] uops_5_debug_pc;
reg [2:0] uops_5_iq_type;
reg [9:0] uops_5_fu_code;
reg [3:0] uops_5_ctrl_br_type;
reg [1:0] uops_5_ctrl_op1_sel;
reg [2:0] uops_5_ctrl_op2_sel;
reg [2:0] uops_5_ctrl_imm_sel;
reg [4:0] uops_5_ctrl_op_fcn;
reg uops_5_ctrl_fcn_dw;
reg [2:0] uops_5_ctrl_csr_cmd;
reg uops_5_ctrl_is_load;
reg uops_5_ctrl_is_sta;
reg uops_5_ctrl_is_std;
reg [1:0] uops_5_iw_state;
reg uops_5_iw_p1_poisoned;
reg uops_5_iw_p2_poisoned;
reg uops_5_is_br;
reg uops_5_is_jalr;
reg uops_5_is_jal;
reg uops_5_is_sfb;
reg [7:0] uops_5_br_mask;
reg [2:0] uops_5_br_tag;
reg [3:0] uops_5_ftq_idx;
reg uops_5_edge_inst;
reg [5:0] uops_5_pc_lob;
reg uops_5_taken;
reg [19:0] uops_5_imm_packed;
reg [11:0] uops_5_csr_addr;
reg [4:0] uops_5_rob_idx;
reg [2:0] uops_5_ldq_idx;
reg [2:0] uops_5_stq_idx;
reg [1:0] uops_5_rxq_idx;
reg [5:0] uops_5_pdst;
reg [5:0] uops_5_prs1;
reg [5:0] uops_5_prs2;
reg [5:0] uops_5_prs3;
reg [3:0] uops_5_ppred;
reg uops_5_prs1_busy;
reg uops_5_prs2_busy;
reg uops_5_prs3_busy;
reg uops_5_ppred_busy;
reg [5:0] uops_5_stale_pdst;
reg uops_5_exception;
reg [63:0] uops_5_exc_cause;
reg uops_5_bypassable;
reg [4:0] uops_5_mem_cmd;
reg [1:0] uops_5_mem_size;
reg uops_5_mem_signed;
reg uops_5_is_fence;
reg uops_5_is_fencei;
reg uops_5_is_amo;
reg uops_5_uses_ldq;
reg uops_5_uses_stq;
reg uops_5_is_sys_pc2epc;
reg uops_5_is_unique;
reg uops_5_flush_on_commit;
reg uops_5_ldst_is_rs1;
reg [5:0] uops_5_ldst;
reg [5:0] uops_5_lrs1;
reg [5:0] uops_5_lrs2;
reg [5:0] uops_5_lrs3;
reg uops_5_ldst_val;
reg [1:0] uops_5_dst_rtype;
reg [1:0] uops_5_lrs1_rtype;
reg [1:0] uops_5_lrs2_rtype;
reg uops_5_frs3_en;
reg uops_5_fp_val;
reg uops_5_fp_single;
reg uops_5_xcpt_pf_if;
reg uops_5_xcpt_ae_if;
reg uops_5_xcpt_ma_if;
reg uops_5_bp_debug_if;
reg uops_5_bp_xcpt_if;
reg [1:0] uops_5_debug_fsrc;
reg [1:0] uops_5_debug_tsrc;
reg [6:0] uops_6_uopc;
reg [31:0] uops_6_inst;
reg [31:0] uops_6_debug_inst;
reg uops_6_is_rvc;
reg [39:0] uops_6_debug_pc;
reg [2:0] uops_6_iq_type;
reg [9:0] uops_6_fu_code;
reg [3:0] uops_6_ctrl_br_type;
reg [1:0] uops_6_ctrl_op1_sel;
reg [2:0] uops_6_ctrl_op2_sel;
reg [2:0] uops_6_ctrl_imm_sel;
reg [4:0] uops_6_ctrl_op_fcn;
reg uops_6_ctrl_fcn_dw;
reg [2:0] uops_6_ctrl_csr_cmd;
reg uops_6_ctrl_is_load;
reg uops_6_ctrl_is_sta;
reg uops_6_ctrl_is_std;
reg [1:0] uops_6_iw_state;
reg uops_6_iw_p1_poisoned;
reg uops_6_iw_p2_poisoned;
reg uops_6_is_br;
reg uops_6_is_jalr;
reg uops_6_is_jal;
reg uops_6_is_sfb;
reg [7:0] uops_6_br_mask;
reg [2:0] uops_6_br_tag;
reg [3:0] uops_6_ftq_idx;
reg uops_6_edge_inst;
reg [5:0] uops_6_pc_lob;
reg uops_6_taken;
reg [19:0] uops_6_imm_packed;
reg [11:0] uops_6_csr_addr;
reg [4:0] uops_6_rob_idx;
reg [2:0] uops_6_ldq_idx;
reg [2:0] uops_6_stq_idx;
reg [1:0] uops_6_rxq_idx;
reg [5:0] uops_6_pdst;
reg [5:0] uops_6_prs1;
reg [5:0] uops_6_prs2;
reg [5:0] uops_6_prs3;
reg [3:0] uops_6_ppred;
reg uops_6_prs1_busy;
reg uops_6_prs2_busy;
reg uops_6_prs3_busy;
reg uops_6_ppred_busy;
reg [5:0] uops_6_stale_pdst;
reg uops_6_exception;
reg [63:0] uops_6_exc_cause;
reg uops_6_bypassable;
reg [4:0] uops_6_mem_cmd;
reg [1:0] uops_6_mem_size;
reg uops_6_mem_signed;
reg uops_6_is_fence;
reg uops_6_is_fencei;
reg uops_6_is_amo;
reg uops_6_uses_ldq;
reg uops_6_uses_stq;
reg uops_6_is_sys_pc2epc;
reg uops_6_is_unique;
reg uops_6_flush_on_commit;
reg uops_6_ldst_is_rs1;
reg [5:0] uops_6_ldst;
reg [5:0] uops_6_lrs1;
reg [5:0] uops_6_lrs2;
reg [5:0] uops_6_lrs3;
reg uops_6_ldst_val;
reg [1:0] uops_6_dst_rtype;
reg [1:0] uops_6_lrs1_rtype;
reg [1:0] uops_6_lrs2_rtype;
reg uops_6_frs3_en;
reg uops_6_fp_val;
reg uops_6_fp_single;
reg uops_6_xcpt_pf_if;
reg uops_6_xcpt_ae_if;
reg uops_6_xcpt_ma_if;
reg uops_6_bp_debug_if;
reg uops_6_bp_xcpt_if;
reg [1:0] uops_6_debug_fsrc;
reg [1:0] uops_6_debug_tsrc;
reg [6:0] uops_7_uopc;
reg [31:0] uops_7_inst;
reg [31:0] uops_7_debug_inst;
reg uops_7_is_rvc;
reg [39:0] uops_7_debug_pc;
reg [2:0] uops_7_iq_type;
reg [9:0] uops_7_fu_code;
reg [3:0] uops_7_ctrl_br_type;
reg [1:0] uops_7_ctrl_op1_sel;
reg [2:0] uops_7_ctrl_op2_sel;
reg [2:0] uops_7_ctrl_imm_sel;
reg [4:0] uops_7_ctrl_op_fcn;
reg uops_7_ctrl_fcn_dw;
reg [2:0] uops_7_ctrl_csr_cmd;
reg uops_7_ctrl_is_load;
reg uops_7_ctrl_is_sta;
reg uops_7_ctrl_is_std;
reg [1:0] uops_7_iw_state;
reg uops_7_iw_p1_poisoned;
reg uops_7_iw_p2_poisoned;
reg uops_7_is_br;
reg uops_7_is_jalr;
reg uops_7_is_jal;
reg uops_7_is_sfb;
reg [7:0] uops_7_br_mask;
reg [2:0] uops_7_br_tag;
reg [3:0] uops_7_ftq_idx;
reg uops_7_edge_inst;
reg [5:0] uops_7_pc_lob;
reg uops_7_taken;
reg [19:0] uops_7_imm_packed;
reg [11:0] uops_7_csr_addr;
reg [4:0] uops_7_rob_idx;
reg [2:0] uops_7_ldq_idx;
reg [2:0] uops_7_stq_idx;
reg [1:0] uops_7_rxq_idx;
reg [5:0] uops_7_pdst;
reg [5:0] uops_7_prs1;
reg [5:0] uops_7_prs2;
reg [5:0] uops_7_prs3;
reg [3:0] uops_7_ppred;
reg uops_7_prs1_busy;
reg uops_7_prs2_busy;
reg uops_7_prs3_busy;
reg uops_7_ppred_busy;
reg [5:0] uops_7_stale_pdst;
reg uops_7_exception;
reg [63:0] uops_7_exc_cause;
reg uops_7_bypassable;
reg [4:0] uops_7_mem_cmd;
reg [1:0] uops_7_mem_size;
reg uops_7_mem_signed;
reg uops_7_is_fence;
reg uops_7_is_fencei;
reg uops_7_is_amo;
reg uops_7_uses_ldq;
reg uops_7_uses_stq;
reg uops_7_is_sys_pc2epc;
reg uops_7_is_unique;
reg uops_7_flush_on_commit;
reg uops_7_ldst_is_rs1;
reg [5:0] uops_7_ldst;
reg [5:0] uops_7_lrs1;
reg [5:0] uops_7_lrs2;
reg [5:0] uops_7_lrs3;
reg uops_7_ldst_val;
reg [1:0] uops_7_dst_rtype;
reg [1:0] uops_7_lrs1_rtype;
reg [1:0] uops_7_lrs2_rtype;
reg uops_7_frs3_en;
reg uops_7_fp_val;
reg uops_7_fp_single;
reg uops_7_xcpt_pf_if;
reg uops_7_xcpt_ae_if;
reg uops_7_xcpt_ma_if;
reg uops_7_bp_debug_if;
reg uops_7_bp_xcpt_if;
reg [1:0] uops_7_debug_fsrc;
reg [1:0] uops_7_debug_tsrc;
reg [6:0] uops_8_uopc;
reg [31:0] uops_8_inst;
reg [31:0] uops_8_debug_inst;
reg uops_8_is_rvc;
reg [39:0] uops_8_debug_pc;
reg [2:0] uops_8_iq_type;
reg [9:0] uops_8_fu_code;
reg [3:0] uops_8_ctrl_br_type;
reg [1:0] uops_8_ctrl_op1_sel;
reg [2:0] uops_8_ctrl_op2_sel;
reg [2:0] uops_8_ctrl_imm_sel;
reg [4:0] uops_8_ctrl_op_fcn;
reg uops_8_ctrl_fcn_dw;
reg [2:0] uops_8_ctrl_csr_cmd;
reg uops_8_ctrl_is_load;
reg uops_8_ctrl_is_sta;
reg uops_8_ctrl_is_std;
reg [1:0] uops_8_iw_state;
reg uops_8_iw_p1_poisoned;
reg uops_8_iw_p2_poisoned;
reg uops_8_is_br;
reg uops_8_is_jalr;
reg uops_8_is_jal;
reg uops_8_is_sfb;
reg [7:0] uops_8_br_mask;
reg [2:0] uops_8_br_tag;
reg [3:0] uops_8_ftq_idx;
reg uops_8_edge_inst;
reg [5:0] uops_8_pc_lob;
reg uops_8_taken;
reg [19:0] uops_8_imm_packed;
reg [11:0] uops_8_csr_addr;
reg [4:0] uops_8_rob_idx;
reg [2:0] uops_8_ldq_idx;
reg [2:0] uops_8_stq_idx;
reg [1:0] uops_8_rxq_idx;
reg [5:0] uops_8_pdst;
reg [5:0] uops_8_prs1;
reg [5:0] uops_8_prs2;
reg [5:0] uops_8_prs3;
reg [3:0] uops_8_ppred;
reg uops_8_prs1_busy;
reg uops_8_prs2_busy;
reg uops_8_prs3_busy;
reg uops_8_ppred_busy;
reg [5:0] uops_8_stale_pdst;
reg uops_8_exception;
reg [63:0] uops_8_exc_cause;
reg uops_8_bypassable;
reg [4:0] uops_8_mem_cmd;
reg [1:0] uops_8_mem_size;
reg uops_8_mem_signed;
reg uops_8_is_fence;
reg uops_8_is_fencei;
reg uops_8_is_amo;
reg uops_8_uses_ldq;
reg uops_8_uses_stq;
reg uops_8_is_sys_pc2epc;
reg uops_8_is_unique;
reg uops_8_flush_on_commit;
reg uops_8_ldst_is_rs1;
reg [5:0] uops_8_ldst;
reg [5:0] uops_8_lrs1;
reg [5:0] uops_8_lrs2;
reg [5:0] uops_8_lrs3;
reg uops_8_ldst_val;
reg [1:0] uops_8_dst_rtype;
reg [1:0] uops_8_lrs1_rtype;
reg [1:0] uops_8_lrs2_rtype;
reg uops_8_frs3_en;
reg uops_8_fp_val;
reg uops_8_fp_single;
reg uops_8_xcpt_pf_if;
reg uops_8_xcpt_ae_if;
reg uops_8_xcpt_ma_if;
reg uops_8_bp_debug_if;
reg uops_8_bp_xcpt_if;
reg [1:0] uops_8_debug_fsrc;
reg [1:0] uops_8_debug_tsrc;
reg [6:0] uops_9_uopc;
reg [31:0] uops_9_inst;
reg [31:0] uops_9_debug_inst;
reg uops_9_is_rvc;
reg [39:0] uops_9_debug_pc;
reg [2:0] uops_9_iq_type;
reg [9:0] uops_9_fu_code;
reg [3:0] uops_9_ctrl_br_type;
reg [1:0] uops_9_ctrl_op1_sel;
reg [2:0] uops_9_ctrl_op2_sel;
reg [2:0] uops_9_ctrl_imm_sel;
reg [4:0] uops_9_ctrl_op_fcn;
reg uops_9_ctrl_fcn_dw;
reg [2:0] uops_9_ctrl_csr_cmd;
reg uops_9_ctrl_is_load;
reg uops_9_ctrl_is_sta;
reg uops_9_ctrl_is_std;
reg [1:0] uops_9_iw_state;
reg uops_9_iw_p1_poisoned;
reg uops_9_iw_p2_poisoned;
reg uops_9_is_br;
reg uops_9_is_jalr;
reg uops_9_is_jal;
reg uops_9_is_sfb;
reg [7:0] uops_9_br_mask;
reg [2:0] uops_9_br_tag;
reg [3:0] uops_9_ftq_idx;
reg uops_9_edge_inst;
reg [5:0] uops_9_pc_lob;
reg uops_9_taken;
reg [19:0] uops_9_imm_packed;
reg [11:0] uops_9_csr_addr;
reg [4:0] uops_9_rob_idx;
reg [2:0] uops_9_ldq_idx;
reg [2:0] uops_9_stq_idx;
reg [1:0] uops_9_rxq_idx;
reg [5:0] uops_9_pdst;
reg [5:0] uops_9_prs1;
reg [5:0] uops_9_prs2;
reg [5:0] uops_9_prs3;
reg [3:0] uops_9_ppred;
reg uops_9_prs1_busy;
reg uops_9_prs2_busy;
reg uops_9_prs3_busy;
reg uops_9_ppred_busy;
reg [5:0] uops_9_stale_pdst;
reg uops_9_exception;
reg [63:0] uops_9_exc_cause;
reg uops_9_bypassable;
reg [4:0] uops_9_mem_cmd;
reg [1:0] uops_9_mem_size;
reg uops_9_mem_signed;
reg uops_9_is_fence;
reg uops_9_is_fencei;
reg uops_9_is_amo;
reg uops_9_uses_ldq;
reg uops_9_uses_stq;
reg uops_9_is_sys_pc2epc;
reg uops_9_is_unique;
reg uops_9_flush_on_commit;
reg uops_9_ldst_is_rs1;
reg [5:0] uops_9_ldst;
reg [5:0] uops_9_lrs1;
reg [5:0] uops_9_lrs2;
reg [5:0] uops_9_lrs3;
reg uops_9_ldst_val;
reg [1:0] uops_9_dst_rtype;
reg [1:0] uops_9_lrs1_rtype;
reg [1:0] uops_9_lrs2_rtype;
reg uops_9_frs3_en;
reg uops_9_fp_val;
reg uops_9_fp_single;
reg uops_9_xcpt_pf_if;
reg uops_9_xcpt_ae_if;
reg uops_9_xcpt_ma_if;
reg uops_9_bp_debug_if;
reg uops_9_bp_xcpt_if;
reg [1:0] uops_9_debug_fsrc;
reg [1:0] uops_9_debug_tsrc;
reg [6:0] uops_10_uopc;
reg [31:0] uops_10_inst;
reg [31:0] uops_10_debug_inst;
reg uops_10_is_rvc;
reg [39:0] uops_10_debug_pc;
reg [2:0] uops_10_iq_type;
reg [9:0] uops_10_fu_code;
reg [3:0] uops_10_ctrl_br_type;
reg [1:0] uops_10_ctrl_op1_sel;
reg [2:0] uops_10_ctrl_op2_sel;
reg [2:0] uops_10_ctrl_imm_sel;
reg [4:0] uops_10_ctrl_op_fcn;
reg uops_10_ctrl_fcn_dw;
reg [2:0] uops_10_ctrl_csr_cmd;
reg uops_10_ctrl_is_load;
reg uops_10_ctrl_is_sta;
reg uops_10_ctrl_is_std;
reg [1:0] uops_10_iw_state;
reg uops_10_iw_p1_poisoned;
reg uops_10_iw_p2_poisoned;
reg uops_10_is_br;
reg uops_10_is_jalr;
reg uops_10_is_jal;
reg uops_10_is_sfb;
reg [7:0] uops_10_br_mask;
reg [2:0] uops_10_br_tag;
reg [3:0] uops_10_ftq_idx;
reg uops_10_edge_inst;
reg [5:0] uops_10_pc_lob;
reg uops_10_taken;
reg [19:0] uops_10_imm_packed;
reg [11:0] uops_10_csr_addr;
reg [4:0] uops_10_rob_idx;
reg [2:0] uops_10_ldq_idx;
reg [2:0] uops_10_stq_idx;
reg [1:0] uops_10_rxq_idx;
reg [5:0] uops_10_pdst;
reg [5:0] uops_10_prs1;
reg [5:0] uops_10_prs2;
reg [5:0] uops_10_prs3;
reg [3:0] uops_10_ppred;
reg uops_10_prs1_busy;
reg uops_10_prs2_busy;
reg uops_10_prs3_busy;
reg uops_10_ppred_busy;
reg [5:0] uops_10_stale_pdst;
reg uops_10_exception;
reg [63:0] uops_10_exc_cause;
reg uops_10_bypassable;
reg [4:0] uops_10_mem_cmd;
reg [1:0] uops_10_mem_size;
reg uops_10_mem_signed;
reg uops_10_is_fence;
reg uops_10_is_fencei;
reg uops_10_is_amo;
reg uops_10_uses_ldq;
reg uops_10_uses_stq;
reg uops_10_is_sys_pc2epc;
reg uops_10_is_unique;
reg uops_10_flush_on_commit;
reg uops_10_ldst_is_rs1;
reg [5:0] uops_10_ldst;
reg [5:0] uops_10_lrs1;
reg [5:0] uops_10_lrs2;
reg [5:0] uops_10_lrs3;
reg uops_10_ldst_val;
reg [1:0] uops_10_dst_rtype;
reg [1:0] uops_10_lrs1_rtype;
reg [1:0] uops_10_lrs2_rtype;
reg uops_10_frs3_en;
reg uops_10_fp_val;
reg uops_10_fp_single;
reg uops_10_xcpt_pf_if;
reg uops_10_xcpt_ae_if;
reg uops_10_xcpt_ma_if;
reg uops_10_bp_debug_if;
reg uops_10_bp_xcpt_if;
reg [1:0] uops_10_debug_fsrc;
reg [1:0] uops_10_debug_tsrc;
reg [6:0] uops_11_uopc;
reg [31:0] uops_11_inst;
reg [31:0] uops_11_debug_inst;
reg uops_11_is_rvc;
reg [39:0] uops_11_debug_pc;
reg [2:0] uops_11_iq_type;
reg [9:0] uops_11_fu_code;
reg [3:0] uops_11_ctrl_br_type;
reg [1:0] uops_11_ctrl_op1_sel;
reg [2:0] uops_11_ctrl_op2_sel;
reg [2:0] uops_11_ctrl_imm_sel;
reg [4:0] uops_11_ctrl_op_fcn;
reg uops_11_ctrl_fcn_dw;
reg [2:0] uops_11_ctrl_csr_cmd;
reg uops_11_ctrl_is_load;
reg uops_11_ctrl_is_sta;
reg uops_11_ctrl_is_std;
reg [1:0] uops_11_iw_state;
reg uops_11_iw_p1_poisoned;
reg uops_11_iw_p2_poisoned;
reg uops_11_is_br;
reg uops_11_is_jalr;
reg uops_11_is_jal;
reg uops_11_is_sfb;
reg [7:0] uops_11_br_mask;
reg [2:0] uops_11_br_tag;
reg [3:0] uops_11_ftq_idx;
reg uops_11_edge_inst;
reg [5:0] uops_11_pc_lob;
reg uops_11_taken;
reg [19:0] uops_11_imm_packed;
reg [11:0] uops_11_csr_addr;
reg [4:0] uops_11_rob_idx;
reg [2:0] uops_11_ldq_idx;
reg [2:0] uops_11_stq_idx;
reg [1:0] uops_11_rxq_idx;
reg [5:0] uops_11_pdst;
reg [5:0] uops_11_prs1;
reg [5:0] uops_11_prs2;
reg [5:0] uops_11_prs3;
reg [3:0] uops_11_ppred;
reg uops_11_prs1_busy;
reg uops_11_prs2_busy;
reg uops_11_prs3_busy;
reg uops_11_ppred_busy;
reg [5:0] uops_11_stale_pdst;
reg uops_11_exception;
reg [63:0] uops_11_exc_cause;
reg uops_11_bypassable;
reg [4:0] uops_11_mem_cmd;
reg [1:0] uops_11_mem_size;
reg uops_11_mem_signed;
reg uops_11_is_fence;
reg uops_11_is_fencei;
reg uops_11_is_amo;
reg uops_11_uses_ldq;
reg uops_11_uses_stq;
reg uops_11_is_sys_pc2epc;
reg uops_11_is_unique;
reg uops_11_flush_on_commit;
reg uops_11_ldst_is_rs1;
reg [5:0] uops_11_ldst;
reg [5:0] uops_11_lrs1;
reg [5:0] uops_11_lrs2;
reg [5:0] uops_11_lrs3;
reg uops_11_ldst_val;
reg [1:0] uops_11_dst_rtype;
reg [1:0] uops_11_lrs1_rtype;
reg [1:0] uops_11_lrs2_rtype;
reg uops_11_frs3_en;
reg uops_11_fp_val;
reg uops_11_fp_single;
reg uops_11_xcpt_pf_if;
reg uops_11_xcpt_ae_if;
reg uops_11_xcpt_ma_if;
reg uops_11_bp_debug_if;
reg uops_11_bp_xcpt_if;
reg [1:0] uops_11_debug_fsrc;
reg [1:0] uops_11_debug_tsrc;
reg [6:0] uops_12_uopc;
reg [31:0] uops_12_inst;
reg [31:0] uops_12_debug_inst;
reg uops_12_is_rvc;
reg [39:0] uops_12_debug_pc;
reg [2:0] uops_12_iq_type;
reg [9:0] uops_12_fu_code;
reg [3:0] uops_12_ctrl_br_type;
reg [1:0] uops_12_ctrl_op1_sel;
reg [2:0] uops_12_ctrl_op2_sel;
reg [2:0] uops_12_ctrl_imm_sel;
reg [4:0] uops_12_ctrl_op_fcn;
reg uops_12_ctrl_fcn_dw;
reg [2:0] uops_12_ctrl_csr_cmd;
reg uops_12_ctrl_is_load;
reg uops_12_ctrl_is_sta;
reg uops_12_ctrl_is_std;
reg [1:0] uops_12_iw_state;
reg uops_12_iw_p1_poisoned;
reg uops_12_iw_p2_poisoned;
reg uops_12_is_br;
reg uops_12_is_jalr;
reg uops_12_is_jal;
reg uops_12_is_sfb;
reg [7:0] uops_12_br_mask;
reg [2:0] uops_12_br_tag;
reg [3:0] uops_12_ftq_idx;
reg uops_12_edge_inst;
reg [5:0] uops_12_pc_lob;
reg uops_12_taken;
reg [19:0] uops_12_imm_packed;
reg [11:0] uops_12_csr_addr;
reg [4:0] uops_12_rob_idx;
reg [2:0] uops_12_ldq_idx;
reg [2:0] uops_12_stq_idx;
reg [1:0] uops_12_rxq_idx;
reg [5:0] uops_12_pdst;
reg [5:0] uops_12_prs1;
reg [5:0] uops_12_prs2;
reg [5:0] uops_12_prs3;
reg [3:0] uops_12_ppred;
reg uops_12_prs1_busy;
reg uops_12_prs2_busy;
reg uops_12_prs3_busy;
reg uops_12_ppred_busy;
reg [5:0] uops_12_stale_pdst;
reg uops_12_exception;
reg [63:0] uops_12_exc_cause;
reg uops_12_bypassable;
reg [4:0] uops_12_mem_cmd;
reg [1:0] uops_12_mem_size;
reg uops_12_mem_signed;
reg uops_12_is_fence;
reg uops_12_is_fencei;
reg uops_12_is_amo;
reg uops_12_uses_ldq;
reg uops_12_uses_stq;
reg uops_12_is_sys_pc2epc;
reg uops_12_is_unique;
reg uops_12_flush_on_commit;
reg uops_12_ldst_is_rs1;
reg [5:0] uops_12_ldst;
reg [5:0] uops_12_lrs1;
reg [5:0] uops_12_lrs2;
reg [5:0] uops_12_lrs3;
reg uops_12_ldst_val;
reg [1:0] uops_12_dst_rtype;
reg [1:0] uops_12_lrs1_rtype;
reg [1:0] uops_12_lrs2_rtype;
reg uops_12_frs3_en;
reg uops_12_fp_val;
reg uops_12_fp_single;
reg uops_12_xcpt_pf_if;
reg uops_12_xcpt_ae_if;
reg uops_12_xcpt_ma_if;
reg uops_12_bp_debug_if;
reg uops_12_bp_xcpt_if;
reg [1:0] uops_12_debug_fsrc;
reg [1:0] uops_12_debug_tsrc;
reg [6:0] uops_13_uopc;
reg [31:0] uops_13_inst;
reg [31:0] uops_13_debug_inst;
reg uops_13_is_rvc;
reg [39:0] uops_13_debug_pc;
reg [2:0] uops_13_iq_type;
reg [9:0] uops_13_fu_code;
reg [3:0] uops_13_ctrl_br_type;
reg [1:0] uops_13_ctrl_op1_sel;
reg [2:0] uops_13_ctrl_op2_sel;
reg [2:0] uops_13_ctrl_imm_sel;
reg [4:0] uops_13_ctrl_op_fcn;
reg uops_13_ctrl_fcn_dw;
reg [2:0] uops_13_ctrl_csr_cmd;
reg uops_13_ctrl_is_load;
reg uops_13_ctrl_is_sta;
reg uops_13_ctrl_is_std;
reg [1:0] uops_13_iw_state;
reg uops_13_iw_p1_poisoned;
reg uops_13_iw_p2_poisoned;
reg uops_13_is_br;
reg uops_13_is_jalr;
reg uops_13_is_jal;
reg uops_13_is_sfb;
reg [7:0] uops_13_br_mask;
reg [2:0] uops_13_br_tag;
reg [3:0] uops_13_ftq_idx;
reg uops_13_edge_inst;
reg [5:0] uops_13_pc_lob;
reg uops_13_taken;
reg [19:0] uops_13_imm_packed;
reg [11:0] uops_13_csr_addr;
reg [4:0] uops_13_rob_idx;
reg [2:0] uops_13_ldq_idx;
reg [2:0] uops_13_stq_idx;
reg [1:0] uops_13_rxq_idx;
reg [5:0] uops_13_pdst;
reg [5:0] uops_13_prs1;
reg [5:0] uops_13_prs2;
reg [5:0] uops_13_prs3;
reg [3:0] uops_13_ppred;
reg uops_13_prs1_busy;
reg uops_13_prs2_busy;
reg uops_13_prs3_busy;
reg uops_13_ppred_busy;
reg [5:0] uops_13_stale_pdst;
reg uops_13_exception;
reg [63:0] uops_13_exc_cause;
reg uops_13_bypassable;
reg [4:0] uops_13_mem_cmd;
reg [1:0] uops_13_mem_size;
reg uops_13_mem_signed;
reg uops_13_is_fence;
reg uops_13_is_fencei;
reg uops_13_is_amo;
reg uops_13_uses_ldq;
reg uops_13_uses_stq;
reg uops_13_is_sys_pc2epc;
reg uops_13_is_unique;
reg uops_13_flush_on_commit;
reg uops_13_ldst_is_rs1;
reg [5:0] uops_13_ldst;
reg [5:0] uops_13_lrs1;
reg [5:0] uops_13_lrs2;
reg [5:0] uops_13_lrs3;
reg uops_13_ldst_val;
reg [1:0] uops_13_dst_rtype;
reg [1:0] uops_13_lrs1_rtype;
reg [1:0] uops_13_lrs2_rtype;
reg uops_13_frs3_en;
reg uops_13_fp_val;
reg uops_13_fp_single;
reg uops_13_xcpt_pf_if;
reg uops_13_xcpt_ae_if;
reg uops_13_xcpt_ma_if;
reg uops_13_bp_debug_if;
reg uops_13_bp_xcpt_if;
reg [1:0] uops_13_debug_fsrc;
reg [1:0] uops_13_debug_tsrc;
reg [6:0] uops_14_uopc;
reg [31:0] uops_14_inst;
reg [31:0] uops_14_debug_inst;
reg uops_14_is_rvc;
reg [39:0] uops_14_debug_pc;
reg [2:0] uops_14_iq_type;
reg [9:0] uops_14_fu_code;
reg [3:0] uops_14_ctrl_br_type;
reg [1:0] uops_14_ctrl_op1_sel;
reg [2:0] uops_14_ctrl_op2_sel;
reg [2:0] uops_14_ctrl_imm_sel;
reg [4:0] uops_14_ctrl_op_fcn;
reg uops_14_ctrl_fcn_dw;
reg [2:0] uops_14_ctrl_csr_cmd;
reg uops_14_ctrl_is_load;
reg uops_14_ctrl_is_sta;
reg uops_14_ctrl_is_std;
reg [1:0] uops_14_iw_state;
reg uops_14_iw_p1_poisoned;
reg uops_14_iw_p2_poisoned;
reg uops_14_is_br;
reg uops_14_is_jalr;
reg uops_14_is_jal;
reg uops_14_is_sfb;
reg [7:0] uops_14_br_mask;
reg [2:0] uops_14_br_tag;
reg [3:0] uops_14_ftq_idx;
reg uops_14_edge_inst;
reg [5:0] uops_14_pc_lob;
reg uops_14_taken;
reg [19:0] uops_14_imm_packed;
reg [11:0] uops_14_csr_addr;
reg [4:0] uops_14_rob_idx;
reg [2:0] uops_14_ldq_idx;
reg [2:0] uops_14_stq_idx;
reg [1:0] uops_14_rxq_idx;
reg [5:0] uops_14_pdst;
reg [5:0] uops_14_prs1;
reg [5:0] uops_14_prs2;
reg [5:0] uops_14_prs3;
reg [3:0] uops_14_ppred;
reg uops_14_prs1_busy;
reg uops_14_prs2_busy;
reg uops_14_prs3_busy;
reg uops_14_ppred_busy;
reg [5:0] uops_14_stale_pdst;
reg uops_14_exception;
reg [63:0] uops_14_exc_cause;
reg uops_14_bypassable;
reg [4:0] uops_14_mem_cmd;
reg [1:0] uops_14_mem_size;
reg uops_14_mem_signed;
reg uops_14_is_fence;
reg uops_14_is_fencei;
reg uops_14_is_amo;
reg uops_14_uses_ldq;
reg uops_14_uses_stq;
reg uops_14_is_sys_pc2epc;
reg uops_14_is_unique;
reg uops_14_flush_on_commit;
reg uops_14_ldst_is_rs1;
reg [5:0] uops_14_ldst;
reg [5:0] uops_14_lrs1;
reg [5:0] uops_14_lrs2;
reg [5:0] uops_14_lrs3;
reg uops_14_ldst_val;
reg [1:0] uops_14_dst_rtype;
reg [1:0] uops_14_lrs1_rtype;
reg [1:0] uops_14_lrs2_rtype;
reg uops_14_frs3_en;
reg uops_14_fp_val;
reg uops_14_fp_single;
reg uops_14_xcpt_pf_if;
reg uops_14_xcpt_ae_if;
reg uops_14_xcpt_ma_if;
reg uops_14_bp_debug_if;
reg uops_14_bp_xcpt_if;
reg [1:0] uops_14_debug_fsrc;
reg [1:0] uops_14_debug_tsrc;
reg [6:0] uops_15_uopc;
reg [31:0] uops_15_inst;
reg [31:0] uops_15_debug_inst;
reg uops_15_is_rvc;
reg [39:0] uops_15_debug_pc;
reg [2:0] uops_15_iq_type;
reg [9:0] uops_15_fu_code;
reg [3:0] uops_15_ctrl_br_type;
reg [1:0] uops_15_ctrl_op1_sel;
reg [2:0] uops_15_ctrl_op2_sel;
reg [2:0] uops_15_ctrl_imm_sel;
reg [4:0] uops_15_ctrl_op_fcn;
reg uops_15_ctrl_fcn_dw;
reg [2:0] uops_15_ctrl_csr_cmd;
reg uops_15_ctrl_is_load;
reg uops_15_ctrl_is_sta;
reg uops_15_ctrl_is_std;
reg [1:0] uops_15_iw_state;
reg uops_15_iw_p1_poisoned;
reg uops_15_iw_p2_poisoned;
reg uops_15_is_br;
reg uops_15_is_jalr;
reg uops_15_is_jal;
reg uops_15_is_sfb;
reg [7:0] uops_15_br_mask;
reg [2:0] uops_15_br_tag;
reg [3:0] uops_15_ftq_idx;
reg uops_15_edge_inst;
reg [5:0] uops_15_pc_lob;
reg uops_15_taken;
reg [19:0] uops_15_imm_packed;
reg [11:0] uops_15_csr_addr;
reg [4:0] uops_15_rob_idx;
reg [2:0] uops_15_ldq_idx;
reg [2:0] uops_15_stq_idx;
reg [1:0] uops_15_rxq_idx;
reg [5:0] uops_15_pdst;
reg [5:0] uops_15_prs1;
reg [5:0] uops_15_prs2;
reg [5:0] uops_15_prs3;
reg [3:0] uops_15_ppred;
reg uops_15_prs1_busy;
reg uops_15_prs2_busy;
reg uops_15_prs3_busy;
reg uops_15_ppred_busy;
reg [5:0] uops_15_stale_pdst;
reg uops_15_exception;
reg [63:0] uops_15_exc_cause;
reg uops_15_bypassable;
reg [4:0] uops_15_mem_cmd;
reg [1:0] uops_15_mem_size;
reg uops_15_mem_signed;
reg uops_15_is_fence;
reg uops_15_is_fencei;
reg uops_15_is_amo;
reg uops_15_uses_ldq;
reg uops_15_uses_stq;
reg uops_15_is_sys_pc2epc;
reg uops_15_is_unique;
reg uops_15_flush_on_commit;
reg uops_15_ldst_is_rs1;
reg [5:0] uops_15_ldst;
reg [5:0] uops_15_lrs1;
reg [5:0] uops_15_lrs2;
reg [5:0] uops_15_lrs3;
reg uops_15_ldst_val;
reg [1:0] uops_15_dst_rtype;
reg [1:0] uops_15_lrs1_rtype;
reg [1:0] uops_15_lrs2_rtype;
reg uops_15_frs3_en;
reg uops_15_fp_val;
reg uops_15_fp_single;
reg uops_15_xcpt_pf_if;
reg uops_15_xcpt_ae_if;
reg uops_15_xcpt_ma_if;
reg uops_15_bp_debug_if;
reg uops_15_bp_xcpt_if;
reg [1:0] uops_15_debug_fsrc;
reg [1:0] uops_15_debug_tsrc;
reg [3:0] enq_ptr_value;
reg [3:0] deq_ptr_value;
reg maybe_full;
wire ptr_match = enq_ptr_value == deq_ptr_value;
wire io_empty_0 = ptr_match & ~maybe_full;
wire full = ptr_match & maybe_full;
wire do_enq = ~full & io_enq_valid;
wire [15:0] _GEN = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}};
wire _GEN_0 = _GEN[deq_ptr_value];
wire [15:0][6:0] _GEN_1 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}};
wire [15:0][31:0] _GEN_2 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}};
wire [15:0][31:0] _GEN_3 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}};
wire [15:0] _GEN_4 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}};
wire [15:0][39:0] _GEN_5 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}};
wire [15:0][2:0] _GEN_6 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}};
wire [15:0][9:0] _GEN_7 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}};
wire [15:0][3:0] _GEN_8 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}};
wire [15:0][1:0] _GEN_9 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}};
wire [15:0][2:0] _GEN_10 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}};
wire [15:0][2:0] _GEN_11 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}};
wire [15:0][4:0] _GEN_12 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}};
wire [15:0] _GEN_13 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}};
wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}};
wire [15:0] _GEN_15 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}};
wire [15:0] _GEN_16 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}};
wire [15:0] _GEN_17 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}};
wire [15:0][1:0] _GEN_18 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}};
wire [15:0] _GEN_19 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}};
wire [15:0] _GEN_20 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}};
wire [15:0] _GEN_21 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}};
wire [15:0] _GEN_22 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}};
wire [15:0] _GEN_23 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}};
wire [15:0] _GEN_24 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}};
wire [15:0][7:0] _GEN_25 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}};
wire [7:0] out_uop_br_mask = _GEN_25[deq_ptr_value];
wire [15:0][2:0] _GEN_26 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}};
wire [15:0][3:0] _GEN_27 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}};
wire [15:0] _GEN_28 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}};
wire [15:0][5:0] _GEN_29 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}};
wire [15:0] _GEN_30 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}};
wire [15:0][19:0] _GEN_31 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}};
wire [15:0][11:0] _GEN_32 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}};
wire [15:0][4:0] _GEN_33 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}};
wire [15:0][2:0] _GEN_34 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}};
wire [15:0][2:0] _GEN_35 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}};
wire [15:0][1:0] _GEN_36 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}};
wire [15:0][5:0] _GEN_37 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}};
wire [15:0][5:0] _GEN_38 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}};
wire [15:0][5:0] _GEN_39 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}};
wire [15:0][5:0] _GEN_40 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}};
wire [15:0][3:0] _GEN_41 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}};
wire [15:0] _GEN_42 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}};
wire [15:0] _GEN_43 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}};
wire [15:0] _GEN_44 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}};
wire [15:0] _GEN_45 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}};
wire [15:0][5:0] _GEN_46 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}};
wire [15:0] _GEN_47 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}};
wire [15:0][63:0] _GEN_48 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}};
wire [15:0] _GEN_49 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}};
wire [15:0][4:0] _GEN_50 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}};
wire [15:0][1:0] _GEN_51 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}};
wire [15:0] _GEN_52 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}};
wire [15:0] _GEN_53 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}};
wire [15:0] _GEN_54 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}};
wire [15:0] _GEN_55 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}};
wire [15:0] _GEN_56 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}};
wire out_uop_uses_ldq = _GEN_56[deq_ptr_value];
wire [15:0] _GEN_57 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}};
wire [15:0] _GEN_58 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}};
wire [15:0] _GEN_59 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}};
wire [15:0] _GEN_60 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}};
wire [15:0] _GEN_61 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}};
wire [15:0][5:0] _GEN_62 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}};
wire [15:0][5:0] _GEN_63 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}};
wire [15:0][5:0] _GEN_64 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}};
wire [15:0][5:0] _GEN_65 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}};
wire [15:0] _GEN_66 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}};
wire [15:0][1:0] _GEN_67 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}};
wire [15:0][1:0] _GEN_68 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}};
wire [15:0][1:0] _GEN_69 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}};
wire [15:0] _GEN_70 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}};
wire [15:0] _GEN_71 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}};
wire [15:0] _GEN_72 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}};
wire [15:0] _GEN_73 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}};
wire [15:0] _GEN_74 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}};
wire [15:0] _GEN_75 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}};
wire [15:0] _GEN_76 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}};
wire [15:0] _GEN_77 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}};
wire [15:0][1:0] _GEN_78 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}};
wire [15:0][1:0] _GEN_79 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}};
wire do_deq = (io_deq_ready | ~_GEN_0) & ~io_empty_0;
wire _GEN_80 = enq_ptr_value == 4'h0;
wire _GEN_81 = do_enq & _GEN_80;
wire _GEN_82 = enq_ptr_value == 4'h1;
wire _GEN_83 = do_enq & _GEN_82;
wire _GEN_84 = enq_ptr_value == 4'h2;
wire _GEN_85 = do_enq & _GEN_84;
wire _GEN_86 = enq_ptr_value == 4'h3;
wire _GEN_87 = do_enq & _GEN_86;
wire _GEN_88 = enq_ptr_value == 4'h4;
wire _GEN_89 = do_enq & _GEN_88;
wire _GEN_90 = enq_ptr_value == 4'h5;
wire _GEN_91 = do_enq & _GEN_90;
wire _GEN_92 = enq_ptr_value == 4'h6;
wire _GEN_93 = do_enq & _GEN_92;
wire _GEN_94 = enq_ptr_value == 4'h7;
wire _GEN_95 = do_enq & _GEN_94;
wire _GEN_96 = enq_ptr_value == 4'h8;
wire _GEN_97 = do_enq & _GEN_96;
wire _GEN_98 = enq_ptr_value == 4'h9;
wire _GEN_99 = do_enq & _GEN_98;
wire _GEN_100 = enq_ptr_value == 4'hA;
wire _GEN_101 = do_enq & _GEN_100;
wire _GEN_102 = enq_ptr_value == 4'hB;
wire _GEN_103 = do_enq & _GEN_102;
wire _GEN_104 = enq_ptr_value == 4'hC;
wire _GEN_105 = do_enq & _GEN_104;
wire _GEN_106 = enq_ptr_value == 4'hD;
wire _GEN_107 = do_enq & _GEN_106;
wire _GEN_108 = enq_ptr_value == 4'hE;
wire _GEN_109 = do_enq & _GEN_108;
wire _GEN_110 = do_enq & (&enq_ptr_value);
wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;
always @(posedge clock) begin
if (reset) begin
valids_0 <= 1'h0;
valids_1 <= 1'h0;
valids_2 <= 1'h0;
valids_3 <= 1'h0;
valids_4 <= 1'h0;
valids_5 <= 1'h0;
valids_6 <= 1'h0;
valids_7 <= 1'h0;
valids_8 <= 1'h0;
valids_9 <= 1'h0;
valids_10 <= 1'h0;
valids_11 <= 1'h0;
valids_12 <= 1'h0;
valids_13 <= 1'h0;
valids_14 <= 1'h0;
valids_15 <= 1'h0;
enq_ptr_value <= 4'h0;
deq_ptr_value <= 4'h0;
maybe_full <= 1'h0;
end
else begin
valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_81 | valids_0 & (io_brupdate_b1_mispredict_mask & uops_0_br_mask) == 8'h0 & ~(io_flush & uops_0_uses_ldq));
valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_83 | valids_1 & (io_brupdate_b1_mispredict_mask & uops_1_br_mask) == 8'h0 & ~(io_flush & uops_1_uses_ldq));
valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_85 | valids_2 & (io_brupdate_b1_mispredict_mask & uops_2_br_mask) == 8'h0 & ~(io_flush & uops_2_uses_ldq));
valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_87 | valids_3 & (io_brupdate_b1_mispredict_mask & uops_3_br_mask) == 8'h0 & ~(io_flush & uops_3_uses_ldq));
valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_89 | valids_4 & (io_brupdate_b1_mispredict_mask & uops_4_br_mask) == 8'h0 & ~(io_flush & uops_4_uses_ldq));
valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_91 | valids_5 & (io_brupdate_b1_mispredict_mask & uops_5_br_mask) == 8'h0 & ~(io_flush & uops_5_uses_ldq));
valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_93 | valids_6 & (io_brupdate_b1_mispredict_mask & uops_6_br_mask) == 8'h0 & ~(io_flush & uops_6_uses_ldq));
valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_95 | valids_7 & (io_brupdate_b1_mispredict_mask & uops_7_br_mask) == 8'h0 & ~(io_flush & uops_7_uses_ldq));
valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_97 | valids_8 & (io_brupdate_b1_mispredict_mask & uops_8_br_mask) == 8'h0 & ~(io_flush & uops_8_uses_ldq));
valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_99 | valids_9 & (io_brupdate_b1_mispredict_mask & uops_9_br_mask) == 8'h0 & ~(io_flush & uops_9_uses_ldq));
valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_101 | valids_10 & (io_brupdate_b1_mispredict_mask & uops_10_br_mask) == 8'h0 & ~(io_flush & uops_10_uses_ldq));
valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_103 | valids_11 & (io_brupdate_b1_mispredict_mask & uops_11_br_mask) == 8'h0 & ~(io_flush & uops_11_uses_ldq));
valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_105 | valids_12 & (io_brupdate_b1_mispredict_mask & uops_12_br_mask) == 8'h0 & ~(io_flush & uops_12_uses_ldq));
valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_107 | valids_13 & (io_brupdate_b1_mispredict_mask & uops_13_br_mask) == 8'h0 & ~(io_flush & uops_13_uses_ldq));
valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_109 | valids_14 & (io_brupdate_b1_mispredict_mask & uops_14_br_mask) == 8'h0 & ~(io_flush & uops_14_uses_ldq));
valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_110 | valids_15 & (io_brupdate_b1_mispredict_mask & uops_15_br_mask) == 8'h0 & ~(io_flush & uops_15_uses_ldq));
if (do_enq)
enq_ptr_value <= enq_ptr_value + 4'h1;
if (do_deq)
deq_ptr_value <= deq_ptr_value + 4'h1;
if (~(do_enq == do_deq))
maybe_full <= do_enq;
end
if (_GEN_81) begin
uops_0_uopc <= io_enq_bits_uop_uopc;
uops_0_inst <= io_enq_bits_uop_inst;
uops_0_debug_inst <= io_enq_bits_uop_debug_inst;
uops_0_is_rvc <= io_enq_bits_uop_is_rvc;
uops_0_debug_pc <= io_enq_bits_uop_debug_pc;
uops_0_iq_type <= io_enq_bits_uop_iq_type;
uops_0_fu_code <= io_enq_bits_uop_fu_code;
uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_0_iw_state <= io_enq_bits_uop_iw_state;
uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_0_is_br <= io_enq_bits_uop_is_br;
uops_0_is_jalr <= io_enq_bits_uop_is_jalr;
uops_0_is_jal <= io_enq_bits_uop_is_jal;
uops_0_is_sfb <= io_enq_bits_uop_is_sfb;
uops_0_br_tag <= io_enq_bits_uop_br_tag;
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_0_edge_inst <= io_enq_bits_uop_edge_inst;
uops_0_pc_lob <= io_enq_bits_uop_pc_lob;
uops_0_taken <= io_enq_bits_uop_taken;
uops_0_imm_packed <= io_enq_bits_uop_imm_packed;
uops_0_csr_addr <= io_enq_bits_uop_csr_addr;
uops_0_rob_idx <= io_enq_bits_uop_rob_idx;
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_0_stq_idx <= io_enq_bits_uop_stq_idx;
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_0_pdst <= io_enq_bits_uop_pdst;
uops_0_prs1 <= io_enq_bits_uop_prs1;
uops_0_prs2 <= io_enq_bits_uop_prs2;
uops_0_prs3 <= io_enq_bits_uop_prs3;
uops_0_ppred <= io_enq_bits_uop_ppred;
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_0_exception <= io_enq_bits_uop_exception;
uops_0_exc_cause <= io_enq_bits_uop_exc_cause;
uops_0_bypassable <= io_enq_bits_uop_bypassable;
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_0_mem_size <= io_enq_bits_uop_mem_size;
uops_0_mem_signed <= io_enq_bits_uop_mem_signed;
uops_0_is_fence <= io_enq_bits_uop_is_fence;
uops_0_is_fencei <= io_enq_bits_uop_is_fencei;
uops_0_is_amo <= io_enq_bits_uop_is_amo;
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_0_uses_stq <= io_enq_bits_uop_uses_stq;
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_0_is_unique <= io_enq_bits_uop_is_unique;
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_0_ldst <= io_enq_bits_uop_ldst;
uops_0_lrs1 <= io_enq_bits_uop_lrs1;
uops_0_lrs2 <= io_enq_bits_uop_lrs2;
uops_0_lrs3 <= io_enq_bits_uop_lrs3;
uops_0_ldst_val <= io_enq_bits_uop_ldst_val;
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_0_frs3_en <= io_enq_bits_uop_frs3_en;
uops_0_fp_val <= io_enq_bits_uop_fp_val;
uops_0_fp_single <= io_enq_bits_uop_fp_single;
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_0_br_mask <= do_enq & _GEN_80 ? _uops_br_mask_T_1 : ({8{~valids_0}} | ~io_brupdate_b1_resolve_mask) & uops_0_br_mask;
if (_GEN_83) begin
uops_1_uopc <= io_enq_bits_uop_uopc;
uops_1_inst <= io_enq_bits_uop_inst;
uops_1_debug_inst <= io_enq_bits_uop_debug_inst;
uops_1_is_rvc <= io_enq_bits_uop_is_rvc;
uops_1_debug_pc <= io_enq_bits_uop_debug_pc;
uops_1_iq_type <= io_enq_bits_uop_iq_type;
uops_1_fu_code <= io_enq_bits_uop_fu_code;
uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_1_iw_state <= io_enq_bits_uop_iw_state;
uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_1_is_br <= io_enq_bits_uop_is_br;
uops_1_is_jalr <= io_enq_bits_uop_is_jalr;
uops_1_is_jal <= io_enq_bits_uop_is_jal;
uops_1_is_sfb <= io_enq_bits_uop_is_sfb;
uops_1_br_tag <= io_enq_bits_uop_br_tag;
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_1_edge_inst <= io_enq_bits_uop_edge_inst;
uops_1_pc_lob <= io_enq_bits_uop_pc_lob;
uops_1_taken <= io_enq_bits_uop_taken;
uops_1_imm_packed <= io_enq_bits_uop_imm_packed;
uops_1_csr_addr <= io_enq_bits_uop_csr_addr;
uops_1_rob_idx <= io_enq_bits_uop_rob_idx;
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_1_stq_idx <= io_enq_bits_uop_stq_idx;
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_1_pdst <= io_enq_bits_uop_pdst;
uops_1_prs1 <= io_enq_bits_uop_prs1;
uops_1_prs2 <= io_enq_bits_uop_prs2;
uops_1_prs3 <= io_enq_bits_uop_prs3;
uops_1_ppred <= io_enq_bits_uop_ppred;
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_1_exception <= io_enq_bits_uop_exception;
uops_1_exc_cause <= io_enq_bits_uop_exc_cause;
uops_1_bypassable <= io_enq_bits_uop_bypassable;
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_1_mem_size <= io_enq_bits_uop_mem_size;
uops_1_mem_signed <= io_enq_bits_uop_mem_signed;
uops_1_is_fence <= io_enq_bits_uop_is_fence;
uops_1_is_fencei <= io_enq_bits_uop_is_fencei;
uops_1_is_amo <= io_enq_bits_uop_is_amo;
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_1_uses_stq <= io_enq_bits_uop_uses_stq;
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_1_is_unique <= io_enq_bits_uop_is_unique;
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_1_ldst <= io_enq_bits_uop_ldst;
uops_1_lrs1 <= io_enq_bits_uop_lrs1;
uops_1_lrs2 <= io_enq_bits_uop_lrs2;
uops_1_lrs3 <= io_enq_bits_uop_lrs3;
uops_1_ldst_val <= io_enq_bits_uop_ldst_val;
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_1_frs3_en <= io_enq_bits_uop_frs3_en;
uops_1_fp_val <= io_enq_bits_uop_fp_val;
uops_1_fp_single <= io_enq_bits_uop_fp_single;
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_1_br_mask <= do_enq & _GEN_82 ? _uops_br_mask_T_1 : ({8{~valids_1}} | ~io_brupdate_b1_resolve_mask) & uops_1_br_mask;
if (_GEN_85) begin
uops_2_uopc <= io_enq_bits_uop_uopc;
uops_2_inst <= io_enq_bits_uop_inst;
uops_2_debug_inst <= io_enq_bits_uop_debug_inst;
uops_2_is_rvc <= io_enq_bits_uop_is_rvc;
uops_2_debug_pc <= io_enq_bits_uop_debug_pc;
uops_2_iq_type <= io_enq_bits_uop_iq_type;
uops_2_fu_code <= io_enq_bits_uop_fu_code;
uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_2_iw_state <= io_enq_bits_uop_iw_state;
uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_2_is_br <= io_enq_bits_uop_is_br;
uops_2_is_jalr <= io_enq_bits_uop_is_jalr;
uops_2_is_jal <= io_enq_bits_uop_is_jal;
uops_2_is_sfb <= io_enq_bits_uop_is_sfb;
uops_2_br_tag <= io_enq_bits_uop_br_tag;
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_2_edge_inst <= io_enq_bits_uop_edge_inst;
uops_2_pc_lob <= io_enq_bits_uop_pc_lob;
uops_2_taken <= io_enq_bits_uop_taken;
uops_2_imm_packed <= io_enq_bits_uop_imm_packed;
uops_2_csr_addr <= io_enq_bits_uop_csr_addr;
uops_2_rob_idx <= io_enq_bits_uop_rob_idx;
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_2_stq_idx <= io_enq_bits_uop_stq_idx;
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_2_pdst <= io_enq_bits_uop_pdst;
uops_2_prs1 <= io_enq_bits_uop_prs1;
uops_2_prs2 <= io_enq_bits_uop_prs2;
uops_2_prs3 <= io_enq_bits_uop_prs3;
uops_2_ppred <= io_enq_bits_uop_ppred;
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_2_exception <= io_enq_bits_uop_exception;
uops_2_exc_cause <= io_enq_bits_uop_exc_cause;
uops_2_bypassable <= io_enq_bits_uop_bypassable;
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_2_mem_size <= io_enq_bits_uop_mem_size;
uops_2_mem_signed <= io_enq_bits_uop_mem_signed;
uops_2_is_fence <= io_enq_bits_uop_is_fence;
uops_2_is_fencei <= io_enq_bits_uop_is_fencei;
uops_2_is_amo <= io_enq_bits_uop_is_amo;
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_2_uses_stq <= io_enq_bits_uop_uses_stq;
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_2_is_unique <= io_enq_bits_uop_is_unique;
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_2_ldst <= io_enq_bits_uop_ldst;
uops_2_lrs1 <= io_enq_bits_uop_lrs1;
uops_2_lrs2 <= io_enq_bits_uop_lrs2;
uops_2_lrs3 <= io_enq_bits_uop_lrs3;
uops_2_ldst_val <= io_enq_bits_uop_ldst_val;
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_2_frs3_en <= io_enq_bits_uop_frs3_en;
uops_2_fp_val <= io_enq_bits_uop_fp_val;
uops_2_fp_single <= io_enq_bits_uop_fp_single;
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_2_br_mask <= do_enq & _GEN_84 ? _uops_br_mask_T_1 : ({8{~valids_2}} | ~io_brupdate_b1_resolve_mask) & uops_2_br_mask;
if (_GEN_87) begin
uops_3_uopc <= io_enq_bits_uop_uopc;
uops_3_inst <= io_enq_bits_uop_inst;
uops_3_debug_inst <= io_enq_bits_uop_debug_inst;
uops_3_is_rvc <= io_enq_bits_uop_is_rvc;
uops_3_debug_pc <= io_enq_bits_uop_debug_pc;
uops_3_iq_type <= io_enq_bits_uop_iq_type;
uops_3_fu_code <= io_enq_bits_uop_fu_code;
uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_3_iw_state <= io_enq_bits_uop_iw_state;
uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_3_is_br <= io_enq_bits_uop_is_br;
uops_3_is_jalr <= io_enq_bits_uop_is_jalr;
uops_3_is_jal <= io_enq_bits_uop_is_jal;
uops_3_is_sfb <= io_enq_bits_uop_is_sfb;
uops_3_br_tag <= io_enq_bits_uop_br_tag;
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_3_edge_inst <= io_enq_bits_uop_edge_inst;
uops_3_pc_lob <= io_enq_bits_uop_pc_lob;
uops_3_taken <= io_enq_bits_uop_taken;
uops_3_imm_packed <= io_enq_bits_uop_imm_packed;
uops_3_csr_addr <= io_enq_bits_uop_csr_addr;
uops_3_rob_idx <= io_enq_bits_uop_rob_idx;
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_3_stq_idx <= io_enq_bits_uop_stq_idx;
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_3_pdst <= io_enq_bits_uop_pdst;
uops_3_prs1 <= io_enq_bits_uop_prs1;
uops_3_prs2 <= io_enq_bits_uop_prs2;
uops_3_prs3 <= io_enq_bits_uop_prs3;
uops_3_ppred <= io_enq_bits_uop_ppred;
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_3_exception <= io_enq_bits_uop_exception;
uops_3_exc_cause <= io_enq_bits_uop_exc_cause;
uops_3_bypassable <= io_enq_bits_uop_bypassable;
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_3_mem_size <= io_enq_bits_uop_mem_size;
uops_3_mem_signed <= io_enq_bits_uop_mem_signed;
uops_3_is_fence <= io_enq_bits_uop_is_fence;
uops_3_is_fencei <= io_enq_bits_uop_is_fencei;
uops_3_is_amo <= io_enq_bits_uop_is_amo;
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_3_uses_stq <= io_enq_bits_uop_uses_stq;
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_3_is_unique <= io_enq_bits_uop_is_unique;
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_3_ldst <= io_enq_bits_uop_ldst;
uops_3_lrs1 <= io_enq_bits_uop_lrs1;
uops_3_lrs2 <= io_enq_bits_uop_lrs2;
uops_3_lrs3 <= io_enq_bits_uop_lrs3;
uops_3_ldst_val <= io_enq_bits_uop_ldst_val;
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_3_frs3_en <= io_enq_bits_uop_frs3_en;
uops_3_fp_val <= io_enq_bits_uop_fp_val;
uops_3_fp_single <= io_enq_bits_uop_fp_single;
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_3_br_mask <= do_enq & _GEN_86 ? _uops_br_mask_T_1 : ({8{~valids_3}} | ~io_brupdate_b1_resolve_mask) & uops_3_br_mask;
if (_GEN_89) begin
uops_4_uopc <= io_enq_bits_uop_uopc;
uops_4_inst <= io_enq_bits_uop_inst;
uops_4_debug_inst <= io_enq_bits_uop_debug_inst;
uops_4_is_rvc <= io_enq_bits_uop_is_rvc;
uops_4_debug_pc <= io_enq_bits_uop_debug_pc;
uops_4_iq_type <= io_enq_bits_uop_iq_type;
uops_4_fu_code <= io_enq_bits_uop_fu_code;
uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_4_iw_state <= io_enq_bits_uop_iw_state;
uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_4_is_br <= io_enq_bits_uop_is_br;
uops_4_is_jalr <= io_enq_bits_uop_is_jalr;
uops_4_is_jal <= io_enq_bits_uop_is_jal;
uops_4_is_sfb <= io_enq_bits_uop_is_sfb;
uops_4_br_tag <= io_enq_bits_uop_br_tag;
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_4_edge_inst <= io_enq_bits_uop_edge_inst;
uops_4_pc_lob <= io_enq_bits_uop_pc_lob;
uops_4_taken <= io_enq_bits_uop_taken;
uops_4_imm_packed <= io_enq_bits_uop_imm_packed;
uops_4_csr_addr <= io_enq_bits_uop_csr_addr;
uops_4_rob_idx <= io_enq_bits_uop_rob_idx;
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_4_stq_idx <= io_enq_bits_uop_stq_idx;
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_4_pdst <= io_enq_bits_uop_pdst;
uops_4_prs1 <= io_enq_bits_uop_prs1;
uops_4_prs2 <= io_enq_bits_uop_prs2;
uops_4_prs3 <= io_enq_bits_uop_prs3;
uops_4_ppred <= io_enq_bits_uop_ppred;
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_4_exception <= io_enq_bits_uop_exception;
uops_4_exc_cause <= io_enq_bits_uop_exc_cause;
uops_4_bypassable <= io_enq_bits_uop_bypassable;
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_4_mem_size <= io_enq_bits_uop_mem_size;
uops_4_mem_signed <= io_enq_bits_uop_mem_signed;
uops_4_is_fence <= io_enq_bits_uop_is_fence;
uops_4_is_fencei <= io_enq_bits_uop_is_fencei;
uops_4_is_amo <= io_enq_bits_uop_is_amo;
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_4_uses_stq <= io_enq_bits_uop_uses_stq;
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_4_is_unique <= io_enq_bits_uop_is_unique;
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_4_ldst <= io_enq_bits_uop_ldst;
uops_4_lrs1 <= io_enq_bits_uop_lrs1;
uops_4_lrs2 <= io_enq_bits_uop_lrs2;
uops_4_lrs3 <= io_enq_bits_uop_lrs3;
uops_4_ldst_val <= io_enq_bits_uop_ldst_val;
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_4_frs3_en <= io_enq_bits_uop_frs3_en;
uops_4_fp_val <= io_enq_bits_uop_fp_val;
uops_4_fp_single <= io_enq_bits_uop_fp_single;
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_4_br_mask <= do_enq & _GEN_88 ? _uops_br_mask_T_1 : ({8{~valids_4}} | ~io_brupdate_b1_resolve_mask) & uops_4_br_mask;
if (_GEN_91) begin
uops_5_uopc <= io_enq_bits_uop_uopc;
uops_5_inst <= io_enq_bits_uop_inst;
uops_5_debug_inst <= io_enq_bits_uop_debug_inst;
uops_5_is_rvc <= io_enq_bits_uop_is_rvc;
uops_5_debug_pc <= io_enq_bits_uop_debug_pc;
uops_5_iq_type <= io_enq_bits_uop_iq_type;
uops_5_fu_code <= io_enq_bits_uop_fu_code;
uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_5_iw_state <= io_enq_bits_uop_iw_state;
uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_5_is_br <= io_enq_bits_uop_is_br;
uops_5_is_jalr <= io_enq_bits_uop_is_jalr;
uops_5_is_jal <= io_enq_bits_uop_is_jal;
uops_5_is_sfb <= io_enq_bits_uop_is_sfb;
uops_5_br_tag <= io_enq_bits_uop_br_tag;
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_5_edge_inst <= io_enq_bits_uop_edge_inst;
uops_5_pc_lob <= io_enq_bits_uop_pc_lob;
uops_5_taken <= io_enq_bits_uop_taken;
uops_5_imm_packed <= io_enq_bits_uop_imm_packed;
uops_5_csr_addr <= io_enq_bits_uop_csr_addr;
uops_5_rob_idx <= io_enq_bits_uop_rob_idx;
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_5_stq_idx <= io_enq_bits_uop_stq_idx;
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_5_pdst <= io_enq_bits_uop_pdst;
uops_5_prs1 <= io_enq_bits_uop_prs1;
uops_5_prs2 <= io_enq_bits_uop_prs2;
uops_5_prs3 <= io_enq_bits_uop_prs3;
uops_5_ppred <= io_enq_bits_uop_ppred;
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_5_exception <= io_enq_bits_uop_exception;
uops_5_exc_cause <= io_enq_bits_uop_exc_cause;
uops_5_bypassable <= io_enq_bits_uop_bypassable;
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_5_mem_size <= io_enq_bits_uop_mem_size;
uops_5_mem_signed <= io_enq_bits_uop_mem_signed;
uops_5_is_fence <= io_enq_bits_uop_is_fence;
uops_5_is_fencei <= io_enq_bits_uop_is_fencei;
uops_5_is_amo <= io_enq_bits_uop_is_amo;
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_5_uses_stq <= io_enq_bits_uop_uses_stq;
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_5_is_unique <= io_enq_bits_uop_is_unique;
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_5_ldst <= io_enq_bits_uop_ldst;
uops_5_lrs1 <= io_enq_bits_uop_lrs1;
uops_5_lrs2 <= io_enq_bits_uop_lrs2;
uops_5_lrs3 <= io_enq_bits_uop_lrs3;
uops_5_ldst_val <= io_enq_bits_uop_ldst_val;
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_5_frs3_en <= io_enq_bits_uop_frs3_en;
uops_5_fp_val <= io_enq_bits_uop_fp_val;
uops_5_fp_single <= io_enq_bits_uop_fp_single;
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_5_br_mask <= do_enq & _GEN_90 ? _uops_br_mask_T_1 : ({8{~valids_5}} | ~io_brupdate_b1_resolve_mask) & uops_5_br_mask;
if (_GEN_93) begin
uops_6_uopc <= io_enq_bits_uop_uopc;
uops_6_inst <= io_enq_bits_uop_inst;
uops_6_debug_inst <= io_enq_bits_uop_debug_inst;
uops_6_is_rvc <= io_enq_bits_uop_is_rvc;
uops_6_debug_pc <= io_enq_bits_uop_debug_pc;
uops_6_iq_type <= io_enq_bits_uop_iq_type;
uops_6_fu_code <= io_enq_bits_uop_fu_code;
uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_6_iw_state <= io_enq_bits_uop_iw_state;
uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_6_is_br <= io_enq_bits_uop_is_br;
uops_6_is_jalr <= io_enq_bits_uop_is_jalr;
uops_6_is_jal <= io_enq_bits_uop_is_jal;
uops_6_is_sfb <= io_enq_bits_uop_is_sfb;
uops_6_br_tag <= io_enq_bits_uop_br_tag;
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_6_edge_inst <= io_enq_bits_uop_edge_inst;
uops_6_pc_lob <= io_enq_bits_uop_pc_lob;
uops_6_taken <= io_enq_bits_uop_taken;
uops_6_imm_packed <= io_enq_bits_uop_imm_packed;
uops_6_csr_addr <= io_enq_bits_uop_csr_addr;
uops_6_rob_idx <= io_enq_bits_uop_rob_idx;
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_6_stq_idx <= io_enq_bits_uop_stq_idx;
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_6_pdst <= io_enq_bits_uop_pdst;
uops_6_prs1 <= io_enq_bits_uop_prs1;
uops_6_prs2 <= io_enq_bits_uop_prs2;
uops_6_prs3 <= io_enq_bits_uop_prs3;
uops_6_ppred <= io_enq_bits_uop_ppred;
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_6_exception <= io_enq_bits_uop_exception;
uops_6_exc_cause <= io_enq_bits_uop_exc_cause;
uops_6_bypassable <= io_enq_bits_uop_bypassable;
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_6_mem_size <= io_enq_bits_uop_mem_size;
uops_6_mem_signed <= io_enq_bits_uop_mem_signed;
uops_6_is_fence <= io_enq_bits_uop_is_fence;
uops_6_is_fencei <= io_enq_bits_uop_is_fencei;
uops_6_is_amo <= io_enq_bits_uop_is_amo;
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_6_uses_stq <= io_enq_bits_uop_uses_stq;
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_6_is_unique <= io_enq_bits_uop_is_unique;
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_6_ldst <= io_enq_bits_uop_ldst;
uops_6_lrs1 <= io_enq_bits_uop_lrs1;
uops_6_lrs2 <= io_enq_bits_uop_lrs2;
uops_6_lrs3 <= io_enq_bits_uop_lrs3;
uops_6_ldst_val <= io_enq_bits_uop_ldst_val;
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_6_frs3_en <= io_enq_bits_uop_frs3_en;
uops_6_fp_val <= io_enq_bits_uop_fp_val;
uops_6_fp_single <= io_enq_bits_uop_fp_single;
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_6_br_mask <= do_enq & _GEN_92 ? _uops_br_mask_T_1 : ({8{~valids_6}} | ~io_brupdate_b1_resolve_mask) & uops_6_br_mask;
if (_GEN_95) begin
uops_7_uopc <= io_enq_bits_uop_uopc;
uops_7_inst <= io_enq_bits_uop_inst;
uops_7_debug_inst <= io_enq_bits_uop_debug_inst;
uops_7_is_rvc <= io_enq_bits_uop_is_rvc;
uops_7_debug_pc <= io_enq_bits_uop_debug_pc;
uops_7_iq_type <= io_enq_bits_uop_iq_type;
uops_7_fu_code <= io_enq_bits_uop_fu_code;
uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_7_iw_state <= io_enq_bits_uop_iw_state;
uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_7_is_br <= io_enq_bits_uop_is_br;
uops_7_is_jalr <= io_enq_bits_uop_is_jalr;
uops_7_is_jal <= io_enq_bits_uop_is_jal;
uops_7_is_sfb <= io_enq_bits_uop_is_sfb;
uops_7_br_tag <= io_enq_bits_uop_br_tag;
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_7_edge_inst <= io_enq_bits_uop_edge_inst;
uops_7_pc_lob <= io_enq_bits_uop_pc_lob;
uops_7_taken <= io_enq_bits_uop_taken;
uops_7_imm_packed <= io_enq_bits_uop_imm_packed;
uops_7_csr_addr <= io_enq_bits_uop_csr_addr;
uops_7_rob_idx <= io_enq_bits_uop_rob_idx;
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_7_stq_idx <= io_enq_bits_uop_stq_idx;
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_7_pdst <= io_enq_bits_uop_pdst;
uops_7_prs1 <= io_enq_bits_uop_prs1;
uops_7_prs2 <= io_enq_bits_uop_prs2;
uops_7_prs3 <= io_enq_bits_uop_prs3;
uops_7_ppred <= io_enq_bits_uop_ppred;
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_7_exception <= io_enq_bits_uop_exception;
uops_7_exc_cause <= io_enq_bits_uop_exc_cause;
uops_7_bypassable <= io_enq_bits_uop_bypassable;
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_7_mem_size <= io_enq_bits_uop_mem_size;
uops_7_mem_signed <= io_enq_bits_uop_mem_signed;
uops_7_is_fence <= io_enq_bits_uop_is_fence;
uops_7_is_fencei <= io_enq_bits_uop_is_fencei;
uops_7_is_amo <= io_enq_bits_uop_is_amo;
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_7_uses_stq <= io_enq_bits_uop_uses_stq;
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_7_is_unique <= io_enq_bits_uop_is_unique;
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_7_ldst <= io_enq_bits_uop_ldst;
uops_7_lrs1 <= io_enq_bits_uop_lrs1;
uops_7_lrs2 <= io_enq_bits_uop_lrs2;
uops_7_lrs3 <= io_enq_bits_uop_lrs3;
uops_7_ldst_val <= io_enq_bits_uop_ldst_val;
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_7_frs3_en <= io_enq_bits_uop_frs3_en;
uops_7_fp_val <= io_enq_bits_uop_fp_val;
uops_7_fp_single <= io_enq_bits_uop_fp_single;
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_7_br_mask <= do_enq & _GEN_94 ? _uops_br_mask_T_1 : ({8{~valids_7}} | ~io_brupdate_b1_resolve_mask) & uops_7_br_mask;
if (_GEN_97) begin
uops_8_uopc <= io_enq_bits_uop_uopc;
uops_8_inst <= io_enq_bits_uop_inst;
uops_8_debug_inst <= io_enq_bits_uop_debug_inst;
uops_8_is_rvc <= io_enq_bits_uop_is_rvc;
uops_8_debug_pc <= io_enq_bits_uop_debug_pc;
uops_8_iq_type <= io_enq_bits_uop_iq_type;
uops_8_fu_code <= io_enq_bits_uop_fu_code;
uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_8_iw_state <= io_enq_bits_uop_iw_state;
uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_8_is_br <= io_enq_bits_uop_is_br;
uops_8_is_jalr <= io_enq_bits_uop_is_jalr;
uops_8_is_jal <= io_enq_bits_uop_is_jal;
uops_8_is_sfb <= io_enq_bits_uop_is_sfb;
uops_8_br_tag <= io_enq_bits_uop_br_tag;
uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_8_edge_inst <= io_enq_bits_uop_edge_inst;
uops_8_pc_lob <= io_enq_bits_uop_pc_lob;
uops_8_taken <= io_enq_bits_uop_taken;
uops_8_imm_packed <= io_enq_bits_uop_imm_packed;
uops_8_csr_addr <= io_enq_bits_uop_csr_addr;
uops_8_rob_idx <= io_enq_bits_uop_rob_idx;
uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_8_stq_idx <= io_enq_bits_uop_stq_idx;
uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_8_pdst <= io_enq_bits_uop_pdst;
uops_8_prs1 <= io_enq_bits_uop_prs1;
uops_8_prs2 <= io_enq_bits_uop_prs2;
uops_8_prs3 <= io_enq_bits_uop_prs3;
uops_8_ppred <= io_enq_bits_uop_ppred;
uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_8_exception <= io_enq_bits_uop_exception;
uops_8_exc_cause <= io_enq_bits_uop_exc_cause;
uops_8_bypassable <= io_enq_bits_uop_bypassable;
uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_8_mem_size <= io_enq_bits_uop_mem_size;
uops_8_mem_signed <= io_enq_bits_uop_mem_signed;
uops_8_is_fence <= io_enq_bits_uop_is_fence;
uops_8_is_fencei <= io_enq_bits_uop_is_fencei;
uops_8_is_amo <= io_enq_bits_uop_is_amo;
uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_8_uses_stq <= io_enq_bits_uop_uses_stq;
uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_8_is_unique <= io_enq_bits_uop_is_unique;
uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_8_ldst <= io_enq_bits_uop_ldst;
uops_8_lrs1 <= io_enq_bits_uop_lrs1;
uops_8_lrs2 <= io_enq_bits_uop_lrs2;
uops_8_lrs3 <= io_enq_bits_uop_lrs3;
uops_8_ldst_val <= io_enq_bits_uop_ldst_val;
uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_8_frs3_en <= io_enq_bits_uop_frs3_en;
uops_8_fp_val <= io_enq_bits_uop_fp_val;
uops_8_fp_single <= io_enq_bits_uop_fp_single;
uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_8_br_mask <= do_enq & _GEN_96 ? _uops_br_mask_T_1 : ({8{~valids_8}} | ~io_brupdate_b1_resolve_mask) & uops_8_br_mask;
if (_GEN_99) begin
uops_9_uopc <= io_enq_bits_uop_uopc;
uops_9_inst <= io_enq_bits_uop_inst;
uops_9_debug_inst <= io_enq_bits_uop_debug_inst;
uops_9_is_rvc <= io_enq_bits_uop_is_rvc;
uops_9_debug_pc <= io_enq_bits_uop_debug_pc;
uops_9_iq_type <= io_enq_bits_uop_iq_type;
uops_9_fu_code <= io_enq_bits_uop_fu_code;
uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_9_iw_state <= io_enq_bits_uop_iw_state;
uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_9_is_br <= io_enq_bits_uop_is_br;
uops_9_is_jalr <= io_enq_bits_uop_is_jalr;
uops_9_is_jal <= io_enq_bits_uop_is_jal;
uops_9_is_sfb <= io_enq_bits_uop_is_sfb;
uops_9_br_tag <= io_enq_bits_uop_br_tag;
uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_9_edge_inst <= io_enq_bits_uop_edge_inst;
uops_9_pc_lob <= io_enq_bits_uop_pc_lob;
uops_9_taken <= io_enq_bits_uop_taken;
uops_9_imm_packed <= io_enq_bits_uop_imm_packed;
uops_9_csr_addr <= io_enq_bits_uop_csr_addr;
uops_9_rob_idx <= io_enq_bits_uop_rob_idx;
uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_9_stq_idx <= io_enq_bits_uop_stq_idx;
uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_9_pdst <= io_enq_bits_uop_pdst;
uops_9_prs1 <= io_enq_bits_uop_prs1;
uops_9_prs2 <= io_enq_bits_uop_prs2;
uops_9_prs3 <= io_enq_bits_uop_prs3;
uops_9_ppred <= io_enq_bits_uop_ppred;
uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_9_exception <= io_enq_bits_uop_exception;
uops_9_exc_cause <= io_enq_bits_uop_exc_cause;
uops_9_bypassable <= io_enq_bits_uop_bypassable;
uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_9_mem_size <= io_enq_bits_uop_mem_size;
uops_9_mem_signed <= io_enq_bits_uop_mem_signed;
uops_9_is_fence <= io_enq_bits_uop_is_fence;
uops_9_is_fencei <= io_enq_bits_uop_is_fencei;
uops_9_is_amo <= io_enq_bits_uop_is_amo;
uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_9_uses_stq <= io_enq_bits_uop_uses_stq;
uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_9_is_unique <= io_enq_bits_uop_is_unique;
uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_9_ldst <= io_enq_bits_uop_ldst;
uops_9_lrs1 <= io_enq_bits_uop_lrs1;
uops_9_lrs2 <= io_enq_bits_uop_lrs2;
uops_9_lrs3 <= io_enq_bits_uop_lrs3;
uops_9_ldst_val <= io_enq_bits_uop_ldst_val;
uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_9_frs3_en <= io_enq_bits_uop_frs3_en;
uops_9_fp_val <= io_enq_bits_uop_fp_val;
uops_9_fp_single <= io_enq_bits_uop_fp_single;
uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_9_br_mask <= do_enq & _GEN_98 ? _uops_br_mask_T_1 : ({8{~valids_9}} | ~io_brupdate_b1_resolve_mask) & uops_9_br_mask;
if (_GEN_101) begin
uops_10_uopc <= io_enq_bits_uop_uopc;
uops_10_inst <= io_enq_bits_uop_inst;
uops_10_debug_inst <= io_enq_bits_uop_debug_inst;
uops_10_is_rvc <= io_enq_bits_uop_is_rvc;
uops_10_debug_pc <= io_enq_bits_uop_debug_pc;
uops_10_iq_type <= io_enq_bits_uop_iq_type;
uops_10_fu_code <= io_enq_bits_uop_fu_code;
uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_10_iw_state <= io_enq_bits_uop_iw_state;
uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_10_is_br <= io_enq_bits_uop_is_br;
uops_10_is_jalr <= io_enq_bits_uop_is_jalr;
uops_10_is_jal <= io_enq_bits_uop_is_jal;
uops_10_is_sfb <= io_enq_bits_uop_is_sfb;
uops_10_br_tag <= io_enq_bits_uop_br_tag;
uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_10_edge_inst <= io_enq_bits_uop_edge_inst;
uops_10_pc_lob <= io_enq_bits_uop_pc_lob;
uops_10_taken <= io_enq_bits_uop_taken;
uops_10_imm_packed <= io_enq_bits_uop_imm_packed;
uops_10_csr_addr <= io_enq_bits_uop_csr_addr;
uops_10_rob_idx <= io_enq_bits_uop_rob_idx;
uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_10_stq_idx <= io_enq_bits_uop_stq_idx;
uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_10_pdst <= io_enq_bits_uop_pdst;
uops_10_prs1 <= io_enq_bits_uop_prs1;
uops_10_prs2 <= io_enq_bits_uop_prs2;
uops_10_prs3 <= io_enq_bits_uop_prs3;
uops_10_ppred <= io_enq_bits_uop_ppred;
uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_10_exception <= io_enq_bits_uop_exception;
uops_10_exc_cause <= io_enq_bits_uop_exc_cause;
uops_10_bypassable <= io_enq_bits_uop_bypassable;
uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_10_mem_size <= io_enq_bits_uop_mem_size;
uops_10_mem_signed <= io_enq_bits_uop_mem_signed;
uops_10_is_fence <= io_enq_bits_uop_is_fence;
uops_10_is_fencei <= io_enq_bits_uop_is_fencei;
uops_10_is_amo <= io_enq_bits_uop_is_amo;
uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_10_uses_stq <= io_enq_bits_uop_uses_stq;
uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_10_is_unique <= io_enq_bits_uop_is_unique;
uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_10_ldst <= io_enq_bits_uop_ldst;
uops_10_lrs1 <= io_enq_bits_uop_lrs1;
uops_10_lrs2 <= io_enq_bits_uop_lrs2;
uops_10_lrs3 <= io_enq_bits_uop_lrs3;
uops_10_ldst_val <= io_enq_bits_uop_ldst_val;
uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_10_frs3_en <= io_enq_bits_uop_frs3_en;
uops_10_fp_val <= io_enq_bits_uop_fp_val;
uops_10_fp_single <= io_enq_bits_uop_fp_single;
uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_10_br_mask <= do_enq & _GEN_100 ? _uops_br_mask_T_1 : ({8{~valids_10}} | ~io_brupdate_b1_resolve_mask) & uops_10_br_mask;
if (_GEN_103) begin
uops_11_uopc <= io_enq_bits_uop_uopc;
uops_11_inst <= io_enq_bits_uop_inst;
uops_11_debug_inst <= io_enq_bits_uop_debug_inst;
uops_11_is_rvc <= io_enq_bits_uop_is_rvc;
uops_11_debug_pc <= io_enq_bits_uop_debug_pc;
uops_11_iq_type <= io_enq_bits_uop_iq_type;
uops_11_fu_code <= io_enq_bits_uop_fu_code;
uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_11_iw_state <= io_enq_bits_uop_iw_state;
uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_11_is_br <= io_enq_bits_uop_is_br;
uops_11_is_jalr <= io_enq_bits_uop_is_jalr;
uops_11_is_jal <= io_enq_bits_uop_is_jal;
uops_11_is_sfb <= io_enq_bits_uop_is_sfb;
uops_11_br_tag <= io_enq_bits_uop_br_tag;
uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_11_edge_inst <= io_enq_bits_uop_edge_inst;
uops_11_pc_lob <= io_enq_bits_uop_pc_lob;
uops_11_taken <= io_enq_bits_uop_taken;
uops_11_imm_packed <= io_enq_bits_uop_imm_packed;
uops_11_csr_addr <= io_enq_bits_uop_csr_addr;
uops_11_rob_idx <= io_enq_bits_uop_rob_idx;
uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_11_stq_idx <= io_enq_bits_uop_stq_idx;
uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_11_pdst <= io_enq_bits_uop_pdst;
uops_11_prs1 <= io_enq_bits_uop_prs1;
uops_11_prs2 <= io_enq_bits_uop_prs2;
uops_11_prs3 <= io_enq_bits_uop_prs3;
uops_11_ppred <= io_enq_bits_uop_ppred;
uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_11_exception <= io_enq_bits_uop_exception;
uops_11_exc_cause <= io_enq_bits_uop_exc_cause;
uops_11_bypassable <= io_enq_bits_uop_bypassable;
uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_11_mem_size <= io_enq_bits_uop_mem_size;
uops_11_mem_signed <= io_enq_bits_uop_mem_signed;
uops_11_is_fence <= io_enq_bits_uop_is_fence;
uops_11_is_fencei <= io_enq_bits_uop_is_fencei;
uops_11_is_amo <= io_enq_bits_uop_is_amo;
uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_11_uses_stq <= io_enq_bits_uop_uses_stq;
uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_11_is_unique <= io_enq_bits_uop_is_unique;
uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_11_ldst <= io_enq_bits_uop_ldst;
uops_11_lrs1 <= io_enq_bits_uop_lrs1;
uops_11_lrs2 <= io_enq_bits_uop_lrs2;
uops_11_lrs3 <= io_enq_bits_uop_lrs3;
uops_11_ldst_val <= io_enq_bits_uop_ldst_val;
uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_11_frs3_en <= io_enq_bits_uop_frs3_en;
uops_11_fp_val <= io_enq_bits_uop_fp_val;
uops_11_fp_single <= io_enq_bits_uop_fp_single;
uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_11_br_mask <= do_enq & _GEN_102 ? _uops_br_mask_T_1 : ({8{~valids_11}} | ~io_brupdate_b1_resolve_mask) & uops_11_br_mask;
if (_GEN_105) begin
uops_12_uopc <= io_enq_bits_uop_uopc;
uops_12_inst <= io_enq_bits_uop_inst;
uops_12_debug_inst <= io_enq_bits_uop_debug_inst;
uops_12_is_rvc <= io_enq_bits_uop_is_rvc;
uops_12_debug_pc <= io_enq_bits_uop_debug_pc;
uops_12_iq_type <= io_enq_bits_uop_iq_type;
uops_12_fu_code <= io_enq_bits_uop_fu_code;
uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_12_iw_state <= io_enq_bits_uop_iw_state;
uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_12_is_br <= io_enq_bits_uop_is_br;
uops_12_is_jalr <= io_enq_bits_uop_is_jalr;
uops_12_is_jal <= io_enq_bits_uop_is_jal;
uops_12_is_sfb <= io_enq_bits_uop_is_sfb;
uops_12_br_tag <= io_enq_bits_uop_br_tag;
uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_12_edge_inst <= io_enq_bits_uop_edge_inst;
uops_12_pc_lob <= io_enq_bits_uop_pc_lob;
uops_12_taken <= io_enq_bits_uop_taken;
uops_12_imm_packed <= io_enq_bits_uop_imm_packed;
uops_12_csr_addr <= io_enq_bits_uop_csr_addr;
uops_12_rob_idx <= io_enq_bits_uop_rob_idx;
uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_12_stq_idx <= io_enq_bits_uop_stq_idx;
uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_12_pdst <= io_enq_bits_uop_pdst;
uops_12_prs1 <= io_enq_bits_uop_prs1;
uops_12_prs2 <= io_enq_bits_uop_prs2;
uops_12_prs3 <= io_enq_bits_uop_prs3;
uops_12_ppred <= io_enq_bits_uop_ppred;
uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_12_exception <= io_enq_bits_uop_exception;
uops_12_exc_cause <= io_enq_bits_uop_exc_cause;
uops_12_bypassable <= io_enq_bits_uop_bypassable;
uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_12_mem_size <= io_enq_bits_uop_mem_size;
uops_12_mem_signed <= io_enq_bits_uop_mem_signed;
uops_12_is_fence <= io_enq_bits_uop_is_fence;
uops_12_is_fencei <= io_enq_bits_uop_is_fencei;
uops_12_is_amo <= io_enq_bits_uop_is_amo;
uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_12_uses_stq <= io_enq_bits_uop_uses_stq;
uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_12_is_unique <= io_enq_bits_uop_is_unique;
uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_12_ldst <= io_enq_bits_uop_ldst;
uops_12_lrs1 <= io_enq_bits_uop_lrs1;
uops_12_lrs2 <= io_enq_bits_uop_lrs2;
uops_12_lrs3 <= io_enq_bits_uop_lrs3;
uops_12_ldst_val <= io_enq_bits_uop_ldst_val;
uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_12_frs3_en <= io_enq_bits_uop_frs3_en;
uops_12_fp_val <= io_enq_bits_uop_fp_val;
uops_12_fp_single <= io_enq_bits_uop_fp_single;
uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_12_br_mask <= do_enq & _GEN_104 ? _uops_br_mask_T_1 : ({8{~valids_12}} | ~io_brupdate_b1_resolve_mask) & uops_12_br_mask;
if (_GEN_107) begin
uops_13_uopc <= io_enq_bits_uop_uopc;
uops_13_inst <= io_enq_bits_uop_inst;
uops_13_debug_inst <= io_enq_bits_uop_debug_inst;
uops_13_is_rvc <= io_enq_bits_uop_is_rvc;
uops_13_debug_pc <= io_enq_bits_uop_debug_pc;
uops_13_iq_type <= io_enq_bits_uop_iq_type;
uops_13_fu_code <= io_enq_bits_uop_fu_code;
uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_13_iw_state <= io_enq_bits_uop_iw_state;
uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_13_is_br <= io_enq_bits_uop_is_br;
uops_13_is_jalr <= io_enq_bits_uop_is_jalr;
uops_13_is_jal <= io_enq_bits_uop_is_jal;
uops_13_is_sfb <= io_enq_bits_uop_is_sfb;
uops_13_br_tag <= io_enq_bits_uop_br_tag;
uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_13_edge_inst <= io_enq_bits_uop_edge_inst;
uops_13_pc_lob <= io_enq_bits_uop_pc_lob;
uops_13_taken <= io_enq_bits_uop_taken;
uops_13_imm_packed <= io_enq_bits_uop_imm_packed;
uops_13_csr_addr <= io_enq_bits_uop_csr_addr;
uops_13_rob_idx <= io_enq_bits_uop_rob_idx;
uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_13_stq_idx <= io_enq_bits_uop_stq_idx;
uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_13_pdst <= io_enq_bits_uop_pdst;
uops_13_prs1 <= io_enq_bits_uop_prs1;
uops_13_prs2 <= io_enq_bits_uop_prs2;
uops_13_prs3 <= io_enq_bits_uop_prs3;
uops_13_ppred <= io_enq_bits_uop_ppred;
uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_13_exception <= io_enq_bits_uop_exception;
uops_13_exc_cause <= io_enq_bits_uop_exc_cause;
uops_13_bypassable <= io_enq_bits_uop_bypassable;
uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_13_mem_size <= io_enq_bits_uop_mem_size;
uops_13_mem_signed <= io_enq_bits_uop_mem_signed;
uops_13_is_fence <= io_enq_bits_uop_is_fence;
uops_13_is_fencei <= io_enq_bits_uop_is_fencei;
uops_13_is_amo <= io_enq_bits_uop_is_amo;
uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_13_uses_stq <= io_enq_bits_uop_uses_stq;
uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_13_is_unique <= io_enq_bits_uop_is_unique;
uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_13_ldst <= io_enq_bits_uop_ldst;
uops_13_lrs1 <= io_enq_bits_uop_lrs1;
uops_13_lrs2 <= io_enq_bits_uop_lrs2;
uops_13_lrs3 <= io_enq_bits_uop_lrs3;
uops_13_ldst_val <= io_enq_bits_uop_ldst_val;
uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_13_frs3_en <= io_enq_bits_uop_frs3_en;
uops_13_fp_val <= io_enq_bits_uop_fp_val;
uops_13_fp_single <= io_enq_bits_uop_fp_single;
uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_13_br_mask <= do_enq & _GEN_106 ? _uops_br_mask_T_1 : ({8{~valids_13}} | ~io_brupdate_b1_resolve_mask) & uops_13_br_mask;
if (_GEN_109) begin
uops_14_uopc <= io_enq_bits_uop_uopc;
uops_14_inst <= io_enq_bits_uop_inst;
uops_14_debug_inst <= io_enq_bits_uop_debug_inst;
uops_14_is_rvc <= io_enq_bits_uop_is_rvc;
uops_14_debug_pc <= io_enq_bits_uop_debug_pc;
uops_14_iq_type <= io_enq_bits_uop_iq_type;
uops_14_fu_code <= io_enq_bits_uop_fu_code;
uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_14_iw_state <= io_enq_bits_uop_iw_state;
uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_14_is_br <= io_enq_bits_uop_is_br;
uops_14_is_jalr <= io_enq_bits_uop_is_jalr;
uops_14_is_jal <= io_enq_bits_uop_is_jal;
uops_14_is_sfb <= io_enq_bits_uop_is_sfb;
uops_14_br_tag <= io_enq_bits_uop_br_tag;
uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_14_edge_inst <= io_enq_bits_uop_edge_inst;
uops_14_pc_lob <= io_enq_bits_uop_pc_lob;
uops_14_taken <= io_enq_bits_uop_taken;
uops_14_imm_packed <= io_enq_bits_uop_imm_packed;
uops_14_csr_addr <= io_enq_bits_uop_csr_addr;
uops_14_rob_idx <= io_enq_bits_uop_rob_idx;
uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_14_stq_idx <= io_enq_bits_uop_stq_idx;
uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_14_pdst <= io_enq_bits_uop_pdst;
uops_14_prs1 <= io_enq_bits_uop_prs1;
uops_14_prs2 <= io_enq_bits_uop_prs2;
uops_14_prs3 <= io_enq_bits_uop_prs3;
uops_14_ppred <= io_enq_bits_uop_ppred;
uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_14_exception <= io_enq_bits_uop_exception;
uops_14_exc_cause <= io_enq_bits_uop_exc_cause;
uops_14_bypassable <= io_enq_bits_uop_bypassable;
uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_14_mem_size <= io_enq_bits_uop_mem_size;
uops_14_mem_signed <= io_enq_bits_uop_mem_signed;
uops_14_is_fence <= io_enq_bits_uop_is_fence;
uops_14_is_fencei <= io_enq_bits_uop_is_fencei;
uops_14_is_amo <= io_enq_bits_uop_is_amo;
uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_14_uses_stq <= io_enq_bits_uop_uses_stq;
uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_14_is_unique <= io_enq_bits_uop_is_unique;
uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_14_ldst <= io_enq_bits_uop_ldst;
uops_14_lrs1 <= io_enq_bits_uop_lrs1;
uops_14_lrs2 <= io_enq_bits_uop_lrs2;
uops_14_lrs3 <= io_enq_bits_uop_lrs3;
uops_14_ldst_val <= io_enq_bits_uop_ldst_val;
uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_14_frs3_en <= io_enq_bits_uop_frs3_en;
uops_14_fp_val <= io_enq_bits_uop_fp_val;
uops_14_fp_single <= io_enq_bits_uop_fp_single;
uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_14_br_mask <= do_enq & _GEN_108 ? _uops_br_mask_T_1 : ({8{~valids_14}} | ~io_brupdate_b1_resolve_mask) & uops_14_br_mask;
if (_GEN_110) begin
uops_15_uopc <= io_enq_bits_uop_uopc;
uops_15_inst <= io_enq_bits_uop_inst;
uops_15_debug_inst <= io_enq_bits_uop_debug_inst;
uops_15_is_rvc <= io_enq_bits_uop_is_rvc;
uops_15_debug_pc <= io_enq_bits_uop_debug_pc;
uops_15_iq_type <= io_enq_bits_uop_iq_type;
uops_15_fu_code <= io_enq_bits_uop_fu_code;
uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;
uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;
uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;
uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;
uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;
uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;
uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;
uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;
uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;
uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;
uops_15_iw_state <= io_enq_bits_uop_iw_state;
uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;
uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;
uops_15_is_br <= io_enq_bits_uop_is_br;
uops_15_is_jalr <= io_enq_bits_uop_is_jalr;
uops_15_is_jal <= io_enq_bits_uop_is_jal;
uops_15_is_sfb <= io_enq_bits_uop_is_sfb;
uops_15_br_tag <= io_enq_bits_uop_br_tag;
uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx;
uops_15_edge_inst <= io_enq_bits_uop_edge_inst;
uops_15_pc_lob <= io_enq_bits_uop_pc_lob;
uops_15_taken <= io_enq_bits_uop_taken;
uops_15_imm_packed <= io_enq_bits_uop_imm_packed;
uops_15_csr_addr <= io_enq_bits_uop_csr_addr;
uops_15_rob_idx <= io_enq_bits_uop_rob_idx;
uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx;
uops_15_stq_idx <= io_enq_bits_uop_stq_idx;
uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx;
uops_15_pdst <= io_enq_bits_uop_pdst;
uops_15_prs1 <= io_enq_bits_uop_prs1;
uops_15_prs2 <= io_enq_bits_uop_prs2;
uops_15_prs3 <= io_enq_bits_uop_prs3;
uops_15_ppred <= io_enq_bits_uop_ppred;
uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy;
uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy;
uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy;
uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy;
uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst;
uops_15_exception <= io_enq_bits_uop_exception;
uops_15_exc_cause <= io_enq_bits_uop_exc_cause;
uops_15_bypassable <= io_enq_bits_uop_bypassable;
uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd;
uops_15_mem_size <= io_enq_bits_uop_mem_size;
uops_15_mem_signed <= io_enq_bits_uop_mem_signed;
uops_15_is_fence <= io_enq_bits_uop_is_fence;
uops_15_is_fencei <= io_enq_bits_uop_is_fencei;
uops_15_is_amo <= io_enq_bits_uop_is_amo;
uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq;
uops_15_uses_stq <= io_enq_bits_uop_uses_stq;
uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;
uops_15_is_unique <= io_enq_bits_uop_is_unique;
uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit;
uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;
uops_15_ldst <= io_enq_bits_uop_ldst;
uops_15_lrs1 <= io_enq_bits_uop_lrs1;
uops_15_lrs2 <= io_enq_bits_uop_lrs2;
uops_15_lrs3 <= io_enq_bits_uop_lrs3;
uops_15_ldst_val <= io_enq_bits_uop_ldst_val;
uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype;
uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;
uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;
uops_15_frs3_en <= io_enq_bits_uop_frs3_en;
uops_15_fp_val <= io_enq_bits_uop_fp_val;
uops_15_fp_single <= io_enq_bits_uop_fp_single;
uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;
uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;
uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;
uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if;
uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;
uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc;
uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc;
end
uops_15_br_mask <= do_enq & (&enq_ptr_value) ? _uops_br_mask_T_1 : ({8{~valids_15}} | ~io_brupdate_b1_resolve_mask) & uops_15_br_mask;
end
ram_16x46 ram_ext (
.R0_addr (deq_ptr_value),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value),
.W0_en (do_enq),
.W0_clk (clock),
.W0_data ({io_enq_bits_sdq_id, io_enq_bits_is_hella, io_enq_bits_addr})
);
assign io_enq_ready = ~full;
assign io_deq_valid = ~io_empty_0 & _GEN_0 & (io_brupdate_b1_mispredict_mask & out_uop_br_mask) == 8'h0 & ~(io_flush & out_uop_uses_ldq);
assign io_deq_bits_uop_uopc = _GEN_1[deq_ptr_value];
assign io_deq_bits_uop_inst = _GEN_2[deq_ptr_value];
assign io_deq_bits_uop_debug_inst = _GEN_3[deq_ptr_value];
assign io_deq_bits_uop_is_rvc = _GEN_4[deq_ptr_value];
assign io_deq_bits_uop_debug_pc = _GEN_5[deq_ptr_value];
assign io_deq_bits_uop_iq_type = _GEN_6[deq_ptr_value];
assign io_deq_bits_uop_fu_code = _GEN_7[deq_ptr_value];
assign io_deq_bits_uop_ctrl_br_type = _GEN_8[deq_ptr_value];
assign io_deq_bits_uop_ctrl_op1_sel = _GEN_9[deq_ptr_value];
assign io_deq_bits_uop_ctrl_op2_sel = _GEN_10[deq_ptr_value];
assign io_deq_bits_uop_ctrl_imm_sel = _GEN_11[deq_ptr_value];
assign io_deq_bits_uop_ctrl_op_fcn = _GEN_12[deq_ptr_value];
assign io_deq_bits_uop_ctrl_fcn_dw = _GEN_13[deq_ptr_value];
assign io_deq_bits_uop_ctrl_csr_cmd = _GEN_14[deq_ptr_value];
assign io_deq_bits_uop_ctrl_is_load = _GEN_15[deq_ptr_value];
assign io_deq_bits_uop_ctrl_is_sta = _GEN_16[deq_ptr_value];
assign io_deq_bits_uop_ctrl_is_std = _GEN_17[deq_ptr_value];
assign io_deq_bits_uop_iw_state = _GEN_18[deq_ptr_value];
assign io_deq_bits_uop_iw_p1_poisoned = _GEN_19[deq_ptr_value];
assign io_deq_bits_uop_iw_p2_poisoned = _GEN_20[deq_ptr_value];
assign io_deq_bits_uop_is_br = _GEN_21[deq_ptr_value];
assign io_deq_bits_uop_is_jalr = _GEN_22[deq_ptr_value];
assign io_deq_bits_uop_is_jal = _GEN_23[deq_ptr_value];
assign io_deq_bits_uop_is_sfb = _GEN_24[deq_ptr_value];
assign io_deq_bits_uop_br_mask = out_uop_br_mask & ~io_brupdate_b1_resolve_mask;
assign io_deq_bits_uop_br_tag = _GEN_26[deq_ptr_value];
assign io_deq_bits_uop_ftq_idx = _GEN_27[deq_ptr_value];
assign io_deq_bits_uop_edge_inst = _GEN_28[deq_ptr_value];
assign io_deq_bits_uop_pc_lob = _GEN_29[deq_ptr_value];
assign io_deq_bits_uop_taken = _GEN_30[deq_ptr_value];
assign io_deq_bits_uop_imm_packed = _GEN_31[deq_ptr_value];
assign io_deq_bits_uop_csr_addr = _GEN_32[deq_ptr_value];
assign io_deq_bits_uop_rob_idx = _GEN_33[deq_ptr_value];
assign io_deq_bits_uop_ldq_idx = _GEN_34[deq_ptr_value];
assign io_deq_bits_uop_stq_idx = _GEN_35[deq_ptr_value];
assign io_deq_bits_uop_rxq_idx = _GEN_36[deq_ptr_value];
assign io_deq_bits_uop_pdst = _GEN_37[deq_ptr_value];
assign io_deq_bits_uop_prs1 = _GEN_38[deq_ptr_value];
assign io_deq_bits_uop_prs2 = _GEN_39[deq_ptr_value];
assign io_deq_bits_uop_prs3 = _GEN_40[deq_ptr_value];
assign io_deq_bits_uop_ppred = _GEN_41[deq_ptr_value];
assign io_deq_bits_uop_prs1_busy = _GEN_42[deq_ptr_value];
assign io_deq_bits_uop_prs2_busy = _GEN_43[deq_ptr_value];
assign io_deq_bits_uop_prs3_busy = _GEN_44[deq_ptr_value];
assign io_deq_bits_uop_ppred_busy = _GEN_45[deq_ptr_value];
assign io_deq_bits_uop_stale_pdst = _GEN_46[deq_ptr_value];
assign io_deq_bits_uop_exception = _GEN_47[deq_ptr_value];
assign io_deq_bits_uop_exc_cause = _GEN_48[deq_ptr_value];
assign io_deq_bits_uop_bypassable = _GEN_49[deq_ptr_value];
assign io_deq_bits_uop_mem_cmd = _GEN_50[deq_ptr_value];
assign io_deq_bits_uop_mem_size = _GEN_51[deq_ptr_value];
assign io_deq_bits_uop_mem_signed = _GEN_52[deq_ptr_value];
assign io_deq_bits_uop_is_fence = _GEN_53[deq_ptr_value];
assign io_deq_bits_uop_is_fencei = _GEN_54[deq_ptr_value];
assign io_deq_bits_uop_is_amo = _GEN_55[deq_ptr_value];
assign io_deq_bits_uop_uses_ldq = out_uop_uses_ldq;
assign io_deq_bits_uop_uses_stq = _GEN_57[deq_ptr_value];
assign io_deq_bits_uop_is_sys_pc2epc = _GEN_58[deq_ptr_value];
assign io_deq_bits_uop_is_unique = _GEN_59[deq_ptr_value];
assign io_deq_bits_uop_flush_on_commit = _GEN_60[deq_ptr_value];
assign io_deq_bits_uop_ldst_is_rs1 = _GEN_61[deq_ptr_value];
assign io_deq_bits_uop_ldst = _GEN_62[deq_ptr_value];
assign io_deq_bits_uop_lrs1 = _GEN_63[deq_ptr_value];
assign io_deq_bits_uop_lrs2 = _GEN_64[deq_ptr_value];
assign io_deq_bits_uop_lrs3 = _GEN_65[deq_ptr_value];
assign io_deq_bits_uop_ldst_val = _GEN_66[deq_ptr_value];
assign io_deq_bits_uop_dst_rtype = _GEN_67[deq_ptr_value];
assign io_deq_bits_uop_lrs1_rtype = _GEN_68[deq_ptr_value];
assign io_deq_bits_uop_lrs2_rtype = _GEN_69[deq_ptr_value];
assign io_deq_bits_uop_frs3_en = _GEN_70[deq_ptr_value];
assign io_deq_bits_uop_fp_val = _GEN_71[deq_ptr_value];
assign io_deq_bits_uop_fp_single = _GEN_72[deq_ptr_value];
assign io_deq_bits_uop_xcpt_pf_if = _GEN_73[deq_ptr_value];
assign io_deq_bits_uop_xcpt_ae_if = _GEN_74[deq_ptr_value];
assign io_deq_bits_uop_xcpt_ma_if = _GEN_75[deq_ptr_value];
assign io_deq_bits_uop_bp_debug_if = _GEN_76[deq_ptr_value];
assign io_deq_bits_uop_bp_xcpt_if = _GEN_77[deq_ptr_value];
assign io_deq_bits_uop_debug_fsrc = _GEN_78[deq_ptr_value];
assign io_deq_bits_uop_debug_tsrc = _GEN_79[deq_ptr_value];
assign io_deq_bits_addr = _ram_ext_R0_data[39:0];
assign io_deq_bits_is_hella = _ram_ext_R0_data[40];
assign io_deq_bits_sdq_id = _ram_ext_R0_data[45:41];
assign io_empty = io_empty_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module cc_banks_2(
input [13:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.internal.firrtl.KnownWidth
import chisel3.util.{Cat, Valid}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.property
/** Base JTAG shifter IO, viewed from input to shift register chain.
* Can be chained together.
*/
class ShifterIO extends Bundle {
val shift = Bool() // advance the scan chain on clock high
val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB
val capture = Bool() // high in the CaptureIR/DR state when this chain is selected
val update = Bool() // high in the UpdateIR/DR state when this chain is selected
/** Sets a output shifter IO's control signals from a input shifter IO's control signals.
*/
def chainControlFrom(in: ShifterIO): Unit = {
shift := in.shift
capture := in.capture
update := in.update
}
}
trait ChainIO extends Bundle {
val chainIn = Input(new ShifterIO)
val chainOut = Output(new ShifterIO)
}
class Capture[+T <: Data](gen: T) extends Bundle {
val bits = Input(gen) // data to capture, should be always valid
val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge
}
object Capture {
def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)
}
/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain
* IO.
*/
trait Chain extends Module {
val io: ChainIO
}
/** One-element shift register, data register for bypass mode.
*
* Implements Clause 10.
*/
class JtagBypassChain(implicit val p: Parameters) extends Chain {
class ModIO extends ChainIO
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val reg = Reg(Bool()) // 10.1.1a single shift register stage
io.chainOut.data := reg
property.cover(io.chainIn.capture, "bypass_chain_capture", "JTAG; bypass_chain_capture; This Bypass Chain captured data")
when (io.chainIn.capture) {
reg := false.B // 10.1.1b capture logic 0 on TCK rising
} .elsewhen (io.chainIn.shift) {
reg := io.chainIn.data
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object JtagBypassChain {
def apply()(implicit p: Parameters) = new JtagBypassChain
}
/** Simple shift register with parallel capture only, for read-only data registers.
*
* Number of stages is the number of bits in gen, which must have a known width.
*
* Useful notes:
* 7.2.1c shifter shifts on TCK rising edge
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
*/
class CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {
override def desiredName = s"CaptureChain_${gen.typeName}"
class ModIO extends ChainIO {
val capture = Capture(gen)
}
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val n = DataMirror.widthOf(gen) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $gen"); -1 // TODO: remove -1 type hack
}
val regs = (0 until n) map (x => Reg(Bool()))
io.chainOut.data := regs(0)
property.cover(io.chainIn.capture, "chain_capture", "JTAG; chain_capture; This Chain captured data")
when (io.chainIn.capture) {
(0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))
io.capture.capture := true.B
} .elsewhen (io.chainIn.shift) {
regs(n-1) := io.chainIn.data
(0 until n-1) map (x => regs(x) := regs(x+1))
io.capture.capture := false.B
} .otherwise {
io.capture.capture := false.B
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object CaptureChain {
def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)
}
/** Simple shift register with parallel capture and update. Useful for general instruction and data
* scan registers.
*
* Number of stages is the max number of bits in genCapture and genUpdate, both of which must have
* known widths. If there is a width mismatch, the unused most significant bits will be zero.
*
* Useful notes:
* 7.2.1c shifter shifts on TCK rising edge
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
*/
class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {
override def desiredName = s"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}"
class ModIO extends ChainIO {
val capture = Capture(genCapture)
val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after
}
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val captureWidth = DataMirror.widthOf(genCapture) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $genCapture"); -1 // TODO: remove -1 type hack
}
val updateWidth = DataMirror.widthOf(genUpdate) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $genUpdate"); -1 // TODO: remove -1 type hack
}
val n = math.max(captureWidth, updateWidth)
val regs = (0 until n) map (x => Reg(Bool()))
io.chainOut.data := regs(0)
val updateBits = Cat(regs.reverse)(updateWidth-1, 0)
io.update.bits := updateBits.asTypeOf(io.update.bits)
val captureBits = io.capture.bits.asUInt
property.cover(io.chainIn.capture, "chain_capture", "JTAG;chain_capture; This Chain captured data")
property.cover(io.chainIn.capture, "chain_update", "JTAG;chain_update; This Chain updated data")
when (io.chainIn.capture) {
(0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))
(captureWidth until n) map (x => regs(x) := 0.U)
io.capture.capture := true.B
io.update.valid := false.B
} .elsewhen (io.chainIn.update) {
io.capture.capture := false.B
io.update.valid := true.B
} .elsewhen (io.chainIn.shift) {
regs(n-1) := io.chainIn.data
(0 until n-1) map (x => regs(x) := regs(x+1))
io.capture.capture := false.B
io.update.valid := false.B
} .otherwise {
io.capture.capture := false.B
io.update.valid := false.B
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object CaptureUpdateChain {
/** Capture-update chain with matching capture and update types.
*/
def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)
def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =
new CaptureUpdateChain(genCapture, genUpdate)
} | module CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate(
input clock,
input reset,
input io_chainIn_shift,
input io_chainIn_data,
input io_chainIn_capture,
input io_chainIn_update,
output io_chainOut_data,
input [6:0] io_capture_bits_addr,
input [31:0] io_capture_bits_data,
input [1:0] io_capture_bits_resp,
output io_capture_capture,
output io_update_valid,
output [6:0] io_update_bits_addr,
output [31:0] io_update_bits_data,
output [1:0] io_update_bits_op
);
reg regs_0;
reg regs_1;
reg regs_2;
reg regs_3;
reg regs_4;
reg regs_5;
reg regs_6;
reg regs_7;
reg regs_8;
reg regs_9;
reg regs_10;
reg regs_11;
reg regs_12;
reg regs_13;
reg regs_14;
reg regs_15;
reg regs_16;
reg regs_17;
reg regs_18;
reg regs_19;
reg regs_20;
reg regs_21;
reg regs_22;
reg regs_23;
reg regs_24;
reg regs_25;
reg regs_26;
reg regs_27;
reg regs_28;
reg regs_29;
reg regs_30;
reg regs_31;
reg regs_32;
reg regs_33;
reg regs_34;
reg regs_35;
reg regs_36;
reg regs_37;
reg regs_38;
reg regs_39;
reg regs_40;
always @(posedge clock) begin
if (io_chainIn_capture) begin
regs_0 <= io_capture_bits_resp[0];
regs_1 <= io_capture_bits_resp[1];
regs_2 <= io_capture_bits_data[0];
regs_3 <= io_capture_bits_data[1];
regs_4 <= io_capture_bits_data[2];
regs_5 <= io_capture_bits_data[3];
regs_6 <= io_capture_bits_data[4];
regs_7 <= io_capture_bits_data[5];
regs_8 <= io_capture_bits_data[6];
regs_9 <= io_capture_bits_data[7];
regs_10 <= io_capture_bits_data[8];
regs_11 <= io_capture_bits_data[9];
regs_12 <= io_capture_bits_data[10];
regs_13 <= io_capture_bits_data[11];
regs_14 <= io_capture_bits_data[12];
regs_15 <= io_capture_bits_data[13];
regs_16 <= io_capture_bits_data[14];
regs_17 <= io_capture_bits_data[15];
regs_18 <= io_capture_bits_data[16];
regs_19 <= io_capture_bits_data[17];
regs_20 <= io_capture_bits_data[18];
regs_21 <= io_capture_bits_data[19];
regs_22 <= io_capture_bits_data[20];
regs_23 <= io_capture_bits_data[21];
regs_24 <= io_capture_bits_data[22];
regs_25 <= io_capture_bits_data[23];
regs_26 <= io_capture_bits_data[24];
regs_27 <= io_capture_bits_data[25];
regs_28 <= io_capture_bits_data[26];
regs_29 <= io_capture_bits_data[27];
regs_30 <= io_capture_bits_data[28];
regs_31 <= io_capture_bits_data[29];
regs_32 <= io_capture_bits_data[30];
regs_33 <= io_capture_bits_data[31];
regs_34 <= io_capture_bits_addr[0];
regs_35 <= io_capture_bits_addr[1];
regs_36 <= io_capture_bits_addr[2];
regs_37 <= io_capture_bits_addr[3];
regs_38 <= io_capture_bits_addr[4];
regs_39 <= io_capture_bits_addr[5];
regs_40 <= io_capture_bits_addr[6];
end
else if (io_chainIn_update | ~io_chainIn_shift) begin
end
else begin
regs_0 <= regs_1;
regs_1 <= regs_2;
regs_2 <= regs_3;
regs_3 <= regs_4;
regs_4 <= regs_5;
regs_5 <= regs_6;
regs_6 <= regs_7;
regs_7 <= regs_8;
regs_8 <= regs_9;
regs_9 <= regs_10;
regs_10 <= regs_11;
regs_11 <= regs_12;
regs_12 <= regs_13;
regs_13 <= regs_14;
regs_14 <= regs_15;
regs_15 <= regs_16;
regs_16 <= regs_17;
regs_17 <= regs_18;
regs_18 <= regs_19;
regs_19 <= regs_20;
regs_20 <= regs_21;
regs_21 <= regs_22;
regs_22 <= regs_23;
regs_23 <= regs_24;
regs_24 <= regs_25;
regs_25 <= regs_26;
regs_26 <= regs_27;
regs_27 <= regs_28;
regs_28 <= regs_29;
regs_29 <= regs_30;
regs_30 <= regs_31;
regs_31 <= regs_32;
regs_32 <= regs_33;
regs_33 <= regs_34;
regs_34 <= regs_35;
regs_35 <= regs_36;
regs_36 <= regs_37;
regs_37 <= regs_38;
regs_38 <= regs_39;
regs_39 <= regs_40;
regs_40 <= io_chainIn_data;
end
end
assign io_chainOut_data = regs_0;
assign io_capture_capture = io_chainIn_capture;
assign io_update_valid = ~io_chainIn_capture & io_chainIn_update;
assign io_update_bits_addr = {regs_40, regs_39, regs_38, regs_37, regs_36, regs_35, regs_34};
assign io_update_bits_data = {regs_33, regs_32, regs_31, regs_30, regs_29, regs_28, regs_27, regs_26, regs_25, regs_24, regs_23, regs_22, regs_21, regs_20, regs_19, regs_18, regs_17, regs_16, regs_15, regs_14, regs_13, regs_12, regs_11, regs_10, regs_9, regs_8, regs_7, regs_6, regs_5, regs_4, regs_3, regs_2};
assign io_update_bits_op = {regs_1, regs_0};
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Unit Decode
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Generate the functional unit control signals from the micro-op opcodes.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.uintToBitPat
import freechips.rocketchip.rocket.CSR
import freechips.rocketchip.rocket.ALU._
import boom.v3.common._
/**
* Control signal bundle for register renaming
*/
class RRdCtrlSigs(implicit p: Parameters) extends BoomBundle
{
val br_type = UInt(BR_N.getWidth.W)
val use_alupipe = Bool()
val use_muldivpipe = Bool()
val use_mempipe = Bool()
val op_fcn = Bits(SZ_ALU_FN.W)
val fcn_dw = Bool()
val op1_sel = UInt(OP1_X.getWidth.W)
val op2_sel = UInt(OP2_X.getWidth.W)
val imm_sel = UInt(IS_X.getWidth.W)
val rf_wen = Bool()
val csr_cmd = Bits(CSR.SZ.W)
def decode(uopc: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
val decoder = freechips.rocketchip.rocket.DecodeLogic(uopc, AluRRdDecode.default, table)
val sigs = Seq(br_type, use_alupipe, use_muldivpipe, use_mempipe, op_fcn,
fcn_dw, op1_sel, op2_sel, imm_sel, rf_wen, csr_cmd)
sigs zip decoder map {case(s,d) => s := d}
this
}
}
/**
* Default register read constants
*/
abstract trait RRdDecodeConstants
{
val default: List[BitPat] =
List[BitPat](BR_N , Y, N, N, FN_ADD , DW_X , OP1_X , OP2_X , IS_X, REN_0, CSR.N)
val table: Array[(BitPat, List[BitPat])]
}
/**
* ALU register read constants
*/
object AluRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopLUI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMM , IS_U, REN_1, CSR.N),
BitPat(uopADDI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopANDI) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopORI) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopXORI) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLTI) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLTIU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLLI) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRAI) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRLI) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopADDIW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLLIW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRAIW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRLIW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopADD) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLL) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSUB) -> List(BR_N , Y, N, N, FN_SUB , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLT) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLTU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopAND) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopOR) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopXOR) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRA) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRL) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopADDW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSUBW) -> List(BR_N , Y, N, N, FN_SUB , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLLW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRAW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRLW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopBEQ) -> List(BR_EQ ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBNE) -> List(BR_NE ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBGE) -> List(BR_GE ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBGEU) -> List(BR_GEU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBLT) -> List(BR_LT ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBLTU) -> List(BR_LTU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N))
}
object JmpRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopJAL) -> List(BR_J , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_J, REN_1, CSR.N),
BitPat(uopJALR) -> List(BR_JR, Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_I, REN_1, CSR.N),
BitPat(uopAUIPC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_IMM , IS_U, REN_1, CSR.N))
}
/**
* Multiply divider register read constants
*/
object MulDivRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopMUL) -> List(BR_N , N, Y, N, FN_MUL, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULH) -> List(BR_N , N, Y, N, FN_MULH, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULHU) -> List(BR_N , N, Y, N, FN_MULHU, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULHSU)-> List(BR_N , N, Y, N, FN_MULHSU,DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULW) -> List(BR_N , N, Y, N, FN_MUL, DW_32 ,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopDIV) -> List(BR_N , N, Y, N, FN_DIV , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVU) -> List(BR_N , N, Y, N, FN_DIVU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREM) -> List(BR_N , N, Y, N, FN_REM , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMU) -> List(BR_N , N, Y, N, FN_REMU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVW) -> List(BR_N , N, Y, N, FN_DIV , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVUW) -> List(BR_N , N, Y, N, FN_DIVU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMW) -> List(BR_N , N, Y, N, FN_REM , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMUW) -> List(BR_N , N, Y, N, FN_REMU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N))
}
/**
* Memory unit register read constants
*/
object MemRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopLD) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_0, CSR.N),
BitPat(uopSTA) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_S, REN_0, CSR.N),
BitPat(uopSTD) -> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),
BitPat(uopSFENCE)-> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),
BitPat(uopAMO_AG)-> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_X, REN_0, CSR.N))
}
/**
* CSR register read constants
*/
object CsrRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopCSRRW) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.W),
BitPat(uopCSRRS) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.S),
BitPat(uopCSRRC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.C),
BitPat(uopCSRRWI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.W),
BitPat(uopCSRRSI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.S),
BitPat(uopCSRRCI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.C),
BitPat(uopWFI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I),
BitPat(uopERET) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I))
}
/**
* FPU register read constants
*/
object FpuRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFCLASS_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCLASS_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_X_W)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_X_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSGNJ_S)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSGNJ_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_S_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// TODO comment out I2F instructions.
BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_X_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_X_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopCMPR_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopCMPR_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMINMAX_S)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMINMAX_D)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMUL_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMUL_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMADD_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMSUB_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMADD_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMSUB_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Fused multiple add register read constants
*/
object IfmvRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Floating point divide and square root register read constants
*/
object FDivRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFDIV_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFDIV_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSQRT_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSQRT_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Register read decoder
*
* @param supportedUnits indicate what functional units are being used
*/
class RegisterReadDecode(supportedUnits: SupportedFuncUnits)(implicit p: Parameters) extends BoomModule
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val io = IO(new BoomBundle {
val iss_valid = Input(Bool())
val iss_uop = Input(new MicroOp())
val rrd_valid = Output(Bool())
val rrd_uop = Output(new MicroOp())
})
// Issued Instruction
val rrd_valid = io.iss_valid
io.rrd_uop := io.iss_uop
var dec_table = AluRRdDecode.table
if (supportedUnits.jmp) dec_table ++= JmpRRdDecode.table
if (supportedUnits.mem) dec_table ++= MemRRdDecode.table
if (supportedUnits.muld) dec_table ++= MulDivRRdDecode.table
if (supportedUnits.csr) dec_table ++= CsrRRdDecode.table
if (supportedUnits.fpu) dec_table ++= FpuRRdDecode.table
if (supportedUnits.fdiv) dec_table ++= FDivRRdDecode.table
if (supportedUnits.ifpu) dec_table ++= IfmvRRdDecode.table
val rrd_cs = Wire(new RRdCtrlSigs()).decode(io.rrd_uop.uopc, dec_table)
// rrd_use_alupipe is unused
io.rrd_uop.ctrl.br_type := rrd_cs.br_type
io.rrd_uop.ctrl.op1_sel := rrd_cs.op1_sel
io.rrd_uop.ctrl.op2_sel := rrd_cs.op2_sel
io.rrd_uop.ctrl.imm_sel := rrd_cs.imm_sel
io.rrd_uop.ctrl.op_fcn := rrd_cs.op_fcn.asUInt
io.rrd_uop.ctrl.fcn_dw := rrd_cs.fcn_dw.asBool
io.rrd_uop.ctrl.is_load := io.rrd_uop.uopc === uopLD
io.rrd_uop.ctrl.is_sta := io.rrd_uop.uopc === uopSTA || io.rrd_uop.uopc === uopAMO_AG
io.rrd_uop.ctrl.is_std := io.rrd_uop.uopc === uopSTD || (io.rrd_uop.ctrl.is_sta && io.rrd_uop.lrs2_rtype === RT_FIX)
when (io.rrd_uop.uopc === uopAMO_AG || (io.rrd_uop.uopc === uopLD && io.rrd_uop.mem_cmd === M_XLR)) {
io.rrd_uop.imm_packed := 0.U
}
val raddr1 = io.rrd_uop.prs1 // although renamed, it'll stay 0 if lrs1 = 0
val csr_ren = (rrd_cs.csr_cmd === CSR.S || rrd_cs.csr_cmd === CSR.C) && raddr1 === 0.U
io.rrd_uop.ctrl.csr_cmd := Mux(csr_ren, CSR.R, rrd_cs.csr_cmd)
//-------------------------------------------------------------
// set outputs
io.rrd_valid := rrd_valid
} | module RegisterReadDecode_1(
input io_iss_valid,
input [6:0] io_iss_uop_uopc,
input [31:0] io_iss_uop_inst,
input [31:0] io_iss_uop_debug_inst,
input io_iss_uop_is_rvc,
input [39:0] io_iss_uop_debug_pc,
input [2:0] io_iss_uop_iq_type,
input [9:0] io_iss_uop_fu_code,
input [1:0] io_iss_uop_iw_state,
input io_iss_uop_is_br,
input io_iss_uop_is_jalr,
input io_iss_uop_is_jal,
input io_iss_uop_is_sfb,
input [7:0] io_iss_uop_br_mask,
input [2:0] io_iss_uop_br_tag,
input [3:0] io_iss_uop_ftq_idx,
input io_iss_uop_edge_inst,
input [5:0] io_iss_uop_pc_lob,
input io_iss_uop_taken,
input [19:0] io_iss_uop_imm_packed,
input [11:0] io_iss_uop_csr_addr,
input [4:0] io_iss_uop_rob_idx,
input [2:0] io_iss_uop_ldq_idx,
input [2:0] io_iss_uop_stq_idx,
input [1:0] io_iss_uop_rxq_idx,
input [5:0] io_iss_uop_pdst,
input [5:0] io_iss_uop_prs1,
input [5:0] io_iss_uop_prs2,
input [5:0] io_iss_uop_prs3,
input [3:0] io_iss_uop_ppred,
input io_iss_uop_prs1_busy,
input io_iss_uop_prs2_busy,
input io_iss_uop_prs3_busy,
input io_iss_uop_ppred_busy,
input [5:0] io_iss_uop_stale_pdst,
input io_iss_uop_exception,
input [63:0] io_iss_uop_exc_cause,
input io_iss_uop_bypassable,
input [4:0] io_iss_uop_mem_cmd,
input [1:0] io_iss_uop_mem_size,
input io_iss_uop_mem_signed,
input io_iss_uop_is_fence,
input io_iss_uop_is_fencei,
input io_iss_uop_is_amo,
input io_iss_uop_uses_ldq,
input io_iss_uop_uses_stq,
input io_iss_uop_is_sys_pc2epc,
input io_iss_uop_is_unique,
input io_iss_uop_flush_on_commit,
input io_iss_uop_ldst_is_rs1,
input [5:0] io_iss_uop_ldst,
input [5:0] io_iss_uop_lrs1,
input [5:0] io_iss_uop_lrs2,
input [5:0] io_iss_uop_lrs3,
input io_iss_uop_ldst_val,
input [1:0] io_iss_uop_dst_rtype,
input [1:0] io_iss_uop_lrs1_rtype,
input [1:0] io_iss_uop_lrs2_rtype,
input io_iss_uop_frs3_en,
input io_iss_uop_fp_val,
input io_iss_uop_fp_single,
input io_iss_uop_xcpt_pf_if,
input io_iss_uop_xcpt_ae_if,
input io_iss_uop_xcpt_ma_if,
input io_iss_uop_bp_debug_if,
input io_iss_uop_bp_xcpt_if,
input [1:0] io_iss_uop_debug_fsrc,
input [1:0] io_iss_uop_debug_tsrc,
output io_rrd_valid,
output [6:0] io_rrd_uop_uopc,
output [31:0] io_rrd_uop_inst,
output [31:0] io_rrd_uop_debug_inst,
output io_rrd_uop_is_rvc,
output [39:0] io_rrd_uop_debug_pc,
output [2:0] io_rrd_uop_iq_type,
output [9:0] io_rrd_uop_fu_code,
output [3:0] io_rrd_uop_ctrl_br_type,
output [1:0] io_rrd_uop_ctrl_op1_sel,
output [2:0] io_rrd_uop_ctrl_op2_sel,
output [2:0] io_rrd_uop_ctrl_imm_sel,
output [4:0] io_rrd_uop_ctrl_op_fcn,
output io_rrd_uop_ctrl_fcn_dw,
output [2:0] io_rrd_uop_ctrl_csr_cmd,
output io_rrd_uop_ctrl_is_load,
output io_rrd_uop_ctrl_is_sta,
output io_rrd_uop_ctrl_is_std,
output [1:0] io_rrd_uop_iw_state,
output io_rrd_uop_is_br,
output io_rrd_uop_is_jalr,
output io_rrd_uop_is_jal,
output io_rrd_uop_is_sfb,
output [7:0] io_rrd_uop_br_mask,
output [2:0] io_rrd_uop_br_tag,
output [3:0] io_rrd_uop_ftq_idx,
output io_rrd_uop_edge_inst,
output [5:0] io_rrd_uop_pc_lob,
output io_rrd_uop_taken,
output [19:0] io_rrd_uop_imm_packed,
output [11:0] io_rrd_uop_csr_addr,
output [4:0] io_rrd_uop_rob_idx,
output [2:0] io_rrd_uop_ldq_idx,
output [2:0] io_rrd_uop_stq_idx,
output [1:0] io_rrd_uop_rxq_idx,
output [5:0] io_rrd_uop_pdst,
output [5:0] io_rrd_uop_prs1,
output [5:0] io_rrd_uop_prs2,
output [5:0] io_rrd_uop_prs3,
output [3:0] io_rrd_uop_ppred,
output io_rrd_uop_prs1_busy,
output io_rrd_uop_prs2_busy,
output io_rrd_uop_prs3_busy,
output io_rrd_uop_ppred_busy,
output [5:0] io_rrd_uop_stale_pdst,
output io_rrd_uop_exception,
output [63:0] io_rrd_uop_exc_cause,
output io_rrd_uop_bypassable,
output [4:0] io_rrd_uop_mem_cmd,
output [1:0] io_rrd_uop_mem_size,
output io_rrd_uop_mem_signed,
output io_rrd_uop_is_fence,
output io_rrd_uop_is_fencei,
output io_rrd_uop_is_amo,
output io_rrd_uop_uses_ldq,
output io_rrd_uop_uses_stq,
output io_rrd_uop_is_sys_pc2epc,
output io_rrd_uop_is_unique,
output io_rrd_uop_flush_on_commit,
output io_rrd_uop_ldst_is_rs1,
output [5:0] io_rrd_uop_ldst,
output [5:0] io_rrd_uop_lrs1,
output [5:0] io_rrd_uop_lrs2,
output [5:0] io_rrd_uop_lrs3,
output io_rrd_uop_ldst_val,
output [1:0] io_rrd_uop_dst_rtype,
output [1:0] io_rrd_uop_lrs1_rtype,
output [1:0] io_rrd_uop_lrs2_rtype,
output io_rrd_uop_frs3_en,
output io_rrd_uop_fp_val,
output io_rrd_uop_fp_single,
output io_rrd_uop_xcpt_pf_if,
output io_rrd_uop_xcpt_ae_if,
output io_rrd_uop_xcpt_ma_if,
output io_rrd_uop_bp_debug_if,
output io_rrd_uop_bp_xcpt_if,
output [1:0] io_rrd_uop_debug_fsrc,
output [1:0] io_rrd_uop_debug_tsrc
);
wire [6:0] rrd_cs_decoder_decoded_invInputs = ~io_iss_uop_uopc;
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], io_iss_uop_uopc[6]};
wire io_rrd_uop_ctrl_is_load_0 = io_iss_uop_uopc == 7'h1;
wire _io_rrd_uop_ctrl_is_sta_T_1 = io_iss_uop_uopc == 7'h43;
wire io_rrd_uop_ctrl_is_sta_0 = io_iss_uop_uopc == 7'h2 | _io_rrd_uop_ctrl_is_sta_T_1;
assign io_rrd_valid = io_iss_valid;
assign io_rrd_uop_uopc = io_iss_uop_uopc;
assign io_rrd_uop_inst = io_iss_uop_inst;
assign io_rrd_uop_debug_inst = io_iss_uop_debug_inst;
assign io_rrd_uop_is_rvc = io_iss_uop_is_rvc;
assign io_rrd_uop_debug_pc = io_iss_uop_debug_pc;
assign io_rrd_uop_iq_type = io_iss_uop_iq_type;
assign io_rrd_uop_fu_code = io_iss_uop_fu_code;
assign io_rrd_uop_ctrl_br_type = {1'h0, |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}};
assign io_rrd_uop_ctrl_op1_sel = {1'h0, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12};
assign io_rrd_uop_ctrl_op2_sel = {1'h0, &{rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]}, |{&{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}}};
assign io_rrd_uop_ctrl_imm_sel = {1'h0, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_12, &{io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12}};
assign io_rrd_uop_ctrl_op_fcn =
{|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_9, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58},
|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_9, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58},
|{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58},
|{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58},
|{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58}};
assign io_rrd_uop_ctrl_fcn_dw = {&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54} == 3'h0;
assign io_rrd_uop_ctrl_csr_cmd = 3'h0;
assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0;
assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0;
assign io_rrd_uop_ctrl_is_std = io_iss_uop_uopc == 7'h3 | io_rrd_uop_ctrl_is_sta_0 & io_iss_uop_lrs2_rtype == 2'h0;
assign io_rrd_uop_iw_state = io_iss_uop_iw_state;
assign io_rrd_uop_is_br = io_iss_uop_is_br;
assign io_rrd_uop_is_jalr = io_iss_uop_is_jalr;
assign io_rrd_uop_is_jal = io_iss_uop_is_jal;
assign io_rrd_uop_is_sfb = io_iss_uop_is_sfb;
assign io_rrd_uop_br_mask = io_iss_uop_br_mask;
assign io_rrd_uop_br_tag = io_iss_uop_br_tag;
assign io_rrd_uop_ftq_idx = io_iss_uop_ftq_idx;
assign io_rrd_uop_edge_inst = io_iss_uop_edge_inst;
assign io_rrd_uop_pc_lob = io_iss_uop_pc_lob;
assign io_rrd_uop_taken = io_iss_uop_taken;
assign io_rrd_uop_imm_packed = _io_rrd_uop_ctrl_is_sta_T_1 | io_rrd_uop_ctrl_is_load_0 & io_iss_uop_mem_cmd == 5'h6 ? 20'h0 : io_iss_uop_imm_packed;
assign io_rrd_uop_csr_addr = io_iss_uop_csr_addr;
assign io_rrd_uop_rob_idx = io_iss_uop_rob_idx;
assign io_rrd_uop_ldq_idx = io_iss_uop_ldq_idx;
assign io_rrd_uop_stq_idx = io_iss_uop_stq_idx;
assign io_rrd_uop_rxq_idx = io_iss_uop_rxq_idx;
assign io_rrd_uop_pdst = io_iss_uop_pdst;
assign io_rrd_uop_prs1 = io_iss_uop_prs1;
assign io_rrd_uop_prs2 = io_iss_uop_prs2;
assign io_rrd_uop_prs3 = io_iss_uop_prs3;
assign io_rrd_uop_ppred = io_iss_uop_ppred;
assign io_rrd_uop_prs1_busy = io_iss_uop_prs1_busy;
assign io_rrd_uop_prs2_busy = io_iss_uop_prs2_busy;
assign io_rrd_uop_prs3_busy = io_iss_uop_prs3_busy;
assign io_rrd_uop_ppred_busy = io_iss_uop_ppred_busy;
assign io_rrd_uop_stale_pdst = io_iss_uop_stale_pdst;
assign io_rrd_uop_exception = io_iss_uop_exception;
assign io_rrd_uop_exc_cause = io_iss_uop_exc_cause;
assign io_rrd_uop_bypassable = io_iss_uop_bypassable;
assign io_rrd_uop_mem_cmd = io_iss_uop_mem_cmd;
assign io_rrd_uop_mem_size = io_iss_uop_mem_size;
assign io_rrd_uop_mem_signed = io_iss_uop_mem_signed;
assign io_rrd_uop_is_fence = io_iss_uop_is_fence;
assign io_rrd_uop_is_fencei = io_iss_uop_is_fencei;
assign io_rrd_uop_is_amo = io_iss_uop_is_amo;
assign io_rrd_uop_uses_ldq = io_iss_uop_uses_ldq;
assign io_rrd_uop_uses_stq = io_iss_uop_uses_stq;
assign io_rrd_uop_is_sys_pc2epc = io_iss_uop_is_sys_pc2epc;
assign io_rrd_uop_is_unique = io_iss_uop_is_unique;
assign io_rrd_uop_flush_on_commit = io_iss_uop_flush_on_commit;
assign io_rrd_uop_ldst_is_rs1 = io_iss_uop_ldst_is_rs1;
assign io_rrd_uop_ldst = io_iss_uop_ldst;
assign io_rrd_uop_lrs1 = io_iss_uop_lrs1;
assign io_rrd_uop_lrs2 = io_iss_uop_lrs2;
assign io_rrd_uop_lrs3 = io_iss_uop_lrs3;
assign io_rrd_uop_ldst_val = io_iss_uop_ldst_val;
assign io_rrd_uop_dst_rtype = io_iss_uop_dst_rtype;
assign io_rrd_uop_lrs1_rtype = io_iss_uop_lrs1_rtype;
assign io_rrd_uop_lrs2_rtype = io_iss_uop_lrs2_rtype;
assign io_rrd_uop_frs3_en = io_iss_uop_frs3_en;
assign io_rrd_uop_fp_val = io_iss_uop_fp_val;
assign io_rrd_uop_fp_single = io_iss_uop_fp_single;
assign io_rrd_uop_xcpt_pf_if = io_iss_uop_xcpt_pf_if;
assign io_rrd_uop_xcpt_ae_if = io_iss_uop_xcpt_ae_if;
assign io_rrd_uop_xcpt_ma_if = io_iss_uop_xcpt_ma_if;
assign io_rrd_uop_bp_debug_if = io_iss_uop_bp_debug_if;
assign io_rrd_uop_bp_xcpt_if = io_iss_uop_bp_xcpt_if;
assign io_rrd_uop_debug_fsrc = io_iss_uop_debug_fsrc;
assign io_rrd_uop_debug_tsrc = io_iss_uop_debug_tsrc;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
} | module Repeater_TLBundleA_a28d64s7k1z3u(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [6:0] io_enq_bits_source,
input [27:0] io_enq_bits_address,
input [7:0] io_enq_bits_mask,
input io_enq_bits_corrupt,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [6:0] io_deq_bits_source,
output [27:0] io_deq_bits_address,
output [7:0] io_deq_bits_mask,
output io_deq_bits_corrupt
);
reg full;
reg [2:0] saved_opcode;
reg [2:0] saved_param;
reg [2:0] saved_size;
reg [6:0] saved_source;
reg [27:0] saved_address;
reg [7:0] saved_mask;
reg saved_corrupt;
wire io_deq_valid_0 = io_enq_valid | full;
wire io_enq_ready_0 = io_deq_ready & ~full;
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;
always @(posedge clock) begin
if (reset)
full <= 1'h0;
else
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);
if (_GEN) begin
saved_opcode <= io_enq_bits_opcode;
saved_param <= io_enq_bits_param;
saved_size <= io_enq_bits_size;
saved_source <= io_enq_bits_source;
saved_address <= io_enq_bits_address;
saved_mask <= io_enq_bits_mask;
saved_corrupt <= io_enq_bits_corrupt;
end
end
assign io_full = full;
assign io_enq_ready = io_enq_ready_0;
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
} | module ClockCrossingReg_w32_TestHarness_UNIQUIFIED(
input clock,
input [31:0] io_d,
output [31:0] io_q,
input io_en
);
reg [31:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
} | module FPToInt(
input clock,
input io_in_valid,
input io_in_bits_ren2,
input [1:0] io_in_bits_typeTagOut,
input io_in_bits_wflags,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_typ,
input [1:0] io_in_bits_fmt,
input [64:0] io_in_bits_in1,
input [64:0] io_in_bits_in2,
output io_out_bits_lt,
output [63:0] io_out_bits_toint,
output [4:0] io_out_bits_exc
);
wire [63:0] toint;
wire _narrow_io_signedOut_T;
wire intType;
wire [2:0] _narrow_io_intExceptionFlags;
wire [63:0] _conv_io_out;
wire [2:0] _conv_io_intExceptionFlags;
wire _dcmp_io_lt;
wire _dcmp_io_eq;
wire [4:0] _dcmp_io_exceptionFlags;
reg in_ren2;
reg [1:0] in_typeTagOut;
reg in_wflags;
reg [2:0] in_rm;
reg [1:0] in_typ;
reg [1:0] in_fmt;
reg [64:0] in_in1;
reg [64:0] in_in2;
wire [12:0] toint_ieee_unrecoded_rawIn_sExp = {1'h0, in_in1[63:52]};
wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
wire [1:0] _toint_ieee_prevUnrecoded_rawIn_isSpecial_T = {in_in1[52], in_in1[30]};
wire toint_ieee_prevUnrecoded_rawIn_isInf = (&_toint_ieee_prevUnrecoded_rawIn_isSpecial_T) & ~(in_in1[29]);
wire toint_ieee_prevUnrecoded_isSubnormal = $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_1 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
wire toint_ieee_unrecoded_rawIn_1_isInf = (&(in_in1[63:62])) & ~(in_in1[61]);
wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402;
wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? _toint_ieee_unrecoded_denormFract_T_3[51:0] : toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : in_in1[51:0];
wire [1:0] _toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1 = {in_in1[52], in_in1[30]};
wire toint_ieee_prevUnrecoded_rawIn_1_isInf = (&_toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1) & ~(in_in1[29]);
wire toint_ieee_prevUnrecoded_isSubnormal_1 = $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_3 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
wire [63:0] toint_ieee = in_typeTagOut[0] ? {in_in1[64], (toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : in_in1[62:52] + 11'h3FF) | {11{(&(in_in1[63:62])) & in_in1[61] | toint_ieee_unrecoded_rawIn_1_isInf}}, toint_ieee_unrecoded_fractOut_1[51:32], (&(in_in1[63:61])) ? {in_in1[31], (toint_ieee_prevUnrecoded_isSubnormal_1 ? 8'h0 : in_in1[30:23] + 8'h7F) | {8{(&_toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1) & in_in1[29] | toint_ieee_prevUnrecoded_rawIn_1_isInf}}, toint_ieee_prevUnrecoded_isSubnormal_1 ? _toint_ieee_prevUnrecoded_denormFract_T_3[22:0] : toint_ieee_prevUnrecoded_rawIn_1_isInf ? 23'h0 : in_in1[22:0]} : toint_ieee_unrecoded_fractOut_1[31:0]} : {2{(&(in_in1[63:61])) ? {in_in1[31], (toint_ieee_prevUnrecoded_isSubnormal ? 8'h0 : in_in1[30:23] + 8'h7F) | {8{(&_toint_ieee_prevUnrecoded_rawIn_isSpecial_T) & in_in1[29] | toint_ieee_prevUnrecoded_rawIn_isInf}}, toint_ieee_prevUnrecoded_isSubnormal ? _toint_ieee_prevUnrecoded_denormFract_T_1[22:0] : toint_ieee_prevUnrecoded_rawIn_isInf ? 23'h0 : in_in1[22:0]} : $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402 ? _toint_ieee_unrecoded_denormFract_T_1[31:0] : (&(in_in1[63:62])) & ~(in_in1[61]) ? 32'h0 : in_in1[31:0]}};
wire [8:0] _classify_out_expOut_commonCase_T = in_in1[60:52] - 9'h100;
wire [8:0] classify_out_expOut = in_in1[63:61] == 3'h0 | in_in1[63:61] > 3'h5 ? {in_in1[63:61], _classify_out_expOut_commonCase_T[5:0]} : _classify_out_expOut_commonCase_T;
wire _classify_out_isNormal_T = classify_out_expOut[8:7] == 2'h1;
wire classify_out_isSubnormal = classify_out_expOut[8:6] == 3'h1 | _classify_out_isNormal_T & classify_out_expOut[6:0] < 7'h2;
wire classify_out_isNormal = _classify_out_isNormal_T & (|(classify_out_expOut[6:1])) | classify_out_expOut[8:7] == 2'h2;
wire classify_out_isZero = classify_out_expOut[8:6] == 3'h0;
wire classify_out_isInf = (&(classify_out_expOut[8:7])) & ~(classify_out_expOut[6]);
wire _classify_out_isNormal_T_4 = in_in1[63:62] == 2'h1;
wire classify_out_isSubnormal_1 = in_in1[63:61] == 3'h1 | _classify_out_isNormal_T_4 & in_in1[61:52] < 10'h2;
wire classify_out_isNormal_1 = _classify_out_isNormal_T_4 & (|(in_in1[61:53])) | in_in1[63:62] == 2'h2;
wire classify_out_isZero_1 = in_in1[63:61] == 3'h0;
wire classify_out_isInf_1 = (&(in_in1[63:62])) & ~(in_in1[61]);
assign intType = in_wflags ? ~in_ren2 & in_typ[1] : ~(in_rm[0]) & in_fmt[0];
assign _narrow_io_signedOut_T = in_typ[0];
wire excSign = in_in1[64] & in_in1[63:61] != 3'h7;
wire invalid = _conv_io_intExceptionFlags[2] | _narrow_io_intExceptionFlags[1];
assign toint = in_wflags ? (in_ren2 ? {toint_ieee[63:32], 31'h0, |(~(in_rm[1:0]) & {_dcmp_io_lt, _dcmp_io_eq})} : ~(in_typ[1]) & invalid ? {_conv_io_out[63:32], ~_narrow_io_signedOut_T == excSign, {31{~excSign}}} : _conv_io_out) : in_rm[0] ? {toint_ieee[63:32], 22'h0, in_typeTagOut[0] ? {(&(in_in1[63:61])) & in_in1[51], (&(in_in1[63:61])) & ~(in_in1[51]), classify_out_isInf_1 & ~(in_in1[64]), classify_out_isNormal_1 & ~(in_in1[64]), classify_out_isSubnormal_1 & ~(in_in1[64]), classify_out_isZero_1 & ~(in_in1[64]), classify_out_isZero_1 & in_in1[64], classify_out_isSubnormal_1 & in_in1[64], classify_out_isNormal_1 & in_in1[64], classify_out_isInf_1 & in_in1[64]} : {(&(classify_out_expOut[8:6])) & in_in1[51], (&(classify_out_expOut[8:6])) & ~(in_in1[51]), classify_out_isInf & ~(in_in1[64]), classify_out_isNormal & ~(in_in1[64]), classify_out_isSubnormal & ~(in_in1[64]), classify_out_isZero & ~(in_in1[64]), classify_out_isZero & in_in1[64], classify_out_isSubnormal & in_in1[64], classify_out_isNormal & in_in1[64], classify_out_isInf & in_in1[64]}} : toint_ieee;
always @(posedge clock) begin
if (io_in_valid) begin
in_ren2 <= io_in_bits_ren2;
in_typeTagOut <= io_in_bits_typeTagOut;
in_wflags <= io_in_bits_wflags;
in_rm <= io_in_bits_rm;
in_typ <= io_in_bits_typ;
in_fmt <= io_in_bits_fmt;
in_in1 <= io_in_bits_in1;
in_in2 <= io_in_bits_in2;
end
end
CompareRecFN dcmp (
.io_a (in_in1),
.io_b (in_in2),
.io_signaling (~(in_rm[1])),
.io_lt (_dcmp_io_lt),
.io_eq (_dcmp_io_eq),
.io_exceptionFlags (_dcmp_io_exceptionFlags)
);
RecFNToIN_e11_s53_i64 conv (
.io_in (in_in1),
.io_roundingMode (in_rm),
.io_signedOut (~_narrow_io_signedOut_T),
.io_out (_conv_io_out),
.io_intExceptionFlags (_conv_io_intExceptionFlags)
);
RecFNToIN_e11_s53_i32 narrow (
.io_in (in_in1),
.io_roundingMode (in_rm),
.io_signedOut (~_narrow_io_signedOut_T),
.io_intExceptionFlags (_narrow_io_intExceptionFlags)
);
assign io_out_bits_lt = _dcmp_io_lt | $signed(in_in1) < 65'sh0 & $signed(in_in2) > -65'sh1;
assign io_out_bits_toint = intType ? toint : {{32{toint[31]}}, toint[31:0]};
assign io_out_bits_exc = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : in_typ[1] ? {|(_conv_io_intExceptionFlags[2:1]), 3'h0, _conv_io_intExceptionFlags[0]} : {invalid, 3'h0, ~invalid & _conv_io_intExceptionFlags[0]}) : 5'h0;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
} | module AsyncQueue(
input io_enq_clock,
input io_enq_reset,
output io_enq_ready,
input io_enq_valid,
input [31:0] io_enq_bits_phit,
input io_deq_clock,
input io_deq_reset,
input io_deq_ready,
output io_deq_valid,
output [31:0] io_deq_bits_phit
);
wire [3:0] _sink_io_async_ridx;
wire _sink_io_async_safe_ridx_valid;
wire _sink_io_async_safe_sink_reset_n;
wire [31:0] _source_io_async_mem_0_phit;
wire [31:0] _source_io_async_mem_1_phit;
wire [31:0] _source_io_async_mem_2_phit;
wire [31:0] _source_io_async_mem_3_phit;
wire [31:0] _source_io_async_mem_4_phit;
wire [31:0] _source_io_async_mem_5_phit;
wire [31:0] _source_io_async_mem_6_phit;
wire [31:0] _source_io_async_mem_7_phit;
wire [3:0] _source_io_async_widx;
wire _source_io_async_safe_widx_valid;
wire _source_io_async_safe_source_reset_n;
AsyncQueueSource_Phit source (
.clock (io_enq_clock),
.reset (io_enq_reset),
.io_enq_ready (io_enq_ready),
.io_enq_valid (io_enq_valid),
.io_enq_bits_phit (io_enq_bits_phit),
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
);
AsyncQueueSink_Phit sink (
.clock (io_deq_clock),
.reset (io_deq_reset),
.io_deq_ready (io_deq_ready),
.io_deq_valid (io_deq_valid),
.io_deq_bits_phit (io_deq_bits_phit),
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module tail_2x4(
input R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input R1_addr,
input R1_en,
input R1_clk,
output [3:0] R1_data,
input W0_addr,
input W0_en,
input W0_clk,
input [3:0] W0_data
);
reg [3:0] Memory[0:1];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 4'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 4'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module next_16x4(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [3:0] W0_data
);
reg [3:0] Memory[0:15];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 4'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Rename FreeList
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import boom.v3.common._
import boom.v3.util._
import org.chipsalliance.cde.config.Parameters
class RenameFreeList(
val plWidth: Int,
val numPregs: Int,
val numLregs: Int)
(implicit p: Parameters) extends BoomModule
{
private val pregSz = log2Ceil(numPregs)
private val n = numPregs
val io = IO(new BoomBundle()(p) {
// Physical register requests.
val reqs = Input(Vec(plWidth, Bool()))
val alloc_pregs = Output(Vec(plWidth, Valid(UInt(pregSz.W))))
// Pregs returned by the ROB.
val dealloc_pregs = Input(Vec(plWidth, Valid(UInt(pregSz.W))))
// Branch info for starting new allocation lists.
val ren_br_tags = Input(Vec(plWidth, Valid(UInt(brTagSz.W))))
// Mispredict info for recovering speculatively allocated registers.
val brupdate = Input(new BrUpdateInfo)
val debug = new Bundle {
val pipeline_empty = Input(Bool())
val freelist = Output(Bits(numPregs.W))
val isprlist = Output(Bits(numPregs.W))
}
})
// The free list register array and its branch allocation lists.
val free_list = RegInit(UInt(numPregs.W), ~(1.U(numPregs.W)))
val br_alloc_lists = Reg(Vec(maxBrCount, UInt(numPregs.W)))
// Select pregs from the free list.
val sels = SelectFirstN(free_list, plWidth)
val sel_fire = Wire(Vec(plWidth, Bool()))
// Allocations seen by branches in each pipeline slot.
val allocs = io.alloc_pregs map (a => UIntToOH(a.bits))
val alloc_masks = (allocs zip io.reqs).scanRight(0.U(n.W)) { case ((a,r),m) => m | a & Fill(n,r) }
// Masks that modify the freelist array.
val sel_mask = (sels zip sel_fire) map { case (s,f) => s & Fill(n,f) } reduce(_|_)
val br_deallocs = br_alloc_lists(io.brupdate.b2.uop.br_tag) & Fill(n, io.brupdate.b2.mispredict)
val dealloc_mask = io.dealloc_pregs.map(d => UIntToOH(d.bits)(numPregs-1,0) & Fill(n,d.valid)).reduce(_|_) | br_deallocs
val br_slots = VecInit(io.ren_br_tags.map(tag => tag.valid)).asUInt
// Create branch allocation lists.
for (i <- 0 until maxBrCount) {
val list_req = VecInit(io.ren_br_tags.map(tag => UIntToOH(tag.bits)(i))).asUInt & br_slots
val new_list = list_req.orR
br_alloc_lists(i) := Mux(new_list, Mux1H(list_req, alloc_masks.slice(1, plWidth+1)),
br_alloc_lists(i) & ~br_deallocs | alloc_masks(0))
}
// Update the free list.
free_list := (free_list & ~sel_mask | dealloc_mask) & ~(1.U(numPregs.W))
// Pipeline logic | hookup outputs.
for (w <- 0 until plWidth) {
val can_sel = sels(w).orR
val r_valid = RegInit(false.B)
val r_sel = RegEnable(OHToUInt(sels(w)), sel_fire(w))
r_valid := r_valid && !io.reqs(w) || can_sel
sel_fire(w) := (!r_valid || io.reqs(w)) && can_sel
io.alloc_pregs(w).bits := r_sel
io.alloc_pregs(w).valid := r_valid
}
io.debug.freelist := free_list | io.alloc_pregs.map(p => UIntToOH(p.bits) & Fill(n,p.valid)).reduce(_|_)
io.debug.isprlist := 0.U // TODO track commit free list.
assert (!(io.debug.freelist & dealloc_mask).orR, "[freelist] Returning a free physical register.")
assert (!io.debug.pipeline_empty || PopCount(io.debug.freelist) >= (numPregs - numLregs - 1).U,
"[freelist] Leaking physical registers.")
} | module RenameFreeList(
input clock,
input reset,
input io_reqs_0,
output io_alloc_pregs_0_valid,
output [5:0] io_alloc_pregs_0_bits,
input io_dealloc_pregs_0_valid,
input [5:0] io_dealloc_pregs_0_bits,
input io_ren_br_tags_0_valid,
input [2:0] io_ren_br_tags_0_bits,
input [2:0] io_brupdate_b2_uop_br_tag,
input io_brupdate_b2_mispredict,
input io_debug_pipeline_empty
);
reg [5:0] r_sel;
reg [51:0] free_list;
reg [51:0] br_alloc_lists_0;
reg [51:0] br_alloc_lists_1;
reg [51:0] br_alloc_lists_2;
reg [51:0] br_alloc_lists_3;
reg [51:0] br_alloc_lists_4;
reg [51:0] br_alloc_lists_5;
reg [51:0] br_alloc_lists_6;
reg [51:0] br_alloc_lists_7;
wire [51:0] sels_0 = free_list[0] ? 52'h1 : free_list[1] ? 52'h2 : free_list[2] ? 52'h4 : free_list[3] ? 52'h8 : free_list[4] ? 52'h10 : free_list[5] ? 52'h20 : free_list[6] ? 52'h40 : free_list[7] ? 52'h80 : free_list[8] ? 52'h100 : free_list[9] ? 52'h200 : free_list[10] ? 52'h400 : free_list[11] ? 52'h800 : free_list[12] ? 52'h1000 : free_list[13] ? 52'h2000 : free_list[14] ? 52'h4000 : free_list[15] ? 52'h8000 : free_list[16] ? 52'h10000 : free_list[17] ? 52'h20000 : free_list[18] ? 52'h40000 : free_list[19] ? 52'h80000 : free_list[20] ? 52'h100000 : free_list[21] ? 52'h200000 : free_list[22] ? 52'h400000 : free_list[23] ? 52'h800000 : free_list[24] ? 52'h1000000 : free_list[25] ? 52'h2000000 : free_list[26] ? 52'h4000000 : free_list[27] ? 52'h8000000 : free_list[28] ? 52'h10000000 : free_list[29] ? 52'h20000000 : free_list[30] ? 52'h40000000 : free_list[31] ? 52'h80000000 : free_list[32] ? 52'h100000000 : free_list[33] ? 52'h200000000 : free_list[34] ? 52'h400000000 : free_list[35] ? 52'h800000000 : free_list[36] ? 52'h1000000000 : free_list[37] ? 52'h2000000000 : free_list[38] ? 52'h4000000000 : free_list[39] ? 52'h8000000000 : free_list[40] ? 52'h10000000000 : free_list[41] ? 52'h20000000000 : free_list[42] ? 52'h40000000000 : free_list[43] ? 52'h80000000000 : free_list[44] ? 52'h100000000000 : free_list[45] ? 52'h200000000000 : free_list[46] ? 52'h400000000000 : free_list[47] ? 52'h800000000000 : free_list[48] ? 52'h1000000000000 : free_list[49] ? 52'h2000000000000 : free_list[50] ? 52'h4000000000000 : {free_list[51], 51'h0};
wire [63:0] allocs_0 = 64'h1 << r_sel;
wire [7:0][51:0] _GEN = {{br_alloc_lists_7}, {br_alloc_lists_6}, {br_alloc_lists_5}, {br_alloc_lists_4}, {br_alloc_lists_3}, {br_alloc_lists_2}, {br_alloc_lists_1}, {br_alloc_lists_0}};
wire [51:0] br_deallocs = _GEN[io_brupdate_b2_uop_br_tag] & {52{io_brupdate_b2_mispredict}};
wire [63:0] _dealloc_mask_T = 64'h1 << io_dealloc_pregs_0_bits;
wire [51:0] dealloc_mask = _dealloc_mask_T[51:0] & {52{io_dealloc_pregs_0_valid}} | br_deallocs;
reg r_valid;
wire sel_fire_0 = (~r_valid | io_reqs_0) & (|sels_0);
wire [30:0] _r_sel_T_1 = {12'h0, sels_0[51:33]} | sels_0[31:1];
wire [14:0] _r_sel_T_3 = _r_sel_T_1[30:16] | _r_sel_T_1[14:0];
wire [6:0] _r_sel_T_5 = _r_sel_T_3[14:8] | _r_sel_T_3[6:0];
wire [2:0] _r_sel_T_7 = _r_sel_T_5[6:4] | _r_sel_T_5[2:0];
wire [51:0] _GEN_0 = allocs_0[51:0] & {52{io_reqs_0}};
always @(posedge clock) begin
if (reset) begin
free_list <= 52'hFFFFFFFFFFFFE;
r_valid <= 1'h0;
end
else begin
free_list <= (free_list & ~(sels_0 & {52{sel_fire_0}}) | dealloc_mask) & 52'hFFFFFFFFFFFFE;
r_valid <= |{r_valid & ~io_reqs_0, sels_0};
end
br_alloc_lists_0 <= io_ren_br_tags_0_bits == 3'h0 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_0 & ~br_deallocs | _GEN_0;
br_alloc_lists_1 <= io_ren_br_tags_0_bits == 3'h1 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_1 & ~br_deallocs | _GEN_0;
br_alloc_lists_2 <= io_ren_br_tags_0_bits == 3'h2 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_2 & ~br_deallocs | _GEN_0;
br_alloc_lists_3 <= io_ren_br_tags_0_bits == 3'h3 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_3 & ~br_deallocs | _GEN_0;
br_alloc_lists_4 <= io_ren_br_tags_0_bits == 3'h4 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_4 & ~br_deallocs | _GEN_0;
br_alloc_lists_5 <= io_ren_br_tags_0_bits == 3'h5 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_5 & ~br_deallocs | _GEN_0;
br_alloc_lists_6 <= io_ren_br_tags_0_bits == 3'h6 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_6 & ~br_deallocs | _GEN_0;
br_alloc_lists_7 <= (&io_ren_br_tags_0_bits) & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_7 & ~br_deallocs | _GEN_0;
if (sel_fire_0)
r_sel <= {|(sels_0[51:32]), |(_r_sel_T_1[30:15]), |(_r_sel_T_3[14:7]), |(_r_sel_T_5[6:3]), |(_r_sel_T_7[2:1]), _r_sel_T_7[2] | _r_sel_T_7[0]};
end
assign io_alloc_pregs_0_valid = r_valid;
assign io_alloc_pregs_0_bits = r_sel;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1(
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire roundingMode_near_even = io_roundingMode == 3'h0;
wire roundingMode_odd = io_roundingMode == 3'h6;
wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;
wire [11:0] _roundMask_T_1 = ~(io_in_sExp[11:0]);
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]);
wire [18:0] _GEN = {roundMask_shift[18:17], roundMask_shift[20:19], roundMask_shift[22:21], roundMask_shift[24:23], roundMask_shift[26:25], roundMask_shift[28:27], roundMask_shift[30:29], roundMask_shift[32:31], roundMask_shift[34:33], roundMask_shift[36]} & 19'h55555;
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]);
wire [53:0] _roundMask_T_129 = _roundMask_T_1[11] ? (_roundMask_T_1[10] ? {~(_roundMask_T_1[9] | _roundMask_T_1[8] | _roundMask_T_1[7] | _roundMask_T_1[6] ? 51'h0 : ~{roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _GEN[18:15] | {roundMask_shift[20:19], roundMask_shift[22:21]} & 4'h5, roundMask_shift[22], _GEN[13] | roundMask_shift[23], roundMask_shift[24], roundMask_shift[25], _GEN[10:7] | {roundMask_shift[28:27], roundMask_shift[30:29]} & 4'h5, roundMask_shift[30], _GEN[5] | roundMask_shift[31], roundMask_shift[32], roundMask_shift[33], {_GEN[2:0], 1'h0} | {roundMask_shift[36:35], roundMask_shift[38:37]} & 4'h5, roundMask_shift[38], roundMask_shift[39], roundMask_shift[40], roundMask_shift[41], roundMask_shift[42], roundMask_shift[43], roundMask_shift[44], roundMask_shift[45], roundMask_shift[46], roundMask_shift[47], roundMask_shift[48], roundMask_shift[49], roundMask_shift[50], roundMask_shift[51], roundMask_shift[52], roundMask_shift[53], roundMask_shift[54], roundMask_shift[55], roundMask_shift[56], roundMask_shift[57], roundMask_shift[58], roundMask_shift[59], roundMask_shift[60], roundMask_shift[61], roundMask_shift[62], roundMask_shift[63]}), 3'h7} : {51'h0, _roundMask_T_1[9] & _roundMask_T_1[8] & _roundMask_T_1[7] & _roundMask_T_1[6] ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} : 3'h0}) : 54'h0;
wire [54:0] _GEN_0 = {1'h1, ~_roundMask_T_129};
wire [54:0] _GEN_1 = {_roundMask_T_129, 1'h1};
wire [54:0] _roundPosBit_T = io_in_sig[55:1] & _GEN_0 & _GEN_1;
wire [54:0] _anyRoundExtra_T = io_in_sig[54:0] & _GEN_1;
wire [109:0] _GEN_2 = {_roundPosBit_T, _anyRoundExtra_T};
wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;
wire [54:0] roundedSig = _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & (|_GEN_2) ? {1'h0, io_in_sig[55:2] | _roundMask_T_129} + 55'h1 & ~(roundingMode_near_even & (|_roundPosBit_T) & _anyRoundExtra_T == 55'h0 ? {_roundMask_T_129, 1'h1} : 55'h0) : {1'h0, io_in_sig[55:2] & ~_roundMask_T_129} | (roundingMode_odd & (|_GEN_2) ? _GEN_0 & _GEN_1 : 55'h0);
wire [13:0] sRoundedExp = {io_in_sExp[12], io_in_sExp} + {12'h0, roundedSig[54:53]};
wire common_totalUnderflow = $signed(sRoundedExp) < 14'sh3CE;
wire isNaNOut = io_invalidExc | io_in_isNaN;
wire notNaN_isSpecialInfOut = io_infiniteExc | io_in_isInf;
wire commonCase = ~isNaNOut & ~notNaN_isSpecialInfOut & ~io_in_isZero;
wire overflow = commonCase & $signed(sRoundedExp[13:10]) > 4'sh2;
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;
wire pegMinNonzeroMagOut = commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);
wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;
wire notNaN_isInfOut = notNaN_isSpecialInfOut | overflow & overflow_roundMagUp;
assign io_out = {~isNaNOut & io_in_sign, sRoundedExp[11:0] & ~(io_in_isZero | common_totalUnderflow ? 12'hE00 : 12'h0) & ~(pegMinNonzeroMagOut ? 12'hC31 : 12'h0) & {1'h1, ~pegMaxFiniteMagOut, 10'h3FF} & {2'h3, ~notNaN_isInfOut, 9'h1FF} | (pegMinNonzeroMagOut ? 12'h3CE : 12'h0) | (pegMaxFiniteMagOut ? 12'hBFF : 12'h0) | (notNaN_isInfOut ? 12'hC00 : 12'h0) | (isNaNOut ? 12'hE00 : 12'h0), (isNaNOut | io_in_isZero | common_totalUnderflow ? {isNaNOut, 51'h0} : roundedSig[51:0]) | {52{pegMaxFiniteMagOut}}};
assign io_exceptionFlags = {io_invalidExc, io_infiniteExc, overflow, commonCase & (common_totalUnderflow | (|_GEN_2) & io_in_sExp[12:11] != 2'h1 & _roundMask_T_129[0]), overflow | commonCase & (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module l2_tlb_ram_0(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [44:0] RW0_wdata,
output [44:0] RW0_rdata
);
l2_tlb_ram_0_ext l2_tlb_ram_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomBTBParams(
nSets: Int = 128,
nWays: Int = 2,
offsetSz: Int = 13,
extendedNSets: Int = 128
)
class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
override val nWays = params.nWays
val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1
val offsetSz = params.offsetSz
val extendedNSets = params.extendedNSets
require(isPow2(nSets))
require(isPow2(extendedNSets) || extendedNSets == 0)
require(extendedNSets <= nSets)
require(extendedNSets >= 1)
class BTBEntry extends Bundle {
val offset = SInt(offsetSz.W)
val extended = Bool()
}
val btbEntrySz = offsetSz + 1
class BTBMeta extends Bundle {
val is_br = Bool()
val tag = UInt(tagSz.W)
}
val btbMetaSz = tagSz + 1
class BTBPredictMeta extends Bundle {
val write_way = UInt(log2Ceil(nWays).W)
}
val s1_meta = Wire(new BTBPredictMeta)
val f3_meta = RegNext(RegNext(s1_meta))
io.f3_meta := f3_meta.asUInt
override val metaSz = s1_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }
val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }
val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))
val mems = (((0 until nWays) map ({w:Int => Seq(
(f"btb_meta_way$w", nSets, bankWidth * btbMetaSz),
(f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended)))
val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })
val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })
val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)
val s1_req_tag = s1_idx >> log2Ceil(nSets)
val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))
val s1_is_br = Wire(Vec(bankWidth, Bool()))
val s1_is_jal = Wire(Vec(bankWidth, Bool()))
val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>
VecInit((0 until nWays) map { w =>
s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)
})
})
val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }
val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }
for (w <- 0 until bankWidth) {
val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)
val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)
s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)
s1_resp(w).bits := Mux(
entry_btb.extended,
s1_req_rebtb,
(s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)
s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br
s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br
io.resp.f2(w) := io.resp_in(0).f2(w)
io.resp.f3(w) := io.resp_in(0).f3(w)
when (RegNext(s1_hits(w))) {
io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))
io.resp.f2(w).is_br := RegNext(s1_is_br(w))
io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))
when (RegNext(s1_is_jal(w))) {
io.resp.f2(w).taken := true.B
}
}
when (RegNext(RegNext(s1_hits(w)))) {
io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)
io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)
io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)
when (RegNext(RegNext(s1_is_jal(w)))) {
io.resp.f3(w).taken := true.B
}
}
}
val alloc_way = if (nWays > 1) {
val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))
val l = log2Ceil(nWays)
val nChunks = (r_metas.getWidth + l - 1) / l
val chunks = (0 until nChunks) map { i =>
r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
}
chunks.reduce(_^_)
} else {
0.U
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
alloc_way)
val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)
val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt
val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt
val new_offset_value = (s1_update.bits.target.asSInt -
(s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)
val offset_is_extended = (new_offset_value > max_offset_value ||
new_offset_value < min_offset_value)
val s1_update_wbtb_data = Wire(new BTBEntry)
s1_update_wbtb_data.extended := offset_is_extended
s1_update_wbtb_data.offset := new_offset_value
val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &
Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))
val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &
(Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |
(Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)
)
)
val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))
for (w <- 0 until bankWidth) {
s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))
s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)
}
for (w <- 0 until nWays) {
when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {
btb(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),
VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wbtb_mask).asBools
)
meta(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),
VecInit(s1_update_wmeta_data.map(_.asUInt))),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wmeta_mask).asBools
)
}
}
when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {
ebtb.write(s1_update_idx, s1_update.bits.target)
}
} | module meta_0(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [123:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [123:0] W0_data,
input [3:0] W0_mask
);
meta_0_ext meta_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module dataArrayWay_3(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
dataArrayWay_0_ext dataArrayWay_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module array_2_0_0(
input [8:0] R0_addr,
input R0_en,
input R0_clk,
output [63:0] R0_data,
input [8:0] W0_addr,
input W0_en,
input W0_clk,
input [63:0] W0_data
);
array_0_0_0_ext array_0_0_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomBTBParams(
nSets: Int = 128,
nWays: Int = 2,
offsetSz: Int = 13,
extendedNSets: Int = 128
)
class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
override val nWays = params.nWays
val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1
val offsetSz = params.offsetSz
val extendedNSets = params.extendedNSets
require(isPow2(nSets))
require(isPow2(extendedNSets) || extendedNSets == 0)
require(extendedNSets <= nSets)
require(extendedNSets >= 1)
class BTBEntry extends Bundle {
val offset = SInt(offsetSz.W)
val extended = Bool()
}
val btbEntrySz = offsetSz + 1
class BTBMeta extends Bundle {
val is_br = Bool()
val tag = UInt(tagSz.W)
}
val btbMetaSz = tagSz + 1
class BTBPredictMeta extends Bundle {
val write_way = UInt(log2Ceil(nWays).W)
}
val s1_meta = Wire(new BTBPredictMeta)
val f3_meta = RegNext(RegNext(s1_meta))
io.f3_meta := f3_meta.asUInt
override val metaSz = s1_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }
val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }
val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))
val mems = (((0 until nWays) map ({w:Int => Seq(
(f"btb_meta_way$w", nSets, bankWidth * btbMetaSz),
(f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended)))
val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })
val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })
val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)
val s1_req_tag = s1_idx >> log2Ceil(nSets)
val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))
val s1_is_br = Wire(Vec(bankWidth, Bool()))
val s1_is_jal = Wire(Vec(bankWidth, Bool()))
val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>
VecInit((0 until nWays) map { w =>
s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)
})
})
val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }
val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }
for (w <- 0 until bankWidth) {
val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)
val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)
s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)
s1_resp(w).bits := Mux(
entry_btb.extended,
s1_req_rebtb,
(s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)
s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br
s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br
io.resp.f2(w) := io.resp_in(0).f2(w)
io.resp.f3(w) := io.resp_in(0).f3(w)
when (RegNext(s1_hits(w))) {
io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))
io.resp.f2(w).is_br := RegNext(s1_is_br(w))
io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))
when (RegNext(s1_is_jal(w))) {
io.resp.f2(w).taken := true.B
}
}
when (RegNext(RegNext(s1_hits(w)))) {
io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)
io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)
io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)
when (RegNext(RegNext(s1_is_jal(w)))) {
io.resp.f3(w).taken := true.B
}
}
}
val alloc_way = if (nWays > 1) {
val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))
val l = log2Ceil(nWays)
val nChunks = (r_metas.getWidth + l - 1) / l
val chunks = (0 until nChunks) map { i =>
r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
}
chunks.reduce(_^_)
} else {
0.U
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
alloc_way)
val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)
val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt
val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt
val new_offset_value = (s1_update.bits.target.asSInt -
(s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)
val offset_is_extended = (new_offset_value > max_offset_value ||
new_offset_value < min_offset_value)
val s1_update_wbtb_data = Wire(new BTBEntry)
s1_update_wbtb_data.extended := offset_is_extended
s1_update_wbtb_data.offset := new_offset_value
val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &
Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))
val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &
(Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |
(Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)
)
)
val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))
for (w <- 0 until bankWidth) {
s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))
s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)
}
for (w <- 0 until nWays) {
when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {
btb(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),
VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wbtb_mask).asBools
)
meta(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),
VecInit(s1_update_wmeta_data.map(_.asUInt))),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wmeta_mask).asBools
)
}
}
when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {
ebtb.write(s1_update_idx, s1_update.bits.target)
}
} | module meta_1(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [123:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [123:0] W0_data,
input [3:0] W0_mask
);
meta_0_ext meta_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
} | module Repeater_TLBundleD_a29d64s6k1z4u(
input clock,
input reset,
input io_repeat,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [1:0] io_enq_bits_param,
input [3:0] io_enq_bits_size,
input [5:0] io_enq_bits_source,
input io_enq_bits_sink,
input io_enq_bits_denied,
input [63:0] io_enq_bits_data,
input io_enq_bits_corrupt,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [1:0] io_deq_bits_param,
output [3:0] io_deq_bits_size,
output [5:0] io_deq_bits_source,
output io_deq_bits_sink,
output io_deq_bits_denied,
output [63:0] io_deq_bits_data,
output io_deq_bits_corrupt
);
reg full;
reg [2:0] saved_opcode;
reg [1:0] saved_param;
reg [3:0] saved_size;
reg [5:0] saved_source;
reg saved_sink;
reg saved_denied;
reg [63:0] saved_data;
reg saved_corrupt;
wire io_deq_valid_0 = io_enq_valid | full;
wire io_enq_ready_0 = io_deq_ready & ~full;
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;
always @(posedge clock) begin
if (reset)
full <= 1'h0;
else
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);
if (_GEN) begin
saved_opcode <= io_enq_bits_opcode;
saved_param <= io_enq_bits_param;
saved_size <= io_enq_bits_size;
saved_source <= io_enq_bits_source;
saved_sink <= io_enq_bits_sink;
saved_denied <= io_enq_bits_denied;
saved_data <= io_enq_bits_data;
saved_corrupt <= io_enq_bits_corrupt;
end
end
assign io_enq_ready = io_enq_ready_0;
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;
assign io_deq_bits_sink = full ? saved_sink : io_enq_bits_sink;
assign io_deq_bits_denied = full ? saved_denied : io_enq_bits_denied;
assign io_deq_bits_data = full ? saved_data : io_enq_bits_data;
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2017 SiFive, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of SiFive nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*
s = sigWidth
c_i = newBit
Division:
width of a is (s+2)
Normal
------
(qi + ci * 2^(-i))*b <= a
q0 = 0
r0 = a
q(i+1) = qi + ci*2^(-i)
ri = a - qi*b
r(i+1) = a - q(i+1)*b
= a - qi*b - ci*2^(-i)*b
r(i+1) = ri - ci*2^(-i)*b
ci = ri >= 2^(-i)*b
summary_i = ri != 0
i = 0 to s+1
(s+1)th bit plus summary_(i+1) gives enough information for rounding
If (a < b), then we need to calculate (s+2)th bit and summary_(i+1)
because we need s bits ignoring the leading zero. (This is skipCycle2
part of Hauser's code.)
Hauser
------
sig_i = qi
rem_i = 2^(i-2)*ri
cycle_i = s+3-i
sig_0 = 0
rem_0 = a/4
cycle_0 = s+3
bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)
sig(i+1) = sig(i) + ci*bit_i
rem(i+1) = 2rem_i - ci*b/2
ci = 2rem_i >= b/2
bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)
cycle(i+1) = cycle_i-1
summary_1 = a <> b
summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0
Proof:
2^i*r(i+1) = 2^i*ri - ci*b. Qed
ci = 2^i*ri >= b. Qed
summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0
Now, note that all of ck's cannot be 0, since that means
a is 0. So when you traverse through a chain of 0 ck's,
from the end,
eventually, you reach a non-zero cj. That is exactly the
value of ri as the reminder remains the same. When all ck's
are 0 except c0 (which must be 1) then summary_1 is set
correctly according
to r1 = a-b != 0. So summary(i+1) is always set correctly
according to r(i+1)
Square root:
width of a is (s+1)
Normal
------
(xi + ci*2^(-i))^2 <= a
xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a
x0 = 0
x(i+1) = xi + ci*2^(-i)
ri = a - xi^2
r(i+1) = a - x(i+1)^2
= a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))
= ri - ci*2^(-i)*(2xi+ci*2^(-i))
= ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1
ci = ri >= 2^(-i)*(2xi + 2^(-i))
summary_i = ri != 0
i = 0 to s+1
For odd expression, do 2 steps initially.
(s+1)th bit plus summary_(i+1) gives enough information for rounding.
Hauser
------
sig_i = xi
rem_i = ri*2^(i-1)
cycle_i = s+2-i
bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)
sig_0 = 0
rem_0 = a/2
cycle_0 = s+2
bit_0 = 1 (= 2^s in terms of bit representation)
sig(i+1) = sig_i + ci * bit_i
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
ci = 2*sig_i + bit_i <= 2*rem_i
bit_i = 2^(cycle_i-2) (in terms of bit representation)
cycle(i+1) = cycle_i-1
summary_1 = a - (2^s) (in terms of bit representation)
summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0
Proof:
ci = 2*sig_i + bit_i <= 2*rem_i
ci = 2xi + 2^(-i) <= ri*2^i. Qed
sig(i+1) = sig_i + ci * bit_i
x(i+1) = xi + ci*2^(-i). Qed
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))
r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed
Same argument as before for summary.
------------------------------
Note that all registers are updated normally until cycle == 2.
At cycle == 2, rem is not updated, but all other registers are updated normally.
But, cycle == 1 does not read rem to calculate anything (note that final summary
is calculated using the values at cycle = 2).
*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))
val inReady = RegInit(true.B) // <-> (cycleNum <= 1)
val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)
val sqrtOp_Z = Reg(Bool())
val majorExc_Z = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_Z = Reg(Bool())
val isInf_Z = Reg(Bool())
val isZero_Z = Reg(Bool())
val sign_Z = Reg(Bool())
val sExp_Z = Reg(SInt((expWidth + 2).W))
val fractB_Z = Reg(UInt(sigWidth.W))
val roundingMode_Z = Reg(UInt(3.W))
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
val rem_Z = Reg(UInt((sigWidth + 2).W))
val notZeroRem_Z = Reg(Bool())
val sigX_Z = Reg(UInt((sigWidth + 2).W))
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rawA_S = io.a
val rawB_S = io.b
//*** IMPROVE THESE:
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +&
Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(expWidth + 1, expWidth - 2)
),
sExpQuot_S_div(expWidth - 3, 0)
).asSInt
val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)
val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val idle = cycleNum === 0.U
val entering = inReady && io.inValid
val entering_normalCase = entering && normalCase_S
val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B
val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B
when (! idle || entering) {
def computeCycleNum(f: UInt => UInt): UInt = {
Mux(entering & ! normalCase_S, f(1.U), 0.U) |
Mux(entering_normalCase,
Mux(io.sqrtOp,
Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),
f((sigWidth + 2).U)
),
0.U
) |
Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |
Mux(skipCycle2, f(1.U), 0.U)
}
inReady := computeCycleNum(_ <= 1.U).asBool
rawOutValid := computeCycleNum(_ === 1.U).asBool
cycleNum := computeCycleNum(x => x)
}
io.inReady := inReady
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering) {
sqrtOp_Z := io.sqrtOp
majorExc_Z := majorExc_S
isNaN_Z := isNaN_S
isInf_Z := isInf_S
isZero_Z := isZero_S
sign_Z := sign_S
sExp_Z :=
Mux(io.sqrtOp,
(rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,
sSatExpQuot_S_div
)
roundingMode_Z := io.roundingMode
}
when (entering || ! inReady && sqrtOp_Z) {
fractB_Z :=
Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |
Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |
Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rem =
Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |
Mux(inReady && oddSqrt_S,
Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,
rawA_S.sig(sigWidth - 3, 0)<<3
),
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady, fractB_Z, 0.U) |
Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) |
Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U)
val trialRem = rem.zext -& trialTerm.zext
val newBit = (0.S <= trialRem)
val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0)
val rem2 = nextRem_Z<<1
val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))
val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)
val trialRem2 =
Mux(newBit,
(trialRem<<1) - trialTerm2_newBit1.zext,
(rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)
val newBit2 = (0.S <= trialRem2)
val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)
val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)
processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||
processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||
!(processTwoBits && newBit2) && nextNotZeroRem_Z
val nextRem_Z_2 =
Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |
Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |
Mux(!processTwoBits, nextRem_Z, 0.U)
when (entering || ! inReady) {
notZeroRem_Z := nextNotZeroRem_Z_2
rem_Z := nextRem_Z_2
sigX_Z :=
Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |
Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) |
Mux(! inReady, sigX_Z, 0.U) |
Mux(! inReady && newBit, bitMask, 0.U) |
Mux(processTwoBits && newBit2, bitMask>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := rawOutValid && ! sqrtOp_Z
io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z
io.roundingModeOut := roundingMode_Z
io.invalidExc := majorExc_Z && isNaN_Z
io.infiniteExc := majorExc_Z && ! isNaN_Z
io.rawOut.isNaN := isNaN_Z
io.rawOut.isInf := isInf_Z
io.rawOut.isZero := isZero_Z
io.rawOut.sign := sign_Z
io.rawOut.sExp := sExp_Z
io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val divSqrtRawFN =
Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))
io.inReady := divSqrtRawFN.io.inReady
divSqrtRawFN.io.inValid := io.inValid
divSqrtRawFN.io.sqrtOp := io.sqrtOp
divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
divSqrtRawFN.io.roundingMode := io.roundingMode
io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div
io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt
io.roundingModeOut := divSqrtRawFN.io.roundingModeOut
io.invalidExc := divSqrtRawFN.io.invalidExc
io.infiniteExc := divSqrtRawFN.io.infiniteExc
io.rawOut := divSqrtRawFN.io.rawOut
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecFNToRaw =
Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))
io.inReady := divSqrtRecFNToRaw.io.inReady
divSqrtRecFNToRaw.io.inValid := io.inValid
divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecFNToRaw.io.a := io.a
divSqrtRecFNToRaw.io.b := io.b
divSqrtRecFNToRaw.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module DivSqrtRawFN_small_e8_s24(
input clock,
input reset,
output io_inReady,
input io_inValid,
input io_sqrtOp,
input io_a_isNaN,
input io_a_isInf,
input io_a_isZero,
input io_a_sign,
input [9:0] io_a_sExp,
input [24:0] io_a_sig,
input io_b_isNaN,
input io_b_isInf,
input io_b_isZero,
input io_b_sign,
input [9:0] io_b_sExp,
input [24:0] io_b_sig,
input [2:0] io_roundingMode,
output io_rawOutValid_div,
output io_rawOutValid_sqrt,
output [2:0] io_roundingModeOut,
output io_invalidExc,
output io_infiniteExc,
output io_rawOut_isNaN,
output io_rawOut_isInf,
output io_rawOut_isZero,
output io_rawOut_sign,
output [9:0] io_rawOut_sExp,
output [26:0] io_rawOut_sig
);
reg [4:0] cycleNum;
reg inReady;
reg rawOutValid;
reg sqrtOp_Z;
reg majorExc_Z;
reg isNaN_Z;
reg isInf_Z;
reg isZero_Z;
reg sign_Z;
reg [9:0] sExp_Z;
reg [23:0] fractB_Z;
reg [2:0] roundingMode_Z;
reg [25:0] rem_Z;
reg notZeroRem_Z;
reg [25:0] sigX_Z;
wire specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero;
wire normalCase_S = io_sqrtOp ? ~specialCaseA_S & ~io_a_sign : ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero);
wire skipCycle2 = cycleNum == 5'h3 & sigX_Z[25];
wire notSigNaNIn_invalidExc_S_div = io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf;
wire notSigNaNIn_invalidExc_S_sqrt = ~io_a_isNaN & ~io_a_isZero & io_a_sign;
wire [10:0] sExpQuot_S_div = {io_a_sExp[9], io_a_sExp} + {{3{io_b_sExp[8]}}, ~(io_b_sExp[7:0])};
wire [23:0] _fractB_Z_T_4 = inReady & ~io_sqrtOp ? {io_b_sig[22:0], 1'h0} : 24'h0;
wire _fractB_Z_T_10 = inReady & io_sqrtOp;
wire [31:0] _bitMask_T = 32'h1 << cycleNum;
wire oddSqrt_S = io_sqrtOp & io_a_sExp[0];
wire entering = inReady & io_inValid;
wire _sigX_Z_T_7 = inReady & oddSqrt_S;
wire [26:0] rem = {1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 26'h0} | (_sigX_Z_T_7 ? {io_a_sig[23:22] - 2'h1, io_a_sig[21:0], 3'h0} : 27'h0) | (inReady ? 27'h0 : {rem_Z, 1'h0});
wire [25:0] _trialTerm_T_3 = inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 26'h0;
wire [25:0] _trialTerm_T_9 = {_trialTerm_T_3[25], _trialTerm_T_3[24:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 24'h0}} | (_sigX_Z_T_7 ? 26'h2800000 : 26'h0);
wire [28:0] trialRem = {2'h0, rem} - {2'h0, {1'h0, _trialTerm_T_9[25], _trialTerm_T_9[24] | ~inReady & ~sqrtOp_Z, _trialTerm_T_9[23:0] | (inReady ? 24'h0 : fractB_Z)} | (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 27'h0)};
wire newBit = $signed(trialRem) > -29'sh1;
wire _GEN = entering | ~inReady;
wire [4:0] _cycleNum_T_15 = {4'h0, entering & ~normalCase_S} | (entering & normalCase_S ? (io_sqrtOp ? {4'hC, ~(io_a_sExp[0])} : 5'h1A) : 5'h0) | (entering | skipCycle2 ? 5'h0 : cycleNum - 5'h1);
wire [25:0] _sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 25'h0} : 26'h0;
wire [24:0] _GEN_0 = _sigX_Z_T_3[24:0] | {inReady & io_sqrtOp, 24'h0};
always @(posedge clock) begin
if (reset) begin
cycleNum <= 5'h0;
inReady <= 1'h1;
rawOutValid <= 1'h0;
end
else if ((|cycleNum) | entering) begin
cycleNum <= {_cycleNum_T_15[4:1], _cycleNum_T_15[0] | skipCycle2};
inReady <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 5'h1 < 5'h2 | skipCycle2;
rawOutValid <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 5'h1 == 5'h1 | skipCycle2;
end
if (entering) begin
sqrtOp_Z <= io_sqrtOp;
majorExc_Z <= io_sqrtOp ? io_a_isNaN & ~(io_a_sig[22]) | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN & ~(io_a_sig[22]) | io_b_isNaN & ~(io_b_sig[22]) | notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero;
isNaN_Z <= io_sqrtOp ? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div;
isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf;
isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero;
sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign;
sExp_Z <= io_sqrtOp ? {io_a_sExp[9], io_a_sExp[9:1]} + 10'h80 : {$signed(sExpQuot_S_div) > 11'sh1BF ? 4'h6 : sExpQuot_S_div[9:6], sExpQuot_S_div[5:0]};
roundingMode_Z <= io_roundingMode;
end
if (entering | ~inReady & sqrtOp_Z)
fractB_Z <= {_fractB_Z_T_4[23] | _fractB_Z_T_10 & ~(io_a_sExp[0]), _fractB_Z_T_4[22:0] | {_fractB_Z_T_10 & io_a_sExp[0], 22'h0} | (inReady ? 23'h0 : fractB_Z[23:1])};
if (_GEN) begin
rem_Z <= newBit ? trialRem[25:0] : rem[25:0];
sigX_Z <= {_sigX_Z_T_3[25], _GEN_0[24], _GEN_0[23:0] | (_sigX_Z_T_7 ? {newBit, 23'h0} : 24'h0)} | (inReady ? 26'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[27:2] : 26'h0);
end
if (_GEN & (inReady | newBit))
notZeroRem_Z <= |trialRem;
end
assign io_inReady = inReady;
assign io_rawOutValid_div = rawOutValid & ~sqrtOp_Z;
assign io_rawOutValid_sqrt = rawOutValid & sqrtOp_Z;
assign io_roundingModeOut = roundingMode_Z;
assign io_invalidExc = majorExc_Z & isNaN_Z;
assign io_infiniteExc = majorExc_Z & ~isNaN_Z;
assign io_rawOut_isNaN = isNaN_Z;
assign io_rawOut_isInf = isInf_Z;
assign io_rawOut_isZero = isZero_Z;
assign io_rawOut_sign = sign_Z;
assign io_rawOut_sExp = sExp_Z;
assign io_rawOut_sig = {sigX_Z, notZeroRem_Z};
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2017 SiFive, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of SiFive nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*
s = sigWidth
c_i = newBit
Division:
width of a is (s+2)
Normal
------
(qi + ci * 2^(-i))*b <= a
q0 = 0
r0 = a
q(i+1) = qi + ci*2^(-i)
ri = a - qi*b
r(i+1) = a - q(i+1)*b
= a - qi*b - ci*2^(-i)*b
r(i+1) = ri - ci*2^(-i)*b
ci = ri >= 2^(-i)*b
summary_i = ri != 0
i = 0 to s+1
(s+1)th bit plus summary_(i+1) gives enough information for rounding
If (a < b), then we need to calculate (s+2)th bit and summary_(i+1)
because we need s bits ignoring the leading zero. (This is skipCycle2
part of Hauser's code.)
Hauser
------
sig_i = qi
rem_i = 2^(i-2)*ri
cycle_i = s+3-i
sig_0 = 0
rem_0 = a/4
cycle_0 = s+3
bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)
sig(i+1) = sig(i) + ci*bit_i
rem(i+1) = 2rem_i - ci*b/2
ci = 2rem_i >= b/2
bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)
cycle(i+1) = cycle_i-1
summary_1 = a <> b
summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0
Proof:
2^i*r(i+1) = 2^i*ri - ci*b. Qed
ci = 2^i*ri >= b. Qed
summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0
Now, note that all of ck's cannot be 0, since that means
a is 0. So when you traverse through a chain of 0 ck's,
from the end,
eventually, you reach a non-zero cj. That is exactly the
value of ri as the reminder remains the same. When all ck's
are 0 except c0 (which must be 1) then summary_1 is set
correctly according
to r1 = a-b != 0. So summary(i+1) is always set correctly
according to r(i+1)
Square root:
width of a is (s+1)
Normal
------
(xi + ci*2^(-i))^2 <= a
xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a
x0 = 0
x(i+1) = xi + ci*2^(-i)
ri = a - xi^2
r(i+1) = a - x(i+1)^2
= a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))
= ri - ci*2^(-i)*(2xi+ci*2^(-i))
= ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1
ci = ri >= 2^(-i)*(2xi + 2^(-i))
summary_i = ri != 0
i = 0 to s+1
For odd expression, do 2 steps initially.
(s+1)th bit plus summary_(i+1) gives enough information for rounding.
Hauser
------
sig_i = xi
rem_i = ri*2^(i-1)
cycle_i = s+2-i
bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)
sig_0 = 0
rem_0 = a/2
cycle_0 = s+2
bit_0 = 1 (= 2^s in terms of bit representation)
sig(i+1) = sig_i + ci * bit_i
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
ci = 2*sig_i + bit_i <= 2*rem_i
bit_i = 2^(cycle_i-2) (in terms of bit representation)
cycle(i+1) = cycle_i-1
summary_1 = a - (2^s) (in terms of bit representation)
summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0
Proof:
ci = 2*sig_i + bit_i <= 2*rem_i
ci = 2xi + 2^(-i) <= ri*2^i. Qed
sig(i+1) = sig_i + ci * bit_i
x(i+1) = xi + ci*2^(-i). Qed
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))
r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed
Same argument as before for summary.
------------------------------
Note that all registers are updated normally until cycle == 2.
At cycle == 2, rem is not updated, but all other registers are updated normally.
But, cycle == 1 does not read rem to calculate anything (note that final summary
is calculated using the values at cycle = 2).
*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))
val inReady = RegInit(true.B) // <-> (cycleNum <= 1)
val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)
val sqrtOp_Z = Reg(Bool())
val majorExc_Z = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_Z = Reg(Bool())
val isInf_Z = Reg(Bool())
val isZero_Z = Reg(Bool())
val sign_Z = Reg(Bool())
val sExp_Z = Reg(SInt((expWidth + 2).W))
val fractB_Z = Reg(UInt(sigWidth.W))
val roundingMode_Z = Reg(UInt(3.W))
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
val rem_Z = Reg(UInt((sigWidth + 2).W))
val notZeroRem_Z = Reg(Bool())
val sigX_Z = Reg(UInt((sigWidth + 2).W))
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rawA_S = io.a
val rawB_S = io.b
//*** IMPROVE THESE:
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +&
Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(expWidth + 1, expWidth - 2)
),
sExpQuot_S_div(expWidth - 3, 0)
).asSInt
val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)
val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val idle = cycleNum === 0.U
val entering = inReady && io.inValid
val entering_normalCase = entering && normalCase_S
val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B
val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B
when (! idle || entering) {
def computeCycleNum(f: UInt => UInt): UInt = {
Mux(entering & ! normalCase_S, f(1.U), 0.U) |
Mux(entering_normalCase,
Mux(io.sqrtOp,
Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),
f((sigWidth + 2).U)
),
0.U
) |
Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |
Mux(skipCycle2, f(1.U), 0.U)
}
inReady := computeCycleNum(_ <= 1.U).asBool
rawOutValid := computeCycleNum(_ === 1.U).asBool
cycleNum := computeCycleNum(x => x)
}
io.inReady := inReady
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering) {
sqrtOp_Z := io.sqrtOp
majorExc_Z := majorExc_S
isNaN_Z := isNaN_S
isInf_Z := isInf_S
isZero_Z := isZero_S
sign_Z := sign_S
sExp_Z :=
Mux(io.sqrtOp,
(rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,
sSatExpQuot_S_div
)
roundingMode_Z := io.roundingMode
}
when (entering || ! inReady && sqrtOp_Z) {
fractB_Z :=
Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |
Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |
Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rem =
Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |
Mux(inReady && oddSqrt_S,
Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,
rawA_S.sig(sigWidth - 3, 0)<<3
),
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady, fractB_Z, 0.U) |
Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) |
Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U)
val trialRem = rem.zext -& trialTerm.zext
val newBit = (0.S <= trialRem)
val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0)
val rem2 = nextRem_Z<<1
val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))
val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)
val trialRem2 =
Mux(newBit,
(trialRem<<1) - trialTerm2_newBit1.zext,
(rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)
val newBit2 = (0.S <= trialRem2)
val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)
val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)
processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||
processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||
!(processTwoBits && newBit2) && nextNotZeroRem_Z
val nextRem_Z_2 =
Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |
Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |
Mux(!processTwoBits, nextRem_Z, 0.U)
when (entering || ! inReady) {
notZeroRem_Z := nextNotZeroRem_Z_2
rem_Z := nextRem_Z_2
sigX_Z :=
Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |
Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) |
Mux(! inReady, sigX_Z, 0.U) |
Mux(! inReady && newBit, bitMask, 0.U) |
Mux(processTwoBits && newBit2, bitMask>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := rawOutValid && ! sqrtOp_Z
io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z
io.roundingModeOut := roundingMode_Z
io.invalidExc := majorExc_Z && isNaN_Z
io.infiniteExc := majorExc_Z && ! isNaN_Z
io.rawOut.isNaN := isNaN_Z
io.rawOut.isInf := isInf_Z
io.rawOut.isZero := isZero_Z
io.rawOut.sign := sign_Z
io.rawOut.sExp := sExp_Z
io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val divSqrtRawFN =
Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))
io.inReady := divSqrtRawFN.io.inReady
divSqrtRawFN.io.inValid := io.inValid
divSqrtRawFN.io.sqrtOp := io.sqrtOp
divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
divSqrtRawFN.io.roundingMode := io.roundingMode
io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div
io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt
io.roundingModeOut := divSqrtRawFN.io.roundingModeOut
io.invalidExc := divSqrtRawFN.io.invalidExc
io.infiniteExc := divSqrtRawFN.io.infiniteExc
io.rawOut := divSqrtRawFN.io.rawOut
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecFNToRaw =
Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))
io.inReady := divSqrtRecFNToRaw.io.inReady
divSqrtRecFNToRaw.io.inValid := io.inValid
divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecFNToRaw.io.a := io.a
divSqrtRecFNToRaw.io.b := io.b
divSqrtRecFNToRaw.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module DivSqrtRecFM_small_e8_s24(
input clock,
input reset,
output io_inReady,
input io_inValid,
input io_sqrtOp,
input [32:0] io_a,
input [32:0] io_b,
input [2:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [32:0] io_out,
output [4:0] io_exceptionFlags
);
wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;
wire _divSqrtRecFNToRaw_io_invalidExc;
wire _divSqrtRecFNToRaw_io_infiniteExc;
wire _divSqrtRecFNToRaw_io_rawOut_isNaN;
wire _divSqrtRecFNToRaw_io_rawOut_isInf;
wire _divSqrtRecFNToRaw_io_rawOut_isZero;
wire _divSqrtRecFNToRaw_io_rawOut_sign;
wire [9:0] _divSqrtRecFNToRaw_io_rawOut_sExp;
wire [26:0] _divSqrtRecFNToRaw_io_rawOut_sig;
DivSqrtRecFMToRaw_small_e8_s24 divSqrtRecFNToRaw (
.clock (clock),
.reset (reset),
.io_inReady (io_inReady),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a (io_a),
.io_b (io_b),
.io_roundingMode (io_roundingMode),
.io_rawOutValid_div (io_outValid_div),
.io_rawOutValid_sqrt (io_outValid_sqrt),
.io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)
);
RoundRawFNToRecFN_e8_s24 roundRawFNToRecFN (
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),
.io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule |
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